diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
| commit | 08f7a8bc005507117ffda41f283adecf7e4d24f2 (patch) | |
| tree | d3588f01b572538601360998b89e23607549934c /tests | |
| parent | 93a8423dea8f8194d83df85a5b3043f9beaf0a1e (diff) | |
| download | gem5-08f7a8bc005507117ffda41f283adecf7e4d24f2.tar.xz | |
stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
Diffstat (limited to 'tests')
23 files changed, 13720 insertions, 13721 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 8dbc85977..3aeb18f28 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.899762 # Number of seconds simulated -sim_ticks 1899762444000 # Number of ticks simulated -final_tick 1899762444000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.897808 # Number of seconds simulated +sim_ticks 1897807508000 # Number of ticks simulated +final_tick 1897807508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165662 # Simulator instruction rate (inst/s) -host_op_rate 165662 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5547317951 # Simulator tick rate (ticks/s) -host_mem_usage 338604 # Number of bytes of host memory used -host_seconds 342.47 # Real time elapsed on the host -sim_insts 56733550 # Number of instructions simulated -sim_ops 56733550 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 853120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24660608 # Number of bytes read from this memory +host_inst_rate 93562 # Simulator instruction rate (inst/s) +host_op_rate 93562 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3130145601 # Simulator tick rate (ticks/s) +host_mem_usage 338704 # Number of bytes of host memory used +host_seconds 606.30 # Real time elapsed on the host +sim_insts 56726638 # Number of instructions simulated +sim_ops 56726638 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 852800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24659584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2651648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 536896 # Number of bytes read from this memory -system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 853120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7795456 # Number of bytes written to this memory -system.physmem.bytes_written::total 7795456 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13330 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385322 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 123904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 537024 # Number of bytes read from this memory +system.physmem.bytes_read::total 28824960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 852800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 123904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976704 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7794816 # Number of bytes written to this memory +system.physmem.bytes_written::total 7794816 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385306 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121804 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121804 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12980890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1395779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15173333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449067 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 514052 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4103385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4103385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4103385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12980890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1395779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 282612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19276718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450402 # Total number of read requests seen -system.physmem.writeReqs 121804 # Total number of write requests seen -system.physmem.cpureqs 579957 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28825728 # Total number of bytes read from memory -system.physmem.bytesWritten 7795456 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7795456 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5038 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28521 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28015 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28417 # Track reads on a per bank basis +system.physmem.num_reads::cpu1.inst 1936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8391 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450390 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121794 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121794 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449361 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12993722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1397217 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 65288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15188558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449361 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 65288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 514649 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4107274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4107274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4107274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449361 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12993722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1397217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 65288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 282971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19295833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450390 # Total number of read requests seen +system.physmem.writeReqs 121794 # Total number of write requests seen +system.physmem.cpureqs 577229 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28824960 # Total number of bytes read from memory +system.physmem.bytesWritten 7794816 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28824960 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7794816 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 5032 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28516 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28182 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28018 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28421 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 28335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28180 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28301 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28181 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28277 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 28045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27882 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27807 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27954 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7961 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 28103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28047 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27949 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7958 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 7786 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7706 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7580 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7703 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7676 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7587 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7619 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7293 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7271 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7481 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7325 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7481 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7700 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7581 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7698 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7706 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7677 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7592 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7617 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7480 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7323 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7475 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2713 # Number of times wr buffer was full causing retry -system.physmem.totGap 1899757983000 # Total gap between requests +system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry +system.physmem.totGap 1897802972000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450402 # Categorize read packet sizes +system.physmem.readPktSize::6 450390 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 121804 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 319830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 33225 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121794 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 319842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33247 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1403 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 1355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -138,224 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5295 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5295 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5295 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5295 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 19 # What write queue length does an incoming req see -system.physmem.totQLat 7756175500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15561175500 # Sum of mem lat for all requests -system.physmem.totBusLat 2251705000 # Total cycles spent in databus access -system.physmem.totBankLat 5553295000 # Total cycles spent in bank access -system.physmem.avgQLat 17222.89 # Average queueing delay per request -system.physmem.avgBankLat 12331.31 # Average bank access latency per request +system.physmem.wrQLenPdf::23 2130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.totQLat 7744912500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15549496250 # Sum of mem lat for all requests +system.physmem.totBusLat 2251660000 # Total cycles spent in databus access +system.physmem.totBankLat 5552923750 # Total cycles spent in bank access +system.physmem.avgQLat 17198.23 # Average queueing delay per request +system.physmem.avgBankLat 12330.73 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34554.21 # Average memory access latency -system.physmem.avgRdBW 15.17 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.17 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.10 # 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mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.401180 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.303731 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.079514 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.165940 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015433 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.303731 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008484 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.079514 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.165940 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31362.312909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 60307.049774 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 32823.975305 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10077.141220 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892105 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.056957 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::total 0.401232 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015436 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.303748 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008520 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.079613 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165989 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015436 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.303748 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008520 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.079613 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165989 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55836.669768 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31384.536475 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64392.115702 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62282.240449 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 32827.581437 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10077.153447 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.787533 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.311962 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10036.213636 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.693478 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.658889 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54047.666159 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84701.467778 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 55986.446652 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37996.548381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82165.343408 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39635.605391 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56467.973220 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37996.548381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63704.447900 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82165.343408 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39635.605391 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53993.863466 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 84491.528555 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 55922.422447 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55836.669768 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37996.360934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64392.115702 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 82167.998942 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39618.924754 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55836.669768 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37996.360934 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64392.115702 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 82167.998942 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39618.924754 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -494,14 +494,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41697 # number of replacements -system.iocache.tagsinuse 0.501565 # Cycle average of tags in use +system.iocache.tagsinuse 0.485600 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1705456155000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.501565 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.031348 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.031348 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 0.485600 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.030350 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.030350 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -512,12 +512,12 @@ system.iocache.overall_misses::tsunami.ide 41729 # system.iocache.overall_misses::total 41729 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21380998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21380998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10589255806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10589255806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10610636804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10610636804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10610636804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10610636804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10586785423 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10586785423 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10608166421 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10608166421 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10608166421 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10608166421 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -536,17 +536,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120796.598870 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120796.598870 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254843.468570 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 254843.468570 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 254274.888063 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 254274.888063 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 254274.888063 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 281737 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254784.015763 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 254784.015763 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 254215.687436 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 254215.687436 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 254215.687436 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 254215.687436 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 281558 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 26988 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 26875 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.439343 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.476577 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -562,12 +562,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41729 system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12176249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12176249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8427244570 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8427244570 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8439420819 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8439420819 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8439420819 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8439420819 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8424787682 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8424787682 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8436963931 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8436963931 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8436963931 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8436963931 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -578,12 +578,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68792.367232 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68792.367232 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202812.008327 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 202812.008327 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202243.543315 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 202243.543315 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202752.880295 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 202752.880295 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202184.666084 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 202184.666084 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202184.666084 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 202184.666084 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -597,35 +597,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12335027 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10393813 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 330568 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7867422 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5239774 # Number of BTB hits +system.cpu0.branchPred.lookups 12324830 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10383801 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 330699 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7879276 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5243296 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.600902 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 784891 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32664 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.545403 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 784421 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32635 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8753494 # DTB read hits -system.cpu0.dtb.read_misses 29787 # DTB read misses -system.cpu0.dtb.read_acv 536 # DTB read access violations -system.cpu0.dtb.read_accesses 623801 # DTB read accesses -system.cpu0.dtb.write_hits 5745053 # DTB write hits -system.cpu0.dtb.write_misses 8131 # DTB write misses -system.cpu0.dtb.write_acv 346 # DTB write access violations -system.cpu0.dtb.write_accesses 207769 # DTB write accesses -system.cpu0.dtb.data_hits 14498547 # DTB hits -system.cpu0.dtb.data_misses 37918 # DTB misses -system.cpu0.dtb.data_acv 882 # DTB access violations -system.cpu0.dtb.data_accesses 831570 # DTB accesses -system.cpu0.itb.fetch_hits 986254 # ITB hits -system.cpu0.itb.fetch_misses 27996 # ITB misses -system.cpu0.itb.fetch_acv 985 # ITB acv -system.cpu0.itb.fetch_accesses 1014250 # ITB accesses +system.cpu0.dtb.read_hits 8754095 # DTB read hits +system.cpu0.dtb.read_misses 29935 # DTB read misses +system.cpu0.dtb.read_acv 546 # DTB read access violations +system.cpu0.dtb.read_accesses 624217 # DTB read accesses +system.cpu0.dtb.write_hits 5744304 # DTB write hits +system.cpu0.dtb.write_misses 8066 # DTB write misses +system.cpu0.dtb.write_acv 350 # DTB write access violations +system.cpu0.dtb.write_accesses 207709 # DTB write accesses +system.cpu0.dtb.data_hits 14498399 # DTB hits +system.cpu0.dtb.data_misses 38001 # DTB misses +system.cpu0.dtb.data_acv 896 # DTB access violations +system.cpu0.dtb.data_accesses 831926 # DTB accesses +system.cpu0.itb.fetch_hits 984231 # ITB hits +system.cpu0.itb.fetch_misses 30400 # ITB misses +system.cpu0.itb.fetch_acv 951 # ITB acv +system.cpu0.itb.fetch_accesses 1014631 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,134 +638,134 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 101860002 # number of cpu cycles simulated +system.cpu0.numCycles 101829868 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24837828 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63180848 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12335027 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6024665 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11886569 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1686741 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36619319 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 32566 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 195803 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 292498 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 224 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7637223 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223881 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 74953254 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.842937 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.180655 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24831231 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63164825 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12324830 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6027717 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11886034 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1687418 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36616651 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 32610 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 197530 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 292271 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 247 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7635312 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223745 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 74945500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.842810 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.180311 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63066685 84.14% 84.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 761791 1.02% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1555671 2.08% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 698950 0.93% 88.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2562608 3.42% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 513718 0.69% 92.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 568258 0.76% 93.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 822289 1.10% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4403284 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63059466 84.14% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 761662 1.02% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1556791 2.08% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 699013 0.93% 88.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2562383 3.42% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 515928 0.69% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 568129 0.76% 93.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 822428 1.10% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4399700 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74953254 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121098 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.620271 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26053984 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36115594 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10809914 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 920077 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1053684 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 507198 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35097 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62027396 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105101 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1053684 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27061357 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14627985 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18001405 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10130422 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4078399 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58721682 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6643 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 642092 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1424191 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39329555 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71492090 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71110334 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 381756 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34559979 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4769568 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1435328 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 208629 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11112444 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9161053 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6009456 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1123532 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 742915 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52110985 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1787265 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 50968553 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87650 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5843461 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2979197 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1210641 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 74953254 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.680005 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.329199 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 74945500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.121034 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.620298 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26048767 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36112585 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10811010 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 918999 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1054138 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 507624 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35116 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62016567 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 105227 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1054138 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27056479 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14636567 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17989986 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10129953 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4078375 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58716570 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6669 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 641571 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1425002 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39326634 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71486416 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71104766 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 381650 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34557314 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4769312 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1434958 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 208601 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11111126 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9162338 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6008284 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124943 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 741369 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52108127 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1785217 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 50965376 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 88359 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5842472 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2979590 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1208696 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 74945500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680033 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329236 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52302643 69.78% 69.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10307098 13.75% 83.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4640048 6.19% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3056236 4.08% 93.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2433864 3.25% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1212107 1.62% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 643283 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 306838 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 51137 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52296103 69.78% 69.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10307056 13.75% 83.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4639666 6.19% 89.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3056082 4.08% 93.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2432821 3.25% 97.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1212271 1.62% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 643524 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 306857 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 51120 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 74953254 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 74945500 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 83602 12.51% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.51% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 310944 46.54% 59.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 273567 40.95% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 83315 12.44% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 310574 46.36% 58.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 276009 41.20% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35163137 68.99% 69.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56167 0.11% 69.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35160159 68.99% 69.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56163 0.11% 69.11% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.11% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 15648 0.03% 69.14% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.14% # Type of FU issued @@ -793,114 +793,114 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.14% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9108259 17.87% 87.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5813234 11.41% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 806455 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9109271 17.87% 87.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5812211 11.40% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 806271 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 50968553 # Type of FU issued -system.cpu0.iq.rate 0.500378 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 668113 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013108 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 177097926 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59488760 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 49954313 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 548196 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 265355 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 258816 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51345953 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 286939 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 543981 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 50965376 # Type of FU issued +system.cpu0.iq.rate 0.500495 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 669898 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 177086282 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59482873 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 49950097 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 548226 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 265331 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 258806 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51344519 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 286981 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 543841 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1095536 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3484 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12649 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 447527 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1097645 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3519 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12633 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 446832 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18428 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 123543 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18414 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 123451 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1053684 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10434033 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 794004 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57098821 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 607587 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9161053 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6009456 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1574353 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 581874 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5211 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12649 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164505 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 346352 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 510857 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50581166 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8806339 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 387386 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1054138 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10442164 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 794127 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57094083 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 608812 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9162338 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6008284 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1572405 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 581948 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5528 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12633 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164589 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 346313 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 510902 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50577895 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8807105 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 387480 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3200571 # number of nop insts executed -system.cpu0.iew.exec_refs 14573024 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8058196 # Number of branches executed -system.cpu0.iew.exec_stores 5766685 # Number of stores executed -system.cpu0.iew.exec_rate 0.496575 # Inst execution rate -system.cpu0.iew.wb_sent 50300704 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50213129 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25063994 # num instructions producing a value -system.cpu0.iew.wb_consumers 33773959 # num instructions consuming a value +system.cpu0.iew.exec_nop 3200739 # number of nop insts executed +system.cpu0.iew.exec_refs 14572965 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8058105 # Number of branches executed +system.cpu0.iew.exec_stores 5765860 # Number of stores executed +system.cpu0.iew.exec_rate 0.496690 # Inst execution rate +system.cpu0.iew.wb_sent 50296670 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50208903 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25061095 # num instructions producing a value +system.cpu0.iew.wb_consumers 33769433 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.492962 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742110 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.493067 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742124 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6307351 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 576624 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 477479 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 73899570 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685982 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.603952 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6306622 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 576521 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 477545 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 73891362 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.686006 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.603918 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 54870784 74.25% 74.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7931577 10.73% 84.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4331737 5.86% 90.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2351789 3.18% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1313178 1.78% 95.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 548800 0.74% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 466874 0.63% 97.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 433224 0.59% 97.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1651607 2.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 54863146 74.25% 74.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7931478 10.73% 84.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4331360 5.86% 90.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2351860 3.18% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1314304 1.78% 95.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 548181 0.74% 96.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 466916 0.63% 97.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 432440 0.59% 97.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1651677 2.24% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 73899570 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50693798 # Number of instructions committed -system.cpu0.commit.committedOps 50693798 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 73891362 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50689891 # Number of instructions committed +system.cpu0.commit.committedOps 50689891 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13627446 # Number of memory references committed -system.cpu0.commit.loads 8065517 # Number of loads committed -system.cpu0.commit.membars 196376 # Number of memory barriers committed -system.cpu0.commit.branches 7658577 # Number of branches committed +system.cpu0.commit.refs 13626145 # Number of memory references committed +system.cpu0.commit.loads 8064693 # Number of loads committed +system.cpu0.commit.membars 196335 # Number of memory barriers committed +system.cpu0.commit.branches 7657959 # Number of branches committed system.cpu0.commit.fp_insts 256550 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46944411 # Number of committed integer instructions. -system.cpu0.commit.function_calls 646517 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1651607 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 46940801 # Number of committed integer instructions. +system.cpu0.commit.function_calls 646411 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1651677 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129054613 # The number of ROB reads -system.cpu0.rob.rob_writes 115056832 # The number of ROB writes -system.cpu0.timesIdled 1051988 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26906748 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3697658339 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47774945 # Number of Instructions Simulated -system.cpu0.committedOps 47774945 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47774945 # Number of Instructions Simulated -system.cpu0.cpi 2.132080 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.132080 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.469026 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.469026 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66569976 # number of integer regfile reads -system.cpu0.int_regfile_writes 36353057 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127037 # number of floating regfile reads -system.cpu0.fp_regfile_writes 128676 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1691103 # number of misc regfile reads -system.cpu0.misc_regfile_writes 806046 # number of misc regfile writes +system.cpu0.rob.rob_reads 129041756 # The number of ROB reads +system.cpu0.rob.rob_writes 115048006 # The number of ROB writes +system.cpu0.timesIdled 1051806 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26884368 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693778600 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47771172 # Number of Instructions Simulated +system.cpu0.committedOps 47771172 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47771172 # Number of Instructions Simulated +system.cpu0.cpi 2.131618 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.131618 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.469127 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.469127 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66565111 # number of integer regfile reads +system.cpu0.int_regfile_writes 36349916 # number of integer regfile writes +system.cpu0.fp_regfile_reads 127030 # number of floating regfile reads +system.cpu0.fp_regfile_writes 128672 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1690077 # number of misc regfile reads +system.cpu0.misc_regfile_writes 805917 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,245 +932,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 863258 # number of replacements -system.cpu0.icache.tagsinuse 510.308888 # Cycle average of tags in use -system.cpu0.icache.total_refs 6729374 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 863770 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.790701 # Average number of references to valid blocks. +system.cpu0.icache.replacements 862820 # number of replacements +system.cpu0.icache.tagsinuse 510.307143 # Cycle average of tags in use +system.cpu0.icache.total_refs 6727960 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 863332 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.793016 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 20507557000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.308888 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996697 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996697 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6729374 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6729374 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6729374 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6729374 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6729374 # number of overall hits -system.cpu0.icache.overall_hits::total 6729374 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 907848 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 907848 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 907848 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 907848 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 907848 # number of overall misses -system.cpu0.icache.overall_misses::total 907848 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12809117491 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12809117491 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12809117491 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12809117491 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12809117491 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12809117491 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7637222 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7637222 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7637222 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7637222 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7637222 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7637222 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118871 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118871 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118871 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118871 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118871 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118871 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14109.319502 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14109.319502 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14109.319502 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14109.319502 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14109.319502 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5737 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 510.307143 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996694 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996694 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6727960 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6727960 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6727960 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6727960 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6727960 # number of overall hits +system.cpu0.icache.overall_hits::total 6727960 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 907351 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 907351 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 907351 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 907351 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 907351 # number of overall misses +system.cpu0.icache.overall_misses::total 907351 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12784635489 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12784635489 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12784635489 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12784635489 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12784635489 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12784635489 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7635311 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7635311 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7635311 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7635311 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7635311 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7635311 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118836 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118836 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118836 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118836 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118836 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118836 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14090.066015 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14090.066015 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14090.066015 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14090.066015 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14090.066015 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14090.066015 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5023 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 178 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 35.633540 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.219101 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43927 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43927 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43927 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43927 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43927 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43927 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863921 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 863921 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 863921 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 863921 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 863921 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 863921 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10545414492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10545414492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10545414492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10545414492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10545414492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10545414492 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113120 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113120 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113120 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113120 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12206.456947 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12206.456947 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12206.456947 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43874 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43874 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43874 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43874 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43874 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43874 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 863477 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 863477 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 863477 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 863477 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 863477 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 863477 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10532261990 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10532261990 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10532261990 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10532261990 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10532261990 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10532261990 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113090 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113090 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113090 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113090 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12197.501485 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12197.501485 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12197.501485 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12197.501485 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1272639 # number of replacements -system.cpu0.dcache.tagsinuse 505.727163 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10328741 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1273151 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.112738 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1272509 # number of replacements +system.cpu0.dcache.tagsinuse 505.757504 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10329025 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1273021 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.113790 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.727163 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987748 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987748 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6350419 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6350419 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3622179 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3622179 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160143 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 160143 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184450 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 184450 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9972598 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9972598 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9972598 # number of overall hits -system.cpu0.dcache.overall_hits::total 9972598 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1584754 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1584754 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1737731 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1737731 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20393 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20393 # number of LoadLockedReq misses +system.cpu0.dcache.occ_blocks::cpu0.data 505.757504 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987808 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987808 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6350853 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6350853 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3621976 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3621976 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160250 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 160250 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 184435 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 184435 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9972829 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9972829 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9972829 # number of overall hits +system.cpu0.dcache.overall_hits::total 9972829 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1585015 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1585015 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1737486 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1737486 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20418 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20418 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2991 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2991 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3322485 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3322485 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3322485 # number of overall misses -system.cpu0.dcache.overall_misses::total 3322485 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34254700500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34254700500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66543857651 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 66543857651 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293744000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 293744000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21938000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 21938000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 100798558151 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 100798558151 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 100798558151 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 100798558151 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935173 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7935173 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359910 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5359910 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180536 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 180536 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187441 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187441 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13295083 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13295083 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13295083 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13295083 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199713 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199713 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324209 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324209 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112958 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112958 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015957 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015957 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249903 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249903 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249903 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249903 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21615.153204 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21615.153204 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38293.531997 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38293.531997 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14404.158290 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14404.158290 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7334.670679 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7334.670679 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30338.303454 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30338.303454 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30338.303454 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2157066 # number of cycles access was blocked +system.cpu0.dcache.demand_misses::cpu0.data 3322501 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3322501 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3322501 # number of overall misses +system.cpu0.dcache.overall_misses::total 3322501 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34267378500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34267378500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 66512674680 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 66512674680 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293615500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 293615500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21928500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 21928500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 100780053180 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 100780053180 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 100780053180 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 100780053180 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7935868 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7935868 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5359462 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5359462 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180668 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 180668 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187426 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187426 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13295330 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13295330 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13295330 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13295330 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199728 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.199728 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324190 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324190 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113014 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113014 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015958 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015958 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249900 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249900 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249900 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249900 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21619.592559 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21619.592559 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38280.984526 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38280.984526 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14380.228230 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14380.228230 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7331.494483 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7331.494483 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30332.587764 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 30332.587764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30332.587764 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 30332.587764 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2151725 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 2274 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48232 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48206 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.722715 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.636041 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 324.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 748565 # number of writebacks -system.cpu0.dcache.writebacks::total 748565 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585493 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 585493 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465453 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1465453 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4489 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4489 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2050946 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2050946 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2050946 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2050946 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999261 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 999261 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272278 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 272278 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15904 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15904 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 748436 # number of writebacks +system.cpu0.dcache.writebacks::total 748436 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 585810 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 585810 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1465270 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1465270 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4533 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4533 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2051080 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2051080 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2051080 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2051080 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 999205 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 999205 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272216 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272216 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15885 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15885 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2991 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2991 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271539 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1271539 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271539 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1271539 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21490960000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21490960000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9698199220 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9698199220 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183494500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183494500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15956000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15956000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31189159220 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31189159220 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31189159220 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31189159220 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454907000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454907000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2130479499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2130479499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3585386499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3585386499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125928 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125928 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050799 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050799 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088093 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088093 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015957 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095640 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095640 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095640 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21506.853565 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21506.853565 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35618.739744 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35618.739744 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.632042 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.632042 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5334.670679 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5334.670679 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24528.668975 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24528.668975 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1271421 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1271421 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1271421 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1271421 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21496696000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21496696000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9690926222 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9690926222 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183269000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183269000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15946500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31187622222 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31187622222 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31187622222 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31187622222 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1452303000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1452303000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128092999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128092999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3580395999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3580395999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125910 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125910 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050792 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050792 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087924 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087924 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015958 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015958 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095629 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095629 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095629 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095629 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21513.799471 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21513.799471 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35600.134533 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35600.134533 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11537.236387 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11537.236387 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5331.494483 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5331.494483 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24529.736588 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24529.736588 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24529.736588 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24529.736588 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1178,35 +1178,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2650086 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2188228 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 78181 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1530727 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 883629 # Number of BTB hits +system.cpu1.branchPred.lookups 2647984 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2186587 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 77884 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1531761 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 883024 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.726100 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 184091 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8336 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 57.647636 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 183996 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8305 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1963408 # DTB read hits -system.cpu1.dtb.read_misses 10761 # DTB read misses -system.cpu1.dtb.read_acv 27 # DTB read access violations -system.cpu1.dtb.read_accesses 325022 # DTB read accesses -system.cpu1.dtb.write_hits 1266270 # DTB write hits -system.cpu1.dtb.write_misses 2185 # DTB write misses +system.cpu1.dtb.read_hits 1962214 # DTB read hits +system.cpu1.dtb.read_misses 10693 # DTB read misses +system.cpu1.dtb.read_acv 25 # DTB read access violations +system.cpu1.dtb.read_accesses 324562 # DTB read accesses +system.cpu1.dtb.write_hits 1265832 # DTB write hits +system.cpu1.dtb.write_misses 2093 # DTB write misses system.cpu1.dtb.write_acv 66 # DTB write access violations -system.cpu1.dtb.write_accesses 133146 # DTB write accesses -system.cpu1.dtb.data_hits 3229678 # DTB hits -system.cpu1.dtb.data_misses 12946 # DTB misses -system.cpu1.dtb.data_acv 93 # DTB access violations -system.cpu1.dtb.data_accesses 458168 # DTB accesses -system.cpu1.itb.fetch_hits 437746 # ITB hits -system.cpu1.itb.fetch_misses 6892 # ITB misses -system.cpu1.itb.fetch_acv 236 # ITB acv -system.cpu1.itb.fetch_accesses 444638 # ITB accesses +system.cpu1.dtb.write_accesses 133005 # DTB write accesses +system.cpu1.dtb.data_hits 3228046 # DTB hits +system.cpu1.dtb.data_misses 12786 # DTB misses +system.cpu1.dtb.data_acv 91 # DTB access violations +system.cpu1.dtb.data_accesses 457567 # DTB accesses +system.cpu1.itb.fetch_hits 437198 # ITB hits +system.cpu1.itb.fetch_misses 6975 # ITB misses +system.cpu1.itb.fetch_acv 228 # ITB acv +system.cpu1.itb.fetch_accesses 444173 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1219,134 +1219,134 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16144974 # number of cpu cycles simulated +system.cpu1.numCycles 16140506 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6121442 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12493756 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2650086 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1067720 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2240899 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 409596 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6344466 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 26232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65860 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 57508 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1513677 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 52961 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 15118787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.826373 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.200485 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 6118318 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12482084 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2647984 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1067020 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2239129 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 408271 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6344159 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26393 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65784 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 57491 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1512128 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 52849 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15112669 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.825935 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199937 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12877888 85.18% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 143885 0.95% 86.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 241695 1.60% 87.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 180531 1.19% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 309762 2.05% 90.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 120449 0.80% 91.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 135595 0.90% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 201831 1.33% 94.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 907151 6.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12873540 85.18% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 143819 0.95% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 241770 1.60% 87.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 180451 1.19% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 309857 2.05% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 119919 0.79% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 135082 0.89% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 201991 1.34% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 906240 6.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 15118787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.164143 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.773848 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6052870 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6602402 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2094481 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 114057 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 254976 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 116126 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7500 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12249807 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22555 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 254976 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6262682 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 497209 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5456490 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1996397 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 651031 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11355545 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 50 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 56660 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 160008 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7474719 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13559101 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13415671 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 143430 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6386740 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1087979 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 456269 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 43986 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2005882 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2076975 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1341554 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 190968 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 103806 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9970569 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 502731 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9700952 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 30075 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1449475 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 723922 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 361264 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 15118787 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.641649 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.316312 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15112669 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164058 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.773339 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6050197 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6601549 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2093593 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 113312 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 254017 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 116024 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7481 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12238533 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22436 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 254017 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6259861 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 497059 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5456265 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1994881 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 650584 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11345893 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 56627 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 159750 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7468114 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13547421 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13404114 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 143307 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6384399 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1083715 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 455985 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 44016 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2004753 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2075172 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1340696 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 190596 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 106471 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9962736 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 502412 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9694977 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 29943 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1444595 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 720781 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 360981 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15112669 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.641513 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.316207 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10852712 71.78% 71.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1956314 12.94% 84.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 839077 5.55% 90.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 560111 3.70% 93.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 472963 3.13% 97.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 218451 1.44% 98.55% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 140254 0.93% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 70720 0.47% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8185 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10849099 71.79% 71.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1954888 12.94% 84.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 839816 5.56% 90.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 558366 3.69% 93.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 473326 3.13% 97.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 218082 1.44% 98.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 140204 0.93% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 70683 0.47% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8205 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 15118787 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15112669 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3675 1.85% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 107078 53.97% 55.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 87636 44.17% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3691 1.86% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 106885 53.95% 55.82% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 87531 44.18% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6050828 62.37% 62.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16408 0.17% 62.58% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6046898 62.37% 62.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16423 0.17% 62.58% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.58% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 10849 0.11% 62.69% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued @@ -1374,353 +1374,353 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2054303 21.18% 83.89% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1289929 13.30% 97.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 273346 2.82% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2053041 21.18% 83.88% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1289229 13.30% 97.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 273248 2.82% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9700952 # Type of FU issued -system.cpu1.iq.rate 0.600865 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 198389 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020450 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 34541883 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11823308 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9430294 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 207272 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 101213 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 98067 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9787736 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 108079 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94689 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9694977 # Type of FU issued +system.cpu1.iq.rate 0.600661 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 198107 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020434 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 34523477 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11810363 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9424990 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 207196 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 101110 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 98065 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9781516 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 108042 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 94596 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 288018 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 887 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1813 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 126704 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 286791 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 870 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1822 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 126158 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 386 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 10289 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.cacheBlocked 10101 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 254976 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 327284 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 41516 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10988492 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 148711 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2076975 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1341554 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 455253 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 34417 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1886 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1813 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 35814 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 100493 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 136307 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9610649 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1981550 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 90303 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 254017 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 327186 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 41525 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10980256 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 148232 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2075172 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1340696 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 454941 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 34335 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2140 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1822 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 35734 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 100242 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 135976 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9604840 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1980291 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 90137 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 515192 # number of nop insts executed -system.cpu1.iew.exec_refs 3256018 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1435370 # Number of branches executed -system.cpu1.iew.exec_stores 1274468 # Number of stores executed -system.cpu1.iew.exec_rate 0.595272 # Inst execution rate -system.cpu1.iew.wb_sent 9557675 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9528361 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4461159 # num instructions producing a value -system.cpu1.iew.wb_consumers 6259469 # num instructions consuming a value +system.cpu1.iew.exec_nop 515108 # number of nop insts executed +system.cpu1.iew.exec_refs 3254225 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1434575 # Number of branches executed +system.cpu1.iew.exec_stores 1273934 # Number of stores executed +system.cpu1.iew.exec_rate 0.595077 # Inst execution rate +system.cpu1.iew.wb_sent 9552134 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9523055 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4457844 # num instructions producing a value +system.cpu1.iew.wb_consumers 6254214 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.590175 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712706 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.590010 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712774 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1504147 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 141467 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 128937 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14863811 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.633307 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.576989 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1499365 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 141431 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 128632 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14858652 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633306 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.577285 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11340708 76.30% 76.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1645490 11.07% 87.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 614395 4.13% 91.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 372484 2.51% 94.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 264045 1.78% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 106401 0.72% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 110365 0.74% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 108140 0.73% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 301783 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11337498 76.30% 76.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1644581 11.07% 87.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 614314 4.13% 91.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 371520 2.50% 94.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 264064 1.78% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 106187 0.71% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 110282 0.74% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 108223 0.73% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 301983 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14863811 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9413351 # Number of instructions committed -system.cpu1.commit.committedOps 9413351 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14858652 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9410077 # Number of instructions committed +system.cpu1.commit.committedOps 9410077 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3003807 # Number of memory references committed -system.cpu1.commit.loads 1788957 # Number of loads committed -system.cpu1.commit.membars 45075 # Number of memory barriers committed -system.cpu1.commit.branches 1347256 # Number of branches committed +system.cpu1.commit.refs 3002919 # Number of memory references committed +system.cpu1.commit.loads 1788381 # Number of loads committed +system.cpu1.commit.membars 45067 # Number of memory barriers committed +system.cpu1.commit.branches 1346773 # Number of branches committed system.cpu1.commit.fp_insts 96765 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8723626 # Number of committed integer instructions. -system.cpu1.commit.function_calls 150668 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 301783 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 8720568 # Number of committed integer instructions. +system.cpu1.commit.function_calls 150616 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 301983 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25388124 # The number of ROB reads -system.cpu1.rob.rob_writes 22088528 # The number of ROB writes -system.cpu1.timesIdled 132804 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1026187 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3782762516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8958605 # Number of Instructions Simulated -system.cpu1.committedOps 8958605 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8958605 # Number of Instructions Simulated -system.cpu1.cpi 1.802175 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.802175 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.554885 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.554885 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12390777 # number of integer regfile reads -system.cpu1.int_regfile_writes 6781957 # number of integer regfile writes -system.cpu1.fp_regfile_reads 53541 # number of floating regfile reads -system.cpu1.fp_regfile_writes 53239 # number of floating regfile writes -system.cpu1.misc_regfile_reads 527070 # number of misc regfile reads -system.cpu1.misc_regfile_writes 221606 # number of misc regfile writes -system.cpu1.icache.replacements 226821 # number of replacements -system.cpu1.icache.tagsinuse 470.843395 # Cycle average of tags in use -system.cpu1.icache.total_refs 1277714 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 227333 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.620451 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 25374737 # The number of ROB reads +system.cpu1.rob.rob_writes 22071443 # The number of ROB writes +system.cpu1.timesIdled 132837 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1027837 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3778857265 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8955466 # Number of Instructions Simulated +system.cpu1.committedOps 8955466 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8955466 # Number of Instructions Simulated +system.cpu1.cpi 1.802308 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.802308 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.554844 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.554844 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12383422 # number of integer regfile reads +system.cpu1.int_regfile_writes 6777735 # number of integer regfile writes +system.cpu1.fp_regfile_reads 53544 # number of floating regfile reads +system.cpu1.fp_regfile_writes 53234 # number of floating regfile writes +system.cpu1.misc_regfile_reads 526951 # number of misc regfile reads +system.cpu1.misc_regfile_writes 221547 # number of misc regfile writes +system.cpu1.icache.replacements 226688 # number of replacements +system.cpu1.icache.tagsinuse 470.806939 # Cycle average of tags in use +system.cpu1.icache.total_refs 1276285 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 227200 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.617452 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 1874198606000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.843395 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919616 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919616 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1277714 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1277714 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1277714 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1277714 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1277714 # number of overall hits -system.cpu1.icache.overall_hits::total 1277714 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 235963 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 235963 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 235963 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 235963 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 235963 # number of overall misses -system.cpu1.icache.overall_misses::total 235963 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3262757999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3262757999 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3262757999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3262757999 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3262757999 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3262757999 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1513677 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1513677 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1513677 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1513677 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1513677 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1513677 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155887 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.155887 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155887 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.155887 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155887 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.155887 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13827.413616 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13827.413616 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13827.413616 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13827.413616 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13827.413616 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 255 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 470.806939 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919545 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919545 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1276285 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1276285 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1276285 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1276285 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1276285 # number of overall hits +system.cpu1.icache.overall_hits::total 1276285 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 235843 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 235843 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 235843 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 235843 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 235843 # number of overall misses +system.cpu1.icache.overall_misses::total 235843 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3268518999 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3268518999 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3268518999 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3268518999 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3268518999 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3268518999 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1512128 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1512128 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1512128 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1512128 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1512128 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1512128 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.155968 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.155968 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.155968 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.155968 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.155968 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.155968 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13858.876452 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13858.876452 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13858.876452 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13858.876452 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13858.876452 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13858.876452 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.153846 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 227395 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 227395 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 227395 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 227395 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 227395 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 227395 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711257499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711257499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711257499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2711257499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711257499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2711257499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150227 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.150227 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150227 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.150227 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11923.118358 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11923.118358 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11923.118358 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8582 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8582 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8582 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8582 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8582 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8582 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 227261 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 227261 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 227261 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 227261 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 227261 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 227261 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2711595499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2711595499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2711595499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2711595499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2711595499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2711595499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.150292 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.150292 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.150292 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.150292 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11931.635868 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11931.635868 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11931.635868 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11931.635868 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11931.635868 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11931.635868 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 108831 # number of replacements -system.cpu1.dcache.tagsinuse 491.507176 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2642897 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 109233 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.195042 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 108752 # number of replacements +system.cpu1.dcache.tagsinuse 491.542258 # Cycle average of tags in use +system.cpu1.dcache.total_refs 2641634 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 109154 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.200982 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 39074075000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 491.507176 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.959975 # 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number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3173212000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7555840185 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7555840185 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56288500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 56288500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22631500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 22631500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10729052185 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10729052185 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10729052185 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10729052185 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1828431 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1828431 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1172976 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1172976 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39385 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 39385 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35760 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 35760 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3001407 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3001407 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3001407 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143053 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.143053 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15164.620480 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15164.620480 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34327.564331 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34327.564331 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10431.523351 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10431.523351 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7193.738080 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7193.738080 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24988.418103 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24988.418103 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24988.418103 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 240297 # number of cycles access was blocked +system.cpu1.dcache.occ_blocks::cpu1.data 491.542258 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.960043 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.960043 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1618348 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1618348 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 952576 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 952576 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33975 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 33975 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32610 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 32610 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2570924 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2570924 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2570924 # number of overall hits +system.cpu1.dcache.overall_hits::total 2570924 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 209179 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 209179 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 220095 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 220095 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5405 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5405 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3147 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3147 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 429274 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 429274 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 429274 # number of overall misses +system.cpu1.dcache.overall_misses::total 429274 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3175995000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3175995000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7543341183 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7543341183 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56499500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 56499500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22652500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22652500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10719336183 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10719336183 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10719336183 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10719336183 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1827527 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1827527 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1172671 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1172671 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39380 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 39380 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35757 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 35757 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3000198 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3000198 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3000198 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3000198 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114460 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114460 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187687 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.187687 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137252 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137252 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.088011 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088011 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143082 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.143082 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143082 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.143082 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15183.144580 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15183.144580 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34273.114714 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34273.114714 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10453.191489 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10453.191489 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7198.125199 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7198.125199 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24970.848882 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24970.848882 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24970.848882 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 24970.848882 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 239004 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3869 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3894 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 62.108297 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 61.377504 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 72108 # number of writebacks -system.cpu1.dcache.writebacks::total 72108 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129790 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 129790 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180827 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 180827 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 598 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 598 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 310617 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 310617 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 310617 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 310617 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79461 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 79461 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39283 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 39283 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4798 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4798 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3146 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3146 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 118744 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 118744 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 118744 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 118744 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 970446000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 970446000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1118523985 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1118523985 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38903500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38903500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16339500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16339500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088969985 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2088969985 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088969985 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2088969985 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30978500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30978500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647630000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647630000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678608500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678608500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043459 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043459 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033490 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033490 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121823 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121823 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039563 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039563 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039563 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12212.859138 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12212.859138 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28473.486877 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28473.486877 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.274281 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.274281 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5193.738080 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5193.738080 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17592.215059 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17592.215059 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 72044 # number of writebacks +system.cpu1.dcache.writebacks::total 72044 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 129793 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 129793 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 180819 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 180819 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 604 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 604 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 310612 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 310612 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 310612 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 310612 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79386 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 79386 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39276 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 39276 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4801 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4801 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3147 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3147 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 118662 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 118662 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 118662 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 118662 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 971821000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 971821000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1116428485 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1116428485 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39070500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39070500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16358500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16358500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2088249485 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2088249485 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2088249485 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2088249485 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30977500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30977500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 647178500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 647178500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 678156000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 678156000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043439 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043439 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033493 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033493 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121915 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121915 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088011 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088011 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039551 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039551 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039551 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039551 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12241.717683 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12241.717683 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28425.208397 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28425.208397 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8137.992085 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8137.992085 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5198.125199 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5198.125199 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17598.300088 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17598.300088 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17598.300088 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17598.300088 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1729,32 +1729,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6548 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 181674 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64152 40.43% 40.43% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 136 0.09% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.21% 41.73% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6549 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 181634 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64148 40.44% 40.44% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.52% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.21% 41.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 194 0.12% 41.86% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92254 58.14% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158662 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63162 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 136 0.11% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.50% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 92227 58.14% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158624 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63158 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.50% 50.80% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 194 0.15% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 62971 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128389 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864385169000 98.14% 98.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63278000 0.00% 98.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 567602000 0.03% 98.17% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 94599000 0.00% 98.18% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34650950500 1.82% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1899761598500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 62964 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128371 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1862438042500 98.14% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62559000 0.00% 98.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 567042000 0.03% 98.17% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 94587500 0.00% 98.17% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 34644439500 1.83% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1897806670500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984567 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682583 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809198 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682707 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809279 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1793,53 +1793,53 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # nu system.cpu0.kern.callpal::swpctx 3469 2.08% 2.26% # number of callpals executed system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151918 91.03% 93.32% # number of callpals executed -system.cpu0.kern.callpal::rdps 6167 3.70% 97.02% # number of callpals executed +system.cpu0.kern.callpal::swpipl 151888 91.03% 93.33% # number of callpals executed +system.cpu0.kern.callpal::rdps 6165 3.69% 97.02% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4490 2.69% 99.72% # number of callpals executed +system.cpu0.kern.callpal::rti 4486 2.69% 99.72% # number of callpals executed system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 166884 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6992 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches +system.cpu0.kern.callpal::total 166848 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1259 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1257 -system.cpu0.kern.mode_good::user 1258 +system.cpu0.kern.mode_good::kernel 1258 +system.cpu0.kern.mode_good::user 1259 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.179777 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.180023 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.304848 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1897853280000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1908310500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.305202 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1895901736500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1904926000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3470 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2463 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 58134 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 18218 36.94% 36.94% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 3.90% 40.84% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2462 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 58111 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18212 36.94% 36.94% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 3.90% 40.85% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 297 0.60% 41.45% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28877 58.55% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 49317 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17831 47.44% 47.44% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.12% 52.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 28864 58.55% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49296 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17825 47.44% 47.44% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 5.12% 52.56% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 297 0.79% 53.35% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17534 46.65% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37587 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874537930000 98.69% 98.69% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532213500 0.03% 98.72% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 134642000 0.01% 98.72% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24250176000 1.28% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1899454961500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978757 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 17528 46.65% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37573 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872585348000 98.69% 98.69% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531683000 0.03% 98.71% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 134630500 0.01% 98.72% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 24248440000 1.28% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1897500101500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978750 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.607196 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.762151 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.607262 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.762192 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1869,30 +1869,30 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # nu system.cpu1.kern.callpal::swpctx 1140 2.22% 2.61% # number of callpals executed system.cpu1.kern.callpal::tbi 6 0.01% 2.62% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.63% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43997 85.81% 88.44% # number of callpals executed -system.cpu1.kern.callpal::rdps 2594 5.06% 93.50% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43980 85.81% 88.44% # number of callpals executed +system.cpu1.kern.callpal::rdps 2592 5.06% 93.50% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.50% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 93.51% # number of callpals executed system.cpu1.kern.callpal::rdusp 1 0.00% 93.51% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 93.52% # number of callpals executed -system.cpu1.kern.callpal::rti 3097 6.04% 99.56% # number of callpals executed +system.cpu1.kern.callpal::rti 3095 6.04% 99.56% # number of callpals executed system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 51275 # number of callpals executed +system.cpu1.kern.callpal::total 51254 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1424 # number of protection mode switches -system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2438 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 709 -system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_switch::user 489 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2436 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 710 +system.cpu1.kern.mode_good::user 489 system.cpu1.kern.mode_good::idle 221 -system.cpu1.kern.mode_switch_good::kernel 0.497893 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.498596 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090648 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.325977 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4822300000 0.25% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 832322500 0.04% 0.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893789827000 99.70% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.090722 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.326512 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4824136000 0.25% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 831285000 0.04% 0.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1891834463500 99.70% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1141 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 856de11b9..af2f9c041 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854307 # Number of seconds simulated -sim_ticks 1854307399500 # Number of ticks simulated -final_tick 1854307399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854310 # Number of seconds simulated +sim_ticks 1854310449000 # Number of ticks simulated +final_tick 1854310449000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106006 # Simulator instruction rate (inst/s) -host_op_rate 106006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3711029376 # Simulator tick rate (ticks/s) -host_mem_usage 333480 # Number of bytes of host memory used -host_seconds 499.67 # Real time elapsed on the host -sim_insts 52968721 # Number of instructions simulated -sim_ops 52968721 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 963456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875584 # Number of bytes read from this memory +host_inst_rate 95500 # Simulator instruction rate (inst/s) +host_op_rate 95500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3343297346 # Simulator tick rate (ticks/s) +host_mem_usage 333588 # Number of bytes of host memory used +host_seconds 554.64 # Real time elapsed on the host +sim_insts 52967561 # Number of instructions simulated +sim_ops 52967561 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875392 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28491392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963456 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7501184 # Number of bytes written to this memory -system.physmem.bytes_written::total 7501184 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15054 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388681 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28492160 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7502272 # Number of bytes written to this memory +system.physmem.bytes_written::total 7502272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388678 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445178 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117206 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117206 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 519577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13415027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15364978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 519577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 519577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4045275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4045275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 519577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13415027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19410253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445178 # Total number of read requests seen -system.physmem.writeReqs 117206 # Total number of write requests seen -system.physmem.cpureqs 565467 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28491392 # Total number of bytes read from memory -system.physmem.bytesWritten 7501184 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28491392 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7501184 # bytesWritten derated as per pkt->getSize() +system.physmem.num_reads::total 445190 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117223 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117223 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13414901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430371 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15365367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520094 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520094 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4045855 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045855 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4045855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13414901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19411222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445190 # Total number of read requests seen +system.physmem.writeReqs 117223 # Total number of write requests seen +system.physmem.cpureqs 562598 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28492160 # Total number of bytes read from memory +system.physmem.bytesWritten 7502272 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28492160 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7502272 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 59 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27748 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27561 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28015 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27749 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27564 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 27303 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27981 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28083 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27812 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27967 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27785 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27788 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28082 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27814 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27796 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 27708 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7541 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7132 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 7542 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7135 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 6966 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7434 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7507 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7202 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7347 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7431 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7363 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7509 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7240 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7384 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7205 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7186 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2907 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854301986000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854305000000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445178 # Categorize read packet sizes +system.physmem.readPktSize::6 445190 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117206 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2704 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117223 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2695 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1417 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 762 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -128,68 +128,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.totQLat 7499469250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15210035500 # Sum of mem lat for all requests -system.physmem.totBusLat 2225595000 # Total cycles spent in databus access -system.physmem.totBankLat 5484971250 # Total cycles spent in bank access -system.physmem.avgQLat 16848.23 # Average queueing delay per request -system.physmem.avgBankLat 12322.48 # Average bank access latency per request +system.physmem.wrQLenPdf::21 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see +system.physmem.totQLat 7465727500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15177783750 # Sum of mem lat for all requests +system.physmem.totBusLat 2225655000 # Total cycles spent in databus access +system.physmem.totBankLat 5486401250 # Total cycles spent in bank access +system.physmem.avgQLat 16771.98 # Average queueing delay per request +system.physmem.avgBankLat 12325.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34170.72 # Average memory access latency -system.physmem.avgRdBW 15.36 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 34097.34 # Average memory access latency +system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.36 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.44 # Average write queue length over time -system.physmem.readRowHits 417746 # Number of row buffer hits during reads -system.physmem.writeRowHits 91351 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.85 # Row buffer hit rate for reads +system.physmem.avgWrQLen 14.50 # Average write queue length over time +system.physmem.readRowHits 417731 # Number of row buffer hits during reads +system.physmem.writeRowHits 91366 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate 77.94 # Row buffer hit rate for writes -system.physmem.avgGap 3297216.82 # Average gap between requests +system.physmem.avgGap 3297052.17 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265036 # Cycle average of tags in use +system.iocache.tagsinuse 1.265060 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1704474218000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265036 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 1.265060 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10707310806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10707310806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10728238804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10728238804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10728238804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10728238804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10634243420 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10634243420 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10655171418 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10655171418 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10655171418 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10655171418 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -224,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 257684.607384 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 257684.607384 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 257117.766423 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 257117.766423 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 257117.766423 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 287181 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255926.150847 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 255926.150847 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255366.600791 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255366.600791 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255366.600791 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255366.600791 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 283342 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27254 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27068 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.537206 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.467785 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8545305081 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8545305081 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8557236330 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8557236330 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8557236330 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8557236330 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472243194 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8472243194 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8484174443 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8484174443 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8484174443 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8484174443 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205653.279770 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 205653.279770 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205086.550749 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 205086.550749 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203894.955574 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203894.955574 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203335.516908 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203335.516908 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203335.516908 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203335.516908 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -285,35 +285,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13852347 # Number of BP lookups -system.cpu.branchPred.condPredicted 11625691 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399405 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9419832 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5813293 # Number of BTB hits +system.cpu.branchPred.lookups 13849744 # Number of BP lookups +system.cpu.branchPred.condPredicted 11622401 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399564 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9420297 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5813323 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.713341 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 901451 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38715 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.710613 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 901783 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38632 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9912757 # DTB read hits -system.cpu.dtb.read_misses 41466 # DTB read misses -system.cpu.dtb.read_acv 543 # DTB read access violations -system.cpu.dtb.read_accesses 941271 # DTB read accesses -system.cpu.dtb.write_hits 6601987 # DTB write hits -system.cpu.dtb.write_misses 10361 # DTB write misses -system.cpu.dtb.write_acv 401 # DTB write access violations -system.cpu.dtb.write_accesses 337783 # DTB write accesses -system.cpu.dtb.data_hits 16514744 # DTB hits -system.cpu.dtb.data_misses 51827 # DTB misses -system.cpu.dtb.data_acv 944 # DTB access violations -system.cpu.dtb.data_accesses 1279054 # DTB accesses -system.cpu.itb.fetch_hits 1307981 # ITB hits -system.cpu.itb.fetch_misses 36519 # ITB misses -system.cpu.itb.fetch_acv 1105 # ITB acv -system.cpu.itb.fetch_accesses 1344500 # ITB accesses +system.cpu.dtb.read_hits 9912266 # DTB read hits +system.cpu.dtb.read_misses 41544 # DTB read misses +system.cpu.dtb.read_acv 542 # DTB read access violations +system.cpu.dtb.read_accesses 940163 # DTB read accesses +system.cpu.dtb.write_hits 6601788 # DTB write hits +system.cpu.dtb.write_misses 10570 # DTB write misses +system.cpu.dtb.write_acv 410 # DTB write access violations +system.cpu.dtb.write_accesses 337668 # DTB write accesses +system.cpu.dtb.data_hits 16514054 # DTB hits +system.cpu.dtb.data_misses 52114 # DTB misses +system.cpu.dtb.data_acv 952 # DTB access violations +system.cpu.dtb.data_accesses 1277831 # DTB accesses +system.cpu.itb.fetch_hits 1306011 # ITB hits +system.cpu.itb.fetch_misses 36868 # ITB misses +system.cpu.itb.fetch_acv 1103 # ITB acv +system.cpu.itb.fetch_accesses 1342879 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,133 +326,133 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 108624305 # number of cpu cycles simulated +system.cpu.numCycles 108629038 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28031603 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70677368 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13852347 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6714744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13246931 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1983028 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37386086 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253691 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 294769 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 735 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8549977 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80529349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877660 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.221433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28026689 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70680176 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13849744 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6715106 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13246427 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1984359 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37388108 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32353 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254081 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 294447 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 699 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8549154 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266665 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80527554 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221537 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67282418 83.55% 83.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 855134 1.06% 84.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1701405 2.11% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 823363 1.02% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2750758 3.42% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 561116 0.70% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645464 0.80% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009589 1.25% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4900102 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67281127 83.55% 83.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 855303 1.06% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1700571 2.11% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 822573 1.02% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2750497 3.42% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561265 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645561 0.80% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1010923 1.26% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4899734 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80529349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127525 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.650659 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29153342 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37060255 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12110722 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963448 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1241581 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 585928 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42780 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69380340 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129844 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1241581 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30275533 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13620847 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19786861 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11346001 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4258524 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65625141 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6921 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 508210 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1478954 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43830191 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79653139 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79174156 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 478983 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38170900 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5659283 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1683041 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240056 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12113189 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10427468 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6890622 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1312006 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 847421 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58167835 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2052016 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56809344 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 88346 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6890448 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3503635 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1391090 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80529349 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705449 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.366907 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80527554 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127496 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.650656 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29153725 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37057832 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12110647 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962931 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1242418 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586230 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42729 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69379302 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129899 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1242418 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30276016 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13626490 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19778343 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11345486 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4258799 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65628358 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6970 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 508418 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1479478 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43831634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79654682 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79176161 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 478521 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38170118 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5661508 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682525 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240085 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12113982 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10427074 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6890989 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1312659 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 851378 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58169067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2051551 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56810875 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 88738 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6892578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3503311 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1390624 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80527554 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.366898 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55889300 69.40% 69.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10803861 13.42% 82.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5162711 6.41% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3375118 4.19% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2651639 3.29% 96.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461034 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 755339 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331829 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 98518 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55885936 69.40% 69.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10804988 13.42% 82.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5163321 6.41% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3374568 4.19% 93.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2652291 3.29% 96.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461239 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 754842 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331822 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 98547 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80529349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80527554 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91375 11.51% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373733 47.09% 58.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 328605 41.40% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91181 11.49% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373750 47.11% 58.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 328508 41.40% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38736276 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38738406 68.19% 68.20% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 61707 0.11% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued @@ -481,114 +481,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10345170 18.21% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6680665 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948997 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10344574 18.21% 86.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6680654 11.76% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949005 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56809344 # Type of FU issued -system.cpu.iq.rate 0.522989 # Inst issue rate -system.cpu.iq.fu_busy_cnt 793713 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013972 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194336981 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66788043 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55575971 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693114 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336007 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327916 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57233562 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362209 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 600992 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56810875 # Type of FU issued +system.cpu.iq.rate 0.522981 # Inst issue rate +system.cpu.iq.fu_busy_cnt 793439 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013966 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194338715 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66791274 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55577661 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692765 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 335658 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327829 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57234972 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362056 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 601138 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1337423 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4170 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 513944 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1337046 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4207 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14068 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 514312 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17964 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 173464 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17961 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 173725 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1241581 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9950428 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684284 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63748308 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 674797 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10427468 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6890622 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1807435 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512768 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18119 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 203235 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412070 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 615305 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56339118 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9982368 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 470225 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1242418 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9954083 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684701 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63749782 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 676077 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10427074 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6890989 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1807007 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18311 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14068 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 203273 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412234 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615507 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56340822 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9981988 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 470052 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3528457 # number of nop insts executed -system.cpu.iew.exec_refs 16609952 # number of memory reference insts executed -system.cpu.iew.exec_branches 8925181 # Number of branches executed -system.cpu.iew.exec_stores 6627584 # Number of stores executed -system.cpu.iew.exec_rate 0.518660 # Inst execution rate -system.cpu.iew.wb_sent 56017641 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55903887 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27773544 # num instructions producing a value -system.cpu.iew.wb_consumers 37603829 # num instructions consuming a value +system.cpu.iew.exec_nop 3529164 # number of nop insts executed +system.cpu.iew.exec_refs 16609586 # number of memory reference insts executed +system.cpu.iew.exec_branches 8925674 # Number of branches executed +system.cpu.iew.exec_stores 6627598 # Number of stores executed +system.cpu.iew.exec_rate 0.518653 # Inst execution rate +system.cpu.iew.wb_sent 56019458 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55905490 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27772636 # num instructions producing a value +system.cpu.iew.wb_consumers 37602554 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.514654 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738583 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514646 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738584 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7472187 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660926 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568042 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79287768 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.708292 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.638038 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7474791 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660927 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 568232 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79285136 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.708301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.637990 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58526272 73.82% 73.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8600403 10.85% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4599837 5.80% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2533746 3.20% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1516837 1.91% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 606860 0.77% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 524643 0.66% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 525259 0.66% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1853911 2.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58523209 73.81% 73.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8600768 10.85% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4599944 5.80% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2533685 3.20% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1517149 1.91% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 606925 0.77% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 524667 0.66% 97.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 525488 0.66% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1853301 2.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79287768 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56158922 # Number of instructions committed -system.cpu.commit.committedOps 56158922 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79285136 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56157758 # Number of instructions committed +system.cpu.commit.committedOps 56157758 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15466723 # Number of memory references committed -system.cpu.commit.loads 9090045 # Number of loads committed +system.cpu.commit.refs 15466705 # Number of memory references committed +system.cpu.commit.loads 9090028 # Number of loads committed system.cpu.commit.membars 226335 # Number of memory barriers committed -system.cpu.commit.branches 8439344 # Number of branches committed +system.cpu.commit.branches 8438960 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52009184 # Number of committed integer instructions. -system.cpu.commit.function_calls 740395 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1853911 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52008025 # Number of committed integer instructions. +system.cpu.commit.function_calls 740393 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1853301 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140815408 # The number of ROB reads -system.cpu.rob.rob_writes 128505533 # The number of ROB writes -system.cpu.timesIdled 1178112 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28094956 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599984053 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52968721 # Number of Instructions Simulated -system.cpu.committedOps 52968721 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52968721 # Number of Instructions Simulated -system.cpu.cpi 2.050725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.050725 # CPI: Total CPI of All Threads -system.cpu.ipc 0.487632 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.487632 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73881531 # number of integer regfile reads -system.cpu.int_regfile_writes 40312822 # number of integer regfile writes -system.cpu.fp_regfile_reads 166061 # number of floating regfile reads -system.cpu.fp_regfile_writes 167429 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987886 # number of misc regfile reads -system.cpu.misc_regfile_writes 938918 # number of misc regfile writes +system.cpu.rob.rob_reads 140814788 # The number of ROB reads +system.cpu.rob.rob_writes 128509305 # The number of ROB writes +system.cpu.timesIdled 1177982 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28101484 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599985419 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52967561 # Number of Instructions Simulated +system.cpu.committedOps 52967561 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52967561 # Number of Instructions Simulated +system.cpu.cpi 2.050860 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.050860 # CPI: Total CPI of All Threads +system.cpu.ipc 0.487600 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.487600 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73882509 # number of integer regfile reads +system.cpu.int_regfile_writes 40314112 # number of integer regfile writes +system.cpu.fp_regfile_reads 165977 # number of floating regfile reads +system.cpu.fp_regfile_writes 167436 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987247 # number of misc regfile reads +system.cpu.misc_regfile_writes 938923 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -620,197 +620,193 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1008795 # number of replacements -system.cpu.icache.tagsinuse 510.288576 # Cycle average of tags in use -system.cpu.icache.total_refs 7484836 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1009303 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.415846 # Average number of references to valid blocks. +system.cpu.icache.replacements 1008504 # number of replacements +system.cpu.icache.tagsinuse 510.288693 # Cycle average of tags in use +system.cpu.icache.total_refs 7484267 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1009012 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.417421 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 20267575000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.288576 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7484837 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7484837 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7484837 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7484837 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7484837 # number of overall hits -system.cpu.icache.overall_hits::total 7484837 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065140 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065140 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065140 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065140 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065140 # number of overall misses -system.cpu.icache.overall_misses::total 1065140 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14678664495 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14678664495 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14678664495 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14678664495 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14678664495 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14678664495 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8549977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8549977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8549977 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8549977 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8549977 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8549977 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124578 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13780.971980 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13780.971980 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13780.971980 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13780.971980 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13780.971980 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7122 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.288693 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996658 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996658 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7484268 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7484268 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7484268 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7484268 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7484268 # number of overall hits +system.cpu.icache.overall_hits::total 7484268 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1064885 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064885 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1064885 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064885 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1064885 # number of overall misses +system.cpu.icache.overall_misses::total 1064885 # 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miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383718 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383718 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014935 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277737 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.167711 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014935 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277737 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.167711 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.652246 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51029.775702 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -819,80 +815,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75694 # number of writebacks -system.cpu.l2cache.writebacks::total 75694 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75711 # number of writebacks +system.cpu.l2cache.writebacks::total 75711 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 547534 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 547534 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6209572959 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6209572959 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 851622750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14804557960 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15656180710 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 851622750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14804557960 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15656180710 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333813500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333813500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882743500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882743500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216557000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216557000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248784 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136896 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.167687 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014915 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277743 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.167687 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56567.436068 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31394.338420 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32706.463148 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14039.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14039.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15070 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273774 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288844 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 37 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115394 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115394 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15070 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404238 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15070 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404238 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 848510264 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8602226741 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9450737005 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 527532 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 527532 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6229012981 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6229012981 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 848510264 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14831239722 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15679749986 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 848510264 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14831239722 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15679749986 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333826500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333826500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882595500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882595500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216422000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216422000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014934 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248776 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136919 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.606557 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.606557 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383718 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383718 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014934 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277737 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167711 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014934 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277737 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167711 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56304.596151 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31420.904618 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.173689 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14257.621622 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14257.621622 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53811.455947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53811.455947 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56567.436068 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38041.364853 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38731.351871 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53980.388764 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53980.388764 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56304.596151 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38110.121392 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38788.411743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56304.596151 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38110.121392 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38788.411743 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -900,161 +896,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1400597 # number of replacements +system.cpu.dcache.replacements 1400618 # number of replacements system.cpu.dcache.tagsinuse 511.995158 # Cycle average of tags in use -system.cpu.dcache.total_refs 11804639 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401109 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.425211 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 11803573 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401130 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.424324 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.995158 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7199170 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7199170 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203355 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186385 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186385 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7198104 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7198104 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203343 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203343 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186395 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186395 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 215505 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 215505 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11402525 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11402525 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11402525 # number of overall hits -system.cpu.dcache.overall_hits::total 11402525 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1802469 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1802469 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1943114 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1943114 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22653 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22653 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 11401447 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11401447 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11401447 # number of overall hits +system.cpu.dcache.overall_hits::total 11401447 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1802656 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1802656 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1943125 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1943125 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22671 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22671 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3745583 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3745583 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3745583 # number of overall misses -system.cpu.dcache.overall_misses::total 3745583 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33840497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33840497500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64776324525 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64776324525 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306197000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 306197000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 76500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 76500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 98616822025 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 98616822025 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 98616822025 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 98616822025 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9001639 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9001639 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6146469 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6146469 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209038 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3745781 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3745781 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3745781 # number of overall misses +system.cpu.dcache.overall_misses::total 3745781 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33855022500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33855022500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64910918483 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64910918483 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306639500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 306639500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 64000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 64000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 98765940983 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98765940983 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 98765940983 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98765940983 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9000760 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9000760 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146468 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209066 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209066 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 215509 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 215509 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15148108 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15148108 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15148108 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15148108 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200238 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200238 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316135 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316135 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108368 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108368 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 15147228 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15147228 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15147228 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15147228 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200278 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200278 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316137 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316137 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108439 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108439 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000019 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000019 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247264 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247264 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247264 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247264 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18774.524000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18774.524000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33336.348009 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33336.348009 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13516.841037 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13516.841037 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19125 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19125 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26328.831059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26328.831059 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26328.831059 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2181836 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.247292 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247292 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247292 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247292 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18780.633965 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18780.633965 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33405.426045 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33405.426045 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13525.627454 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13525.627454 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26367.249175 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26367.249175 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26367.249175 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26367.249175 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2192171 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 774 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95774 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95789 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.781089 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.885415 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 129 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840320 # number of writebacks -system.cpu.dcache.writebacks::total 840320 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718906 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 718906 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642971 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642971 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5109 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5109 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2361877 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2361877 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2361877 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2361877 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083563 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083563 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300143 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300143 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17544 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17544 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840363 # number of writebacks +system.cpu.dcache.writebacks::total 840363 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719064 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 719064 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642999 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642999 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5119 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5119 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2362063 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2362063 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2362063 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2362063 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083592 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083592 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300126 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300126 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17552 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17552 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383706 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383706 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383706 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383706 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21325000500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21325000500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9835893766 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9835893766 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200292500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200292500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 68500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 68500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31160894266 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31160894266 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31160894266 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31160894266 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423890500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423890500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997911498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997911498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421801998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421801998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120374 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120374 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048832 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048832 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083927 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383718 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383718 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383718 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383718 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21332679000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21332679000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9855100772 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9855100772 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200264000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200264000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 56000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 56000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31187779772 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31187779772 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31187779772 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31187779772 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423903500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423903500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997763498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997763498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421666998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421666998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120389 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120389 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048829 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048829 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083954 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083954 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091345 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091345 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091345 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19680.443592 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19680.443592 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32770.691857 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32770.691857 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11416.581167 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11416.581167 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17125 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17125 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22519.880861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22519.880861 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091351 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091351 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091351 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091351 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19687.003042 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19687.003042 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32836.544558 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32836.544558 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11409.753874 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11409.753874 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22539.115464 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22539.115464 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22539.115464 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22539.115464 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1064,27 +1060,27 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211000 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105560 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182231 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818335798500 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63864000 0.00% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 549180000 0.03% 98.09% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35357724000 1.91% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854306566500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1818337876500 98.06% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63843000 0.00% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 549015500 0.03% 98.09% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35358867000 1.91% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854309602000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694335 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815438 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1123,7 +1119,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175116 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1132,20 +1128,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191959 # number of callpals executed +system.cpu.kern.callpal::total 191960 # number of callpals executed system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326723 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29457551500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2704315000 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822144692000 98.27% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394549 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29457658500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2706866000 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822145069500 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 1f0f241e7..65a9d1fb5 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.841686 # Nu sim_ticks 1841685557500 # Number of ticks simulated final_tick 1841685557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 244491 # Simulator instruction rate (inst/s) -host_op_rate 244491 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6478446279 # Simulator tick rate (ticks/s) -host_mem_usage 315916 # Number of bytes of host memory used -host_seconds 284.28 # Real time elapsed on the host +host_inst_rate 257826 # Simulator instruction rate (inst/s) +host_op_rate 257826 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6831790357 # Simulator tick rate (ticks/s) +host_mem_usage 316032 # Number of bytes of host memory used +host_seconds 269.58 # Real time elapsed on the host sim_insts 69503534 # Number of instructions simulated sim_ops 69503534 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 474240 # Number of bytes read from this memory @@ -60,7 +60,7 @@ system.physmem.bw_total::cpu2.data 1468811 # To system.physmem.bw_total::total 19501926 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 109963 # Total number of read requests seen system.physmem.writeReqs 45515 # Total number of write requests seen -system.physmem.cpureqs 155620 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 155519 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 7037632 # Total number of bytes read from memory system.physmem.bytesWritten 2912960 # Total number of bytes written to memory system.physmem.bytesConsumedRd 7037632 # bytesRead derated as per pkt->getSize() @@ -100,7 +100,7 @@ system.physmem.perBankWrReqs::13 2879 # Tr system.physmem.perBankWrReqs::14 2851 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 2768 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 102 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry system.physmem.totGap 1840673470000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -180,14 +180,14 @@ system.physmem.wrQLenPdf::28 8 # Wh system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.totQLat 2376401250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4386835000 # Sum of mem lat for all requests +system.physmem.totQLat 2376402250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4386836000 # Sum of mem lat for all requests system.physmem.totBusLat 549785000 # Total cycles spent in databus access system.physmem.totBankLat 1460648750 # Total cycles spent in bank access -system.physmem.avgQLat 21612.10 # Average queueing delay per request +system.physmem.avgQLat 21612.11 # Average queueing delay per request system.physmem.avgBankLat 13283.82 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39895.91 # Average memory access latency +system.physmem.avgMemAccLat 39895.92 # Average memory access latency system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s @@ -512,12 +512,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4305588904 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4305588904 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4314766902 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4314766902 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4314766902 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4314766902 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4305944082 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4305944082 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4315122080 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4315122080 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4315122080 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4315122080 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -536,12 +536,12 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103619.293993 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 103619.293993 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 103409.632163 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 103409.632163 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 103409.632163 # average overall miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103627.841789 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 103627.841789 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 103418.144518 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 103418.144518 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 103418.144518 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 103418.144518 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 116041 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11151 # number of cycles access was blocked @@ -562,12 +562,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 16837 system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433126461 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3433126461 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3438715710 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3438715710 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3438715710 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3438715710 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3433481639 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3433481639 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3439070888 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3439070888 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3439070888 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3439070888 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses @@ -578,12 +578,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204742.751729 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204742.751729 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204235.654214 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 204235.654214 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204763.933624 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204763.933624 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204256.749302 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204256.749302 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204256.749302 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204256.749302 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 6f639a911..5aca0e128 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533144 # Number of seconds simulated -sim_ticks 2533143973500 # Number of ticks simulated -final_tick 2533143973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533141 # Number of seconds simulated +sim_ticks 2533140518500 # Number of ticks simulated +final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55009 # Simulator instruction rate (inst/s) -host_op_rate 70781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2310577470 # Simulator tick rate (ticks/s) -host_mem_usage 405260 # Number of bytes of host memory used -host_seconds 1096.33 # Real time elapsed on the host -sim_insts 60307579 # Number of instructions simulated -sim_ops 77599125 # Number of ops (including micro ops) simulated +host_inst_rate 42664 # Simulator instruction rate (inst/s) +host_op_rate 54897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1792038006 # Simulator tick rate (ticks/s) +host_mem_usage 435912 # Number of bytes of host memory used +host_seconds 1413.55 # Real time elapsed on the host +sim_insts 60307702 # Number of instructions simulated +sim_ops 77599241 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory -system.physmem.bytes_read::total 129430480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798408 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096817 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59099 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813117 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683783 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096817 # Total number of read requests seen -system.physmem.writeReqs 813117 # Total number of write requests seen -system.physmem.cpureqs 218351 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966196288 # Total number of bytes read from memory -system.physmem.bytesWritten 52039488 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129430480 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943948 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943386 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943985 # Track reads on a per bank basis +system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096807 # Total number of read requests seen +system.physmem.writeReqs 813124 # Total number of write requests seen +system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195648 # Total number of bytes read from memory +system.physmem.bytesWritten 52039936 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50900 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533142848500 # Total gap between requests +system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533139407500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154573 # Categorize read packet sizes +system.physmem.readPktSize::6 154563 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59099 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108698 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10857 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59106 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16749 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12584 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -139,15 +139,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2788 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2837 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see @@ -160,25 +160,25 @@ system.physmem.wrQLenPdf::17 35353 # Wh system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32722 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32565 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.totQLat 393251142750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485645877750 # Sum of mem lat for all requests -system.physmem.totBusLat 75482950000 # Total cycles spent in databus access -system.physmem.totBankLat 16911785000 # Total cycles spent in bank access -system.physmem.avgQLat 26049.00 # Average queueing delay per request -system.physmem.avgBankLat 1120.24 # Average bank access latency per request +system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see +system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests +system.physmem.totBusLat 75482565000 # Total cycles spent in databus access +system.physmem.totBankLat 16909241250 # Total cycles spent in bank access +system.physmem.avgQLat 26044.77 # Average queueing delay per request +system.physmem.avgBankLat 1120.08 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32169.24 # Average memory access latency +system.physmem.avgMemAccLat 32164.85 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -186,12 +186,12 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 9.55 # Average write queue length over time -system.physmem.readRowHits 15020272 # Number of row buffer hits during reads -system.physmem.writeRowHits 793090 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159217.68 # Average gap between requests +system.physmem.avgWrQLen 11.32 # Average write queue length over time +system.physmem.readRowHits 15020284 # Number of row buffer hits during reads +system.physmem.writeRowHits 793162 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes +system.physmem.avgGap 159217.50 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -210,20 +210,20 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14675749 # Number of BP lookups -system.cpu.branchPred.condPredicted 11761615 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705306 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9809113 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7951342 # Number of BTB hits +system.cpu.branchPred.lookups 14656582 # Number of BP lookups +system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.060765 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398937 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987411 # DTB read hits +system.cpu.checker.dtb.read_hits 14987438 # DTB read hits system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11227746 # DTB write hits +system.cpu.checker.dtb.write_hits 11227743 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -234,13 +234,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994713 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229935 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994740 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229932 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215157 # DTB hits +system.cpu.checker.dtb.hits 26215181 # DTB hits system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26224648 # DTB accesses -system.cpu.checker.itb.inst_hits 61481576 # ITB inst hits +system.cpu.checker.dtb.accesses 26224672 # DTB accesses +system.cpu.checker.itb.inst_hits 61481703 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -257,36 +257,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486047 # ITB inst accesses -system.cpu.checker.itb.hits 61481576 # DTB hits +system.cpu.checker.itb.inst_accesses 61486174 # ITB inst accesses +system.cpu.checker.itb.hits 61481703 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486047 # DTB accesses -system.cpu.checker.numCycles 77884929 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486174 # DTB accesses +system.cpu.checker.numCycles 77885049 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51399217 # DTB read hits -system.cpu.dtb.read_misses 64403 # DTB read misses -system.cpu.dtb.write_hits 11701345 # DTB write hits -system.cpu.dtb.write_misses 15902 # DTB write misses +system.cpu.dtb.read_hits 51396633 # DTB read hits +system.cpu.dtb.read_misses 64067 # DTB read misses +system.cpu.dtb.write_hits 11699653 # DTB write hits +system.cpu.dtb.write_misses 15746 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6540 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2566 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 409 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51463620 # DTB read accesses -system.cpu.dtb.write_accesses 11717247 # DTB write accesses +system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51460700 # DTB read accesses +system.cpu.dtb.write_accesses 11715399 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100562 # DTB hits -system.cpu.dtb.misses 80305 # DTB misses -system.cpu.dtb.accesses 63180867 # DTB accesses -system.cpu.itb.inst_hits 12332677 # ITB inst hits -system.cpu.itb.inst_misses 11271 # ITB inst misses +system.cpu.dtb.hits 63096286 # DTB hits +system.cpu.dtb.misses 79813 # DTB misses +system.cpu.dtb.accesses 63176099 # DTB accesses +system.cpu.itb.inst_hits 12325480 # ITB inst hits +system.cpu.itb.inst_misses 11172 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -295,113 +295,113 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4946 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4964 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2981 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12343948 # ITB inst accesses -system.cpu.itb.hits 12332677 # DTB hits -system.cpu.itb.misses 11271 # DTB misses -system.cpu.itb.accesses 12343948 # DTB accesses -system.cpu.numCycles 471840254 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12336652 # ITB inst accesses +system.cpu.itb.hits 12325480 # DTB hits +system.cpu.itb.misses 11172 # DTB misses +system.cpu.itb.accesses 12336652 # DTB accesses +system.cpu.numCycles 471810648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30570540 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96039987 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14675749 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9350279 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21160212 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5300332 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123049 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95587623 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87979 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195754 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12329197 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900896 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5353 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151365911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785063 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130221030 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303083 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712964 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496255 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215475 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108052 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757455 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745629 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8805968 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151365911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203543 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32532272 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95215917 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19186051 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962874 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3468797 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957839 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171569 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112632707 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566700 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3468797 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34474935 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36706470 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52522148 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18150584 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6042977 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106114460 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20538 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4062916 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 612 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110534596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485505463 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485414558 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90905 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32144721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830610 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737120 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12168217 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20326621 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13518825 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1978093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2487494 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97939378 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124329035 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167924 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21751378 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57069924 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501194 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151365911 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821381 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534880 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107121434 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13552589 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7069165 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5942277 3.93% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12602111 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2786608 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1699306 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465403 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127018 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107106602 70.78% 70.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13535056 8.94% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151365911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60927 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available @@ -430,383 +430,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365559 94.64% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412870 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58631029 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93272 0.08% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52917261 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12321634 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124329035 # Type of FU issued -system.cpu.iq.rate 0.263498 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839358 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409088132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121690697 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85968255 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23084 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12548 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132792486 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12241 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623354 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued +system.cpu.iq.rate 0.263438 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4672096 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6462 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1786745 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107738 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893837 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3468797 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27950970 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433267 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100144689 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200366 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20326621 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13518825 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410950 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112625 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3575 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350763 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619825 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121548947 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52086338 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2780088 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221732 # number of nop insts executed -system.cpu.iew.exec_refs 64299340 # number of memory reference insts executed -system.cpu.iew.exec_branches 11561583 # Number of branches executed -system.cpu.iew.exec_stores 12213002 # Number of stores executed -system.cpu.iew.exec_rate 0.257606 # Inst execution rate -system.cpu.iew.wb_sent 120388158 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85978549 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47221894 # num instructions producing a value -system.cpu.iew.wb_consumers 88170402 # num instructions consuming a value +system.cpu.iew.exec_nop 221429 # number of nop insts executed +system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed +system.cpu.iew.exec_branches 11545908 # Number of branches executed +system.cpu.iew.exec_stores 12211356 # Number of stores executed +system.cpu.iew.exec_rate 0.257527 # Inst execution rate +system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47220023 # num instructions producing a value +system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182220 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535575 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21486542 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536246 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147897114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525700 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515001 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120445936 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13320013 9.01% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3904517 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120442 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1947230 1.32% 95.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 967442 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598856 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701557 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2891121 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147897114 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60457960 # Number of instructions committed -system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458083 # Number of instructions committed +system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386605 # Number of memory references committed -system.cpu.commit.loads 15654525 # Number of loads committed -system.cpu.commit.membars 403599 # Number of memory barriers committed -system.cpu.commit.branches 9961316 # Number of branches committed +system.cpu.commit.refs 27386631 # Number of memory references committed +system.cpu.commit.loads 15654552 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961338 # 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Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307579 # Number of Instructions Simulated -system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated -system.cpu.cpi 7.823896 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823896 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550318453 # number of integer regfile reads -system.cpu.int_regfile_writes 88458214 # number of integer regfile writes -system.cpu.fp_regfile_reads 8290 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 30125052 # number of misc regfile reads -system.cpu.misc_regfile_writes 831890 # number of misc regfile writes -system.cpu.icache.replacements 979629 # number of replacements -system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use -system.cpu.icache.total_refs 11269534 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980141 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.497870 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 242306963 # The number of ROB reads +system.cpu.rob.rob_writes 201917005 # The number of ROB writes +system.cpu.timesIdled 1770758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320479438 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594387345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307702 # Number of Instructions Simulated +system.cpu.committedOps 77599241 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated +system.cpu.cpi 7.823390 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823390 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550141266 # number of integer regfile reads +system.cpu.int_regfile_writes 88418140 # number of integer regfile writes +system.cpu.fp_regfile_reads 8398 # number of floating regfile reads +system.cpu.fp_regfile_writes 2928 # number of floating regfile writes +system.cpu.misc_regfile_reads 30126321 # number of misc regfile reads +system.cpu.misc_regfile_writes 831893 # number of misc regfile writes +system.cpu.icache.replacements 979850 # number of replacements +system.cpu.icache.tagsinuse 511.615737 # Cycle average of tags in use +system.cpu.icache.total_refs 11261998 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980362 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.487591 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.615737 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11269534 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11269534 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11269534 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11269534 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11269534 # number of overall hits -system.cpu.icache.overall_hits::total 11269534 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059538 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12329072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12329072 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12329072 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12329072 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12329072 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085938 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085938 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085938 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085938 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085938 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.077515 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.077515 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.077515 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.077515 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4855 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11261998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11261998 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11261998 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11261998 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11261998 # number of overall hits +system.cpu.icache.overall_hits::total 11261998 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059902 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059902 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059902 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059902 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059902 # number of overall misses +system.cpu.icache.overall_misses::total 1059902 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993800493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13993800493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13993800493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13993800493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13993800493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13993800493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12321900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12321900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12321900 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12321900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12321900 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12321900 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086018 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086018 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086018 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086018 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086018 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13202.919226 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13202.919226 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13202.919226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13202.919226 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4527 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 305 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 299 # 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mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079565 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079565 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11607.496864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11607.496864 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64344 # number of replacements -system.cpu.l2cache.tagsinuse 51347.743422 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885451 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129735 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.533094 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498197459500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36929.519444 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.551079 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8159.886035 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6231.786516 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563500 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64334 # number of replacements +system.cpu.l2cache.tagsinuse 51346.876619 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1884630 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129728 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.527550 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498196259500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36934.415864 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.547842 # 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number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193900481784 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193905562614 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026768 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986815 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986815 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # 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Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13754193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13754193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259605 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259605 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243146 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21013798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21013798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21013798 # number of overall hits -system.cpu.dcache.overall_hits::total 21013798 # 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number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24713374 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713374 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713374 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713374 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050865 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050865 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289840 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289840 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052572 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052572 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # 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average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13272.276052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13272.276052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35221.449509 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35221.449509 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13338.916475 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13338.916475 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30864.270185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30864.270185 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29973 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17225 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2670 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.225843 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.353175 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30848.794773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30848.794773 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29383 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15931 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2645 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 250 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.108885 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 63.724000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742502511 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742502511 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138335511 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138335511 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047441 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047441 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12989830414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12989830414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12989830414 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12989830414 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36713909190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36713909190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219109545190 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219109545190 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047374 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025688 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025688 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12471.232437 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12471.232437 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32888.297655 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32888.297655 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.940867 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.940867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025683 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025683 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.038230 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.038230 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32863.891589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32863.891589 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11566.822930 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11566.822930 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1103,16 +1103,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610797601 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229610797601 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 5e12f3369..ee857cd58 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102940 # Number of seconds simulated -sim_ticks 1102940172000 # Number of ticks simulated -final_tick 1102940172000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102937 # Number of seconds simulated +sim_ticks 1102936899000 # Number of ticks simulated +final_tick 1102936899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65652 # Simulator instruction rate (inst/s) -host_op_rate 84510 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1175755462 # Simulator tick rate (ticks/s) -host_mem_usage 411412 # Number of bytes of host memory used -host_seconds 938.07 # Real time elapsed on the host -sim_insts 61586245 # Number of instructions simulated -sim_ops 79276446 # Number of ops (including micro ops) simulated +host_inst_rate 56405 # Simulator instruction rate (inst/s) +host_op_rate 72609 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010130266 # Simulator tick rate (ticks/s) +host_mem_usage 440004 # Number of bytes of host memory used +host_seconds 1091.88 # Real time elapsed on the host +sim_insts 61587196 # Number of instructions simulated +sim_ops 79280303 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4368500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 408960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4359540 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory -system.physmem.bytes_read::total 59192100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4269568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 406528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5228208 # Number of bytes read from this memory +system.physmem.bytes_read::total 59164324 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 408960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4242368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296912 # Number of bytes written to this memory +system.physmem.bytes_written::total 7269712 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6398 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6390 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68190 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257967 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66712 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6352 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81717 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257533 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66287 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823548 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44208004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3960777 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823123 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44208136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952665 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4757770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53667553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367773 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3871079 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4740260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53642528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739379 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3846429 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6615873 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3871079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44208004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3976190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6591231 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3846429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44208136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3968078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7487151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60283426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257967 # Total number of read requests seen -system.physmem.writeReqs 823548 # Total number of write requests seen -system.physmem.cpureqs 242288 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400509888 # Total number of bytes read from memory -system.physmem.bytesWritten 52707072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59192100 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296912 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12562 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391216 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391542 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390512 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391259 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51565 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51007 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51680 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52040 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51500 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51252 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 368587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7469649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60233760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257533 # Total number of read requests seen +system.physmem.writeReqs 823123 # Total number of write requests seen +system.physmem.cpureqs 241438 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400482112 # Total number of bytes read from memory +system.physmem.bytesWritten 52679872 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59164324 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7269712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12571 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390831 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391593 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391498 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390850 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390450 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391246 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51251 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51666 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51720 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52026 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51302 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51417 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51807 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51192 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51881 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102939019000 # Total gap between requests +system.physmem.numWrRetry 32625 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102935703000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163014 # Categorize read packet sizes +system.physmem.readPktSize::6 162580 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66712 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 493693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66287 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 494185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 392337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1085468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1097761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1063978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 15313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 7884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -160,59 +160,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see -system.physmem.totQLat 199192058500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239013617250 # Sum of mem lat for all requests -system.physmem.totBusLat 31289230000 # Total cycles spent in databus access -system.physmem.totBankLat 8532328750 # Total cycles spent in bank access -system.physmem.avgQLat 31830.77 # Average queueing delay per request -system.physmem.avgBankLat 1363.46 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32641 # What write queue length does an incoming req see +system.physmem.totQLat 199281441500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239111429000 # Sum of mem lat for all requests +system.physmem.totBusLat 31287030000 # Total cycles spent in databus access +system.physmem.totBankLat 8542957500 # Total cycles spent in bank access +system.physmem.avgQLat 31847.29 # Average queueing delay per request +system.physmem.avgBankLat 1365.26 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38194.23 # Average memory access latency -system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.62 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38212.55 # Average memory access latency +system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.76 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.64 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.59 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 12.05 # Average write queue length over time -system.physmem.readRowHits 6213954 # Number of row buffer hits during reads -system.physmem.writeRowHits 800040 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.59 # Average write queue length over time +system.physmem.readRowHits 6213376 # Number of row buffer hits during reads +system.physmem.writeRowHits 799550 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155749.02 # Average gap between requests +system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes +system.physmem.avgGap 155767.45 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -231,251 +231,251 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72718 # number of replacements -system.l2c.tagsinuse 53743.140165 # Cycle average of tags in use -system.l2c.total_refs 1840331 # Total number of references to valid blocks. -system.l2c.sampled_refs 137862 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.349081 # Average number of references to valid blocks. +system.l2c.replacements 72282 # number of replacements +system.l2c.tagsinuse 53744.299693 # Cycle average of tags in use +system.l2c.total_refs 1841477 # Total number of references to valid blocks. +system.l2c.sampled_refs 137500 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.392560 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39373.587396 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.826422 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 1.187080 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4008.736100 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2822.118244 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.062372 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.921462 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3716.187342 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3805.513745 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600793 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061168 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043062 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39371.893894 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 5.466670 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.665850 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4003.284493 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2820.568488 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.108443 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.919823 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3725.007986 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3804.384047 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600767 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061085 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043038 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000170 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056705 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058068 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820055 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386239 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166660 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30329 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 197820 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403245 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 580806 # number of Writeback hits -system.l2c.Writeback_hits::total 580806 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1235 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1978 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 145 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 346 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48231 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58599 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106830 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386239 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214891 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30329 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5168 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 590386 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256419 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510075 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22141 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4502 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386239 # number of overall hits -system.l2c.overall_hits::cpu0.data 214891 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30329 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5168 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590386 # number of overall hits -system.l2c.overall_hits::cpu1.data 256419 # number of overall hits -system.l2c.overall_hits::total 1510075 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # 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average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37179.775156 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41262.630513 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39418.215750 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -678,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 5998401 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4575821 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294349 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3757481 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2911128 # Number of BTB hits +system.cpu0.branchPred.lookups 6001640 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4577059 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296005 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3758008 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2912273 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.475521 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672992 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28616 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.495125 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673236 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28713 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8907261 # DTB read hits -system.cpu0.dtb.read_misses 28773 # DTB read misses -system.cpu0.dtb.write_hits 5136781 # DTB write hits -system.cpu0.dtb.write_misses 5705 # DTB write misses +system.cpu0.dtb.read_hits 8910999 # DTB read hits +system.cpu0.dtb.read_misses 29151 # DTB read misses +system.cpu0.dtb.write_hits 5140269 # DTB write hits +system.cpu0.dtb.write_misses 5702 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1814 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1035 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 560 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8936034 # DTB read accesses -system.cpu0.dtb.write_accesses 5142486 # DTB write accesses +system.cpu0.dtb.perms_faults 584 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8940150 # DTB read accesses +system.cpu0.dtb.write_accesses 5145971 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14044042 # DTB hits -system.cpu0.dtb.misses 34478 # DTB misses -system.cpu0.dtb.accesses 14078520 # DTB accesses -system.cpu0.itb.inst_hits 4215431 # ITB inst hits -system.cpu0.itb.inst_misses 5154 # ITB inst misses +system.cpu0.dtb.hits 14051268 # DTB hits +system.cpu0.dtb.misses 34853 # DTB misses +system.cpu0.dtb.accesses 14086121 # DTB accesses +system.cpu0.itb.inst_hits 4221147 # ITB inst hits +system.cpu0.itb.inst_misses 5166 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -722,144 +722,144 @@ system.cpu0.itb.flush_entries 1347 # Nu system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4220585 # ITB inst accesses -system.cpu0.itb.hits 4215431 # DTB hits -system.cpu0.itb.misses 5154 # DTB misses -system.cpu0.itb.accesses 4220585 # DTB accesses -system.cpu0.numCycles 67803924 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4226313 # ITB inst accesses +system.cpu0.itb.hits 4221147 # DTB hits +system.cpu0.itb.misses 5166 # DTB misses +system.cpu0.itb.accesses 4226313 # DTB accesses +system.cpu0.numCycles 67826289 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11747073 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32000754 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5998401 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3584120 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7510773 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1450164 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 64498 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20642358 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46878 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85526 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4213800 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157670 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2178 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41143503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385262 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11756286 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32014298 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6001640 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3585509 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7517140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1455004 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 67247 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20650253 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46433 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85685 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 203 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4219566 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157765 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2202 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41172573 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004783 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385116 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33640113 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 564874 1.37% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 815232 1.98% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 675522 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773200 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558709 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669860 1.63% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351529 0.85% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3094464 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33662869 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565639 1.37% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818038 1.99% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 675166 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 774675 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559568 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 667522 1.62% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352154 0.86% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3096942 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41143503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088467 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471960 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12253117 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20585756 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6814381 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512539 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 977710 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 934268 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64694 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39987776 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212486 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 977710 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12820427 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5742393 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12731772 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6709970 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2161231 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38889294 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1829 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 434890 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1234500 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 47 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39244828 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175643455 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175609334 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34121 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30926653 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8318174 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411256 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370334 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5351915 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7647673 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5682766 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124413 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1217910 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36816448 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895564 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37227077 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80165 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6275180 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13166441 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256842 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41143503 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904811 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512506 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41172573 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088485 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12265416 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20593296 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6819123 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 513990 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 980748 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935580 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64947 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40010595 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213478 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 980748 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12833750 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5743138 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12737000 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6715008 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2162929 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38912871 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1796 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435724 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1235455 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39264355 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175753145 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175718969 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34176 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30934227 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8330127 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411039 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370083 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5348370 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7652222 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5686978 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1127413 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1231482 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36837080 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895317 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37247377 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80474 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6286180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13172304 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256448 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41172573 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904665 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512453 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26013518 63.23% 63.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5726772 13.92% 77.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3163675 7.69% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471330 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2096927 5.10% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 946781 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 487184 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184280 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53036 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26032414 63.23% 63.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5734790 13.93% 77.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3160933 7.68% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2474953 6.01% 90.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2097868 5.10% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 946815 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 486964 1.18% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184157 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53679 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41143503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41172573 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25911 2.42% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841841 78.68% 81.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 201703 18.85% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26092 2.44% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 843251 78.76% 81.24% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 200824 18.76% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22320567 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46962 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22332748 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46981 0.13% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued @@ -869,14 +869,14 @@ system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Ty system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued @@ -885,363 +885,367 @@ system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Ty system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9363552 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5443123 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9367267 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5447389 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37227077 # Type of FU issued -system.cpu0.iq.rate 0.549040 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1069907 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028740 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116773591 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43995152 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34325365 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8374 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4656 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38240450 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4385 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307272 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37247377 # Type of FU issued +system.cpu0.iq.rate 0.549158 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070619 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028743 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116844627 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44026356 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34344813 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8420 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4690 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3883 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38261309 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4408 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307850 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372635 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2428 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13158 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 533443 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1374402 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2480 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12973 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 535370 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192715 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5605 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192711 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5613 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 977710 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4125178 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98819 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37830480 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 84891 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7647673 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5682766 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571414 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40435 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2836 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13158 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149420 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117102 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266522 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36852561 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9222790 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 374516 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 980748 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4124012 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98712 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37850539 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85674 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7652222 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5686978 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571475 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40167 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2962 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12973 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149952 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118190 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 268142 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36871873 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9226575 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 375504 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118468 # number of nop insts executed -system.cpu0.iew.exec_refs 14619280 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4853073 # Number of branches executed -system.cpu0.iew.exec_stores 5396490 # Number of stores executed -system.cpu0.iew.exec_rate 0.543517 # Inst execution rate -system.cpu0.iew.wb_sent 36658484 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34329238 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18277167 # num instructions producing a value -system.cpu0.iew.wb_consumers 35166979 # num instructions consuming a value +system.cpu0.iew.exec_nop 118142 # number of nop insts executed +system.cpu0.iew.exec_refs 14626690 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4856874 # Number of branches executed +system.cpu0.iew.exec_stores 5400115 # Number of stores executed +system.cpu0.iew.exec_rate 0.543622 # Inst execution rate +system.cpu0.iew.wb_sent 36677250 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34348696 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18291021 # num instructions producing a value +system.cpu0.iew.wb_consumers 35196356 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506302 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519725 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506422 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519685 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6089898 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638722 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 230765 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40165793 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778810 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740848 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6101158 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638869 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232197 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40191825 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778547 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740754 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28496220 70.95% 70.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5717219 14.23% 85.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1914261 4.77% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974261 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784320 1.95% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 523319 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386116 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 218199 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1151878 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28520633 70.96% 70.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5717076 14.22% 85.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1914444 4.76% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974820 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784169 1.95% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 523265 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386798 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 217938 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1152682 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40165793 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23678008 # Number of instructions committed -system.cpu0.commit.committedOps 31281512 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40191825 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23681661 # Number of instructions committed +system.cpu0.commit.committedOps 31291235 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11424361 # Number of memory references committed -system.cpu0.commit.loads 6275038 # Number of loads committed -system.cpu0.commit.membars 229662 # Number of memory barriers committed -system.cpu0.commit.branches 4244821 # Number of branches committed +system.cpu0.commit.refs 11429428 # Number of memory references committed +system.cpu0.commit.loads 6277820 # Number of loads committed +system.cpu0.commit.membars 229679 # Number of memory barriers committed +system.cpu0.commit.branches 4245347 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27638419 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489334 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1151878 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27647557 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489379 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1152682 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75534199 # The number of ROB reads -system.cpu0.rob.rob_writes 75722713 # The number of ROB writes -system.cpu0.timesIdled 360446 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26660421 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138034694 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23597266 # Number of Instructions Simulated -system.cpu0.committedOps 31200770 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23597266 # Number of Instructions Simulated -system.cpu0.cpi 2.873381 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.873381 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348022 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348022 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171786019 # number of integer regfile reads -system.cpu0.int_regfile_writes 34080976 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3260 # number of floating regfile reads -system.cpu0.fp_regfile_writes 902 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13006141 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451094 # number of misc regfile writes -system.cpu0.icache.replacements 392511 # number of replacements -system.cpu0.icache.tagsinuse 511.076367 # Cycle average of tags in use -system.cpu0.icache.total_refs 3789958 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393023 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.643095 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 75580359 # The number of ROB reads +system.cpu0.rob.rob_writes 75767781 # The number of ROB writes +system.cpu0.timesIdled 360539 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26653716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138005786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23600919 # Number of Instructions Simulated +system.cpu0.committedOps 31210493 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23600919 # Number of Instructions Simulated +system.cpu0.cpi 2.873883 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.873883 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347961 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347961 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171874490 # number of integer regfile reads +system.cpu0.int_regfile_writes 34096600 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads +system.cpu0.fp_regfile_writes 872 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13012666 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451076 # number of misc regfile writes +system.cpu0.icache.replacements 392591 # number of replacements +system.cpu0.icache.tagsinuse 511.076357 # Cycle average of tags in use +system.cpu0.icache.total_refs 3795579 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393103 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.655431 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076367 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.076357 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3789958 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3789958 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3789958 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3789958 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3789958 # number of overall hits -system.cpu0.icache.overall_hits::total 3789958 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423709 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423709 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423709 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423709 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423709 # number of overall misses -system.cpu0.icache.overall_misses::total 423709 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803688497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5803688497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5803688497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5803688497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5803688497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5803688497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213667 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4213667 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4213667 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4213667 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4213667 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4213667 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13697.345341 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13697.345341 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13697.345341 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13697.345341 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2656 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3795579 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3795579 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3795579 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3795579 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3795579 # number of overall hits +system.cpu0.icache.overall_hits::total 3795579 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423854 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423854 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423854 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423854 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423854 # number of overall misses +system.cpu0.icache.overall_misses::total 423854 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5804082997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5804082997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5804082997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5804082997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5804082997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5804082997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4219433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4219433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4219433 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4219433 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4219433 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4219433 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100453 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100453 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100453 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100453 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100453 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100453 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.590239 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13693.590239 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13693.590239 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13693.590239 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2620 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 149 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.825503 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.124183 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30672 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30672 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30672 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30672 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30672 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30672 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393037 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393037 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393037 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393037 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393037 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393037 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4746801497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4746801497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4746801497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4746801497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4746801497 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4746801497 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093277 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093277 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093277 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.238268 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30736 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30736 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30736 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30736 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30736 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30736 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393118 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393118 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393118 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393118 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393118 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393118 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745929997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745929997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745929997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4745929997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745929997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4745929997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7902000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7902000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093168 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093168 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12072.532921 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275921 # number of replacements -system.cpu0.dcache.tagsinuse 460.698692 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9260016 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276433 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.498229 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 276649 # number of replacements +system.cpu0.dcache.tagsinuse 460.596566 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9262154 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 277161 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.417956 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.698692 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.899802 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.899802 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5779987 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5779987 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159663 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159663 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139233 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139233 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137076 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137076 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8939650 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8939650 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8939650 # number of overall hits -system.cpu0.dcache.overall_hits::total 8939650 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392818 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392818 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1582384 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1582384 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8769 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8769 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1975202 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1975202 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1975202 # number of overall misses -system.cpu0.dcache.overall_misses::total 1975202 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5481439500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5481439500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60566359369 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60566359369 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87760500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 87760500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46440000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46440000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66047798869 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66047798869 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66047798869 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66047798869 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172805 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6172805 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4742047 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4742047 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10914852 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10914852 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10914852 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10914852 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063637 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063637 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333692 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333692 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059249 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059249 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051640 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051640 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180965 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180965 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180965 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180965 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.145431 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.145431 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38275.386612 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38275.386612 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10008.039685 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10008.039685 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.864952 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.864952 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33438.503439 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33438.503439 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8565 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5561 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 643 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.320373 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 68.654321 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 460.596566 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899603 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899603 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5782081 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5782081 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3160908 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3160908 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139098 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139098 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137052 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137052 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8942989 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8942989 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8942989 # number of overall hits +system.cpu0.dcache.overall_hits::total 8942989 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 394048 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 394048 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1583429 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1583429 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8774 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8774 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977477 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977477 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977477 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977477 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5492603000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5492603000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60464990363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60464990363 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87990000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 87990000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46572500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46572500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 65957593363 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 65957593363 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 65957593363 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 65957593363 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176129 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6176129 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744337 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744337 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147872 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147872 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144541 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144541 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10920466 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10920466 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10920466 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10920466 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063802 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063802 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333751 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333751 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051812 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051812 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181080 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181080 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181080 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181080 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.918609 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.918609 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38186.107721 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38186.107721 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10028.493276 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10028.493276 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6218.787555 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6218.787555 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33354.417454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33354.417454 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8825 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4351 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 671 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.152012 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 54.387500 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks -system.cpu0.dcache.writebacks::total 256512 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204354 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204354 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452130 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1452130 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 476 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 476 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656484 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1656484 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656484 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1656484 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188464 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188464 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130254 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130254 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8293 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8293 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7464 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7464 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318718 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318718 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378480500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378480500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4031341491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4031341491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65938500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65938500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31512000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31512000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6409821991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6409821991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6409821991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6409821991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514864500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514864500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180302878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180302878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695167378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695167378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030531 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030531 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027468 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027468 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056033 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056033 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051640 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051640 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029200 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029200 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12620.343938 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12620.343938 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30949.847920 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30949.847920 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7951.103340 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7951.103340 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4221.864952 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4221.864952 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 257146 # number of writebacks +system.cpu0.dcache.writebacks::total 257146 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204997 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204997 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453030 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1453030 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 464 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 464 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658027 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1658027 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658027 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1658027 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189051 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189051 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130399 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130399 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8310 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8310 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319450 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319450 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2382504500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2382504500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4025705992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4025705992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66268000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66268000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31600500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31600500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6408210492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6408210492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6408210492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6408210492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514784000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514784000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180269878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180269878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695053878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695053878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030610 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030610 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051798 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051798 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029252 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029252 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12602.443256 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12602.443256 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30872.215216 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30872.215216 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7974.488568 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7974.488568 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4220.715908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4220.715908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1249,38 +1253,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9068423 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7455270 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 408018 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6064102 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5241151 # Number of BTB hits +system.cpu1.branchPred.lookups 9057370 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7441884 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 409640 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6090561 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5229548 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.429137 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772299 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42697 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.863158 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772754 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42888 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42898238 # DTB read hits -system.cpu1.dtb.read_misses 36741 # DTB read misses -system.cpu1.dtb.write_hits 6823025 # DTB write hits -system.cpu1.dtb.write_misses 10725 # DTB write misses +system.cpu1.dtb.read_hits 42905047 # DTB read hits +system.cpu1.dtb.read_misses 36603 # DTB read misses +system.cpu1.dtb.write_hits 6822006 # DTB write hits +system.cpu1.dtb.write_misses 10721 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2008 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2490 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2003 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2568 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 298 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42934979 # DTB read accesses -system.cpu1.dtb.write_accesses 6833750 # DTB write accesses +system.cpu1.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42941650 # DTB read accesses +system.cpu1.dtb.write_accesses 6832727 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49721263 # DTB hits -system.cpu1.dtb.misses 47466 # DTB misses -system.cpu1.dtb.accesses 49768729 # DTB accesses -system.cpu1.itb.inst_hits 8394494 # ITB inst hits -system.cpu1.itb.inst_misses 5446 # ITB inst misses +system.cpu1.dtb.hits 49727053 # DTB hits +system.cpu1.dtb.misses 47324 # DTB misses +system.cpu1.dtb.accesses 49774377 # DTB accesses +system.cpu1.itb.inst_hits 8402267 # ITB inst hits +system.cpu1.itb.inst_misses 5496 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1289,114 +1293,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1530 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1510 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8399940 # ITB inst accesses -system.cpu1.itb.hits 8394494 # DTB hits -system.cpu1.itb.misses 5446 # DTB misses -system.cpu1.itb.accesses 8399940 # DTB accesses -system.cpu1.numCycles 408755802 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8407763 # ITB inst accesses +system.cpu1.itb.hits 8402267 # DTB hits +system.cpu1.itb.misses 5496 # DTB misses +system.cpu1.itb.accesses 8407763 # DTB accesses +system.cpu1.numCycles 408754758 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19793701 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66043012 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9068423 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6013450 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14139093 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3958938 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 65451 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77253219 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41710 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129512 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8392686 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 740378 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2825 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114124947 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700718 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.045131 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19786435 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66033865 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9057370 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6002302 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14145991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3963679 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 66957 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77248735 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42710 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129584 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 102 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8400411 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 741502 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2853 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114126440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700482 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.044104 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99993030 87.62% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796567 0.70% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937489 0.82% 89.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1887963 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1516591 1.33% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 569617 0.50% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2129815 1.87% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410324 0.36% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5883551 5.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99987714 87.61% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 797074 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 939049 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1891067 1.66% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1525429 1.34% 92.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 571908 0.50% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2134670 1.87% 94.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410312 0.36% 94.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5869217 5.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114124947 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022185 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161571 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21308374 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76909285 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12783383 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523008 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2600897 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105255 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98147 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75181804 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327202 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2600897 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22691617 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31944842 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40730815 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11827860 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4328916 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69723383 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18766 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668457 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3086605 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 426 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73713482 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321023926 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 320964994 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58932 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49048009 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24665473 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444684 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387735 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7872422 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13201823 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8142648 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1033883 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1534096 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63487985 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1158001 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89118015 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94635 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16215431 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45695453 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277388 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114124947 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780881 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519165 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114126440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022158 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161549 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21303172 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76905866 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12788673 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523903 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2604826 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105931 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 97877 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75200071 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 325666 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2604826 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22687981 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31933680 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40739903 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11832589 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4327461 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69726432 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18789 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 667798 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3085321 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1194 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73678442 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321083951 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321025301 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58650 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49043171 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24635271 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 445050 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388065 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7869897 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13205633 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8143981 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1031020 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1549372 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63452075 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1154123 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89105675 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94570 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16177961 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45638243 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 273609 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114126440 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780763 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519063 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83732864 73.37% 73.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8404718 7.36% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4298594 3.77% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3768314 3.30% 87.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10582090 9.27% 97.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1967507 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1024622 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 272364 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73874 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83740358 73.38% 73.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8394887 7.36% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4311710 3.78% 84.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3761165 3.30% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10575130 9.27% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1975219 1.73% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1022890 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 270730 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 74351 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114124947 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114126440 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29701 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29540 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 995 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1424,399 +1428,399 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7545557 95.86% 96.25% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 295033 3.75% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7547716 95.90% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 292001 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37610156 42.20% 42.55% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59163 0.07% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43962640 49.33% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7170532 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37588774 42.18% 42.54% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59166 0.07% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43972144 49.35% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7170135 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89118015 # Type of FU issued -system.cpu1.iq.rate 0.218023 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7871289 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088324 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300359292 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80869896 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53629107 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8062 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6802 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96667481 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7826 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342650 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89105675 # Type of FU issued +system.cpu1.iq.rate 0.217993 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7870252 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088325 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300334896 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80792722 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53591705 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14852 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6792 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96654176 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7819 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342901 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3449296 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3766 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17093 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1304806 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3454829 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3906 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17123 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1307403 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31906048 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888017 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31911868 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888624 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2600897 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24182074 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360611 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64750813 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 110749 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13201823 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8142648 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869251 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65576 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3534 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17093 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201242 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155476 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 356718 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86688682 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43267985 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2429333 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2604826 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24177502 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360064 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64710295 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 111591 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13205633 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8143981 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 865041 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65040 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3489 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17123 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 203707 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155314 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 359021 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86656699 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43274731 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2448976 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104827 # number of nop insts executed -system.cpu1.iew.exec_refs 50376799 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6999376 # Number of branches executed -system.cpu1.iew.exec_stores 7108814 # Number of stores executed -system.cpu1.iew.exec_rate 0.212079 # Inst execution rate -system.cpu1.iew.wb_sent 85711710 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53635909 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29908204 # num instructions producing a value -system.cpu1.iew.wb_consumers 53361522 # num instructions consuming a value +system.cpu1.iew.exec_nop 104097 # number of nop insts executed +system.cpu1.iew.exec_refs 50382465 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6984824 # Number of branches executed +system.cpu1.iew.exec_stores 7107734 # Number of stores executed +system.cpu1.iew.exec_rate 0.212002 # Inst execution rate +system.cpu1.iew.wb_sent 85679792 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53598497 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29912489 # num instructions producing a value +system.cpu1.iew.wb_consumers 53377026 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131217 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560483 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131126 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560400 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16119527 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880613 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311377 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111524050 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431703 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.400207 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16097351 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880514 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 313181 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111521614 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431660 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.399918 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94787660 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8229182 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2114661 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254724 1.13% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1244333 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 567856 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 997712 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 503621 0.45% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1824301 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94783688 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8232715 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2113496 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1251152 1.12% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1245297 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 569963 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1001738 0.90% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 503665 0.45% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1819900 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111524050 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38058618 # Number of instructions committed -system.cpu1.commit.committedOps 48145315 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111521614 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38055916 # Number of instructions committed +system.cpu1.commit.committedOps 48139449 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16590369 # Number of memory references committed -system.cpu1.commit.loads 9752527 # Number of loads committed -system.cpu1.commit.membars 190082 # Number of memory barriers committed -system.cpu1.commit.branches 5966603 # Number of branches committed +system.cpu1.commit.refs 16587382 # Number of memory references committed +system.cpu1.commit.loads 9750804 # Number of loads committed +system.cpu1.commit.membars 190065 # Number of memory barriers committed +system.cpu1.commit.branches 5966253 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42681078 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534481 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1824301 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42675584 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534450 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1819900 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172920681 # The number of ROB reads -system.cpu1.rob.rob_writes 131224345 # The number of ROB writes -system.cpu1.timesIdled 1408365 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294630855 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796488086 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37988979 # Number of Instructions Simulated -system.cpu1.committedOps 48075676 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37988979 # Number of Instructions Simulated -system.cpu1.cpi 10.759852 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.759852 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387889245 # number of integer regfile reads -system.cpu1.int_regfile_writes 56198451 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4879 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18462900 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405383 # number of misc regfile writes -system.cpu1.icache.replacements 596769 # number of replacements -system.cpu1.icache.tagsinuse 480.741673 # Cycle average of tags in use -system.cpu1.icache.total_refs 7750669 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597281 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.976587 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 172894643 # The number of ROB reads +system.cpu1.rob.rob_writes 131171187 # The number of ROB writes +system.cpu1.timesIdled 1407429 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294628318 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796480472 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37986277 # Number of Instructions Simulated +system.cpu1.committedOps 48069810 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37986277 # Number of Instructions Simulated +system.cpu1.cpi 10.760590 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.760590 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092932 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092932 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387762774 # number of integer regfile reads +system.cpu1.int_regfile_writes 56160786 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4853 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18458538 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405362 # number of misc regfile writes +system.cpu1.icache.replacements 596198 # number of replacements +system.cpu1.icache.tagsinuse 480.885955 # Cycle average of tags in use +system.cpu1.icache.total_refs 7759207 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 596710 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.003313 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.741673 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938949 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938949 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7750669 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7750669 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7750669 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7750669 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7750669 # number of overall hits -system.cpu1.icache.overall_hits::total 7750669 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641966 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641966 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641966 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641966 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641966 # number of overall misses -system.cpu1.icache.overall_misses::total 641966 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8653423491 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8653423491 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8653423491 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8653423491 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8653423491 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8653423491 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8392635 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8392635 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8392635 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8392635 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8392635 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8392635 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076492 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076492 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076492 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076492 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076492 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076492 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.566661 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13479.566661 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13479.566661 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13479.566661 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2249 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 480.885955 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.939230 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.939230 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7759207 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7759207 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7759207 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7759207 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7759207 # number of overall hits +system.cpu1.icache.overall_hits::total 7759207 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641153 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641153 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641153 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641153 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641153 # number of overall misses +system.cpu1.icache.overall_misses::total 641153 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8644043496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8644043496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8644043496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8644043496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8644043496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8644043496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8400360 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8400360 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8400360 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8400360 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8400360 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8400360 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076324 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076324 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076324 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076324 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076324 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076324 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13482.029244 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13482.029244 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13482.029244 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13482.029244 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2220 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.630303 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.293413 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44655 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44655 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44655 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44655 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44655 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44655 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597311 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597311 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597311 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 597311 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 597311 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 597311 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076959992 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076959992 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076959992 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7076959992 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076959992 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7076959992 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44405 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44405 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44405 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44405 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44405 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44405 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596748 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 596748 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 596748 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 596748 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 596748 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 596748 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076621996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076621996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076621996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7076621996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076621996 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7076621996 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071171 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071171 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071171 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11848.032251 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071038 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071038 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071038 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.643843 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360267 # number of replacements -system.cpu1.dcache.tagsinuse 474.654017 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12671092 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 360637 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.135308 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 359991 # number of replacements +system.cpu1.dcache.tagsinuse 474.520156 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12670892 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360323 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.165371 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 474.654017 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.927059 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.927059 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8304151 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8304151 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4137952 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4137952 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97565 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97565 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94853 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94853 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12442103 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12442103 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12442103 # number of overall hits -system.cpu1.dcache.overall_hits::total 12442103 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 399179 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 399179 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1556589 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1556589 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13972 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13972 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10605 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10605 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1955768 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1955768 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1955768 # number of overall misses -system.cpu1.dcache.overall_misses::total 1955768 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6101251500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6101251500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61874023496 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61874023496 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129109000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129109000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53792000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53792000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67975274996 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67975274996 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67975274996 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67975274996 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703330 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8703330 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5694541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111537 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111537 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105458 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105458 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14397871 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14397871 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14397871 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14397871 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045865 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045865 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273348 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273348 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100561 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100561 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135837 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135837 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135837 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135837 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15284.500187 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15284.500187 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39749.749931 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39749.749931 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9240.552534 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9240.552534 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.324375 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.324375 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34756.308006 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34756.308006 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 25344 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 13325 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.610811 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 84.872611 # average number of cycles each access was blocked +system.cpu1.dcache.occ_blocks::cpu1.data 474.520156 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.926797 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.926797 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8303862 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8303862 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138320 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138320 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97526 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97526 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94815 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94815 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12442182 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12442182 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12442182 # number of overall hits +system.cpu1.dcache.overall_hits::total 12442182 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 400057 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 400057 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1554920 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1554920 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13970 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13970 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10628 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10628 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1954977 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1954977 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1954977 # number of overall misses +system.cpu1.dcache.overall_misses::total 1954977 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6105054500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6105054500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61696466986 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61696466986 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129466000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129466000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53986500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53986500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67801521486 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67801521486 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67801521486 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67801521486 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703919 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8703919 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693240 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5693240 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111496 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111496 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105443 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105443 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14397159 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14397159 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14397159 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14397159 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045963 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045963 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273117 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273117 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125296 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125296 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100794 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100794 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135789 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135789 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135789 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135789 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15260.461634 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15260.461634 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39678.225880 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39678.225880 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9267.430208 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9267.430208 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.648099 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.648099 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34681.493177 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34681.493177 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 24449 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13557 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3317 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.370817 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 83.685185 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324294 # number of writebacks -system.cpu1.dcache.writebacks::total 324294 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171223 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171223 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395128 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395128 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566351 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566351 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566351 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566351 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227956 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 227956 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161461 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161461 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12522 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12522 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389417 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389417 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389417 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389417 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2851782000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2851782000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5138031205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5138031205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88180500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88180500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32594000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32594000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 324138 # number of writebacks +system.cpu1.dcache.writebacks::total 324138 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172104 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172104 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393517 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1393517 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565621 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1565621 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565621 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1565621 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227953 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 227953 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161403 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161403 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12514 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12514 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10624 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10624 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389356 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389356 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389356 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389356 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2849477500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2849477500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5127514196 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5127514196 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88527000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88527000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32740500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32740500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989813205 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7989813205 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989813205 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7989813205 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990081000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990081000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691035962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691035962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681116962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681116962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026192 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026192 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112268 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112268 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100514 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100514 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027047 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027047 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12510.230044 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12510.230044 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31822.119304 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31822.119304 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7042.045999 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7042.045999 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.905660 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.905660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7976991696 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7976991696 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7976991696 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7976991696 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989374500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989374500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35732843580 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35732843580 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204722218080 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204722218080 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026190 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112237 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112237 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100756 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100756 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027044 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027044 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12500.285146 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12500.285146 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31768.394615 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31768.394615 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7074.236855 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7074.236855 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3081.748870 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3081.748870 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1838,17 +1842,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540139410201 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540139410201 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540139410201 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540139410201 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540238105555 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540238105555 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540238105555 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540238105555 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41727 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41724 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 9b1cbcf2d..3671417ef 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,132 +1,144 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533144 # Number of seconds simulated -sim_ticks 2533143973500 # Number of ticks simulated -final_tick 2533143973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533141 # Number of seconds simulated +sim_ticks 2533140518500 # Number of ticks simulated +final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64483 # Simulator instruction rate (inst/s) -host_op_rate 82972 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2708528376 # Simulator tick rate (ticks/s) -host_mem_usage 405264 # Number of bytes of host memory used -host_seconds 935.25 # Real time elapsed on the host -sim_insts 60307579 # Number of instructions simulated -sim_ops 77599125 # Number of ops (including micro ops) simulated +host_inst_rate 41838 # Simulator instruction rate (inst/s) +host_op_rate 53833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1757330352 # Simulator tick rate (ticks/s) +host_mem_usage 435908 # Number of bytes of host memory used +host_seconds 1441.47 # Real time elapsed on the host +sim_insts 60307702 # Number of instructions simulated +sim_ops 77599241 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory -system.physmem.bytes_read::total 129430480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798408 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096817 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59099 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813117 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683783 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096817 # Total number of read requests seen -system.physmem.writeReqs 813117 # Total number of write requests seen -system.physmem.cpureqs 218351 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966196288 # Total number of bytes read from memory -system.physmem.bytesWritten 52039488 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129430480 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943948 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943386 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943985 # Track reads on a per bank basis +system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096807 # Total number of read requests seen +system.physmem.writeReqs 813124 # Total number of write requests seen +system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195648 # Total number of bytes read from memory +system.physmem.bytesWritten 52039936 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50900 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533142848500 # Total gap between requests +system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533139407500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154573 # Categorize read packet sizes +system.physmem.readPktSize::6 154563 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59099 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108698 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10857 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59106 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16749 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12584 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -139,15 +151,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2788 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2837 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see @@ -160,25 +172,25 @@ system.physmem.wrQLenPdf::17 35353 # Wh system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32722 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32565 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.totQLat 393251142750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485645877750 # Sum of mem lat for all requests -system.physmem.totBusLat 75482950000 # Total cycles spent in databus access -system.physmem.totBankLat 16911785000 # Total cycles spent in bank access -system.physmem.avgQLat 26049.00 # Average queueing delay per request -system.physmem.avgBankLat 1120.24 # Average bank access latency per request +system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see +system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests +system.physmem.totBusLat 75482565000 # Total cycles spent in databus access +system.physmem.totBankLat 16909241250 # Total cycles spent in bank access +system.physmem.avgQLat 26044.77 # Average queueing delay per request +system.physmem.avgBankLat 1120.08 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32169.24 # Average memory access latency +system.physmem.avgMemAccLat 32164.85 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -186,62 +198,50 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 9.55 # Average write queue length over time -system.physmem.readRowHits 15020272 # Number of row buffer hits during reads -system.physmem.writeRowHits 793090 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159217.68 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.avgWrQLen 11.32 # Average write queue length over time +system.physmem.readRowHits 15020284 # Number of row buffer hits during reads +system.physmem.writeRowHits 793162 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes +system.physmem.avgGap 159217.50 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14675749 # Number of BP lookups -system.cpu.branchPred.condPredicted 11761615 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705306 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9809113 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7951342 # Number of BTB hits +system.cpu.branchPred.lookups 14656582 # Number of BP lookups +system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.060765 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398937 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51399217 # DTB read hits -system.cpu.dtb.read_misses 64403 # DTB read misses -system.cpu.dtb.write_hits 11701345 # DTB write hits -system.cpu.dtb.write_misses 15902 # DTB write misses +system.cpu.dtb.read_hits 51396633 # DTB read hits +system.cpu.dtb.read_misses 64067 # DTB read misses +system.cpu.dtb.write_hits 11699653 # DTB write hits +system.cpu.dtb.write_misses 15746 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3557 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2566 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 409 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51463620 # DTB read accesses -system.cpu.dtb.write_accesses 11717247 # DTB write accesses +system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51460700 # DTB read accesses +system.cpu.dtb.write_accesses 11715399 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100562 # DTB hits -system.cpu.dtb.misses 80305 # DTB misses -system.cpu.dtb.accesses 63180867 # DTB accesses -system.cpu.itb.inst_hits 12332677 # ITB inst hits -system.cpu.itb.inst_misses 11271 # ITB inst misses +system.cpu.dtb.hits 63096286 # DTB hits +system.cpu.dtb.misses 79813 # DTB misses +system.cpu.dtb.accesses 63176099 # DTB accesses +system.cpu.itb.inst_hits 12325480 # ITB inst hits +system.cpu.itb.inst_misses 11172 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -250,113 +250,113 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2475 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2484 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2981 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12343948 # ITB inst accesses -system.cpu.itb.hits 12332677 # DTB hits -system.cpu.itb.misses 11271 # DTB misses -system.cpu.itb.accesses 12343948 # DTB accesses -system.cpu.numCycles 471840254 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12336652 # ITB inst accesses +system.cpu.itb.hits 12325480 # DTB hits +system.cpu.itb.misses 11172 # DTB misses +system.cpu.itb.accesses 12336652 # DTB accesses +system.cpu.numCycles 471810648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30570540 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96039987 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14675749 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9350279 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21160212 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5300332 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123049 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95587623 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87979 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195754 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12329197 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900896 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5353 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151365911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785063 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130221030 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303083 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712964 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496255 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215475 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108052 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757455 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745629 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8805968 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151365911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203543 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32532272 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95215917 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19186051 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962874 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3468797 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957839 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171569 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112632707 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566700 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3468797 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34474935 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36706470 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52522148 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18150584 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6042977 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106114460 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20538 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4062916 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 612 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110534596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485505463 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485414558 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90905 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32144721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830610 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737120 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12168217 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20326621 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13518825 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1978093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2487494 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97939378 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124329035 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167924 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21751378 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57069924 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501194 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151365911 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821381 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534880 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107121434 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13552589 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7069165 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5942277 3.93% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12602111 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2786608 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1699306 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465403 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127018 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107106602 70.78% 70.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13535056 8.94% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151365911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60927 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available @@ -385,383 +385,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365559 94.64% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412870 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58631029 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93272 0.08% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52917261 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12321634 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124329035 # Type of FU issued -system.cpu.iq.rate 0.263498 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839358 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409088132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121690697 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85968255 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23084 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12548 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132792486 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12241 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623354 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued +system.cpu.iq.rate 0.263438 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4672096 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6462 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1786745 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107738 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893837 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3468797 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27950970 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433267 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100144689 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200366 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20326621 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13518825 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410950 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112625 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3575 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350763 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619825 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121548947 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52086338 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2780088 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221732 # number of nop insts executed -system.cpu.iew.exec_refs 64299340 # number of memory reference insts executed -system.cpu.iew.exec_branches 11561583 # Number of branches executed -system.cpu.iew.exec_stores 12213002 # Number of stores executed -system.cpu.iew.exec_rate 0.257606 # Inst execution rate -system.cpu.iew.wb_sent 120388158 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85978549 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47221894 # num instructions producing a value -system.cpu.iew.wb_consumers 88170402 # num instructions consuming a value +system.cpu.iew.exec_nop 221429 # number of nop insts executed +system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed +system.cpu.iew.exec_branches 11545908 # Number of branches executed +system.cpu.iew.exec_stores 12211356 # Number of stores executed +system.cpu.iew.exec_rate 0.257527 # Inst execution rate +system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47220023 # num instructions producing a value +system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182220 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535575 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21486542 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536246 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147897114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525700 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515001 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120445936 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13320013 9.01% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3904517 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120442 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1947230 1.32% 95.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 967442 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598856 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701557 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2891121 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147897114 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60457960 # Number of instructions committed -system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458083 # Number of instructions committed +system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386605 # Number of memory references committed -system.cpu.commit.loads 15654525 # Number of loads committed -system.cpu.commit.membars 403599 # Number of memory barriers committed -system.cpu.commit.branches 9961316 # Number of branches committed +system.cpu.commit.refs 27386631 # Number of memory references committed +system.cpu.commit.loads 15654552 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961338 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. -system.cpu.commit.function_calls 991257 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2891121 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854854 # Number of committed integer instructions. +system.cpu.commit.function_calls 991262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2890603 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242393474 # The number of ROB reads -system.cpu.rob.rob_writes 202038068 # The number of ROB writes -system.cpu.timesIdled 1769308 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320474343 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307579 # Number of Instructions Simulated -system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated -system.cpu.cpi 7.823896 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823896 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550318447 # number of integer regfile reads -system.cpu.int_regfile_writes 88458212 # number of integer regfile writes -system.cpu.fp_regfile_reads 8290 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 30125052 # number of misc regfile reads -system.cpu.misc_regfile_writes 831890 # number of misc regfile writes -system.cpu.icache.replacements 979629 # number of replacements -system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use -system.cpu.icache.total_refs 11269534 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980141 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.497870 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 242306963 # The number of ROB reads +system.cpu.rob.rob_writes 201917005 # The number of ROB writes +system.cpu.timesIdled 1770758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320479438 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594387345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307702 # Number of Instructions Simulated +system.cpu.committedOps 77599241 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated +system.cpu.cpi 7.823390 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823390 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550141263 # number of integer regfile reads +system.cpu.int_regfile_writes 88418139 # number of integer regfile writes +system.cpu.fp_regfile_reads 8398 # number of floating regfile reads +system.cpu.fp_regfile_writes 2928 # number of floating regfile writes +system.cpu.misc_regfile_reads 30126321 # number of misc regfile reads +system.cpu.misc_regfile_writes 831893 # number of misc regfile writes +system.cpu.icache.replacements 979850 # number of replacements +system.cpu.icache.tagsinuse 511.615737 # Cycle average of tags in use +system.cpu.icache.total_refs 11261998 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980362 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.487591 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.615737 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11269534 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11269534 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11269534 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11269534 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11269534 # number of overall hits -system.cpu.icache.overall_hits::total 11269534 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059538 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059538 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059538 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059538 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059538 # number of overall misses -system.cpu.icache.overall_misses::total 1059538 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993400496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13993400496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13993400496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13993400496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13993400496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13993400496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12329072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12329072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12329072 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12329072 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12329072 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12329072 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085938 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085938 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085938 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085938 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085938 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.077515 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.077515 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.077515 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.077515 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4855 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11261998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11261998 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11261998 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11261998 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11261998 # number of overall hits +system.cpu.icache.overall_hits::total 11261998 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059902 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059902 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059902 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059902 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059902 # number of overall misses +system.cpu.icache.overall_misses::total 1059902 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993800493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13993800493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13993800493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13993800493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13993800493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13993800493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12321900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12321900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12321900 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12321900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12321900 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12321900 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086018 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086018 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086018 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086018 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086018 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13202.919226 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13202.919226 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13202.919226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13202.919226 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4527 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 305 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 299 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.918033 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.140468 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79361 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149502 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541016289 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5568433372 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6111959453 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2360290 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149502 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541016289 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5568433372 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6111959453 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002461767 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007542597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26898020017 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26898020017 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193900481784 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193905562614 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026768 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986815 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986815 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541224 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541224 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092645 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092645 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44000.650633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46960.238516 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45398.827041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541132 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541132 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092676 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092676 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43917.224531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46559.141717 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45164.826474 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38126.365322 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38126.365322 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38087.123504 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38087.123504 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -882,161 +882,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643553 # number of replacements +system.cpu.dcache.replacements 643403 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21507678 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644065 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.393645 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21507300 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643915 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.400837 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13754193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13754193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259605 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259605 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243146 # 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number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 13753934 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753934 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259500 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259500 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243166 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243166 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247603 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247603 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21013434 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21013434 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21013434 # number of overall hits +system.cpu.dcache.overall_hits::total 21013434 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737092 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104414938731 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104414938731 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180553500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180553500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3699940 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699940 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699940 # number of overall misses +system.cpu.dcache.overall_misses::total 3699940 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9782888500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9782888500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104355801234 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104355801234 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 179982000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 179982000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114215639231 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114215639231 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114215639231 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114215639231 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14492025 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14492025 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256654 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24714376 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24714376 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24714376 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24714376 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050913 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289830 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289830 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052631 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052631 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 114138689734 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114138689734 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114138689734 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114138689734 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222348 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222348 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256659 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256659 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24713374 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713374 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713374 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713374 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050865 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050865 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289840 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289840 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052572 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052572 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149734 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149734 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149734 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149734 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.105775 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.105775 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35242.622463 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35242.622463 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13366.412496 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.412496 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13272.276052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13272.276052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35221.449509 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35221.449509 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13338.916475 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13338.916475 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30864.270185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30864.270185 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29973 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17225 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2670 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.225843 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.353175 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30848.794773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30848.794773 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29383 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15931 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2645 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 250 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.108885 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 63.724000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks -system.cpu.dcache.writebacks::total 607832 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351946 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351946 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713780 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713780 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1332 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1332 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065726 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065726 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065726 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065726 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385886 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385886 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248966 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248966 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12176 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12176 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 607769 # number of writebacks +system.cpu.dcache.writebacks::total 607769 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351375 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351375 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713851 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713851 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065226 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065226 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065226 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065226 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385717 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385717 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248997 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248997 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12159 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12159 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634852 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634852 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634852 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4812474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4812474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8188067914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8188067914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141180000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141180000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 634714 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634714 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634714 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634714 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4806820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4806820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8183010414 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8183010414 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140641000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140641000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13000541914 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13000541914 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13000541914 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13000541914 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395833000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395833000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742502511 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742502511 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138335511 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138335511 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047441 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047441 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12989830414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12989830414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12989830414 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12989830414 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36713909190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36713909190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219109545190 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219109545190 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047374 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025688 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025688 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12471.232437 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12471.232437 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32888.297655 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32888.297655 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.940867 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.940867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025683 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025683 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.038230 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.038230 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32863.891589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32863.891589 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11566.822930 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11566.822930 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1058,16 +1058,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610797601 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229610797601 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index d1147fb64..7a69bab79 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401153 # Number of seconds simulated -sim_ticks 2401153455000 # Number of ticks simulated -final_tick 2401153455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401336 # Number of seconds simulated +sim_ticks 2401336466000 # Number of ticks simulated +final_tick 2401336466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200255 # Simulator instruction rate (inst/s) -host_op_rate 257182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7970039029 # Simulator tick rate (ticks/s) -host_mem_usage 397936 # Number of bytes of host memory used -host_seconds 301.27 # Real time elapsed on the host -sim_insts 60331276 # Number of instructions simulated -sim_ops 77481997 # Number of ops (including micro ops) simulated +host_inst_rate 184517 # Simulator instruction rate (inst/s) +host_op_rate 236966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7343776984 # Simulator tick rate (ticks/s) +host_mem_usage 427572 # Number of bytes of host memory used +host_seconds 326.99 # Real time elapsed on the host +sim_insts 60334938 # Number of instructions simulated +sim_ops 77485485 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -26,149 +26,149 @@ system.realview.nvmem.bw_total::total 8 # To system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7085840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 500256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7098320 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 85312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 678208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 177920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1312828 # Number of bytes read from this memory -system.physmem.bytes_read::total 124662252 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 85312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 177920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 765408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3746944 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1490908 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1325456 # Number of bytes written to this memory -system.physmem.bytes_written::total 6762760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 85696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 673152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 178560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1305852 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661996 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 500256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 85696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 178560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3746176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1490900 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1325460 # Number of bytes written to this memory +system.physmem.bytes_written::total 6761992 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110945 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1333 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2780 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20527 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512434 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58546 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 372727 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 331364 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812500 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47818298 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1339 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2790 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20418 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58534 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 372725 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 331365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812488 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47814654 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2951015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 208324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2955987 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 74098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 546749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51917653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 74098 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620913 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 552008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2816463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47818298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 74359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 543802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51913590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 208324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35687 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 74359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318369 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560038 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620863 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 551968 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815929 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47814654 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3571928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 208324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3576850 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 365516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 74098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1098757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54734116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12597264 # Total number of read requests seen -system.physmem.writeReqs 398689 # Total number of write requests seen -system.physmem.cpureqs 55044 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 806224896 # Total number of bytes read from memory -system.physmem.bytesWritten 25516096 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102751100 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2642476 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 35687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 363384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 74359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1095770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54729518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12617991 # Total number of read requests seen +system.physmem.writeReqs 398645 # Total number of write requests seen +system.physmem.cpureqs 54826 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807551424 # Total number of bytes read from memory +system.physmem.bytesWritten 25513280 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102907452 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2639540 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 787593 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 787339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 787599 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 787924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 787752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 787476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 787626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 787678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 787361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 786762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 786761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 787020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 787004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 786857 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 787043 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 787469 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2346 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 789133 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 789207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 789032 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 788938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 788613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 788036 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 788045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 788296 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788320 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788751 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 24965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24768 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24655 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25297 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24838 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24777 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24963 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24891 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25066 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24855 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 24641 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25299 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24939 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24843 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25226 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 780903 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400118241500 # Total gap between requests +system.physmem.numWrRetry 14345 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400301266000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 15 # Categorize read packet sizes -system.physmem.readPktSize::3 12562016 # Categorize read packet sizes +system.physmem.readPktSize::3 12582912 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35233 # Categorize read packet sizes +system.physmem.readPktSize::6 35064 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 381227 # Categorize write packet sizes +system.physmem.writePktSize::2 381229 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17462 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 814730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 790825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 796437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2993221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2257059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2257380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2245823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6938 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17416 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 815827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 797714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2260876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2261203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6952 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -185,326 +185,326 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2977 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17335 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 17331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14404 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14347 # What write queue length does an incoming req see -system.physmem.totQLat 276742406750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 352442416750 # Sum of mem lat for all requests -system.physmem.totBusLat 62986320000 # Total cycles spent in databus access -system.physmem.totBankLat 12713690000 # Total cycles spent in bank access -system.physmem.avgQLat 21968.45 # Average queueing delay per request -system.physmem.avgBankLat 1009.24 # Average bank access latency per request +system.physmem.wrQLenPdf::25 14384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14346 # What write queue length does an incoming req see +system.physmem.totQLat 277202035000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 353023032500 # Sum of mem lat for all requests +system.physmem.totBusLat 63089955000 # Total cycles spent in databus access +system.physmem.totBankLat 12731042500 # Total cycles spent in bank access +system.physmem.avgQLat 21968.79 # Average queueing delay per request +system.physmem.avgBankLat 1008.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27977.70 # Average memory access latency -system.physmem.avgRdBW 335.77 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.79 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 27977.75 # Average memory access latency +system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.85 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.71 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12542718 # Number of row buffer hits during reads -system.physmem.writeRowHits 392355 # Number of row buffer hits during writes +system.physmem.readRowHits 12563370 # Number of row buffer hits during reads +system.physmem.writeRowHits 392291 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184681.97 # 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mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023036 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45130.683597 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 47562.460485 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 47550.582794 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10083.144814 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45296.247934 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 46994.995323 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 47975.113272 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10077.717172 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.266667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32440.935981 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40491.915620 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37733.022718 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.624157 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32386.759992 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40372.476772 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37640.243422 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33842.995492 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41348.301568 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39876.474832 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33842.995492 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41348.301568 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39876.474832 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -656,436 +656,436 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8076292 # DTB read hits -system.cpu0.dtb.read_misses 6232 # DTB read misses -system.cpu0.dtb.write_hits 6627548 # DTB write hits -system.cpu0.dtb.write_misses 2039 # DTB write misses +system.cpu0.dtb.read_hits 8079595 # DTB read hits +system.cpu0.dtb.read_misses 6254 # DTB read misses +system.cpu0.dtb.write_hits 6630051 # DTB write hits +system.cpu0.dtb.write_misses 2055 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5689 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5732 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 126 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 128 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8082524 # DTB read accesses -system.cpu0.dtb.write_accesses 6629587 # DTB write accesses +system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8085849 # DTB read accesses +system.cpu0.dtb.write_accesses 6632106 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14703840 # DTB hits -system.cpu0.dtb.misses 8271 # DTB misses -system.cpu0.dtb.accesses 14712111 # DTB accesses -system.cpu0.itb.inst_hits 32739442 # ITB inst hits -system.cpu0.itb.inst_misses 3479 # ITB inst misses +system.cpu0.dtb.hits 14709646 # DTB hits +system.cpu0.dtb.misses 8309 # DTB misses +system.cpu0.dtb.accesses 14717955 # DTB accesses +system.cpu0.itb.inst_hits 32707746 # ITB inst hits +system.cpu0.itb.inst_misses 3496 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2588 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32742921 # ITB inst accesses -system.cpu0.itb.hits 32739442 # DTB hits -system.cpu0.itb.misses 3479 # DTB misses -system.cpu0.itb.accesses 32742921 # DTB accesses -system.cpu0.numCycles 113988971 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32711242 # ITB inst accesses +system.cpu0.itb.hits 32707746 # DTB hits +system.cpu0.itb.misses 3496 # DTB misses +system.cpu0.itb.accesses 32711242 # DTB accesses +system.cpu0.numCycles 113988289 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32238592 # Number of instructions committed -system.cpu0.committedOps 42426848 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37569901 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses -system.cpu0.num_func_calls 1188707 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4243711 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37569901 # number of integer instructions -system.cpu0.num_fp_insts 5136 # number of float instructions -system.cpu0.num_int_register_reads 191405612 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39677066 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15367259 # number of memory refs -system.cpu0.num_load_insts 8443691 # Number of load instructions -system.cpu0.num_store_insts 6923568 # Number of store instructions -system.cpu0.num_idle_cycles 13415307720.919615 # Number of idle cycles -system.cpu0.num_busy_cycles -13301318749.919615 # Number of busy cycles -system.cpu0.not_idle_fraction -116.689524 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.689524 # Percentage of idle cycles +system.cpu0.committedInsts 32205724 # Number of instructions committed +system.cpu0.committedOps 42407604 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37554027 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5120 # Number of float alu accesses +system.cpu0.num_func_calls 1187729 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4239348 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37554027 # number of integer instructions +system.cpu0.num_fp_insts 5120 # number of float instructions +system.cpu0.num_int_register_reads 191333530 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39644160 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3702 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1420 # number of times the floating registers were written +system.cpu0.num_mem_refs 15372618 # number of memory refs +system.cpu0.num_load_insts 8447076 # Number of load instructions +system.cpu0.num_store_insts 6925542 # Number of store instructions +system.cpu0.num_idle_cycles 13415449988.373053 # Number of idle cycles +system.cpu0.num_busy_cycles -13301461699.373053 # Number of busy cycles +system.cpu0.not_idle_fraction -116.691476 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.691476 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 892272 # number of replacements -system.cpu0.icache.tagsinuse 511.604135 # Cycle average of tags in use -system.cpu0.icache.total_refs 44302234 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892784 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.622567 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 82896 # number of quiesce instructions executed +system.cpu0.icache.replacements 892496 # number of replacements +system.cpu0.icache.tagsinuse 511.604237 # Cycle average of tags in use +system.cpu0.icache.total_refs 44360992 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 893008 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 49.675918 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 8108819000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 477.646185 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.780881 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 16.177069 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.932903 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.034728 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.031596 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 478.427369 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 17.974038 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 15.202829 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.934428 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.035106 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.029693 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32272136 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8284220 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3745878 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44302234 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32272136 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8284220 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3745878 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44302234 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32272136 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8284220 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3745878 # number of overall hits -system.cpu0.icache.overall_hits::total 44302234 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 469978 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 135194 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 311533 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916705 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 469978 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 135194 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 311533 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916705 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 469978 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 135194 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 311533 # number of overall misses -system.cpu0.icache.overall_misses::total 916705 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1823611000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4151773488 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5975384488 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1823611000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4151773488 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5975384488 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1823611000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4151773488 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5975384488 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32742114 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8419414 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4057411 # 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number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 406 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 406 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 691063 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 691063 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 691063 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 691063 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65419 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137122 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 202541 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29767 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52891 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82658 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1720 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3471 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5191 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 95186 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 190013 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 285199 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 95186 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 190013 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 285199 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 781124500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1779796500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2560921000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 671346500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1430416990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2101763490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19076000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40648000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59724000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1452471000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3210213490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4662684490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1452471000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3210213490 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4662684490 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27580693500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29009829000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56590522500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281089000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14115638625 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396727625 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861782500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43125467625 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71987250125 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033441 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028925 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014651 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021578 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019445 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008091 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047810 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045268 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020747 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011863 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011863 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11940.330791 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.656802 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12643.963444 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22553.381261 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27044.619879 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25427.224104 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.697674 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11710.746183 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11505.297631 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597590 # number of writebacks +system.cpu0.dcache.writebacks::total 597590 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145454 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 145454 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 546284 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 546284 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 421 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 421 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 691738 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 691738 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 691738 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 691738 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65235 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 136322 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 201557 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29114 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52948 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1716 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3454 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5170 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94349 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 189270 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 283619 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 94349 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 189270 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 283619 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779717500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1769361500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2549079000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 660454500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1423557990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2084012490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19032000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40419500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59451500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1440172000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3192919490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4633091490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1440172000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3192919490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4633091490 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27487398000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29017842000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56505240000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281263000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147361293 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15428624293 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28768661000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43165203293 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71933864293 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033106 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028888 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014585 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021118 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019478 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008032 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047802 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044971 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020666 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.441174 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.280674 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12646.938583 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22685.117126 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26885.963398 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25395.584924 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.909091 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11702.229299 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11499.323017 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1098,218 +1098,218 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2171794 # DTB read hits -system.cpu1.dtb.read_misses 2101 # DTB read misses -system.cpu1.dtb.write_hits 1466259 # DTB write hits -system.cpu1.dtb.write_misses 389 # DTB write misses +system.cpu1.dtb.read_hits 2185339 # DTB read hits +system.cpu1.dtb.read_misses 2099 # DTB read misses +system.cpu1.dtb.write_hits 1465312 # DTB write hits +system.cpu1.dtb.write_misses 382 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1728 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 36 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 80 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2173895 # DTB read accesses -system.cpu1.dtb.write_accesses 1466648 # DTB write accesses +system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2187438 # DTB read accesses +system.cpu1.dtb.write_accesses 1465694 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3638053 # DTB hits -system.cpu1.dtb.misses 2490 # DTB misses -system.cpu1.dtb.accesses 3640543 # DTB accesses -system.cpu1.itb.inst_hits 8419414 # ITB inst hits -system.cpu1.itb.inst_misses 1129 # ITB inst misses +system.cpu1.dtb.hits 3650651 # DTB hits +system.cpu1.dtb.misses 2481 # DTB misses +system.cpu1.dtb.accesses 3653132 # DTB accesses +system.cpu1.itb.inst_hits 8513719 # ITB inst hits +system.cpu1.itb.inst_misses 1131 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 827 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 841 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8420543 # ITB inst accesses -system.cpu1.itb.hits 8419414 # DTB hits -system.cpu1.itb.misses 1129 # DTB misses -system.cpu1.itb.accesses 8420543 # DTB accesses -system.cpu1.numCycles 574251142 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8514850 # ITB inst accesses +system.cpu1.itb.hits 8513719 # DTB hits +system.cpu1.itb.misses 1131 # DTB misses +system.cpu1.itb.accesses 8514850 # DTB accesses +system.cpu1.numCycles 574637078 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8213191 # Number of instructions committed -system.cpu1.committedOps 10466435 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9372254 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses -system.cpu1.num_func_calls 317964 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1146067 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9372254 # number of integer instructions -system.cpu1.num_fp_insts 2062 # number of float instructions -system.cpu1.num_int_register_reads 54024867 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10146423 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3811897 # number of memory refs -system.cpu1.num_load_insts 2267853 # Number of load instructions -system.cpu1.num_store_insts 1544044 # Number of store instructions -system.cpu1.num_idle_cycles 537580210.089888 # Number of idle cycles -system.cpu1.num_busy_cycles 36670931.910112 # Number of busy cycles -system.cpu1.not_idle_fraction 0.063859 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.936141 # Percentage of idle cycles +system.cpu1.committedInsts 8294211 # Number of instructions committed +system.cpu1.committedOps 10531754 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9421872 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses +system.cpu1.num_func_calls 319530 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1158784 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9421872 # number of integer instructions +system.cpu1.num_fp_insts 2078 # number of float instructions +system.cpu1.num_int_register_reads 54337439 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10233618 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written +system.cpu1.num_mem_refs 3824850 # number of memory refs +system.cpu1.num_load_insts 2281405 # Number of load instructions +system.cpu1.num_store_insts 1543445 # Number of store instructions +system.cpu1.num_idle_cycles 540667957.850120 # Number of idle cycles +system.cpu1.num_busy_cycles 33969120.149880 # Number of busy cycles +system.cpu1.not_idle_fraction 0.059114 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.940886 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4709991 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3829375 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 221875 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3139297 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527298 # Number of BTB hits +system.cpu2.branchPred.lookups 4687055 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3808844 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 220686 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3132450 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2515746 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.505221 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 410694 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21534 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.312407 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 409998 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21415 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10865348 # DTB read hits -system.cpu2.dtb.read_misses 22611 # DTB read misses -system.cpu2.dtb.write_hits 3267482 # DTB write hits -system.cpu2.dtb.write_misses 5780 # DTB write misses +system.cpu2.dtb.read_hits 10844149 # DTB read hits +system.cpu2.dtb.read_misses 22603 # DTB read misses +system.cpu2.dtb.write_hits 3263914 # DTB write hits +system.cpu2.dtb.write_misses 5857 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID system.cpu2.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 877 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 154 # Number of TLB faults due to prefetch +system.cpu2.dtb.align_faults 825 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 449 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10887959 # DTB read accesses -system.cpu2.dtb.write_accesses 3273262 # DTB write accesses +system.cpu2.dtb.perms_faults 466 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10866752 # DTB read accesses +system.cpu2.dtb.write_accesses 3269771 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14132830 # DTB hits -system.cpu2.dtb.misses 28391 # DTB misses -system.cpu2.dtb.accesses 14161221 # DTB accesses -system.cpu2.itb.inst_hits 4058794 # ITB inst hits -system.cpu2.itb.inst_misses 4496 # ITB inst misses +system.cpu2.dtb.hits 14108063 # DTB hits +system.cpu2.dtb.misses 28460 # DTB misses +system.cpu2.dtb.accesses 14136523 # DTB accesses +system.cpu2.itb.inst_hits 4055013 # ITB inst hits +system.cpu2.itb.inst_misses 4560 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1567 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1575 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1061 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1017 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4063290 # ITB inst accesses -system.cpu2.itb.hits 4058794 # DTB hits -system.cpu2.itb.misses 4496 # DTB misses -system.cpu2.itb.accesses 4063290 # DTB accesses -system.cpu2.numCycles 88265633 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4059573 # ITB inst accesses +system.cpu2.itb.hits 4055013 # DTB hits +system.cpu2.itb.misses 4560 # DTB misses +system.cpu2.itb.accesses 4059573 # DTB accesses +system.cpu2.numCycles 88254759 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9438008 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32342862 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4709991 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2937992 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6815885 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1813158 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 52200 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19319240 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 990 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33528 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 57014 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 272 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4057414 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 309972 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1938 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36961797 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050032 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436638 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9429776 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32237470 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4687055 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2925744 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6801535 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1807730 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51877 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19337159 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 319 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 987 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33898 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57137 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 401 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4053658 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 309769 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36952841 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.047181 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.432989 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30150982 81.57% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 382433 1.03% 82.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 508858 1.38% 83.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 812110 2.20% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 648973 1.76% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344473 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1008779 2.73% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 237853 0.64% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2867336 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30156381 81.61% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 380935 1.03% 82.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 507291 1.37% 84.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 812322 2.20% 86.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 657376 1.78% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 343317 0.93% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1003055 2.71% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 237893 0.64% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2854271 7.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36961797 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053362 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.366426 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10050266 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19257143 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6169060 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 292369 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1191852 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 610072 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53860 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36648451 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 182697 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1191852 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10623039 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6559507 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11162234 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5869128 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1554979 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34406679 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2425 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 416595 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 876326 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 106 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 36902595 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157291448 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157264010 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27438 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25708511 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11194083 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 230845 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207258 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3329183 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6509687 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3839458 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 526321 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 767723 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31666176 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511259 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34215654 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 53951 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7402351 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19875920 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155450 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36961797 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.925703 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.580463 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36952841 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053108 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.365277 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10041048 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19275643 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6155197 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 292391 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1187539 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608222 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53447 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36559853 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 181421 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1187539 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10612647 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6555727 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11181502 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5856266 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1558172 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34319277 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2410 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 422959 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 872955 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 107 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 36779919 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 156919879 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 156892837 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27042 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25654971 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11124947 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231561 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207869 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3330119 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6484809 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3835337 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 528235 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 785937 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31561835 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 513874 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34144653 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 53839 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7344925 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19731311 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 156774 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36952841 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.924006 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.578400 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24411546 66.05% 66.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3907285 10.57% 76.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2341872 6.34% 82.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974558 5.34% 88.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2782177 7.53% 95.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 896473 2.43% 98.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 480042 1.30% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 133126 0.36% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34718 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24411645 66.06% 66.06% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3911686 10.59% 76.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2348900 6.36% 83.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1966009 5.32% 88.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2782600 7.53% 95.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 888012 2.40% 98.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 476049 1.29% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 133134 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34806 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36961797 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36952841 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16658 1.09% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16764 1.09% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available @@ -1338,148 +1338,148 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407260 91.71% 92.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110601 7.21% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407478 91.75% 92.84% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109853 7.16% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61295 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19329502 56.49% 56.67% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 25951 0.08% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 9 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 376 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11364260 33.21% 89.96% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3434245 10.04% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61419 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19283233 56.48% 56.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25726 0.08% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 370 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11342799 33.22% 89.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3431088 10.05% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34215654 # Type of FU issued -system.cpu2.iq.rate 0.387644 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1534519 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044848 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107003021 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39584963 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27346219 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6827 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3771 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3100 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35685269 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3609 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 207108 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34144653 # Type of FU issued +system.cpu2.iq.rate 0.386887 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1534095 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044929 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106851627 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39425823 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27268218 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6778 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3706 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3093 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35613758 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3571 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205973 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1576105 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1884 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9268 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 580803 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1568043 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1874 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9216 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 577978 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5370889 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352686 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5372164 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352557 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1191852 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4868557 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91379 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32255245 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 59750 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6509687 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3839458 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 369212 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31393 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2360 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9268 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105822 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88057 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193879 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33230591 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11076582 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 985063 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1187539 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4864839 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 90375 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32148379 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60078 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6484809 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3835337 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 371219 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 30634 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2404 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9216 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105461 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 87459 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 192920 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33152533 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11055310 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 992120 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 77810 # number of nop insts executed -system.cpu2.iew.exec_refs 14478078 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3688656 # Number of branches executed -system.cpu2.iew.exec_stores 3401496 # Number of stores executed -system.cpu2.iew.exec_rate 0.376484 # Inst execution rate -system.cpu2.iew.wb_sent 32812407 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27349319 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15625261 # num instructions producing a value -system.cpu2.iew.wb_consumers 28412503 # num instructions consuming a value +system.cpu2.iew.exec_nop 72670 # number of nop insts executed +system.cpu2.iew.exec_refs 14453415 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3670278 # Number of branches executed +system.cpu2.iew.exec_stores 3398105 # Number of stores executed +system.cpu2.iew.exec_rate 0.375646 # Inst execution rate +system.cpu2.iew.wb_sent 32735616 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27271311 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15591378 # num instructions producing a value +system.cpu2.iew.wb_consumers 28369462 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.309852 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549943 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309007 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549583 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7344146 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 355809 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168786 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35769820 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.688862 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.716544 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7280422 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357100 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 167971 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35765164 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.687670 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.714660 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27147085 75.89% 75.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4176329 11.68% 87.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1256730 3.51% 91.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 649005 1.81% 92.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 570906 1.60% 94.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 316592 0.89% 95.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 399111 1.12% 96.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 290067 0.81% 97.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 963995 2.69% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27144865 75.90% 75.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4185503 11.70% 87.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1252343 3.50% 91.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 650255 1.82% 92.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 570350 1.59% 94.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 312906 0.87% 95.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 397008 1.11% 96.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 289788 0.81% 97.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 962146 2.69% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35769820 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19931262 # Number of instructions committed -system.cpu2.commit.committedOps 24640483 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35765164 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19883492 # Number of instructions committed +system.cpu2.commit.committedOps 24594616 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8192237 # Number of memory references committed -system.cpu2.commit.loads 4933582 # Number of loads committed -system.cpu2.commit.membars 94126 # Number of memory barriers committed -system.cpu2.commit.branches 3155533 # Number of branches committed +system.cpu2.commit.refs 8174125 # Number of memory references committed +system.cpu2.commit.loads 4916766 # Number of loads committed +system.cpu2.commit.membars 94500 # Number of memory barriers committed +system.cpu2.commit.branches 3146107 # Number of branches committed system.cpu2.commit.fp_insts 3055 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21875712 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294009 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 963995 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 21842455 # Number of committed integer instructions. +system.cpu2.commit.function_calls 293773 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 962146 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66266303 # The number of ROB reads -system.cpu2.rob.rob_writes 65202475 # The number of ROB writes -system.cpu2.timesIdled 360564 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51303836 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567277023 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19879493 # Number of Instructions Simulated -system.cpu2.committedOps 24588714 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19879493 # Number of Instructions Simulated -system.cpu2.cpi 4.440034 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.440034 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.225223 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.225223 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153509449 # number of integer regfile reads -system.cpu2.int_regfile_writes 29174173 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22340 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20840 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9001304 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240409 # number of misc regfile writes +system.cpu2.rob.rob_reads 66150526 # The number of ROB reads +system.cpu2.rob.rob_writes 64978873 # The number of ROB writes +system.cpu2.timesIdled 360296 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51301918 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567267972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19835003 # Number of Instructions Simulated +system.cpu2.committedOps 24546127 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19835003 # Number of Instructions Simulated +system.cpu2.cpi 4.449445 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.449445 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.224747 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.224747 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153135451 # number of integer regfile reads +system.cpu2.int_regfile_writes 29084509 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22287 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes +system.cpu2.misc_regfile_reads 8972562 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241289 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1494,10 +1494,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 979501914046 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 979501914046 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 979501914046 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 979501914046 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981130976648 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 981130976648 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981130976648 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 981130976648 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 8c9cf8058..56b72ce02 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.541288 # Number of seconds simulated -sim_ticks 2541288206500 # Number of ticks simulated -final_tick 2541288206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.541275 # Number of seconds simulated +sim_ticks 2541275479000 # Number of ticks simulated +final_tick 2541275479000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64704 # Simulator instruction rate (inst/s) -host_op_rate 83256 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2726411009 # Simulator tick rate (ticks/s) -host_mem_usage 408332 # Number of bytes of host memory used -host_seconds 932.10 # Real time elapsed on the host -sim_insts 60310239 # Number of instructions simulated -sim_ops 77602695 # Number of ops (including micro ops) simulated +host_inst_rate 58368 # Simulator instruction rate (inst/s) +host_op_rate 75104 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2459458086 # Simulator tick rate (ticks/s) +host_mem_usage 437960 # Number of bytes of host memory used +host_seconds 1033.27 # Real time elapsed on the host +sim_insts 60310144 # Number of instructions simulated +sim_ops 77602537 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -24,137 +24,137 @@ system.realview.nvmem.bw_inst_read::total 25 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 503232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4160720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 503040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4153104 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 298048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4933980 # Number of bytes read from this memory -system.physmem.bytes_read::total 131009132 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 503232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 298048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 801280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1345260 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1670852 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802288 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 296576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4940508 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 503040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 296576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785600 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1346056 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1670056 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801712 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7863 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 65045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7860 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 64926 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4657 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77100 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293522 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336315 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417713 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47657140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 198022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1637248 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 4634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77202 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293480 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59150 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336514 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417514 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47657379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 197948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1634260 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 117282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1941527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51552253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 198022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 117282 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315305 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489865 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529361 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657482 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47657140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 198022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2166610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 116704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1944106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51551453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 197948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 116704 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 657172 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47657379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 197948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2163937 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 117282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2599009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54228961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293522 # Total number of read requests seen -system.physmem.writeReqs 813187 # Total number of write requests seen -system.physmem.cpureqs 218489 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978785408 # Total number of bytes read from memory -system.physmem.bytesWritten 52043968 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131009132 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6802288 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4667 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955614 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956031 # Track reads on a per bank basis +system.physmem.bw_total::cpu1.inst 116704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2601278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54227949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293480 # Total number of read requests seen +system.physmem.writeReqs 813178 # Total number of write requests seen +system.physmem.cpureqs 218453 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978782720 # Total number of bytes read from memory +system.physmem.bytesWritten 52043392 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131006444 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4682 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955733 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955667 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955442 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955569 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956164 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956098 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955607 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955922 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956025 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 955431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955324 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955982 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50430 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50809 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 955322 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50413 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50859 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51371 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50904 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50728 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51236 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1856598 # Number of times wr buffer was full causing retry -system.physmem.totGap 2541287063000 # Total gap between requests +system.physmem.numWrRetry 32469 # Number of times wr buffer was full causing retry +system.physmem.totGap 2541274319500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154663 # Categorize read packet sizes +system.physmem.readPktSize::6 154621 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59159 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 992041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2698919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60155 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59150 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054746 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2723048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2699101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60161 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 59416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -168,46 +168,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32483 # What write queue length does an incoming req see -system.physmem.totQLat 346675714750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439850413500 # Sum of mem lat for all requests -system.physmem.totBusLat 76467555000 # Total cycles spent in databus access -system.physmem.totBankLat 16707143750 # Total cycles spent in bank access -system.physmem.avgQLat 22668.16 # Average queueing delay per request -system.physmem.avgBankLat 1092.43 # Average bank access latency per request +system.physmem.wrQLenPdf::18 35256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32475 # What write queue length does an incoming req see +system.physmem.totQLat 346695398500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439867444750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467350000 # Total cycles spent in databus access +system.physmem.totBankLat 16704696250 # Total cycles spent in bank access +system.physmem.avgQLat 22669.51 # Average queueing delay per request +system.physmem.avgBankLat 1092.28 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28760.59 # Average memory access latency +system.physmem.avgMemAccLat 28761.78 # Average memory access latency system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s @@ -215,235 +215,235 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.14 # Average write queue length over time -system.physmem.readRowHits 15218363 # Number of row buffer hits during reads -system.physmem.writeRowHits 794663 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.12 # Average write queue length over time +system.physmem.readRowHits 15218335 # Number of row buffer hits during reads +system.physmem.writeRowHits 794661 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes -system.physmem.avgGap 157778.17 # Average gap between requests -system.l2c.replacements 64431 # number of replacements -system.l2c.tagsinuse 51403.772051 # Cycle average of tags in use -system.l2c.total_refs 1904252 # Total number of references to valid blocks. -system.l2c.sampled_refs 129822 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.668176 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2505297860000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36947.477101 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 17.181776 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.004228 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5147.781121 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3278.488158 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 8.683561 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3058.770363 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2945.385742 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563774 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000262 # Average percentage of cache occupancy +system.physmem.avgGap 157777.88 # Average gap between requests +system.l2c.replacements 64389 # number of replacements +system.l2c.tagsinuse 51396.917216 # Cycle average of tags in use +system.l2c.total_refs 1903765 # Total number of references to valid blocks. +system.l2c.sampled_refs 129779 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.669284 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2505294633000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36944.332930 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 18.025643 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5127.291089 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3277.380324 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 9.553076 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3076.231813 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2944.101992 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563726 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000275 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078549 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.050026 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000133 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.046673 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044943 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784359 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32227 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7171 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 490580 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 213578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30476 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6774 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 480341 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 174067 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435214 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608440 # number of Writeback hits -system.l2c.Writeback_hits::total 608440 # number of Writeback hits +system.l2c.occ_percent::cpu0.inst 0.078236 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.050009 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000146 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.046940 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044923 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784255 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32015 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7355 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 491964 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 214249 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30395 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6870 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 478610 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 173362 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1434820 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608422 # number of Writeback hits +system.l2c.Writeback_hits::total 608422 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57838 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55045 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112883 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32227 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7171 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 490580 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 271416 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30476 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6774 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 480341 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 229112 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548097 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32227 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7171 # number of overall hits -system.l2c.overall_hits::cpu0.inst 490580 # number of overall hits -system.l2c.overall_hits::cpu0.data 271416 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30476 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6774 # number of overall hits -system.l2c.overall_hits::cpu1.inst 480341 # number of overall hits -system.l2c.overall_hits::cpu1.data 229112 # number of overall hits -system.l2c.overall_hits::total 1548097 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7754 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6099 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57870 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55015 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112885 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32015 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7355 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 491964 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 272119 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5052330 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84119678267 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82847227004 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166971957601 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10487963006 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13201284574 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 23689247580 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050830 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94648810575 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95938677921 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 190592539326 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027591 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025787 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015847 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988372 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988448 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.988408 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5052330 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94607641273 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96048511578 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190661205181 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025807 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015817 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988424 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990607 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.989452 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508840 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571050 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541281 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091706 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091706 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44257.251609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46034.955512 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44333.289689 # average ReadReq mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508276 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571571 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541302 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091708 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091708 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44222.681044 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46327.958415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44435.697238 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10052.097882 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.130045 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10055.671772 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.775447 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39846.195494 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.299468 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38438.418461 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39592.848256 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37458.838234 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38417.087453 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -634,155 +634,155 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7613725 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6072642 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 379429 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4956500 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4052223 # Number of BTB hits +system.cpu0.branchPred.lookups 7621777 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6075515 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 381764 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4964344 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4051622 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.755735 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 731018 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.614449 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 732539 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39625 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26054269 # DTB read hits -system.cpu0.dtb.read_misses 40148 # DTB read misses -system.cpu0.dtb.write_hits 5888543 # DTB write hits -system.cpu0.dtb.write_misses 9328 # DTB write misses +system.cpu0.dtb.read_hits 26065013 # DTB read hits +system.cpu0.dtb.read_misses 39990 # DTB read misses +system.cpu0.dtb.write_hits 5895229 # DTB write hits +system.cpu0.dtb.write_misses 9395 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1467 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 272 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5652 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1415 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 635 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26094417 # DTB read accesses -system.cpu0.dtb.write_accesses 5897871 # DTB write accesses +system.cpu0.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26105003 # DTB read accesses +system.cpu0.dtb.write_accesses 5904624 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31942812 # DTB hits -system.cpu0.dtb.misses 49476 # DTB misses -system.cpu0.dtb.accesses 31992288 # DTB accesses -system.cpu0.itb.inst_hits 6107608 # ITB inst hits -system.cpu0.itb.inst_misses 7459 # ITB inst misses +system.cpu0.dtb.hits 31960242 # DTB hits +system.cpu0.dtb.misses 49385 # DTB misses +system.cpu0.dtb.accesses 32009627 # DTB accesses +system.cpu0.itb.inst_hits 6121620 # ITB inst hits +system.cpu0.itb.inst_misses 7590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2620 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2650 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1567 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1597 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6115067 # ITB inst accesses -system.cpu0.itb.hits 6107608 # DTB hits -system.cpu0.itb.misses 7459 # DTB misses -system.cpu0.itb.accesses 6115067 # DTB accesses -system.cpu0.numCycles 239065725 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6129210 # ITB inst accesses +system.cpu0.itb.hits 6121620 # DTB hits +system.cpu0.itb.misses 7590 # DTB misses +system.cpu0.itb.accesses 6129210 # DTB accesses +system.cpu0.numCycles 238950356 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15475182 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47810378 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7613725 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4783241 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10599303 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2556412 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 92588 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49524214 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1680 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 51259 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101215 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6105640 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 396425 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3088 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77615764 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.762044 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119690 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15511561 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47861098 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7621777 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4784161 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10616760 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2562446 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 93609 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49488171 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1985 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 51736 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101083 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6119617 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 397619 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3186 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77638963 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.762623 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119947 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67024086 86.35% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 687549 0.89% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 884780 1.14% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1227446 1.58% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1139052 1.47% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 576391 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1322616 1.70% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 397461 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4356383 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67029800 86.34% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 691008 0.89% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 886701 1.14% 88.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1229558 1.58% 89.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1143059 1.47% 91.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 577576 0.74% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1327799 1.71% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 398469 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4354993 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77615764 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.199988 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16521961 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49260251 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9602479 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 548826 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1680126 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1023427 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90450 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56271590 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 301516 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1680126 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17454704 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18993172 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27018669 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9147780 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3319243 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53454491 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13507 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 621630 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2155035 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 566 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55623215 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243327513 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243280007 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47506 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40387894 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15235321 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429274 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381163 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6745844 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10343403 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6774259 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1062911 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1310407 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49609262 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1043693 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63170275 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 95774 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10510467 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26507766 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 267313 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77615764 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.813885 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519252 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77638963 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031897 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.200297 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16561693 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49223207 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9616319 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 551624 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1684026 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1027423 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90511 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56351612 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 302709 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1684026 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17495833 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18963913 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27008828 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9162852 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3321475 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53533397 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13490 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 620965 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2156088 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 544 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55691405 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243710313 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243662711 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47602 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40470990 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15220415 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429980 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381705 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6754845 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10370790 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6781090 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1064335 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1313359 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49665444 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1039347 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63215993 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96269 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10485149 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26517521 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 261916 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77638963 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.814230 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519509 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54780189 70.58% 70.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7210578 9.29% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3685843 4.75% 84.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3149398 4.06% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6278761 8.09% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1404530 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 809241 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231115 0.30% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66109 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54786055 70.57% 70.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7213649 9.29% 79.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3700645 4.77% 84.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3137751 4.04% 88.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6288496 8.10% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1404757 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 809185 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 232478 0.30% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65947 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77615764 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77638963 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29823 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29964 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 4 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available @@ -810,13 +810,13 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4228133 94.76% 95.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 204148 4.58% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4227609 94.71% 95.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 206392 4.62% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195616 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29937335 47.39% 47.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46928 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195815 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29964622 47.40% 47.71% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46968 0.07% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued @@ -832,7 +832,7 @@ system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued @@ -840,474 +840,474 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1205 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26771956 42.38% 90.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6217218 9.84% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26783752 42.37% 90.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6223613 9.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63170275 # Type of FU issued -system.cpu0.iq.rate 0.264238 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4462107 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070636 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208551330 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61172484 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44142185 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12154 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6481 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5464 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67430354 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6412 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323195 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63215993 # Type of FU issued +system.cpu0.iq.rate 0.264557 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4463969 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070615 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208668164 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61198847 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44188793 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12222 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6485 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5502 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67477689 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6458 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 323157 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2268860 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3534 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16121 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 886667 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2276582 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3606 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15957 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 887836 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17166750 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367684 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17155494 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367481 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1680126 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14230285 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 233349 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50770143 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105944 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10343403 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6774259 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 742754 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56167 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3335 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16121 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186307 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146952 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 333259 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62002420 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26414016 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1167855 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1684026 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14200734 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 233893 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50821833 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107458 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10370790 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6781090 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 738100 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56554 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3388 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15957 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 188011 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 147687 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 335698 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62040059 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26425172 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1175934 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117188 # number of nop insts executed -system.cpu0.iew.exec_refs 32573974 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6027717 # Number of branches executed -system.cpu0.iew.exec_stores 6159958 # Number of stores executed -system.cpu0.iew.exec_rate 0.259353 # Inst execution rate -system.cpu0.iew.wb_sent 61473665 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44147649 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24301400 # num instructions producing a value -system.cpu0.iew.wb_consumers 44653762 # num instructions consuming a value +system.cpu0.iew.exec_nop 117042 # number of nop insts executed +system.cpu0.iew.exec_refs 32592128 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6029174 # Number of branches executed +system.cpu0.iew.exec_stores 6166956 # Number of stores executed +system.cpu0.iew.exec_rate 0.259636 # Inst execution rate +system.cpu0.iew.wb_sent 61509785 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44194295 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24341972 # num instructions producing a value +system.cpu0.iew.wb_consumers 44715542 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184667 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544218 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184952 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544374 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10356873 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 776380 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 290234 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75935638 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.525589 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.508198 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10343604 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 777431 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 292475 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75954937 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.526454 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.509299 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61722766 81.28% 81.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6904437 9.09% 90.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2039889 2.69% 93.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1134781 1.49% 94.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1032872 1.36% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547307 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 702356 0.92% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 369637 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1481593 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61716542 81.25% 81.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6915967 9.11% 90.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2042261 2.69% 93.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1137231 1.50% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1037452 1.37% 95.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 547322 0.72% 96.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 703732 0.93% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 369670 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1484760 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75935638 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31265183 # Number of instructions committed -system.cpu0.commit.committedOps 39910920 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75954937 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31329293 # Number of instructions committed +system.cpu0.commit.committedOps 39986762 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13962135 # Number of memory references committed -system.cpu0.commit.loads 8074543 # Number of loads committed -system.cpu0.commit.membars 212305 # Number of memory barriers committed -system.cpu0.commit.branches 5202337 # Number of branches committed -system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35261936 # Number of committed integer instructions. -system.cpu0.commit.function_calls 513908 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1481593 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13987462 # Number of memory references committed +system.cpu0.commit.loads 8094208 # Number of loads committed +system.cpu0.commit.membars 212609 # Number of memory barriers committed +system.cpu0.commit.branches 5213704 # Number of branches committed +system.cpu0.commit.fp_insts 5481 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35328328 # Number of committed integer instructions. +system.cpu0.commit.function_calls 514863 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1484760 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123744681 # The number of ROB reads -system.cpu0.rob.rob_writes 102258102 # The number of ROB writes -system.cpu0.timesIdled 883709 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161449961 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289675923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31185911 # Number of Instructions Simulated -system.cpu0.committedOps 39831648 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31185911 # Number of Instructions Simulated -system.cpu0.cpi 7.665825 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.665825 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130449 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130449 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280645626 # number of integer regfile reads -system.cpu0.int_regfile_writes 45419186 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22697 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15480369 # number of misc regfile reads -system.cpu0.misc_regfile_writes 429671 # number of misc regfile writes -system.cpu0.icache.replacements 983987 # number of replacements -system.cpu0.icache.tagsinuse 511.561827 # Cycle average of tags in use -system.cpu0.icache.total_refs 11034736 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984499 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.208479 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123824951 # The number of ROB reads +system.cpu0.rob.rob_writes 102387078 # The number of ROB writes +system.cpu0.timesIdled 884056 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161311393 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289794473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31249850 # Number of Instructions Simulated +system.cpu0.committedOps 39907319 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31249850 # Number of Instructions Simulated +system.cpu0.cpi 7.646448 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.646448 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130780 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130780 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280856495 # number of integer regfile reads +system.cpu0.int_regfile_writes 45466199 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22714 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19802 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15537514 # number of misc regfile reads +system.cpu0.misc_regfile_writes 430329 # number of misc regfile writes +system.cpu0.icache.replacements 983581 # number of replacements +system.cpu0.icache.tagsinuse 511.609112 # Cycle average of tags in use +system.cpu0.icache.total_refs 11036717 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984093 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.215116 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 357.606132 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 153.955695 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.698449 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.300695 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5565566 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5469170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11034736 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5565566 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5469170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11034736 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5565566 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5469170 # number of overall hits -system.cpu0.icache.overall_hits::total 11034736 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539949 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 524997 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1064946 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539949 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 524997 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1064946 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539949 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 524997 # number of overall misses -system.cpu0.icache.overall_misses::total 1064946 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7306962994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971237994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14278200988 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7306962994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6971237994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14278200988 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7306962994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6971237994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14278200988 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6105515 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5994167 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12099682 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6105515 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5994167 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12099682 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6105515 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5994167 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12099682 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088436 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087585 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.088014 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088436 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087585 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.088014 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088436 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087585 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.088014 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13532.691039 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13278.624438 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.441305 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13407.441305 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13407.441305 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4578 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 356.975852 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 154.633260 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.697218 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.302018 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999237 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5578101 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5458616 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11036717 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5578101 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5458616 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11036717 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5578101 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5458616 # number of overall hits +system.cpu0.icache.overall_hits::total 11036717 # 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number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7337521992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6947086995 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14284608987 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7337521992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6947086995 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14284608987 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6119492 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5981837 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12101329 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6119492 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5981837 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71655500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73661500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 333450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 301692 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635142 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 333450 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 301692 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635142 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2906449500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2315533500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5221983000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3953585991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4507381433 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8460967424 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71518000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74200000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145718000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 144000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6872974486 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6813593935 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13686568421 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6872974486 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6813593935 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13686568421 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91950216500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90410818500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361035000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14891141407 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18622831131 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33513972538 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 133000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6860035491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6822914933 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13682950424 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6860035491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6822914933 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13682950424 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91872733500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90487640000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182360373500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14914514407 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18644008670 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33558523077 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106841357907 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109033649631 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875007538 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028325 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024716 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025590 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046091 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048965 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047481 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106787247907 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109131648670 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215918896577 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028326 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024690 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023095 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025632 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046183 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048892 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047493 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000047 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13570.863488 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13459.536635 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.104300 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33324.999044 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34625.388955 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.412143 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11721.822346 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12099.457950 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.253258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025661 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025661 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13564.742258 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13467.180221 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.307392 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33171.842019 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34738.167387 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33988.251790 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.981243 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.954927 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11934.316134 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1322,155 +1322,155 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7039242 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5645782 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 344121 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4649860 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3812908 # Number of BTB hits +system.cpu1.branchPred.lookups 7016100 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5626613 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 342958 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4632911 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3801004 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.000490 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 671568 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34742 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.043536 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 670740 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35021 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25307959 # DTB read hits -system.cpu1.dtb.read_misses 36376 # DTB read misses -system.cpu1.dtb.write_hits 5825723 # DTB write hits -system.cpu1.dtb.write_misses 9311 # DTB write misses +system.cpu1.dtb.read_hits 25297638 # DTB read hits +system.cpu1.dtb.read_misses 36209 # DTB read misses +system.cpu1.dtb.write_hits 5817747 # DTB write hits +system.cpu1.dtb.write_misses 9250 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5515 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1387 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5517 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1319 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 651 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25344335 # DTB read accesses -system.cpu1.dtb.write_accesses 5835034 # DTB write accesses +system.cpu1.dtb.perms_faults 648 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25333847 # DTB read accesses +system.cpu1.dtb.write_accesses 5826997 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31133682 # DTB hits -system.cpu1.dtb.misses 45687 # DTB misses -system.cpu1.dtb.accesses 31179369 # DTB accesses -system.cpu1.itb.inst_hits 5996114 # ITB inst hits -system.cpu1.itb.inst_misses 6834 # ITB inst misses +system.cpu1.dtb.hits 31115385 # DTB hits +system.cpu1.dtb.misses 45459 # DTB misses +system.cpu1.dtb.accesses 31160844 # DTB accesses +system.cpu1.itb.inst_hits 5983825 # ITB inst hits +system.cpu1.itb.inst_misses 6876 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2600 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1422 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6002948 # ITB inst accesses -system.cpu1.itb.hits 5996114 # DTB hits -system.cpu1.itb.misses 6834 # DTB misses -system.cpu1.itb.accesses 6002948 # DTB accesses -system.cpu1.numCycles 234172204 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5990701 # ITB inst accesses +system.cpu1.itb.hits 5983825 # DTB hits +system.cpu1.itb.misses 6876 # DTB misses +system.cpu1.itb.accesses 5990701 # DTB accesses +system.cpu1.numCycles 234271094 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15150430 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46599302 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7039242 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4484476 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10276938 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2612454 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82512 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47518747 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2108 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 42921 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94711 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 94 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5994168 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 443200 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2937 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74957939 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773072 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.138667 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15106075 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46495215 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7016100 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4471744 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10263244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2607774 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 83065 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47539930 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2033 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42850 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94637 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 151 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5981839 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 442153 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2974 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74917861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.771750 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.136158 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64688840 86.30% 86.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 619651 0.83% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 831575 1.11% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1205005 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1040099 1.39% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 534718 0.71% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1368218 1.83% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351871 0.47% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4317962 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64662198 86.31% 86.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 618220 0.83% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 830780 1.11% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1202992 1.61% 89.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1054171 1.41% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 533923 0.71% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1365534 1.82% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 350745 0.47% 94.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4299298 5.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74957939 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030060 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.198996 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16159118 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47313522 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9319419 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 458702 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1705045 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 945660 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85957 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54861176 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 287371 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1705045 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17094797 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18547389 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25741637 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8764339 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3102678 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51699813 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7117 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 482642 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2122595 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 48 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53761457 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237355866 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237312988 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42878 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38005573 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15755883 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 403501 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 357316 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6247551 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9846699 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6699378 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 894839 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1124277 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47671789 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 942558 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60820762 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 80974 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10554667 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27991193 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236389 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74957939 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811399 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521506 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74917861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029949 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.198468 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16114785 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47334136 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9307437 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 457642 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1701687 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 943149 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85752 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54765911 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286536 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1701687 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17049791 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18574833 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25739106 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8750674 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3099680 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51604165 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7083 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 481938 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2120083 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 47 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53629483 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 236928405 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 236886159 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42246 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37922365 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15707117 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 402858 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 356707 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6241200 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9820106 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6689053 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 876297 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1123238 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47543883 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 946480 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60738625 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 81609 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10509389 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27830287 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 241377 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74917861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.810736 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521004 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53217841 71.00% 71.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6660852 8.89% 79.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3522155 4.70% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2891310 3.86% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6221103 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1440067 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 734950 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210065 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59596 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53210773 71.03% 71.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6641164 8.86% 79.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3529295 4.71% 84.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2876551 3.84% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6221124 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1436861 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 733077 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210173 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 58843 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74957939 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74917861 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24217 0.55% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24144 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available @@ -1498,148 +1498,148 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4143294 94.86% 95.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 200406 4.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4145479 94.86% 95.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200357 4.58% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 168050 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28446121 46.77% 47.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46643 0.08% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 906 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26040786 42.82% 89.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6118237 10.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 167851 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28384328 46.73% 47.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46613 0.08% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 903 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26029174 42.85% 89.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6109728 10.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60820762 # Type of FU issued -system.cpu1.iq.rate 0.259727 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4367918 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071816 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201083162 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59177242 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41793523 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10683 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5961 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4808 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65014989 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5641 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 303389 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60738625 # Type of FU issued +system.cpu1.iq.rate 0.259266 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4369980 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071947 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 200881299 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59008077 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41690782 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10661 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5857 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4774 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 64935130 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5624 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 302237 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2265840 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3135 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14672 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 854347 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2258994 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3096 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14702 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 849711 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16937147 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 456872 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16948413 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 457547 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1705045 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13964953 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229910 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48720174 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98231 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9846699 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6699378 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 669323 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49676 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3736 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14672 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 165888 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133425 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 299313 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59456626 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25635805 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1364136 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1701687 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13992381 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229468 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48596033 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98735 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9820106 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6689053 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 673721 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49557 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3683 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14702 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 165794 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 132525 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 298319 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59364884 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25624684 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1373741 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105827 # number of nop insts executed -system.cpu1.iew.exec_refs 31702395 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5527346 # Number of branches executed -system.cpu1.iew.exec_stores 6066590 # Number of stores executed -system.cpu1.iew.exec_rate 0.253901 # Inst execution rate -system.cpu1.iew.wb_sent 58878116 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41798331 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22764679 # num instructions producing a value -system.cpu1.iew.wb_consumers 41753721 # num instructions consuming a value +system.cpu1.iew.exec_nop 105670 # number of nop insts executed +system.cpu1.iew.exec_refs 31682928 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5509079 # Number of branches executed +system.cpu1.iew.exec_stores 6058244 # Number of stores executed +system.cpu1.iew.exec_rate 0.253403 # Inst execution rate +system.cpu1.iew.wb_sent 58786539 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41695556 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22722145 # num instructions producing a value +system.cpu1.iew.wb_consumers 41696703 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178494 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545213 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177980 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.544939 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10481198 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 706169 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 259373 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73252894 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516596 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.497283 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10421777 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 705103 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 258416 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73216174 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.515817 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.496135 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59734394 81.55% 81.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6658117 9.09% 90.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1908666 2.61% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1009766 1.38% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 959602 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 525640 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 705032 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 372807 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1378870 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59718106 81.56% 81.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6653283 9.09% 90.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1904372 2.60% 93.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1008936 1.38% 94.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 956792 1.31% 95.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 521917 0.71% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 703785 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 374006 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1374977 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73252894 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29195437 # Number of instructions committed -system.cpu1.commit.committedOps 37842156 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73216174 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29131232 # Number of instructions committed +system.cpu1.commit.committedOps 37766156 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13425890 # Number of memory references committed -system.cpu1.commit.loads 7580859 # Number of loads committed -system.cpu1.commit.membars 191347 # Number of memory barriers committed -system.cpu1.commit.branches 4759387 # Number of branches committed -system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33596023 # Number of committed integer instructions. -system.cpu1.commit.function_calls 477418 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1378870 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13400454 # Number of memory references committed +system.cpu1.commit.loads 7561112 # Number of loads committed +system.cpu1.commit.membars 191037 # Number of memory barriers committed +system.cpu1.commit.branches 4747981 # Number of branches committed +system.cpu1.commit.fp_insts 4731 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33529515 # Number of committed integer instructions. +system.cpu1.commit.function_calls 476457 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1374977 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119325211 # The number of ROB reads -system.cpu1.rob.rob_writes 98404070 # The number of ROB writes -system.cpu1.timesIdled 873125 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159214265 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285839594 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29124328 # Number of Instructions Simulated -system.cpu1.committedOps 37771047 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29124328 # Number of Instructions Simulated -system.cpu1.cpi 8.040433 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.040433 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124371 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124371 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269378788 # number of integer regfile reads -system.cpu1.int_regfile_writes 42887039 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22080 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19702 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14812812 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402828 # number of misc regfile writes +system.cpu1.rob.rob_reads 119155388 # The number of ROB reads +system.cpu1.rob.rob_writes 98129561 # The number of ROB writes +system.cpu1.timesIdled 872896 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159353233 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285655752 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29060294 # Number of Instructions Simulated +system.cpu1.committedOps 37695218 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29060294 # Number of Instructions Simulated +system.cpu1.cpi 8.061553 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.061553 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124046 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124046 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 268946784 # number of integer regfile reads +system.cpu1.int_regfile_writes 42787312 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22150 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19734 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14724221 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402169 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1654,10 +1654,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192668399444 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192668399444 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192686110607 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192686110607 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 5db5edca0..14a2c325e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.132858 # Number of seconds simulated -sim_ticks 5132857897000 # Number of ticks simulated -final_tick 5132857897000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.136865 # Number of seconds simulated +sim_ticks 5136864508000 # Number of ticks simulated +final_tick 5136864508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156379 # Simulator instruction rate (inst/s) -host_op_rate 309121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1967786651 # Simulator tick rate (ticks/s) -host_mem_usage 752412 # Number of bytes of host memory used -host_seconds 2608.44 # Real time elapsed on the host -sim_insts 407905700 # Number of instructions simulated -sim_ops 806325509 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2501312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3200 # Number of bytes read from this memory +host_inst_rate 161248 # Simulator instruction rate (inst/s) +host_op_rate 318747 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2030694494 # Simulator tick rate (ticks/s) +host_mem_usage 783308 # Number of bytes of host memory used +host_seconds 2529.61 # Real time elapsed on the host +sim_insts 407895398 # Number of instructions simulated +sim_ops 806304609 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2499136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1078144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10788736 # Number of bytes read from this memory -system.physmem.bytes_read::total 14371776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1078144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1078144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9560192 # Number of bytes written to this memory -system.physmem.bytes_written::total 9560192 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 39083 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 50 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 1076928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10801024 # Number of bytes read from this memory +system.physmem.bytes_read::total 14380480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1076928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1076928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9561920 # Number of bytes written to this memory +system.physmem.bytes_written::total 9561920 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 39049 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16846 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168574 # Number of read requests responded to by this memory -system.physmem.num_reads::total 224559 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149378 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149378 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 487314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 623 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 16827 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168766 # Number of read requests responded to by this memory +system.physmem.num_reads::total 224695 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149405 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149405 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 486510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 586 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 210048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2101896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2799956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 210048 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 210048 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1862548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1862548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1862548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 487314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 209647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2102649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2799466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 209647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 209647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1861431 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1861431 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1861431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 486510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 586 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 210048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2101896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4662504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 224559 # Total number of read requests seen -system.physmem.writeReqs 149378 # Total number of write requests seen -system.physmem.cpureqs 379116 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 14371776 # Total number of bytes read from memory -system.physmem.bytesWritten 9560192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14371776 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9560192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 86 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3988 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12988 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 13113 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 16256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 16230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13981 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13311 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 15635 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13184 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 13446 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 15958 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9012 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 8453 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 8452 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 11545 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 8811 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8570 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8847 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 11675 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 9048 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8676 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8758 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 11176 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 8354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 8087 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 8705 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 209647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2102649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4660898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 224695 # Total number of read requests seen +system.physmem.writeReqs 149405 # Total number of write requests seen +system.physmem.cpureqs 378068 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 14380480 # Total number of bytes read from memory +system.physmem.bytesWritten 9561920 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14380480 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9561920 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 102 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3959 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 13042 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 13152 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 16282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13201 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13511 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 16248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13928 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13310 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 15618 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 13156 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13394 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 15933 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9055 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 8495 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 8476 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 11557 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8626 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8868 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 11671 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8652 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 8710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 11130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8376 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 8093 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8654 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 11209 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1191 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132857844500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136864456000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 224559 # Categorize read packet sizes +system.physmem.readPktSize::6 224695 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 149378 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 172944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 19784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3483 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3003 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149405 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 173100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 19795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3025 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 817 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 909 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -136,46 +136,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6439 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.totQLat 4795272000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9305637000 # Sum of mem lat for all requests -system.physmem.totBusLat 1122365000 # Total cycles spent in databus access -system.physmem.totBankLat 3388000000 # Total cycles spent in bank access -system.physmem.avgQLat 21362.36 # Average queueing delay per request -system.physmem.avgBankLat 15093.13 # Average bank access latency per request +system.physmem.totQLat 4766626250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9279378750 # Sum of mem lat for all requests +system.physmem.totBusLat 1122965000 # Total cycles spent in databus access +system.physmem.totBankLat 3389787500 # Total cycles spent in bank access +system.physmem.avgQLat 21223.40 # Average queueing delay per request +system.physmem.avgBankLat 15093.02 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41455.48 # Average memory access latency +system.physmem.avgMemAccLat 41316.42 # Average memory access latency system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s @@ -183,45 +183,45 @@ system.physmem.avgConsumedWrBW 1.86 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.03 # Average write queue length over time -system.physmem.readRowHits 193515 # Number of row buffer hits during reads -system.physmem.writeRowHits 105640 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.72 # Row buffer hit rate for writes -system.physmem.avgGap 13726531.06 # Average gap between requests -system.iocache.replacements 47576 # number of replacements -system.iocache.tagsinuse 0.103924 # Cycle average of tags in use +system.physmem.avgWrQLen 11.02 # Average write queue length over time +system.physmem.readRowHits 193644 # Number of row buffer hits during reads +system.physmem.writeRowHits 105706 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.75 # Row buffer hit rate for writes +system.physmem.avgGap 13731260.24 # Average gap between requests +system.iocache.replacements 47574 # number of replacements +system.iocache.tagsinuse 0.116323 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47592 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 4991909238000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.103924 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006495 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006495 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses -system.iocache.ReadReq_misses::total 911 # number of ReadReq misses +system.iocache.occ_blocks::pc.south_bridge.ide 0.116323 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007270 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007270 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses -system.iocache.demand_misses::total 47631 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses -system.iocache.overall_misses::total 47631 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146639932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 146639932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10056560160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10056560160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10203200092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10203200092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10203200092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10203200092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses +system.iocache.demand_misses::total 47629 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses +system.iocache.overall_misses::total 47629 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144901871 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144901871 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10053195615 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10053195615 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10198097486 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10198097486 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10198097486 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10198097486 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -230,40 +230,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160965.896817 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160965.896817 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215251.715753 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 215251.715753 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214213.434360 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 214213.434360 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214213.434360 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 214213.434360 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 137627 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 159407.998900 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 159407.998900 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215179.700664 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 215179.700664 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214115.297109 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 214115.297109 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214115.297109 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 214115.297109 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 138033 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12509 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12531 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.002238 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.015322 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99246962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 99246962 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7625786368 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7625786368 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7725033330 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7725033330 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7725033330 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7725033330 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97611900 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 97611900 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7622408830 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7622408830 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7720020730 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7720020730 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7720020730 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7720020730 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,18 +272,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108942.878156 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 108942.878156 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163223.167123 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 163223.167123 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162184.991497 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162184.991497 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162184.991497 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162184.991497 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107383.828383 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 107383.828383 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163150.873930 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 163150.873930 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162086.559239 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 162086.559239 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162086.559239 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 162086.559239 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -293,142 +293,142 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 86194611 # Number of BP lookups -system.cpu.branchPred.condPredicted 86194611 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1105724 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81284951 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79210874 # Number of BTB hits +system.cpu.branchPred.lookups 86192778 # Number of BP lookups +system.cpu.branchPred.condPredicted 86192778 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1105969 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 81285940 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79207876 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.448387 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 97.443514 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.numCycles 448157181 # number of cpu cycles simulated +system.cpu.numCycles 448117283 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27411589 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 425916361 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86194611 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79210874 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 163569758 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4698258 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 127091 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 63100705 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36134 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 51634 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 488 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9006921 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 482292 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2784 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 257851520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.260962 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.418035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27407295 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 425903825 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86192778 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79207876 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163564309 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4697150 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125610 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 63070837 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 35658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 51192 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 380 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9007924 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 482953 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2789 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 257808166 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.261396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.418051 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94708741 36.73% 36.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1565189 0.61% 37.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71915500 27.89% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 936812 0.36% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1597915 0.62% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2418163 0.94% 67.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1071060 0.42% 67.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1376608 0.53% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 82261532 31.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 94670555 36.72% 36.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1565511 0.61% 37.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71913522 27.89% 65.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 935622 0.36% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1598852 0.62% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2418850 0.94% 67.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1070189 0.42% 67.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1376236 0.53% 68.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 82258829 31.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 257851520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.192331 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.950373 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31130056 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 60542452 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 159362996 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3261895 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3554121 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 837710983 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 948 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3554121 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33866246 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 37401594 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 11010183 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159560886 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12458490 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834077749 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19680 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5867270 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4756403 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 8649 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 995584301 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1810575684 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1810574876 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 808 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964290633 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31293661 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 458949 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 466891 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 28798932 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17055930 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10122177 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1247187 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 990912 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 827964566 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1250540 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 823033686 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 148209 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21990342 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33439565 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 197993 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 257851520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.191890 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.384052 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 257808166 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192344 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.950429 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31124176 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 60511588 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 159357091 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3262426 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3552885 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 837683480 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 953 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3552885 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33860427 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37375460 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 11010468 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159557932 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 12450994 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834052267 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19515 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5867687 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4751018 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8643 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 995567635 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1810525606 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1810524958 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 648 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964273740 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 31293888 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 458980 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 466833 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 28792477 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17053482 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10121038 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1248085 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 996765 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 827936036 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1250306 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 823005910 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 148163 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21984013 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33436004 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 197912 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 257808166 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.192319 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.383919 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 71392246 27.69% 27.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15523930 6.02% 33.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10289230 3.99% 37.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7461063 2.89% 40.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75902807 29.44% 70.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3840005 1.49% 71.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72510870 28.12% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 779318 0.30% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 152051 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71353106 27.68% 27.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15525279 6.02% 33.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10289212 3.99% 37.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7463811 2.90% 40.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75897283 29.44% 70.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3839331 1.49% 71.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72507991 28.12% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 780183 0.30% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 151970 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 257851520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 257808166 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 361997 33.96% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 553138 51.89% 85.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 150897 14.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 363662 34.07% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 553259 51.83% 85.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 150581 14.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 310952 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795510781 96.66% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 310965 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795485356 96.66% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued @@ -457,246 +457,246 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.69% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17835089 2.17% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9376864 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17833485 2.17% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9376104 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 823033686 # Type of FU issued -system.cpu.iq.rate 1.836484 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1066032 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001295 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905263509 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 851215281 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 818564848 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 272 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 382 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823788636 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 130 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1638773 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 823005910 # Type of FU issued +system.cpu.iq.rate 1.836586 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1067502 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905165811 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 851180208 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 818537057 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 213 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 302 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823762347 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 100 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1638684 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3081166 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22705 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11479 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1710957 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3078529 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 22784 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11411 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1710138 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1932446 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12217 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12218 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3554121 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 26141117 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2116575 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 829215106 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 320591 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17055930 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10122177 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 718653 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1615740 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10506 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11479 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 648838 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 592977 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1241815 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 821161230 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17423630 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1872455 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3552885 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 26109999 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2115264 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 829186342 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 321096 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17053482 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10121038 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 718511 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1615692 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10262 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11411 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 648780 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 593291 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1242071 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 821133450 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17423083 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1872459 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26568531 # number of memory reference insts executed -system.cpu.iew.exec_branches 83193011 # Number of branches executed -system.cpu.iew.exec_stores 9144901 # Number of stores executed -system.cpu.iew.exec_rate 1.832306 # Inst execution rate -system.cpu.iew.wb_sent 820700229 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 818564922 # cumulative count of insts written-back -system.cpu.iew.wb_producers 639778882 # num instructions producing a value -system.cpu.iew.wb_consumers 1045529467 # num instructions consuming a value +system.cpu.iew.exec_refs 26567058 # number of memory reference insts executed +system.cpu.iew.exec_branches 83190955 # Number of branches executed +system.cpu.iew.exec_stores 9143975 # Number of stores executed +system.cpu.iew.exec_rate 1.832407 # Inst execution rate +system.cpu.iew.wb_sent 820672114 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 818537115 # cumulative count of insts written-back +system.cpu.iew.wb_producers 639752264 # num instructions producing a value +system.cpu.iew.wb_consumers 1045484939 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.826513 # insts written-back per cycle +system.cpu.iew.wb_rate 1.826614 # insts written-back per cycle system.cpu.iew.wb_fanout 0.611919 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22781132 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1052545 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1110334 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 254297399 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.170797 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.853937 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 22773726 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1052392 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1110510 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 254255281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.171240 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.853929 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82526547 32.45% 32.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11810769 4.64% 37.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3910269 1.54% 38.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74942576 29.47% 68.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2436425 0.96% 69.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1481605 0.58% 69.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 941054 0.37% 70.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70918807 27.89% 97.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5329347 2.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 82490050 32.44% 32.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11810591 4.65% 37.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3912535 1.54% 38.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74936309 29.47% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2436608 0.96% 69.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1481517 0.58% 69.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 940613 0.37% 70.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70914138 27.89% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5332920 2.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 254297399 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407905700 # Number of instructions committed -system.cpu.commit.committedOps 806325509 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 254255281 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407895398 # Number of instructions committed +system.cpu.commit.committedOps 806304609 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22385981 # Number of memory references committed -system.cpu.commit.loads 13974761 # Number of loads committed -system.cpu.commit.membars 473457 # Number of memory barriers committed -system.cpu.commit.branches 82185695 # Number of branches committed +system.cpu.commit.refs 22385850 # Number of memory references committed +system.cpu.commit.loads 13974950 # Number of loads committed +system.cpu.commit.membars 473369 # Number of memory barriers committed +system.cpu.commit.branches 82185287 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735267209 # Number of committed integer instructions. +system.cpu.commit.int_insts 735250581 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5329347 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5332920 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1077996488 # The number of ROB reads -system.cpu.rob.rob_writes 1661786087 # The number of ROB writes -system.cpu.timesIdled 1219722 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 190305661 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9817556036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407905700 # Number of Instructions Simulated -system.cpu.committedOps 806325509 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407905700 # Number of Instructions Simulated -system.cpu.cpi 1.098678 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.098678 # CPI: Total CPI of All Threads -system.cpu.ipc 0.910184 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.910184 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1506617542 # number of integer regfile reads -system.cpu.int_regfile_writes 976738350 # number of integer regfile writes -system.cpu.fp_regfile_reads 74 # number of floating regfile reads -system.cpu.misc_regfile_reads 264608213 # number of misc regfile reads -system.cpu.misc_regfile_writes 402112 # number of misc regfile writes -system.cpu.icache.replacements 1045620 # number of replacements -system.cpu.icache.tagsinuse 510.123573 # Cycle average of tags in use -system.cpu.icache.total_refs 7898000 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1046132 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.549716 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1077922480 # The number of ROB reads +system.cpu.rob.rob_writes 1661728217 # The number of ROB writes +system.cpu.timesIdled 1219694 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 190309117 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9825609154 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407895398 # Number of Instructions Simulated +system.cpu.committedOps 806304609 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407895398 # Number of Instructions Simulated +system.cpu.cpi 1.098608 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.098608 # CPI: Total CPI of All Threads +system.cpu.ipc 0.910243 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.910243 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1506572228 # number of integer regfile reads +system.cpu.int_regfile_writes 976715078 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.misc_regfile_reads 264599077 # number of misc regfile reads +system.cpu.misc_regfile_writes 402085 # number of misc regfile writes +system.cpu.icache.replacements 1045531 # number of replacements +system.cpu.icache.tagsinuse 510.125027 # Cycle average of tags in use +system.cpu.icache.total_refs 7898981 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1046043 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.551297 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.123573 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996335 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996335 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7898000 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7898000 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7898000 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7898000 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7898000 # number of overall hits -system.cpu.icache.overall_hits::total 7898000 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1108918 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1108918 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1108918 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1108918 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1108918 # number of overall misses -system.cpu.icache.overall_misses::total 1108918 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15254848492 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15254848492 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15254848492 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15254848492 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15254848492 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15254848492 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9006918 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9006918 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9006918 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9006918 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9006918 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9006918 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123118 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.123118 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.123118 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.123118 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.123118 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.123118 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13756.516255 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13756.516255 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13756.516255 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13756.516255 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13756.516255 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13756.516255 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 9824 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 510.125027 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996338 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996338 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7898981 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7898981 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7898981 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7898981 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7898981 # number of overall hits +system.cpu.icache.overall_hits::total 7898981 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108941 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108941 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108941 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108941 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108941 # number of overall misses +system.cpu.icache.overall_misses::total 1108941 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15254214993 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15254214993 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15254214993 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15254214993 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15254214993 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15254214993 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9007922 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9007922 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9007922 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9007922 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9007922 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9007922 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123107 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123107 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123107 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123107 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123107 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123107 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13755.659673 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13755.659673 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13755.659673 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13755.659673 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13755.659673 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13755.659673 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 11697 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 280 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.189189 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.775000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60463 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 60463 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 60463 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 60463 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 60463 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 60463 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048455 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1048455 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1048455 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1048455 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1048455 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1048455 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12565081992 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12565081992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12565081992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12565081992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12565081992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12565081992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116406 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.116406 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116406 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.116406 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11984.378912 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11984.378912 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11984.378912 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11984.378912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11984.378912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11984.378912 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60573 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 60573 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 60573 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 60573 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 60573 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 60573 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1048368 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1048368 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1048368 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1048368 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1048368 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1048368 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12562155993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12562155993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12562155993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12562155993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12562155993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12562155993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116383 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116383 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116383 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116383 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116383 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116383 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11982.582445 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11982.582445 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11982.582445 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11982.582445 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11982.582445 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11982.582445 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 9450 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.008249 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 25808 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 9463 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.727254 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5103990002500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.008249 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375516 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.375516 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25828 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25828 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 9623 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.015619 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 25274 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 9637 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.622600 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5103989981500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.015619 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375976 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.375976 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25281 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25281 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25830 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25830 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25830 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25830 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10341 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 10341 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10341 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 10341 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10341 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 10341 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 115658000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 115658000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 115658000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 115658000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 115658000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 115658000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36169 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 36169 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25283 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25283 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25283 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25283 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10506 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 10506 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10506 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 10506 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10506 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 10506 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 117420000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 117420000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 117420000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 117420000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 117420000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 117420000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 35787 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 35787 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36171 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 36171 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36171 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 36171 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.285908 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.285908 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.285892 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.285892 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.285892 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.285892 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11184.411566 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11184.411566 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11184.411566 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11184.411566 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11184.411566 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11184.411566 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 35789 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 35789 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 35789 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 35789 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.293570 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.293570 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.293554 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.293554 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.293554 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.293554 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11176.470588 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11176.470588 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11176.470588 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11176.470588 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11176.470588 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11176.470588 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,78 +705,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1982 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1982 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10341 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10341 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10341 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 10341 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10341 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 10341 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 94976000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 94976000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 94976000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 94976000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 94976000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 94976000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.285908 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.285908 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.285892 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.285892 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.285892 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.285892 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9184.411566 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9184.411566 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9184.411566 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9184.411566 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1917 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1917 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10506 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10506 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10506 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 10506 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10506 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 10506 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96408000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96408000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96408000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96408000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96408000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96408000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.293570 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.293570 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.293554 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.293554 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.293554 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.293554 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9176.470588 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9176.470588 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9176.470588 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9176.470588 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 109668 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.956689 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 133742 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 109682 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.219361 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.replacements 107366 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 12.959117 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 135123 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 107381 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.258351 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5099781673000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.956689 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809793 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.809793 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 133765 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 133765 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 133765 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 133765 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 133765 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 133765 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110693 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 110693 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110693 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 110693 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110693 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 110693 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1390562000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1390562000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1390562000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 1390562000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1390562000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 1390562000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 244458 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 244458 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 244458 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 244458 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 244458 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 244458 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.452810 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.452810 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.452810 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.452810 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.452810 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.452810 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12562.330048 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12562.330048 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12562.330048 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12562.330048 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12562.330048 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12562.330048 # average overall miss latency +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.959117 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.809945 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.809945 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135139 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 135139 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135139 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 135139 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135139 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 135139 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 108408 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 108408 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 108408 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 108408 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108408 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 108408 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1365628000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1365628000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1365628000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 1365628000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1365628000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 1365628000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243547 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 243547 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243547 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 243547 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243547 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 243547 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.445121 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.445121 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.445121 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.445121 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.445121 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.445121 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12597.114604 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12597.114604 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12597.114604 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12597.114604 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12597.114604 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12597.114604 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -785,146 +785,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 35480 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 35480 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110693 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110693 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110693 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 110693 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110693 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 110693 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1169176000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1169176000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1169176000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1169176000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.452810 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.452810 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.452810 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.452810 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10562.330048 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10562.330048 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10562.330048 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10562.330048 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 35267 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 35267 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 108408 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 108408 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 108408 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 108408 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 108408 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 108408 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1148812000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1148812000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1148812000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1148812000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.445121 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.445121 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.445121 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.445121 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10597.114604 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10597.114604 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10597.114604 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10597.114604 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1659150 # number of replacements -system.cpu.dcache.tagsinuse 511.992464 # Cycle average of tags in use -system.cpu.dcache.total_refs 19077771 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1659662 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.494974 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1660204 # number of replacements +system.cpu.dcache.tagsinuse 511.993130 # Cycle average of tags in use +system.cpu.dcache.total_refs 19074634 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1660716 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.485789 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.992464 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10988579 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10988579 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8084208 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8084208 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19072787 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19072787 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19072787 # number of overall hits -system.cpu.dcache.overall_hits::total 19072787 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2233798 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2233798 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317777 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317777 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2551575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2551575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2551575 # number of overall misses -system.cpu.dcache.overall_misses::total 2551575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32133763000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32133763000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9654013491 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9654013491 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41787776491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41787776491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41787776491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41787776491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13222377 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13222377 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8401985 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8401985 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21624362 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21624362 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21624362 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21624362 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168941 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.168941 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037822 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037822 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117995 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117995 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117995 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117995 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14385.259097 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14385.259097 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30379.837090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30379.837090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16377.247971 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16377.247971 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16377.247971 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16377.247971 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 403205 # number of cycles access was blocked +system.cpu.dcache.occ_blocks::cpu.data 511.993130 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10985848 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10985848 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8083807 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8083807 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19069655 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19069655 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19069655 # number of overall hits +system.cpu.dcache.overall_hits::total 19069655 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2236198 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2236198 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317897 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317897 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2554095 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2554095 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2554095 # number of overall misses +system.cpu.dcache.overall_misses::total 2554095 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32136809500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32136809500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9657348993 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9657348993 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41794158493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41794158493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41794158493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41794158493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13222046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13222046 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8401704 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8401704 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21623750 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21623750 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21623750 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21623750 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169126 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.169126 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037837 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118115 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118115 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118115 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118115 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14371.182471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14371.182471 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30378.861685 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30378.861685 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16363.588078 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16363.588078 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16363.588078 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16363.588078 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 398738 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42533 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42519 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.479816 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.377878 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560680 # number of writebacks -system.cpu.dcache.writebacks::total 1560680 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862352 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 862352 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25015 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25015 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 887367 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 887367 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 887367 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 887367 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371446 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1371446 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 292762 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 292762 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1664208 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1664208 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1664208 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1664208 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17485386500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17485386500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8810445491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8810445491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26295831991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26295831991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26295831991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26295831991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296686000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296686000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470456500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470456500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767142500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767142500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103722 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103722 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076960 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076960 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076960 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076960 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7306325074 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8271727351 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89185441500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89185441500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2304074500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2304074500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91489516000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91489516000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000463 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000737 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016087 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026892 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.915322 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915322 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459746 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459746 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000463 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000737 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016087 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102225 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.066263 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000463 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000737 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016087 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102225 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.066263 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57080.359789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56744.791619 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56901.366120 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10267.149704 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10267.149704 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39409.463271 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39409.463271 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57028.999762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56326.692819 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56598.443800 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10260.489962 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10260.489962 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39367.440588 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39367.440588 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57080.359789 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43179.924798 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44454.977116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 112595.920000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57028.999762 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43052.331499 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44331.507659 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 116192.404255 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57080.359789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43179.924798 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44454.977116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57028.999762 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43052.331499 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44331.507659 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index fbbf2dd62..8e79dde0f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,26 +4,26 @@ sim_seconds 5.204983 # Nu sim_ticks 5204982530500 # Number of ticks simulated final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107235 # Simulator instruction rate (inst/s) -host_op_rate 205734 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5169140013 # Simulator tick rate (ticks/s) -host_mem_usage 810688 # Number of bytes of host memory used -host_seconds 1006.93 # Real time elapsed on the host -sim_insts 107979054 # Number of instructions simulated -sim_ops 207160582 # Number of ops (including micro ops) simulated +host_inst_rate 97445 # Simulator instruction rate (inst/s) +host_op_rate 186950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4697195864 # Simulator tick rate (ticks/s) +host_mem_usage 811856 # Number of bytes of host memory used +host_seconds 1108.10 # Real time elapsed on the host +sim_insts 107979048 # Number of instructions simulated +sim_ops 207160548 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 137616 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 65352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 864449224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 69078733 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 864449144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 69078721 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 87568 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 42392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 160961632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 27339818 # Number of bytes read from this memory -system.physmem.bytes_read::total 1122197487 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 864449224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 160961632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1025410856 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 160961656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 27339822 # Number of bytes read from this memory +system.physmem.bytes_read::total 1122197423 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 864449144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 160961656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1025410800 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 48342743 # Number of bytes written to this memory @@ -32,13 +32,13 @@ system.physmem.bytes_written::total 72643771 # Nu system.physmem.num_reads::pc.south_bridge.ide 810 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 17202 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 8169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 108056153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 12053065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 108056143 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 12053062 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 10946 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 5299 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 20120204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 4057615 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144329463 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 20120207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 4057616 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144329454 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 7125507 # Number of write requests responded to by this memory @@ -47,16 +47,16 @@ system.physmem.num_writes::total 10106709 # Nu system.physmem.bw_read::pc.south_bridge.ide 6754 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 26439 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 12556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 166081100 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13271655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 166081085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13271653 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 16824 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 8145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 30924529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5252624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 215600625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 166081100 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 30924529 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197005629 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 30924533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5252625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 215600613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 166081085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 30924533 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197005618 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 574662 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 9287782 # Write bandwidth from this memory (bytes/s) @@ -65,16 +65,16 @@ system.physmem.bw_write::total 13956583 # Wr system.physmem.bw_total::pc.south_bridge.ide 581415 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 26439 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 12559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 166081100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 22559437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 166081085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 22559435 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 16824 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 8145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 30924529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 30924533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 9346761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 229557208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 229557196 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 810 # Total number of read requests seen system.physmem.writeReqs 46736 # Total number of write requests seen -system.physmem.cpureqs 48918 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 47278 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 51840 # Total number of bytes read from memory system.physmem.bytesWritten 2991104 # Total number of bytes written to memory system.physmem.bytesConsumedRd 35152 # bytesRead derated as per pkt->getSize() @@ -114,7 +114,7 @@ system.physmem.perBankWrReqs::13 2864 # Tr system.physmem.perBankWrReqs::14 3048 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 3040 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1670 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry system.physmem.totGap 63182142000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -278,23 +278,23 @@ system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 system.cpu0.numCycles 10407785676 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 92551747 # Number of instructions committed -system.cpu0.committedOps 178518572 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 168457773 # Number of integer alu accesses +system.cpu0.committedInsts 92551738 # Number of instructions committed +system.cpu0.committedOps 178518541 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 168457745 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16414014 # number of instructions that are conditional controls -system.cpu0.num_int_insts 168457773 # number of integer instructions +system.cpu0.num_conditional_control_insts 16414009 # number of instructions that are conditional controls +system.cpu0.num_int_insts 168457745 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 415888554 # number of times the integer registers were read -system.cpu0.num_int_register_writes 210334552 # number of times the integer registers were written +system.cpu0.num_int_register_reads 415888462 # number of times the integer registers were read +system.cpu0.num_int_register_writes 210334505 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 20039559 # number of memory refs -system.cpu0.num_load_insts 12899832 # Number of load instructions +system.cpu0.num_mem_refs 20039556 # number of memory refs +system.cpu0.num_load_insts 12899829 # Number of load instructions system.cpu0.num_store_insts 7139727 # Number of store instructions -system.cpu0.num_idle_cycles 9669887298.959074 # Number of idle cycles -system.cpu0.num_busy_cycles 737898377.040926 # Number of busy cycles +system.cpu0.num_idle_cycles 9669887390.939814 # Number of idle cycles +system.cpu0.num_busy_cycles 737898285.060187 # Number of busy cycles system.cpu0.not_idle_fraction 0.070899 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.929101 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -302,23 +302,23 @@ system.cpu0.kern.inst.quiesce 0 # nu system.cpu1.numCycles 10409965061 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15427307 # Number of instructions committed -system.cpu1.committedOps 28642010 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 28123688 # Number of integer alu accesses +system.cpu1.committedInsts 15427310 # Number of instructions committed +system.cpu1.committedOps 28642007 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 28123684 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1978312 # number of instructions that are conditional controls -system.cpu1.num_int_insts 28123688 # number of integer instructions +system.cpu1.num_conditional_control_insts 1978311 # number of instructions that are conditional controls +system.cpu1.num_int_insts 28123684 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 73029248 # number of times the integer registers were read -system.cpu1.num_int_register_writes 31865943 # number of times the integer registers were written +system.cpu1.num_int_register_reads 73029212 # number of times the integer registers were read +system.cpu1.num_int_register_writes 31865924 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 7025199 # number of memory refs -system.cpu1.num_load_insts 4066765 # Number of load instructions +system.cpu1.num_mem_refs 7025200 # number of memory refs +system.cpu1.num_load_insts 4066766 # Number of load instructions system.cpu1.num_store_insts 2958434 # Number of store instructions -system.cpu1.num_idle_cycles 10280018133.934025 # Number of idle cycles -system.cpu1.num_busy_cycles 129946927.065975 # Number of busy cycles +system.cpu1.num_idle_cycles 10280018132.934025 # Number of idle cycles +system.cpu1.num_busy_cycles 129946928.065975 # Number of busy cycles system.cpu1.not_idle_fraction 0.012483 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.987517 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 83f6a1bd8..f6859d15c 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.199930 # Number of seconds simulated -sim_ticks 199930442500 # Number of ticks simulated -final_tick 199930442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.199979 # Number of seconds simulated +sim_ticks 199978768500 # Number of ticks simulated +final_tick 199978768500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127290 # Simulator instruction rate (inst/s) -host_op_rate 143512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50370674 # Simulator tick rate (ticks/s) -host_mem_usage 265580 # Number of bytes of host memory used -host_seconds 3969.18 # Real time elapsed on the host +host_inst_rate 109627 # Simulator instruction rate (inst/s) +host_op_rate 123597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43391530 # Simulator tick rate (ticks/s) +host_mem_usage 297064 # Number of bytes of host memory used +host_seconds 4608.71 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9265152 # Number of bytes read from this memory -system.physmem.bytes_read::total 9481344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6247552 # Number of bytes written to this memory -system.physmem.bytes_written::total 6247552 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3378 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144768 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148146 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97618 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97618 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1081336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46341877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47423213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1081336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1081336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31248628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31248628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31248628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1081336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46341877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78671841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148147 # Total number of read requests seen -system.physmem.writeReqs 97618 # Total number of write requests seen -system.physmem.cpureqs 247832 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9481344 # Total number of bytes read from memory -system.physmem.bytesWritten 6247552 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9481344 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6247552 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9166 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9182 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9622 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 9866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9514 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9403 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9092 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9052 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 9254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8851 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9077 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9034 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9025 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9210 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5950 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 216704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9257984 # Number of bytes read from this memory +system.physmem.bytes_read::total 9474688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216704 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6246208 # Number of bytes written to this memory +system.physmem.bytes_written::total 6246208 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144656 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148042 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97597 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97597 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1083635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46294835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47378470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1083635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1083635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31234356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31234356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31234356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1083635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46294835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78612825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148043 # Total number of read requests seen +system.physmem.writeReqs 97597 # Total number of write requests seen +system.physmem.cpureqs 245655 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9474688 # Total number of bytes read from memory +system.physmem.bytesWritten 6246208 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9474688 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6246208 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 8 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9178 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9513 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9082 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9057 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 9249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9050 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9211 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5953 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 5982 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6482 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6271 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6483 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 6170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6223 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6032 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5908 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6109 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6062 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6237 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6224 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6034 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5978 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5903 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6100 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5948 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6051 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6106 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2058 # Number of times wr buffer was full causing retry -system.physmem.totGap 199930425500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry +system.physmem.totGap 199978745500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148147 # Categorize read packet sizes +system.physmem.readPktSize::6 148043 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97618 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 137980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97597 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 138031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,68 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4226 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.totQLat 1712037750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4981606500 # Sum of mem lat for all requests -system.physmem.totBusLat 740435000 # Total cycles spent in databus access -system.physmem.totBankLat 2529133750 # Total cycles spent in bank access -system.physmem.avgQLat 11561.03 # Average queueing delay per request -system.physmem.avgBankLat 17078.70 # Average bank access latency per request +system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.totQLat 1694406500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4963552750 # Sum of mem lat for all requests +system.physmem.totBusLat 739875000 # Total cycles spent in databus access +system.physmem.totBankLat 2529271250 # Total cycles spent in bank access +system.physmem.avgQLat 11450.63 # Average queueing delay per request +system.physmem.avgBankLat 17092.56 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33639.73 # Average memory access latency -system.physmem.avgRdBW 47.42 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.42 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 33543.18 # Average memory access latency +system.physmem.avgRdBW 47.38 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 31.23 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 31.23 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.71 # Average write queue length over time -system.physmem.readRowHits 125393 # Number of row buffer hits during reads -system.physmem.writeRowHits 52794 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.08 # Row buffer hit rate for writes -system.physmem.avgGap 813502.43 # Average gap between requests -system.cpu.branchPred.lookups 182807672 # Number of BP lookups -system.cpu.branchPred.condPredicted 143119940 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265200 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 92612738 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87226650 # Number of BTB hits +system.physmem.avgWrQLen 8.16 # Average write queue length over time +system.physmem.readRowHits 125326 # Number of row buffer hits during reads +system.physmem.writeRowHits 52813 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 54.11 # Row buffer hit rate for writes +system.physmem.avgGap 814113.11 # Average gap between requests +system.cpu.branchPred.lookups 182790798 # Number of BP lookups +system.cpu.branchPred.condPredicted 143104560 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7266331 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93146978 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87211884 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.184290 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12677704 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116304 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.628248 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12679404 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 115837 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +229,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 399860886 # number of cpu cycles simulated +system.cpu.numCycles 399957538 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119358222 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761608008 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182807672 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99904354 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170147877 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35680811 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75396284 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 468 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114514342 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2439022 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 392517505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.176152 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.990501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119379666 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761592104 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182790798 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99891288 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170154666 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35685574 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75463742 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 612 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114537866 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2438685 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 392618085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.175656 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.990351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222382247 56.66% 56.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14190044 3.62% 60.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22888927 5.83% 66.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22740218 5.79% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20908888 5.33% 77.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11594217 2.95% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13063164 3.33% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11994936 3.06% 86.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52754864 13.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222476087 56.66% 56.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14184800 3.61% 60.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22904886 5.83% 66.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22739285 5.79% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20904776 5.32% 77.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11596191 2.95% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13057185 3.33% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11992863 3.05% 86.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52762012 13.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392517505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457178 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.904682 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129005298 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70927026 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158858538 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6186097 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27540546 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26127343 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76683 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825553021 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 296390 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27540546 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135586345 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9628782 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46469860 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158285767 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15006205 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800628342 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1130 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3045894 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8758928 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 294 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954382842 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500628672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500627387 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1285 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 392618085 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457026 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.904182 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129039701 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 70981785 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158852483 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6198857 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27545259 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26125355 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76645 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825586648 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296519 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27545259 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135624497 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9643215 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46459353 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158288427 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15057334 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800646746 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1025 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3043913 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8811846 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 273 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954314143 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500751257 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500749947 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1310 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288130551 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292970 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41448640 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170247105 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73473871 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28488219 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15923707 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755060750 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775315 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665323167 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1373619 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187375419 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479909972 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797683 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 392517505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.695015 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735938 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288061852 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293040 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293037 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41604001 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170281813 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73487632 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28633593 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16029977 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755108515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665313430 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1367099 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187428477 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 480217782 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 392618085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.694556 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735285 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 137188203 34.95% 34.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69757763 17.77% 52.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71444239 18.20% 70.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53382766 13.60% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31199092 7.95% 92.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16084863 4.10% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8731670 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2913347 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1815562 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 137184245 34.94% 34.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69848764 17.79% 52.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71484982 18.21% 70.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53385142 13.60% 84.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31215558 7.95% 92.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16050252 4.09% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8736886 2.23% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2893580 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1818676 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 392517505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392618085 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 478854 5.03% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6518035 68.44% 73.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2526744 26.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 479033 5.02% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6517674 68.35% 73.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2539591 26.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447790300 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383235 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447798832 67.31% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383465 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153391187 23.06% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63758352 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153381199 23.05% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63749839 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665323167 # Type of FU issued -system.cpu.iq.rate 1.663887 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9523633 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014314 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1734060876 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947018314 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646045006 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665313430 # Type of FU issued +system.cpu.iq.rate 1.663460 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9536298 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014334 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1734148123 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947118126 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646033691 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674846691 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8570702 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674849617 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8562339 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44217550 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 42225 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810789 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16613394 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44252258 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42000 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 809672 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16627155 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19530 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4440 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19517 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4404 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27540546 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5027645 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 374127 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760395240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1110246 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170247105 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73473871 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286773 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 218357 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11618 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810789 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4336068 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4004006 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8340074 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655902697 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150107572 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9420470 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27545259 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5023337 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 374520 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760443219 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1117317 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170281813 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73487632 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218824 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12460 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 809672 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4339991 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4001230 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341221 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655886711 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150097752 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9426719 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1559175 # number of nop insts executed -system.cpu.iew.exec_refs 212574642 # number of memory reference insts executed -system.cpu.iew.exec_branches 138502057 # Number of branches executed -system.cpu.iew.exec_stores 62467070 # Number of stores executed -system.cpu.iew.exec_rate 1.640327 # Inst execution rate -system.cpu.iew.wb_sent 651021062 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646045022 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374765758 # num instructions producing a value -system.cpu.iew.wb_consumers 646459860 # num instructions consuming a value +system.cpu.iew.exec_nop 1559311 # number of nop insts executed +system.cpu.iew.exec_refs 212556043 # number of memory reference insts executed +system.cpu.iew.exec_branches 138504207 # Number of branches executed +system.cpu.iew.exec_stores 62458291 # Number of stores executed +system.cpu.iew.exec_rate 1.639891 # Inst execution rate +system.cpu.iew.wb_sent 651006973 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646033707 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374766500 # num instructions producing a value +system.cpu.iew.wb_consumers 646470459 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615674 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579720 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615256 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579712 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189453742 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189501793 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7191165 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 364976959 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.564395 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233817 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7192333 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 365072826 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.563984 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233117 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157310366 43.10% 43.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98490082 26.99% 70.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33805907 9.26% 79.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18787402 5.15% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16180614 4.43% 88.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7431287 2.04% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6987633 1.91% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3169968 0.87% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22813700 6.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157316892 43.09% 43.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98576092 27.00% 70.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33819222 9.26% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18783601 5.15% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16197747 4.44% 88.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7430684 2.04% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6971298 1.91% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3187688 0.87% 93.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22789602 6.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 364976959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 365072826 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,199 +472,199 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22813700 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22789602 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1102578030 # The number of ROB reads -system.cpu.rob.rob_writes 1548505178 # The number of ROB writes -system.cpu.timesIdled 308567 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7343381 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1102746046 # The number of ROB reads +system.cpu.rob.rob_writes 1548606173 # The number of ROB writes +system.cpu.timesIdled 308814 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7339453 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.791431 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.791431 # CPI: Total CPI of All Threads -system.cpu.ipc 1.263534 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.263534 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058706465 # number of integer regfile reads -system.cpu.int_regfile_writes 752037507 # number of integer regfile writes +system.cpu.cpi 0.791622 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.791622 # CPI: Total CPI of All Threads +system.cpu.ipc 1.263228 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.263228 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058599019 # number of integer regfile reads +system.cpu.int_regfile_writes 752005627 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210820275 # number of misc regfile reads +system.cpu.misc_regfile_reads 210805238 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.icache.replacements 15019 # number of replacements -system.cpu.icache.tagsinuse 1100.569602 # Cycle average of tags in use -system.cpu.icache.total_refs 114493231 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16877 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6783.980032 # Average number of references to valid blocks. +system.cpu.icache.replacements 14802 # number of replacements +system.cpu.icache.tagsinuse 1101.055470 # Cycle average of tags in use +system.cpu.icache.total_refs 114516987 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16660 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6873.768727 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1100.569602 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537388 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537388 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114493231 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114493231 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114493231 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114493231 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114493231 # number of overall hits -system.cpu.icache.overall_hits::total 114493231 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21111 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21111 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21111 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21111 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21111 # number of overall misses -system.cpu.icache.overall_misses::total 21111 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 514757500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 514757500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 514757500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 514757500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 514757500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 514757500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114514342 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114514342 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114514342 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114514342 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114514342 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114514342 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24383.378334 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24383.378334 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24383.378334 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24383.378334 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1152 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1101.055470 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537625 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537625 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114516991 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114516991 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114516991 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114516991 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114516991 # number of overall hits +system.cpu.icache.overall_hits::total 114516991 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20874 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20874 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20874 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20874 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20874 # number of overall misses +system.cpu.icache.overall_misses::total 20874 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 507579000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 507579000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 507579000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 507579000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 507579000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 507579000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114537865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114537865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114537865 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114537865 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114537865 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114537865 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000182 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000182 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000182 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000182 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000182 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000182 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24316.326531 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24316.326531 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24316.326531 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24316.326531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24316.326531 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24316.326531 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.615385 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 37.307692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4153 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4153 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4153 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4153 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4153 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4153 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16958 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16958 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16958 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16958 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16958 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16958 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375680500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 375680500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375680500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 375680500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375680500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 375680500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22153.585328 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22153.585328 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22153.585328 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22153.585328 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4132 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4132 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4132 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4132 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4132 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4132 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16742 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16742 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16742 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16742 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2557493580 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3952267092 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3952267092 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180723170 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6329037502 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6509760672 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180723170 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6329037502 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6509760672 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051252 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054158 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.109756 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.109756 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290422 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290422 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122073 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122073 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53500.050326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54694.981245 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.792518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3386 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43376 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46762 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101281 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3386 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144657 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148043 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3386 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144657 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148043 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 178901170 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2348139621 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2527040791 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3963100640 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3963100640 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178901170 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6311240261 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6490141431 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178901170 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6311240261 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6490141431 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203376 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051154 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054085 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094118 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094118 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290345 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290345 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203376 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122004 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203376 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122004 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52835.549321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54134.535711 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54040.477118 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39010.078489 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39010.078489 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39129.754248 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39129.754248 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52835.549321 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43629.000055 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43839.569794 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52835.549321 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43629.000055 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43839.569794 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192631 # number of replacements -system.cpu.dcache.tagsinuse 4058.209057 # Cycle average of tags in use -system.cpu.dcache.total_refs 190187917 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196727 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.923394 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1192680 # number of replacements +system.cpu.dcache.tagsinuse 4058.218189 # Cycle average of tags in use +system.cpu.dcache.total_refs 190190086 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196776 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.918700 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.209057 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990774 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990774 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136218647 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136218647 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50991635 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50991635 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488827 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488827 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 4058.218189 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990776 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990776 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136220587 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136220587 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50991825 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50991825 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488806 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488806 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187210282 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187210282 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187210282 # number of overall hits -system.cpu.dcache.overall_hits::total 187210282 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1699163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1699163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3247671 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3247671 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 187212412 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187212412 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187212412 # number of overall hits +system.cpu.dcache.overall_hits::total 187212412 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1696903 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1696903 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3247481 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3247481 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4946834 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4946834 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4946834 # number of overall misses -system.cpu.dcache.overall_misses::total 4946834 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26685574500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26685574500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57046648448 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57046648448 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 615500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 615500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83732222948 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83732222948 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83732222948 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83732222948 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137917810 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137917810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4944384 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4944384 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4944384 # number of overall misses +system.cpu.dcache.overall_misses::total 4944384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26525701000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26525701000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57242727951 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57242727951 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1087000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1087000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83768428951 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83768428951 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83768428951 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83768428951 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137917490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137917490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488868 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488868 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488847 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488847 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192157116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192157116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192157116 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192157116 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012320 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012320 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 192156796 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192156796 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192156796 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192156796 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012304 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059873 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059873 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15705.129231 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15705.129231 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17565.402545 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17565.402545 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15012.195122 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15012.195122 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16926.426670 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16926.426670 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18054 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1658 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 601 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.889023 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26.207987 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.025731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025731 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025731 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025731 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15631.831048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15631.831048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17626.809195 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17626.809195 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26512.195122 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26512.195122 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16942.136564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16942.136564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16942.136564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16942.136564 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18871 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17919 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1660 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 609 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.368072 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 29.423645 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110977 # number of writebacks -system.cpu.dcache.writebacks::total 1110977 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850754 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 850754 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899270 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2899270 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1111118 # number of writebacks +system.cpu.dcache.writebacks::total 1111118 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 848410 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 848410 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899112 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2899112 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3750024 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3750024 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3750024 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3750024 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848409 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848409 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348401 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348401 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196810 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196810 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196810 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11849237000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11849237000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8091181496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8091181496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19940418496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19940418496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19940418496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19940418496 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 3747522 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3747522 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3747522 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3747522 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848493 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848493 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348369 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348369 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196862 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196862 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196862 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196862 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11822842000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11822842000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8101779997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8101779997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19924621997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19924621997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19924621997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19924621997 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13966.420677 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13966.420677 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23223.760827 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23223.760827 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13933.929920 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13933.929920 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23256.317287 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23256.317287 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16647.384575 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16647.384575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16647.384575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16647.384575 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 44aca7e96..412eefc9d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.434779 # Nu sim_ticks 434778577000 # Number of ticks simulated final_tick 434778577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65958 # Simulator instruction rate (inst/s) -host_op_rate 121963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34681028 # Simulator tick rate (ticks/s) -host_mem_usage 469672 # Number of bytes of host memory used -host_seconds 12536.50 # Real time elapsed on the host +host_inst_rate 92341 # Simulator instruction rate (inst/s) +host_op_rate 170748 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48553388 # Simulator tick rate (ticks/s) +host_mem_usage 422424 # Number of bytes of host memory used +host_seconds 8954.65 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 207616 # Number of bytes read from this memory @@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 56304964 # To system.physmem.bw_total::total 100008607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 385749 # Total number of read requests seen system.physmem.writeReqs 293653 # Total number of write requests seen -system.physmem.cpureqs 898439 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 895346 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 24687808 # Total number of bytes read from memory system.physmem.bytesWritten 18793792 # Total number of bytes written to memory system.physmem.bytesConsumedRd 24687808 # bytesRead derated as per pkt->getSize() @@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 17888 # Tr system.physmem.perBankWrReqs::14 18802 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 18117 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3123 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry system.physmem.totGap 434778560000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 37 # Wh system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see -system.physmem.totQLat 3433767500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12026720000 # Sum of mem lat for all requests +system.physmem.totQLat 3433770500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12026723000 # Sum of mem lat for all requests system.physmem.totBusLat 1927915000 # Total cycles spent in databus access system.physmem.totBankLat 6665037500 # Total cycles spent in bank access -system.physmem.avgQLat 8905.39 # Average queueing delay per request +system.physmem.avgQLat 8905.40 # Average queueing delay per request system.physmem.avgBankLat 17285.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31191.00 # Average memory access latency +system.physmem.avgMemAccLat 31191.01 # Average memory access latency system.physmem.avgRdBW 56.78 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 43.23 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 56.78 # Average consumed read bandwidth in MB/s @@ -196,17 +196,17 @@ system.cpu.fetch.Branches 214994146 # Nu system.cpu.fetch.predictedBranches 147887338 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 371275147 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 83409102 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231974123 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 231974121 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 33791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 326928 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 173497134 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 3845609 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 854248204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 854248202 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.593680 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.388732 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 487377953 57.05% 57.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 487377951 57.05% 57.05% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 24712671 2.89% 59.95% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 27340185 3.20% 63.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 28885218 3.38% 66.53% # Number of instructions fetched each cycle (Total) @@ -218,11 +218,11 @@ system.cpu.fetch.rateDist::8 183370419 21.47% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 854248204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 854248202 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.247246 # Number of branch fetches per cycle system.cpu.fetch.rate 1.372267 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 237078092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 188537109 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 188537107 # Number of cycles decode is blocked system.cpu.decode.RunCycles 313423018 # Number of cycles decode is running system.cpu.decode.UnblockCycles 45192344 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 70017641 # Number of cycles decode is squashing @@ -230,7 +230,7 @@ system.cpu.decode.DecodedInsts 2166915251 # Nu system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 70017641 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 270505809 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54166582 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 54166580 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16246 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 322705449 # Number of cycles rename is running system.cpu.rename.UnblockCycles 136836477 # Number of cycles rename is unblocking @@ -259,11 +259,11 @@ system.cpu.iq.iqSquashedInstsIssued 841556 # Nu system.cpu.iq.iqSquashedInstsExamined 499552115 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 818199817 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 23145 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 854248204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 854248202 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.116852 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.887224 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233580311 27.34% 27.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233580309 27.34% 27.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 145624549 17.05% 44.39% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 138385021 16.20% 60.59% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 133093921 15.58% 76.17% # Number of insts issued each cycle @@ -275,7 +275,7 @@ system.cpu.iq.issued_per_cycle::8 1900056 0.22% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 854248204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 854248202 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4959094 32.46% 32.46% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available @@ -348,7 +348,7 @@ system.cpu.iq.FU_type_0::total 1808317213 # Ty system.cpu.iq.rate 2.079584 # Inst issue rate system.cpu.iq.fu_busy_cnt 15278274 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4486980237 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4486980235 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2533813283 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1768843031 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads @@ -368,7 +368,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 12353 # system.cpu.iew.lsq.thread0.cacheBlocked 585 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 70017641 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16317048 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 16317046 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 2892217 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 2034046776 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 2393263 # Number of squashed instructions skipped by dispatch @@ -401,11 +401,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 505092905 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 13168881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 784230563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 784230561 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.949667 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.458347 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 290802586 37.08% 37.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290802584 37.08% 37.08% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 195769482 24.96% 62.04% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 62065599 7.91% 69.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 92211558 11.76% 81.72% # Number of insts commited each cycle @@ -417,7 +417,7 @@ system.cpu.commit.committed_per_cycle::8 69877590 8.91% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 784230563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 784230561 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -430,10 +430,10 @@ system.cpu.commit.int_insts 1528317561 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 69877590 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2748434579 # The number of ROB reads +system.cpu.rob.rob_reads 2748434577 # The number of ROB reads system.cpu.rob.rob_writes 4138359582 # The number of ROB writes system.cpu.timesIdled 322597 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15308951 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 15308953 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated @@ -532,14 +532,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4129.492827 system.cpu.icache.overall_avg_mshr_miss_latency::total 4129.492827 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 353068 # number of replacements -system.cpu.l2cache.tagsinuse 29624.531163 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29624.531166 # Cycle average of tags in use system.cpu.l2cache.total_refs 3697718 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 385429 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 9.593772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 201975419000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21048.484716 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21048.484720 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 232.592119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8343.454327 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8343.454326 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.642349 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.007098 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.254622 # Average percentage of cache occupancy @@ -573,18 +573,18 @@ system.cpu.l2cache.overall_misses::cpu.inst 3245 # system.cpu.l2cache.overall_misses::cpu.data 382536 # number of overall misses system.cpu.l2cache.overall_misses::total 385781 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201201000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10144981454 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 10346182454 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10144983954 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 10346184954 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7392500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 7392500 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10367117000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 10367117000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 201201000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20512098454 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20713299454 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20512100954 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20713301954 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 201201000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20512098454 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20713299454 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20512100954 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20713301954 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 7061 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1762430 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1769491 # number of ReadReq accesses(hits+misses) @@ -614,18 +614,18 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459567 system.cpu.l2cache.overall_miss_rate::cpu.data 0.150976 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151834 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62003.389831 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.709453 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.413123 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.723676 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.427088 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.243085 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.243085 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50139.855101 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50139.855101 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.354471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53691.860029 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53691.866510 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.354471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53691.860029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53691.866510 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -650,18 +650,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 3245 system.cpu.l2cache.overall_mshr_misses::cpu.data 382536 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160858519 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7969651402 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8130509921 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7969654402 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8130512921 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2164647428 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2164647428 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7779866278 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7779866278 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160858519 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15749517680 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15910376199 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15749520680 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15910379199 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160858519 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15749517680 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15910376199 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15749520680 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15910379199 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099733 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101169 # mshr miss rate for ReadReq accesses @@ -676,18 +676,18 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.459567 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150976 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151834 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49571.192296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45340.847245 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45417.529737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45340.864313 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45417.546496 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.947133 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.947133 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37626.793243 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37626.793243 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.334672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41241.990142 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.334672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41241.990142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2529656 # number of replacements system.cpu.dcache.tagsinuse 4087.796251 # Cycle average of tags in use @@ -716,12 +716,12 @@ system.cpu.dcache.overall_misses::cpu.data 3900651 # system.cpu.dcache.overall_misses::total 3900651 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 51401791500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 51401791500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898482499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23898482499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75300273999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75300273999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75300273999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75300273999 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898481499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23898481499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75300272999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75300272999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75300272999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75300272999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 259505338 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 259505338 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) @@ -740,12 +740,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17753.363092 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 17753.363092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.920793 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.920793 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19304.540191 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19304.540191 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.919798 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.919798 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19304.539934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19304.539934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 6530 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 642 # number of cycles access was blocked diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index a79a513d0..36773aebe 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042726 # Nu sim_ticks 42726055500 # Number of ticks simulated final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89848 # Simulator instruction rate (inst/s) -host_op_rate 89848 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43455006 # Simulator tick rate (ticks/s) -host_mem_usage 257260 # Number of bytes of host memory used -host_seconds 983.23 # Real time elapsed on the host +host_inst_rate 80618 # Simulator instruction rate (inst/s) +host_op_rate 80618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38990762 # Simulator tick rate (ticks/s) +host_mem_usage 257380 # Number of bytes of host memory used +host_seconds 1095.80 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory @@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 237287713 # To system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165519 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279530 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 279517 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 10593216 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() @@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 7250 # Tr system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry system.physmem.totGap 42726035000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 1 # Wh system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.totQLat 7053839750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9647402250 # Sum of mem lat for all requests +system.physmem.totQLat 7053831750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9647394250 # Sum of mem lat for all requests system.physmem.totBusLat 827595000 # Total cycles spent in databus access system.physmem.totBankLat 1765967500 # Total cycles spent in bank access -system.physmem.avgQLat 42616.50 # Average queueing delay per request +system.physmem.avgQLat 42616.45 # Average queueing delay per request system.physmem.avgBankLat 10669.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58285.77 # Average memory access latency +system.physmem.avgMemAccLat 58285.72 # Average memory access latency system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s @@ -403,14 +403,14 @@ system.cpu.l2cache.overall_misses::total 165519 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 455300000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513155000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1968455000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996427000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11996427000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996609634 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11996609634 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 455300000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13509582000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13964882000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13509764634 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13965064634 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 455300000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13509582000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13964882000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13509764634 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13965064634 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses) @@ -438,14 +438,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.569383 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64063.599268 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54981.832056 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 56845.760656 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91652.038719 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91652.038719 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91653.434033 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91653.434033 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84370.265649 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.457352 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84371.369051 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84370.265649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.457352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84371.369051 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,14 +470,14 @@ system.cpu.l2cache.overall_mshr_misses::total 165519 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366897656 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1170781845 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537679501 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407190958 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407190958 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407373592 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407373592 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366897656 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11577972803 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11944870459 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578155437 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11945053093 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366897656 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11577972803 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11944870459 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578155437 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11945053093 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses @@ -492,14 +492,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51624.828479 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42541.399113 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44405.668852 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79510.363264 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79510.363264 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79511.758578 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79511.758578 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73088.878601 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72167.262326 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73088.878601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72167.262326 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200249 # number of replacements system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 74c8f08b1..b5df8dc7b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023888 # Nu sim_ticks 23888231000 # Number of ticks simulated final_tick 23888231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143918 # Simulator instruction rate (inst/s) -host_op_rate 143918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43194720 # Simulator tick rate (ticks/s) -host_mem_usage 260336 # Number of bytes of host memory used -host_seconds 553.04 # Real time elapsed on the host +host_inst_rate 183235 # Simulator instruction rate (inst/s) +host_op_rate 183235 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54995028 # Simulator tick rate (ticks/s) +host_mem_usage 260452 # Number of bytes of host memory used +host_seconds 434.37 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 490944 # Number of bytes read from this memory @@ -604,14 +604,14 @@ system.cpu.l2cache.overall_misses::total 166330 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 493837000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1614539500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 2108376500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12203454500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12203454500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12203503384 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12203503384 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 493837000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13817994000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14311831000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13818042884 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14311879884 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 493837000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13817994000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14311831000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13818042884 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14311879884 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 93652 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 62106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 155758 # number of ReadReq accesses(hits+misses) @@ -639,14 +639,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.555949 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64368.743483 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57947.724499 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 59334.060337 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93301.435059 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93301.435059 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 93301.808801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 93301.808801 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86044.796489 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87093.262766 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86045.090387 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64368.743483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87092.954657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86044.796489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87093.262766 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86045.090387 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -671,14 +671,14 @@ system.cpu.l2cache.overall_mshr_misses::total 166330 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 398141894 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1271865950 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1670007844 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10613542919 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10613542919 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10613591803 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10613591803 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 398141894 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11885408869 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12283550763 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11885457753 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12283599647 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 398141894 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11885408869 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12283550763 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11885457753 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12283599647 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081920 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228136 # mshr miss rate for ReadReq accesses @@ -693,14 +693,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.555949 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51895.450209 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45648.767138 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46997.462824 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81145.776010 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81145.776010 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81146.149752 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81146.149752 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74912.439039 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73850.776450 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51895.450209 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74912.130929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73850.482553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74912.439039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73850.776450 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 201434 # number of replacements system.cpu.dcache.tagsinuse 4076.506217 # Cycle average of tags in use diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6f25374e1..f9d46e356 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025578 # Number of seconds simulated -sim_ticks 25578307500 # Number of ticks simulated -final_tick 25578307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025579 # Number of seconds simulated +sim_ticks 25578679000 # Number of ticks simulated +final_tick 25578679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122516 # Simulator instruction rate (inst/s) -host_op_rate 173866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44194830 # Simulator tick rate (ticks/s) -host_mem_usage 267056 # Number of bytes of host memory used -host_seconds 578.76 # Real time elapsed on the host +host_inst_rate 106593 # Simulator instruction rate (inst/s) +host_op_rate 151269 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38451628 # Simulator tick rate (ticks/s) +host_mem_usage 298528 # Number of bytes of host memory used +host_seconds 665.22 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372288 # Number of bytes written to this memory system.physmem.bytes_written::total 5372288 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83942 # Number of write requests responded to by this memory system.physmem.num_writes::total 83942 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11654876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 310553151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 322208027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11654876 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11654876 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 210032974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 210032974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 210032974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11654876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 310553151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 532241001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128775 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 11654707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 310553645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 322208352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11654707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11654707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 210029924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 210029924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 210029924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11654707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 310553645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 532238275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128777 # Total number of read requests seen system.physmem.writeReqs 83942 # Total number of write requests seen -system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8241536 # Total number of bytes read from memory +system.physmem.cpureqs 213038 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241664 # Total number of bytes read from memory system.physmem.bytesWritten 5372288 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8241536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 5372288 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 319 # Reqs where no action is needed system.physmem.perBankRdReqs::0 7977 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8192 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 8064 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 8161 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 8170 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 8108 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8047 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7986 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 8126 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 8035 # Track reads on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 5132 # Tr system.physmem.perBankWrReqs::15 5152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25578289000 # Total gap between requests +system.physmem.totGap 25578660500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128775 # Categorize read packet sizes +system.physmem.readPktSize::6 128777 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,9 +92,9 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 83942 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2088 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -124,7 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3552 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 3640 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3648 # What write queue length does an incoming req see @@ -147,7 +147,7 @@ system.physmem.wrQLenPdf::19 3649 # Wh system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 98 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see @@ -156,14 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3208033250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5250782000 # Sum of mem lat for all requests -system.physmem.totBusLat 643865000 # Total cycles spent in databus access -system.physmem.totBankLat 1398883750 # Total cycles spent in bank access -system.physmem.avgQLat 24912.31 # Average queueing delay per request -system.physmem.avgBankLat 10863.18 # Average bank access latency per request +system.physmem.totQLat 3210060500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5252104250 # Sum of mem lat for all requests +system.physmem.totBusLat 643875000 # Total cycles spent in databus access +system.physmem.totBankLat 1398168750 # Total cycles spent in bank access +system.physmem.avgQLat 24927.67 # Average queueing delay per request +system.physmem.avgBankLat 10857.45 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40775.49 # Average memory access latency +system.physmem.avgMemAccLat 40785.12 # Average memory access latency system.physmem.avgRdBW 322.21 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 210.03 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 322.21 # Average consumed read bandwidth in MB/s @@ -172,19 +172,19 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 4.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.21 # Average read queue length over time system.physmem.avgWrQLen 9.59 # Average write queue length over time -system.physmem.readRowHits 116753 # Number of row buffer hits during reads -system.physmem.writeRowHits 52875 # Number of row buffer hits during writes +system.physmem.readRowHits 116755 # Number of row buffer hits during reads +system.physmem.writeRowHits 52878 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes -system.physmem.avgGap 120245.63 # Average gap between requests -system.cpu.branchPred.lookups 16623364 # Number of BP lookups -system.cpu.branchPred.condPredicted 12760071 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602765 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10462695 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7764975 # Number of BTB hits +system.physmem.avgGap 120246.24 # Average gap between requests +system.cpu.branchPred.lookups 16623550 # Number of BP lookups +system.cpu.branchPred.condPredicted 12760225 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 602776 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10462790 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7764993 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.215821 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 74.215319 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825730 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 113390 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -229,99 +229,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 51156616 # number of cpu cycles simulated +system.cpu.numCycles 51157359 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12528030 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85177625 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16623364 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9590704 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21186632 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2363015 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10581483 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 556 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 12528196 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85178151 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16623550 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9590723 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21186766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2362966 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10580824 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 65 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 592 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11675113 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179601 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46030680 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.591102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 11675240 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179625 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46030286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.591135 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335079 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24864286 54.02% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2136700 4.64% 58.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1964680 4.27% 62.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042011 4.44% 67.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1465176 3.18% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1378812 3.00% 73.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958023 2.08% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1192746 2.59% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10028246 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24863758 54.02% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2136664 4.64% 58.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1964751 4.27% 62.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2042058 4.44% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1465237 3.18% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1378794 3.00% 73.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 958007 2.08% 75.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1192757 2.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10028260 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46030680 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324950 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.665036 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14611647 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8930047 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19464619 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1393461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1630906 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3329793 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104768 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116826129 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 364020 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1630906 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16323488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2561901 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 880060 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19095828 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5538497 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114955733 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 140 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 16360 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4684188 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 46030286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324949 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.665022 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14611843 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8929429 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19464778 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1393400 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1630836 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3329843 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104767 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116826409 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 364015 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1630836 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16323672 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2560343 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 881200 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19095931 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5538304 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114955778 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16357 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4684077 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 269 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115265758 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529627924 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529622592 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 115266627 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529628092 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529622760 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 5332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16133086 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20210 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20206 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13085457 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29620481 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22434207 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3897313 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4409985 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111515856 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35838 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107234062 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 271666 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10778201 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25823888 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2052 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46030680 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.329622 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.987561 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16133955 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20202 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20198 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13085199 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29620303 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22433978 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3897320 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4410132 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111515414 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35833 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107233709 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 271611 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10777789 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25822592 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2047 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46030286 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.329634 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.987559 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10772740 23.40% 23.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8089543 17.57% 40.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7436956 16.16% 57.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7132439 15.49% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5411666 11.76% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3908589 8.49% 92.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1839107 4.00% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 868081 1.89% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571559 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10772482 23.40% 23.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8089494 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7436899 16.16% 57.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7132502 15.50% 72.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5411548 11.76% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3908660 8.49% 92.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839023 4.00% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 868143 1.89% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 571535 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46030680 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46030286 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112263 4.55% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112260 4.55% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available @@ -350,13 +350,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1357458 55.03% 59.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 996979 40.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1357456 55.03% 59.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 996870 40.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56624593 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91608 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56624482 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91603 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 187 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28897959 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21619708 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28897893 26.95% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21619537 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107234062 # Type of FU issued -system.cpu.iq.rate 2.096191 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2466700 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023003 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263236655 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122357738 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105553758 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 107233709 # Type of FU issued +system.cpu.iq.rate 2.096154 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2466586 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023002 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263235386 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122356888 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105553525 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 515 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109700502 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 109700035 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2179129 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 2179098 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2313373 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29813 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1878469 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2313195 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6752 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29821 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1878240 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 507 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1630906 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1049242 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45608 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111561445 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 293593 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29620481 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22434207 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19918 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6795 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5249 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29813 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 391440 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181697 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 573137 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106207608 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28598944 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1026454 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1630836 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1047773 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45606 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111560996 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 293586 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29620303 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22433978 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19913 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6800 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5244 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29821 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391475 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181717 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573192 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106207305 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28598865 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1026404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9751 # number of nop insts executed -system.cpu.iew.exec_refs 49933957 # number of memory reference insts executed -system.cpu.iew.exec_branches 14599960 # Number of branches executed -system.cpu.iew.exec_stores 21335013 # Number of stores executed -system.cpu.iew.exec_rate 2.076127 # Inst execution rate -system.cpu.iew.wb_sent 105772826 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105553928 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53290488 # num instructions producing a value -system.cpu.iew.wb_consumers 103570522 # num instructions consuming a value +system.cpu.iew.exec_nop 9749 # number of nop insts executed +system.cpu.iew.exec_refs 49933799 # number of memory reference insts executed +system.cpu.iew.exec_branches 14599943 # Number of branches executed +system.cpu.iew.exec_stores 21334934 # Number of stores executed +system.cpu.iew.exec_rate 2.076090 # Inst execution rate +system.cpu.iew.wb_sent 105772568 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105553695 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53290851 # num instructions producing a value +system.cpu.iew.wb_consumers 103571318 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.063349 # insts written-back per cycle +system.cpu.iew.wb_rate 2.063314 # insts written-back per cycle system.cpu.iew.wb_fanout 0.514533 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10929916 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10929447 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499809 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44399774 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.266508 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764024 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 499822 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44399450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764020 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15322992 34.51% 34.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11640164 26.22% 60.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3466305 7.81% 68.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2879897 6.49% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880990 4.24% 79.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1948005 4.39% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685170 1.54% 85.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565050 1.27% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6011201 13.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15322466 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11640372 26.22% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3466304 7.81% 68.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2879944 6.49% 75.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880994 4.24% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1947998 4.39% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685125 1.54% 85.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565076 1.27% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6011171 13.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44399774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44399450 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,70 +472,70 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6011201 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6011171 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149925618 # The number of ROB reads -system.cpu.rob.rob_writes 224764611 # The number of ROB writes -system.cpu.timesIdled 74074 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5125936 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 149924855 # The number of ROB reads +system.cpu.rob.rob_writes 224763597 # The number of ROB writes +system.cpu.timesIdled 74024 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5127073 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.721454 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.721454 # CPI: Total CPI of All Threads -system.cpu.ipc 1.386089 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.386089 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511542927 # number of integer regfile reads -system.cpu.int_regfile_writes 103323311 # number of integer regfile writes +system.cpu.cpi 0.721465 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.721465 # CPI: Total CPI of All Threads +system.cpu.ipc 1.386069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.386069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511541679 # number of integer regfile reads +system.cpu.int_regfile_writes 103323268 # number of integer regfile writes system.cpu.fp_regfile_reads 788 # number of floating regfile reads system.cpu.fp_regfile_writes 660 # number of floating regfile writes -system.cpu.misc_regfile_reads 49174075 # number of misc regfile reads +system.cpu.misc_regfile_reads 49173958 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes system.cpu.icache.replacements 28620 # number of replacements -system.cpu.icache.tagsinuse 1814.212486 # Cycle average of tags in use -system.cpu.icache.total_refs 11640356 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1814.215623 # Cycle average of tags in use +system.cpu.icache.total_refs 11640482 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 30656 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379.708899 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 379.713009 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.212486 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885846 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885846 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11640361 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11640361 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11640361 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11640361 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11640361 # number of overall hits -system.cpu.icache.overall_hits::total 11640361 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34752 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34752 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34752 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34752 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34752 # number of overall misses -system.cpu.icache.overall_misses::total 34752 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 732057000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 732057000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 732057000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 732057000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 732057000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 732057000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11675113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11675113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11675113 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11675113 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11675113 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11675113 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1814.215623 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885847 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885847 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11640487 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11640487 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11640487 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11640487 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11640487 # number of overall hits +system.cpu.icache.overall_hits::total 11640487 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34753 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34753 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34753 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34753 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34753 # number of overall misses +system.cpu.icache.overall_misses::total 34753 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 732473500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 732473500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 732473500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 732473500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 732473500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 732473500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11675240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11675240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11675240 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11675240 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11675240 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11675240 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002977 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.002977 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.002977 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.002977 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.002977 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.002977 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21065.176105 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21065.176105 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21065.176105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21065.176105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21065.176105 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21076.554542 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21076.554542 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21076.554542 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21076.554542 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21076.554542 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21076.554542 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 767 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked @@ -544,132 +544,132 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 31.958333 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3763 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3763 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3763 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3763 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3763 # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19182.871341 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19182.871341 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19182.871341 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19182.871341 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19182.871341 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19191.648650 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19191.648650 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19191.648650 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19191.648650 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19191.648650 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395829 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.309548 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.943787 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.943787 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955441 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955441 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955423 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955423 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153060 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.764596 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.764594 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.667810 # 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average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65099.272572 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65509.152037 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65494.284229 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65099.272572 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65509.152037 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65494.284229 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -690,167 +690,167 @@ system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 77 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1210142513 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1455463053 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3199316 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3199316 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5398042204 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5398042204 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245046791 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6604408020 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6849454811 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245046791 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6604408020 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6849454811 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5395861980 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5395861980 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245320540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606004493 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6851325033 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245320540 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606004493 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6851325033 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394681 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308632 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394710 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308652 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.943787 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.943787 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955441 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955441 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955423 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955423 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764214 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764212 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.667411 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764214 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764212 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.667411 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52596.435072 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55188.518047 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54733.109850 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52655.192101 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55356.228581 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54881.713914 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10029.203762 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10029.203762 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52788.974877 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52788.974877 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52596.435072 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53211.576429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53189.320994 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52596.435072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53211.576429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53189.320994 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52767.653853 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52767.653853 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52655.192101 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53223.581535 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53203.017876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52655.192101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53223.581535 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53203.017876 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158314 # number of replacements -system.cpu.dcache.tagsinuse 4072.315596 # Cycle average of tags in use -system.cpu.dcache.total_refs 44364658 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162410 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.164571 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158317 # number of replacements +system.cpu.dcache.tagsinuse 4072.315940 # Cycle average of tags in use +system.cpu.dcache.total_refs 44364640 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162413 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.159415 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.315596 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4072.315940 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26064858 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26064858 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18267205 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18267205 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 26064832 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26064832 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267213 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44332063 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44332063 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44332063 # number of overall hits -system.cpu.dcache.overall_hits::total 44332063 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124444 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124444 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1582696 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1582696 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 44332045 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44332045 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44332045 # number of overall hits +system.cpu.dcache.overall_hits::total 44332045 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124417 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124417 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582688 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582688 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707140 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707140 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707140 # number of overall misses -system.cpu.dcache.overall_misses::total 1707140 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4243660500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4243660500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98452063982 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98452063982 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1707105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707105 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707105 # number of overall misses +system.cpu.dcache.overall_misses::total 1707105 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247904000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4247904000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98406408482 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98406408482 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1297000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 1297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102695724482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102695724482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102695724482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102695724482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26189302 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26189302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 102654312482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102654312482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102654312482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102654312482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26189249 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26189249 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16031 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 16031 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46039203 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46039203 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46039203 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46039203 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 46039150 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46039150 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46039150 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46039150 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004751 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079733 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.079733 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002807 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002807 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037080 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037080 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037080 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037080 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34100.965093 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34100.965093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62205.290202 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62205.290202 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.037079 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037079 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037079 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037079 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34142.472492 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34142.472492 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62176.757821 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62176.757821 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28822.222222 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28822.222222 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60156.592009 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60156.592009 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5240 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60133.566759 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60133.566759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60133.566759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60133.566759 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5187 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.305785 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.516393 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129088 # number of writebacks -system.cpu.dcache.writebacks::total 129088 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69028 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69028 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475364 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475364 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 129090 # number of writebacks +system.cpu.dcache.writebacks::total 129090 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69000 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69000 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475354 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475354 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544392 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544392 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544392 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544392 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55416 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55416 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162748 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162748 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162748 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162748 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1874890000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1874890000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6816019991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6816019991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8690909991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8690909991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8690909991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8690909991 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1544354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55417 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55417 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107334 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107334 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162751 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162751 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162751 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162751 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878666500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878666500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6813869491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6813869491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8692535991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8692535991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8692535991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8692535991 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses @@ -859,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33833.008517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33833.008517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63504.080712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63504.080712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33900.544959 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33900.544959 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63482.861824 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63482.861824 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 4d872659d..6baeed8b3 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.993559 # Nu sim_ticks 993559170500 # Number of ticks simulated final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139940 # Simulator instruction rate (inst/s) -host_op_rate 139940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76403951 # Simulator tick rate (ticks/s) -host_mem_usage 449176 # Number of bytes of host memory used -host_seconds 13004.03 # Real time elapsed on the host +host_inst_rate 90803 # Simulator instruction rate (inst/s) +host_op_rate 90803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49576515 # Simulator tick rate (ticks/s) +host_mem_usage 449304 # Number of bytes of host memory used +host_seconds 20040.92 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -36,7 +36,7 @@ system.physmem.bw_total::cpu.data 126177745 # To system.physmem.bw_total::total 191811167 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1959688 # Total number of read requests seen system.physmem.writeReqs 1018058 # Total number of write requests seen -system.physmem.cpureqs 2977859 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 125420032 # Total number of bytes read from memory system.physmem.bytesWritten 65155712 # Total number of bytes written to memory system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize() @@ -76,7 +76,7 @@ system.physmem.perBankWrReqs::13 64147 # Tr system.physmem.perBankWrReqs::14 63647 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 64278 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 113 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry system.physmem.totGap 993559118500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index e183c5fce..75aae5e90 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.665771 # Number of seconds simulated -sim_ticks 665770972500 # Number of ticks simulated -final_tick 665770972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.665696 # Number of seconds simulated +sim_ticks 665695988500 # Number of ticks simulated +final_tick 665695988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179472 # Simulator instruction rate (inst/s) -host_op_rate 179472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68827168 # Simulator tick rate (ticks/s) -host_mem_usage 452252 # Number of bytes of host memory used -host_seconds 9673.08 # Real time elapsed on the host +host_inst_rate 147850 # Simulator instruction rate (inst/s) +host_op_rate 147850 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56693787 # Simulator tick rate (ticks/s) +host_mem_usage 452372 # Number of bytes of host memory used +host_seconds 11741.96 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 62016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125796608 # Number of bytes read from this memory -system.physmem.bytes_read::total 125858624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65265344 # Number of bytes written to this memory -system.physmem.bytes_written::total 65265344 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965572 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966541 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019771 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019771 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 188948772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 189041922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98029723 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98029723 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98029723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 188948772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 287071645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966541 # Total number of read requests seen -system.physmem.writeReqs 1019771 # Total number of write requests seen -system.physmem.cpureqs 2988947 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125858624 # Total number of bytes read from memory -system.physmem.bytesWritten 65265344 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125858624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65265344 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 566 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125794176 # Number of bytes read from this memory +system.physmem.bytes_read::total 125855680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65263360 # Number of bytes written to this memory +system.physmem.bytes_written::total 65263360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965534 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966495 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019740 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019740 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 188966402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 189058793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 98037785 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 98037785 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 98037785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 188966402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 287096578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966495 # Total number of read requests seen +system.physmem.writeReqs 1019740 # Total number of write requests seen +system.physmem.cpureqs 2986251 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125855680 # Total number of bytes read from memory +system.physmem.bytesWritten 65263360 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125855680 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65263360 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 570 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 122314 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 124202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 122637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 122329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 122200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 124178 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 123636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122601 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 120701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 121432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121606 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 121460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 123481 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125598 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 124291 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 123180 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 124411 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63480 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 62406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63107 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63874 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63470 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63464 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 63489 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63362 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64287 # Track writes on a per bank basis +system.physmem.perBankRdReqs::7 121425 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 121612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 122268 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 121458 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 123448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125589 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 124287 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 123163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 124393 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63486 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 62408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 63108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 63839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 64141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 63465 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 63456 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 63488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 63819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 64238 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64665 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64277 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 63760 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64358 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2635 # Number of times wr buffer was full causing retry -system.physmem.totGap 665770904000 # Total gap between requests +system.physmem.numWrRetry 16 # Number of times wr buffer was full causing retry +system.physmem.totGap 665695920000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966541 # Categorize read packet sizes +system.physmem.readPktSize::6 1966495 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019771 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1625771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 77503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019740 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1625686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 234777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 77588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -124,88 +124,88 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44298 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 44337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.totQLat 34478547500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102599787500 # Sum of mem lat for all requests -system.physmem.totBusLat 9829875000 # Total cycles spent in databus access -system.physmem.totBankLat 58291365000 # Total cycles spent in bank access -system.physmem.avgQLat 17537.63 # Average queueing delay per request -system.physmem.avgBankLat 29650.10 # Average bank access latency per request +system.physmem.totQLat 34438847000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 102566423250 # Sum of mem lat for all requests +system.physmem.totBusLat 9829625000 # Total cycles spent in databus access +system.physmem.totBankLat 58297951250 # Total cycles spent in bank access +system.physmem.avgQLat 17517.88 # Average queueing delay per request +system.physmem.avgBankLat 29654.21 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52187.74 # Average memory access latency -system.physmem.avgRdBW 189.04 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 98.03 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 189.04 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 98.03 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52172.09 # Average memory access latency +system.physmem.avgRdBW 189.06 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 98.04 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 189.06 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 98.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.14 # Average write queue length over time -system.physmem.readRowHits 776350 # Number of row buffer hits during reads -system.physmem.writeRowHits 285987 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.04 # Row buffer hit rate for writes -system.physmem.avgGap 222940.84 # Average gap between requests -system.cpu.branchPred.lookups 381390262 # Number of BP lookups -system.cpu.branchPred.condPredicted 296397889 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16086653 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262140629 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259559256 # Number of BTB hits +system.physmem.avgWrQLen 10.61 # Average write queue length over time +system.physmem.readRowHits 776012 # Number of row buffer hits during reads +system.physmem.writeRowHits 286087 # Number of row buffer hits during writes +system.physmem.readRowHitRate 39.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.05 # Row buffer hit rate for writes +system.physmem.avgGap 222921.48 # Average gap between requests +system.cpu.branchPred.lookups 381386947 # Number of BP lookups +system.cpu.branchPred.condPredicted 296385810 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16088637 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262415494 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259543645 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.015272 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24699160 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3055 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.905610 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24703591 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3035 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613788534 # DTB read hits -system.cpu.dtb.read_misses 11249325 # DTB read misses +system.cpu.dtb.read_hits 613791968 # DTB read hits +system.cpu.dtb.read_misses 11248781 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625037859 # DTB read accesses -system.cpu.dtb.write_hits 212245958 # DTB write hits -system.cpu.dtb.write_misses 7142739 # DTB write misses +system.cpu.dtb.read_accesses 625040749 # DTB read accesses +system.cpu.dtb.write_hits 212266069 # DTB write hits +system.cpu.dtb.write_misses 7139950 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219388697 # DTB write accesses -system.cpu.dtb.data_hits 826034492 # DTB hits -system.cpu.dtb.data_misses 18392064 # DTB misses +system.cpu.dtb.write_accesses 219406019 # DTB write accesses +system.cpu.dtb.data_hits 826058037 # DTB hits +system.cpu.dtb.data_misses 18388731 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844426556 # DTB accesses -system.cpu.itb.fetch_hits 390787767 # ITB hits -system.cpu.itb.fetch_misses 43 # ITB misses +system.cpu.dtb.data_accesses 844446768 # DTB accesses +system.cpu.itb.fetch_hits 390789739 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390787810 # ITB accesses +system.cpu.itb.fetch_accesses 390789783 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,138 +219,138 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1331541946 # number of cpu cycles simulated +system.cpu.numCycles 1331391978 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402238482 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3159760476 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381390262 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284258416 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574242721 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140320135 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 173885771 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1317 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390787767 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8065204 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1266865295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494157 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152669 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402247693 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3159701831 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381386947 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284247236 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574240478 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140323731 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 173777898 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1315 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 390789739 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8060023 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1266766339 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494305 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152696 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 692622574 54.67% 54.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42615431 3.36% 58.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21758353 1.72% 59.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39697295 3.13% 62.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129259260 10.20% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61526950 4.86% 77.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38544819 3.04% 80.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28129154 2.22% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212711459 16.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 692525861 54.67% 54.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42625697 3.36% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21759185 1.72% 59.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39691714 3.13% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129252182 10.20% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61534262 4.86% 77.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38544537 3.04% 80.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28127846 2.22% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212705055 16.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1266865295 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286428 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.373009 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433949818 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 155380202 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542435049 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18604092 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116496134 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58311036 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 855 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3087126857 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2089 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116496134 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456815247 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 101557658 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5194 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535499027 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56492035 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3005134049 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 566488 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1739616 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50408333 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2246840239 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3897438135 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3896197591 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1240544 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1266766339 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.286457 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.373232 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 433937783 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 155286584 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542483654 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18560300 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116498018 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58313191 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 862 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3087105649 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2059 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116498018 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456816204 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 101540810 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6220 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535489445 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56415642 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3005086963 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 566623 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1738834 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 50324811 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2246778226 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3897347889 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3896105158 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1242731 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 870637276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 168 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 870575263 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 167 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 166 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121366950 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679350790 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255350759 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67967300 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 37114772 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2723579625 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 126 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508981641 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3091159 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 978310045 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 415071720 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 97 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1266865295 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.980464 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.972855 # Number of insts issued each cycle +system.cpu.rename.skidInsts 121265991 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679360736 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255356957 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68007624 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36872048 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2723554804 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 129 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2508984537 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3092752 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 978311226 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 415025058 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 100 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1266766339 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.980621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.972970 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 426523141 33.67% 33.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201951837 15.94% 49.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185492394 14.64% 64.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153160708 12.09% 76.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133131866 10.51% 86.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81031270 6.40% 93.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65244416 5.15% 98.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15224722 1.20% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5104941 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 426534847 33.67% 33.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201890440 15.94% 49.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185333352 14.63% 64.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153215856 12.10% 76.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133163574 10.51% 86.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 81070069 6.40% 93.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65235911 5.15% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15218602 1.20% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5103688 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1266865295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1266766339 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2143481 11.64% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11871999 64.46% 76.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4401590 23.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2143232 11.63% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11878025 64.46% 76.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4404432 23.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643559437 65.51% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643533281 65.51% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 99 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 261 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 268 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 162 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 31 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 192 0.00% 65.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 26 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.51% # Type of FU issued @@ -373,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.51% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641411468 25.56% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224010136 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641423714 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224026917 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508981641 # Type of FU issued -system.cpu.iq.rate 1.884268 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18417070 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007340 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6304440735 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3700781380 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412589185 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1896071 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1214370 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 849902 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526461544 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 937167 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62583251 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2508984537 # Type of FU issued +system.cpu.iq.rate 1.884482 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18425689 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007344 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6304354052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3700755338 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2412575558 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1899802 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1217218 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 851053 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2526471243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 938983 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62590757 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234755127 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 263530 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107682 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94622257 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234765073 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 264281 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 108176 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94628455 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 167 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1505929 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 156 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1505453 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116496134 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45259128 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1153276 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2865598045 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8882954 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679350790 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255350759 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 126 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 296462 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17110 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107682 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10363121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8561161 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18924282 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461596227 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625038408 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47385414 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116498018 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 45291754 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1153048 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2865571059 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8871235 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679360736 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255356957 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 129 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 296395 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17051 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 108176 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10360108 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8562955 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18923063 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2461579211 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625041270 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47405326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142018294 # number of nop insts executed -system.cpu.iew.exec_refs 844427141 # number of memory reference insts executed -system.cpu.iew.exec_branches 300792164 # Number of branches executed -system.cpu.iew.exec_stores 219388733 # Number of stores executed -system.cpu.iew.exec_rate 1.848681 # Inst execution rate -system.cpu.iew.wb_sent 2441396740 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413439087 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388573479 # num instructions producing a value -system.cpu.iew.wb_consumers 1764243384 # num instructions consuming a value +system.cpu.iew.exec_nop 142016126 # number of nop insts executed +system.cpu.iew.exec_refs 844447329 # number of memory reference insts executed +system.cpu.iew.exec_branches 300798489 # Number of branches executed +system.cpu.iew.exec_stores 219406059 # Number of stores executed +system.cpu.iew.exec_rate 1.848876 # Inst execution rate +system.cpu.iew.wb_sent 2441376362 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2413426611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388583006 # num instructions producing a value +system.cpu.iew.wb_consumers 1764301470 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.812515 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.787065 # average fanout of values written-back +system.cpu.iew.wb_rate 1.812709 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.787044 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 824671147 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 824638318 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16085857 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1150369161 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.581910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.512649 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16087839 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1150268321 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.582048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.512804 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 636844570 55.36% 55.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174611268 15.18% 70.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86171312 7.49% 78.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53631613 4.66% 82.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34569452 3.01% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25367501 2.21% 87.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21831937 1.90% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22907604 1.99% 91.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94433904 8.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 636823398 55.36% 55.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174498580 15.17% 70.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86188355 7.49% 78.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53663047 4.67% 82.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34548846 3.00% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25343487 2.20% 87.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21850232 1.90% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22917524 1.99% 91.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94434852 8.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1150369161 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1150268321 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,189 +461,189 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94433904 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94434852 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3614607330 # The number of ROB reads -system.cpu.rob.rob_writes 5405498913 # The number of ROB writes -system.cpu.timesIdled 817784 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64676651 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3614472713 # The number of ROB reads +system.cpu.rob.rob_writes 5405435258 # The number of ROB writes +system.cpu.timesIdled 818038 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64625639 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.766998 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.766998 # CPI: Total CPI of All Threads -system.cpu.ipc 1.303785 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.303785 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3317361939 # number of integer regfile reads -system.cpu.int_regfile_writes 1931707111 # number of integer regfile writes -system.cpu.fp_regfile_reads 30073 # number of floating regfile reads -system.cpu.fp_regfile_writes 529 # number of floating regfile writes +system.cpu.cpi 0.766912 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.766912 # CPI: Total CPI of All Threads +system.cpu.ipc 1.303931 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.303931 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3317336179 # number of integer regfile reads +system.cpu.int_regfile_writes 1931663734 # number of integer regfile writes +system.cpu.fp_regfile_reads 30582 # number of floating regfile reads +system.cpu.fp_regfile_writes 562 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 776.168102 # Cycle average of tags in use -system.cpu.icache.total_refs 390786293 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 969 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 403288.228070 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 772.833210 # Cycle average of tags in use +system.cpu.icache.total_refs 390788277 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 961 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 406647.530697 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 776.168102 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.378988 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.378988 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390786293 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390786293 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390786293 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390786293 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390786293 # number of overall hits -system.cpu.icache.overall_hits::total 390786293 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1474 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1474 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1474 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1474 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1474 # number of overall misses -system.cpu.icache.overall_misses::total 1474 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 87004499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 87004499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 87004499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 87004499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 87004499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 87004499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390787767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390787767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390787767 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390787767 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390787767 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390787767 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 772.833210 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.377360 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.377360 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 390788277 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 390788277 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 390788277 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 390788277 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 390788277 # number of overall hits +system.cpu.icache.overall_hits::total 390788277 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1461 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1461 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1461 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1461 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1461 # number of overall misses +system.cpu.icache.overall_misses::total 1461 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 84586499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 84586499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 84586499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 84586499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 84586499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 84586499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 390789738 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 390789738 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 390789738 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 390789738 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 390789738 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 390789738 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59026.118725 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59026.118725 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59026.118725 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59026.118725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59026.118725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59026.118725 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1157 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57896.303217 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 57896.303217 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 57896.303217 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 57896.303217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 57896.303217 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 57896.303217 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1190 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 289.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 238 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 505 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 505 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 505 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 505 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75065.967304 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62721.362229 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75447.107254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75440.836728 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62721.362229 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75447.107254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75440.836728 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214107 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.214190 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61254.942768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75750.557143 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -652,180 +652,180 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019771 # number of writebacks -system.cpu.l2cache.writebacks::total 1019771 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190438 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191407 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 775134 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 775134 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 969 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50305.499484 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62988.955050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62982.705361 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214107 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214190 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48838.479709 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63300.969359 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63289.303810 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62472.130081 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62472.130081 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48838.479709 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62974.126429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62967.218526 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48838.479709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62974.126429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62967.218526 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176037 # number of replacements -system.cpu.dcache.tagsinuse 4087.525084 # Cycle average of tags in use -system.cpu.dcache.total_refs 694351222 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180133 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.636292 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9176040 # number of replacements +system.cpu.dcache.tagsinuse 4087.524129 # Cycle average of tags in use +system.cpu.dcache.total_refs 694346796 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180136 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.635785 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.525084 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4087.524129 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997931 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997931 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538704902 # 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number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 518986048308 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 518986048308 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549984845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549984845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 519240752713 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 519240752713 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 519240752713 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 519240752713 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 549981274 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 549981274 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710713347 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710713347 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710713347 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710713347 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020510 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020510 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031620 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023022 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023022 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023022 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023022 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26145.856854 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26145.856854 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44087.783760 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44087.783760 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710709776 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710709776 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710709776 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710709776 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020512 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020512 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031618 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.031618 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023023 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023023 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023023 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023023 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26167.913100 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26167.913100 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44085.212756 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44085.212756 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31718.737826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31718.737826 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31718.737826 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12309965 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5809756 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 734892 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.750713 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.196979 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31732.644407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31732.644407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31732.644407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31732.644407 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12246964 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5806156 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 735074 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.660859 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.140339 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3724718 # number of writebacks -system.cpu.dcache.writebacks::total 3724718 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3983366 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3983366 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198630 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3198630 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7181996 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7181996 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7181996 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7181996 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296577 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296577 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724734 # number of writebacks +system.cpu.dcache.writebacks::total 3724734 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3984427 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3984427 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198422 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3198422 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7182849 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7182849 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7182849 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7182849 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883572 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883572 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180132 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180132 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180132 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180132 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159251608500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 159251608500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71602703007 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71602703007 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159317479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 159317479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71504257401 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71504257401 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230854311507 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230854311507 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230854311507 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230854311507 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230821736901 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230821736901 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230821736901 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230821736901 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013267 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013267 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012917 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012917 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012917 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.522913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.522913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38014.660048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38014.660048 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21834.592465 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21834.592465 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37962.051571 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37962.051571 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25147.166893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25147.166893 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25143.610296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25143.610296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25143.610296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25143.610296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 8f6283962..765d31514 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517371 # Number of seconds simulated -sim_ticks 517371024000 # Number of ticks simulated -final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517386 # Number of seconds simulated +sim_ticks 517386284000 # Number of ticks simulated +final_tick 517386284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139447 # Simulator instruction rate (inst/s) -host_op_rate 155563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46709499 # Simulator tick rate (ticks/s) -host_mem_usage 485516 # Number of bytes of host memory used -host_seconds 11076.36 # Real time elapsed on the host +host_inst_rate 116249 # Simulator instruction rate (inst/s) +host_op_rate 129685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38940374 # Simulator tick rate (ticks/s) +host_mem_usage 515484 # Number of bytes of host memory used +host_seconds 13286.63 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143734144 # Number of bytes read from this memory -system.physmem.bytes_read::total 143782208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70446784 # Number of bytes written to this memory -system.physmem.bytes_written::total 70446784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246597 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100731 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100731 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277816378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 277909279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136162987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136162987 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136162987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277816378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 414072265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246597 # Total number of read requests seen -system.physmem.writeReqs 1100731 # Total number of write requests seen -system.physmem.cpureqs 3350452 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143782208 # Total number of bytes read from memory -system.physmem.bytesWritten 70446784 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143782208 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70446784 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 642 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143753728 # Number of bytes read from this memory +system.physmem.bytes_read::total 143802048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70452928 # Number of bytes written to this memory +system.physmem.bytes_written::total 70452928 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2246152 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246907 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100827 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100827 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 93393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277846036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 277939428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 93393 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 93393 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136170846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136170846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136170846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 93393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277846036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 414110274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246907 # Total number of read requests seen +system.physmem.writeReqs 1100827 # Total number of write requests seen +system.physmem.cpureqs 3347751 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143802048 # Total number of bytes read from memory +system.physmem.bytesWritten 70452928 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143802048 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70452928 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 626 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 141495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 139690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 142295 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140068 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141091 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 138519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 136203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 141066 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 139208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 139271 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 141669 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69094 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 68448 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69468 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 68952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 69046 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 67828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 66957 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69534 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69263 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 69109 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 68653 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68959 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 141345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 139694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 141615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 141701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 142344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 140081 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 141241 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 140671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 138680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 136252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 140704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 140722 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 141030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 139261 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 139241 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 141699 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69025 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 68435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 69163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 69463 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 69359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 68971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 69032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68404 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 67870 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 66992 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 69579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 69317 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 69127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 68645 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 68513 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 68932 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3124 # Number of times wr buffer was full causing retry -system.physmem.totGap 517370944500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times wr buffer was full causing retry +system.physmem.totGap 517386204500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246597 # Categorize read packet sizes +system.physmem.readPktSize::6 2246907 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100731 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1563680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 451075 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 162592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100827 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1563682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 451240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 68808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,68 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 44125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 44008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see -system.physmem.totQLat 51812524750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 131293078500 # Sum of mem lat for all requests -system.physmem.totBusLat 11229775000 # Total cycles spent in databus access -system.physmem.totBankLat 68250778750 # Total cycles spent in bank access -system.physmem.avgQLat 23069.26 # Average queueing delay per request -system.physmem.avgBankLat 30388.31 # Average bank access latency per request +system.physmem.totQLat 51773260500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 131271366750 # Sum of mem lat for all requests +system.physmem.totBusLat 11231405000 # Total cycles spent in databus access +system.physmem.totBankLat 68266701250 # Total cycles spent in bank access +system.physmem.avgQLat 23048.43 # Average queueing delay per request +system.physmem.avgBankLat 30390.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58457.57 # Average memory access latency -system.physmem.avgRdBW 277.91 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 136.16 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 277.91 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 136.16 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 58439.42 # Average memory access latency +system.physmem.avgRdBW 277.94 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 136.17 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 277.94 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 136.17 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.23 # Data bus utilization in percentage +system.physmem.busUtil 3.24 # Data bus utilization in percentage system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 10.92 # Average write queue length over time -system.physmem.readRowHits 827855 # Number of row buffer hits during reads -system.physmem.writeRowHits 271156 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes -system.physmem.avgGap 154562.37 # Average gap between requests -system.cpu.branchPred.lookups 303290873 # Number of BP lookups -system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174596633 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits +system.physmem.avgWrQLen 10.87 # Average write queue length over time +system.physmem.readRowHits 827731 # Number of row buffer hits during reads +system.physmem.writeRowHits 271594 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 24.67 # Row buffer hit rate for writes +system.physmem.avgGap 154548.18 # Average gap between requests +system.cpu.branchPred.lookups 303270186 # Number of BP lookups +system.cpu.branchPred.condPredicted 249470609 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15218764 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 173872286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161453824 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.481343 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.857711 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17556602 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 209 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,99 +229,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1034742049 # number of cpu cycles simulated +system.cpu.numCycles 1034772569 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303290873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155399906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 380 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 288562414 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5732154 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958634216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.523474 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.213325 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298199766 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2186256801 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303270186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179010426 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435094842 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87837458 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155394915 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 268 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 288550611 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5724997 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 958581863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.523504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.213349 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 523513675 54.61% 54.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25518990 2.66% 57.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39095186 4.08% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48349741 5.04% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43010158 4.49% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46440341 4.84% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38425121 4.01% 79.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18710957 1.95% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175570047 18.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 523487088 54.61% 54.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25513973 2.66% 57.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39086986 4.08% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48352591 5.04% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43006673 4.49% 70.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46441362 4.84% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38409512 4.01% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18721015 1.95% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175562663 18.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958634216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293108 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.112936 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 329763250 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 133666994 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405221512 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20079412 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69903048 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46058380 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2367190993 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2433 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69903048 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 353304996 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63447183 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15614 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400231748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71731627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2304653779 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 133097 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5040028 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58589233 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 7 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2280042978 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10643127773 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10643124880 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2893 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 958581863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.293079 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.112790 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 329745900 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 133661747 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405202825 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20079986 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69891405 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46059780 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 688 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2367115109 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2459 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69891405 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 353286700 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63436503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16572 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400214250 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71736433 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2304580712 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133421 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5040530 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 58596294 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 8 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2279975350 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10642754356 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10642751444 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2912 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 573723048 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 497 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 494 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158827938 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624515157 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220983969 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86332349 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71315853 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2201513470 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018112827 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4002858 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 473886256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1126241029 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958634216 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.105196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906381 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 573655420 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 616 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 613 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 158838581 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624481317 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220982521 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86134760 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71220480 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2201443562 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 640 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018130110 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4002265 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 473800004 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1125761712 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 470 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 958581863 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.105329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906457 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277594004 28.96% 28.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151404549 15.79% 44.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161201477 16.82% 61.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119812250 12.50% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123999377 12.94% 87.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73820536 7.70% 94.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38419650 4.01% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9808498 1.02% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2573875 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 277596353 28.96% 28.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151362321 15.79% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161174547 16.81% 61.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119755421 12.49% 74.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124050787 12.94% 87.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73850082 7.70% 94.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38416449 4.01% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9807044 1.02% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2568859 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958634216 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 958581863 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 872312 3.66% 3.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5645 0.02% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 872338 3.65% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5545 0.02% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available @@ -349,13 +349,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18268766 76.62% 80.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4697940 19.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18290184 76.58% 80.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4715401 19.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236677496 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 926030 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236676135 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925418 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -377,90 +377,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 33 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 42 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587482532 29.11% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193026708 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587478696 29.11% 90.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193049790 9.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018112827 # Type of FU issued -system.cpu.iq.rate 1.950354 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23844663 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011815 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5022707128 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2675590256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957438118 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 556 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2041957357 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64629974 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018130110 # Type of FU issued +system.cpu.iq.rate 1.950313 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23883468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011834 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5022727533 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2675434216 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957455216 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 532 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042013436 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 142 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64634043 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138588388 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271831 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192988 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46136924 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138554548 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 275107 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 193018 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46135476 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4659196 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4656763 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69903048 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28888784 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1501235 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2201514122 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6139547 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624515157 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220983969 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 460 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 475783 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 89669 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192988 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8156378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9617829 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17774207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988116656 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573901246 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29996171 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69891405 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28868892 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1502139 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2201444330 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6139194 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624481317 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220982521 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 578 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 475852 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 89903 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 193018 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8153538 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9615023 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17768561 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988122287 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573893211 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30007823 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 130 # number of nop insts executed -system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed -system.cpu.iew.exec_branches 238330373 # Number of branches executed -system.cpu.iew.exec_stores 190143920 # Number of stores executed -system.cpu.iew.exec_rate 1.921365 # Inst execution rate -system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957438221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296419261 # num instructions producing a value -system.cpu.iew.wb_consumers 2061223018 # num instructions consuming a value +system.cpu.iew.exec_nop 128 # number of nop insts executed +system.cpu.iew.exec_refs 764057589 # number of memory reference insts executed +system.cpu.iew.exec_branches 238332739 # Number of branches executed +system.cpu.iew.exec_stores 190164378 # Number of stores executed +system.cpu.iew.exec_rate 1.921313 # Inst execution rate +system.cpu.iew.wb_sent 1965900634 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957455330 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296412413 # num instructions producing a value +system.cpu.iew.wb_consumers 2061187346 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.891716 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628956 # average fanout of values written-back +system.cpu.iew.wb_rate 1.891677 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.628964 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 478537797 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 478468669 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15221576 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888731168 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.938802 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727796 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15218100 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 888690458 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.938891 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727933 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 401249220 45.15% 45.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192209497 21.63% 66.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72554391 8.16% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35214687 3.96% 78.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19001350 2.14% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30768614 3.46% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20079948 2.26% 86.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11444333 1.29% 88.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106209128 11.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 401243318 45.15% 45.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192174198 21.62% 66.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72553521 8.16% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35226900 3.96% 78.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18988678 2.14% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30770684 3.46% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20065099 2.26% 86.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11431293 1.29% 88.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106236767 11.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888731168 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 888690458 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -471,70 +471,70 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106209128 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106236767 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2984133091 # The number of ROB reads -system.cpu.rob.rob_writes 4473274350 # The number of ROB writes -system.cpu.timesIdled 1017651 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76107833 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2983995614 # The number of ROB reads +system.cpu.rob.rob_writes 4473124072 # The number of ROB writes +system.cpu.timesIdled 1018062 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76190706 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.669925 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.669925 # CPI: Total CPI of All Threads -system.cpu.ipc 1.492703 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.492703 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956233395 # number of integer regfile reads -system.cpu.int_regfile_writes 1937436072 # number of integer regfile writes -system.cpu.fp_regfile_reads 98 # number of floating regfile reads -system.cpu.fp_regfile_writes 104 # number of floating regfile writes -system.cpu.misc_regfile_reads 737527238 # number of misc regfile reads +system.cpu.cpi 0.669945 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.669945 # CPI: Total CPI of All Threads +system.cpu.ipc 1.492659 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.492659 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9956292181 # number of integer regfile reads +system.cpu.int_regfile_writes 1937433329 # number of integer regfile writes +system.cpu.fp_regfile_reads 115 # number of floating regfile reads +system.cpu.fp_regfile_writes 119 # number of floating regfile writes +system.cpu.misc_regfile_reads 737551848 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 22 # number of replacements -system.cpu.icache.tagsinuse 625.709575 # Cycle average of tags in use -system.cpu.icache.total_refs 288561231 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370425.200257 # Average number of references to valid blocks. +system.cpu.icache.replacements 24 # number of replacements +system.cpu.icache.tagsinuse 627.796190 # Cycle average of tags in use +system.cpu.icache.total_refs 288549428 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 783 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 368517.787995 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 625.709575 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.305522 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.305522 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 288561231 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 288561231 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 288561231 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 288561231 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 288561231 # number of overall hits -system.cpu.icache.overall_hits::total 288561231 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 627.796190 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306541 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306541 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 288549428 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 288549428 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 288549428 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 288549428 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 288549428 # number of overall hits +system.cpu.icache.overall_hits::total 288549428 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1183 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1183 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1183 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1183 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1183 # number of overall misses system.cpu.icache.overall_misses::total 1183 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 68862000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 68862000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 68862000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 68862000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 68862000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 68862000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 288562414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 288562414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 288562414 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 288562414 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 288562414 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 288562414 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66818000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66818000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66818000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66818000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66818000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66818000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 288550611 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 288550611 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 288550611 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 288550611 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 288550611 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 288550611 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58209.636517 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58209.636517 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58209.636517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58209.636517 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56481.825866 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56481.825866 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56481.825866 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56481.825866 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56481.825866 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56481.825866 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -543,120 +543,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 65 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 404 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 404 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 404 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 404 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46813500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46813500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46813500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46813500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46813500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46813500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 400 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 400 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 400 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 400 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 400 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 783 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 783 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 783 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 783 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46629500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 46629500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46629500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 46629500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46629500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 46629500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60094.351733 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60094.351733 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59552.362708 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59552.362708 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59552.362708 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59552.362708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59552.362708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59552.362708 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2213910 # number of replacements -system.cpu.l2cache.tagsinuse 31531.957469 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9247495 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2243685 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.121566 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2214216 # number of replacements +system.cpu.l2cache.tagsinuse 31531.914906 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9246344 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2243990 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.120493 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 20448147251 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14435.927117 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 20.343245 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17075.687107 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440550 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000621 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.521109 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.962279 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 14434.884106 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 20.460044 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17076.570756 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440518 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000624 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.521136 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.962278 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6290241 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6290268 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3781695 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3781695 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1066899 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1066899 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6289407 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6289434 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3781376 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3781376 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1066860 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1066860 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7357140 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7357167 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7356267 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7356294 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 27 # 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number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9602994 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9603773 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965340 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184086 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.184165 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965340 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233870 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233930 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965340 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82044.172855 # average overall miss latency +system.cpu.l2cache.overall_hits::cpu.data 7356267 # number of overall hits +system.cpu.l2cache.overall_hits::total 7356294 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 756 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1419505 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1420261 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 826656 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826656 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 756 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2246161 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2246917 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 756 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233976 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233916 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233976 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60273.809524 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80148.534524 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80137.955277 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85268.415762 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85268.415762 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60273.809524 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82032.807532 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82025.486478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60273.809524 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82032.807532 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82025.486478 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,187 +665,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100731 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36118599 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156391540883 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 156427659482 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184085 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184164 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233869 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419496 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1420251 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826656 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60227207126 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35881848 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156370756270 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156406638118 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35881848 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156370756270 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156406638118 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964240 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184137 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184216 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436572 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436572 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233975 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233975 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47525.626490 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67730.764401 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67720.023427 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72856.432574 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72856.432574 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47525.626490 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69617.174737 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69609.751591 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47525.626490 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69617.174737 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69609.751591 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 323000428500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 229631369718 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 229631369718 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 423500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 423500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 552631798218 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 552631798218 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 552631798218 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 552631798218 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500530116 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500530116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17015493 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17015493 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17015493 # number of overall misses +system.cpu.dcache.overall_misses::total 17015493 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 322799095500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 322799095500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 229643990242 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 229643990242 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 608000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 608000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 552443085742 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 552443085742 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 552443085742 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 552443085742 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500520613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500520613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673116163 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673116163 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673116163 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673116163 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025281 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025281 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025281 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025281 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28139.570735 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28139.570735 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389561 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389561 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 141166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 141166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32474.859624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32474.859624 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26343962 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1054966 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1182360 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64552 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.280830 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.342886 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673106660 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673106660 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673106660 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673106660 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022929 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032095 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025279 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025279 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025279 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025279 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28127.326131 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28127.326131 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41458.412097 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41458.412097 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 202666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 202666.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32467.063149 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32467.063149 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32467.063149 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32467.063149 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26333844 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1054452 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1182092 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 64550 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.277322 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16.335430 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781695 # number of writebacks -system.cpu.dcache.writebacks::total 3781695 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3769070 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3769070 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645155 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3645155 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781376 # number of writebacks +system.cpu.dcache.writebacks::total 3781376 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767440 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3767440 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645625 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3645625 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7414225 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7414225 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7414225 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7414225 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709443 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7709443 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893551 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893551 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602994 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602994 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602994 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602994 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186232562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 186232562000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83589909224 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83589909224 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269822471224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 269822471224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269822471224 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 269822471224 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7413065 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7413065 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7413065 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7413065 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708912 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708912 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893516 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893516 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9602428 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9602428 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9602428 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9602428 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186208076000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 186208076000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83587939217 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83587939217 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269796015217 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 269796015217 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269796015217 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 269796015217 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24156.422455 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24156.422455 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.524876 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.524876 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24154.910057 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24154.910057 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.300453 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.300453 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28096.645475 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28096.645475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28096.645475 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28096.645475 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 3e3128027..91c2fb18d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.954691 # Nu sim_ticks 1954691371500 # Number of ticks simulated final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 798728 # Simulator instruction rate (inst/s) -host_op_rate 798728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26318676085 # Simulator tick rate (ticks/s) -host_mem_usage 332420 # Number of bytes of host memory used -host_seconds 74.27 # Real time elapsed on the host +host_inst_rate 888978 # Simulator instruction rate (inst/s) +host_op_rate 888978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29292473013 # Simulator tick rate (ticks/s) +host_mem_usage 331536 # Number of bytes of host memory used +host_seconds 66.73 # Real time elapsed on the host sim_insts 59321614 # Number of instructions simulated sim_ops 59321614 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory @@ -50,13 +50,13 @@ system.physmem.bw_total::cpu1.data 199364 # To system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 447836 # Total number of read requests seen system.physmem.writeReqs 119953 # Total number of write requests seen -system.physmem.cpureqs 572898 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 570963 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 28661504 # Total number of bytes read from memory system.physmem.bytesWritten 7676992 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 3162 # Reqs where no action is needed system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis @@ -90,7 +90,7 @@ system.physmem.perBankWrReqs::13 7492 # Tr system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 12 # Number of times wr buffer was full causing retry system.physmem.totGap 1954684300500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -106,26 +106,26 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 119953 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407019 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4805 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1540 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1510 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 781 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see @@ -161,23 +161,23 @@ system.physmem.wrQLenPdf::19 5215 # Wh system.physmem.wrQLenPdf::20 5215 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5215 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.totQLat 4783798250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13397999500 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::23 1508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see +system.physmem.totQLat 4783941000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13398087250 # Sum of mem lat for all requests system.physmem.totBusLat 2238835000 # Total cycles spent in databus access -system.physmem.totBankLat 6375366250 # Total cycles spent in bank access -system.physmem.avgQLat 10683.68 # Average queueing delay per request -system.physmem.avgBankLat 14238.13 # Average bank access latency per request +system.physmem.totBankLat 6375311250 # Total cycles spent in bank access +system.physmem.avgQLat 10684.00 # Average queueing delay per request +system.physmem.avgBankLat 14238.01 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29921.81 # Average memory access latency +system.physmem.avgMemAccLat 29922.01 # Average memory access latency system.physmem.avgRdBW 14.66 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.66 # Average consumed read bandwidth in MB/s @@ -192,14 +192,14 @@ system.physmem.readRowHitRate 93.77 # Ro system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes system.physmem.avgGap 3442624.46 # Average gap between requests system.l2c.replacements 340771 # number of replacements -system.l2c.tagsinuse 65303.436480 # Cycle average of tags in use -system.l2c.total_refs 2493415 # Total number of references to valid blocks. +system.l2c.tagsinuse 65303.436431 # Cycle average of tags in use +system.l2c.total_refs 2493405 # Total number of references to valid blocks. system.l2c.sampled_refs 405943 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.142279 # Average number of references to valid blocks. +system.l2c.avg_refs 6.142254 # Average number of references to valid blocks. system.l2c.warmup_cycle 6937754751 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55559.705668 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4839.489270 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4775.815267 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 55559.705591 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4839.489284 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4775.815281 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 117.980929 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 10.445347 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.847774 # Average percentage of cache occupancy @@ -209,39 +209,39 @@ system.l2c.occ_percent::cpu1.inst 0.001800 # Av system.l2c.occ_percent::cpu1.data 0.000159 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.996451 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 902966 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 773506 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 773500 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 86370 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 33767 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1796609 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 820435 # number of Writeback hits -system.l2c.Writeback_hits::total 820435 # number of Writeback hits +system.l2c.ReadReq_hits::total 1796603 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 820431 # number of Writeback hits +system.l2c.Writeback_hits::total 820431 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 171833 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 171831 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 12858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 184691 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 184689 # number of ReadExReq hits system.l2c.demand_hits::cpu0.inst 902966 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 945339 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 945331 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 86370 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 46625 # number of demand (read+write) hits -system.l2c.demand_hits::total 1981300 # number of demand (read+write) hits +system.l2c.demand_hits::total 1981292 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 902966 # number of overall hits -system.l2c.overall_hits::cpu0.data 945339 # number of overall hits +system.l2c.overall_hits::cpu0.data 945331 # number of overall hits system.l2c.overall_hits::cpu1.inst 86370 # number of overall hits system.l2c.overall_hits::cpu1.data 46625 # number of overall hits -system.l2c.overall_hits::total 1981300 # number of overall hits +system.l2c.overall_hits::total 1981292 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 12959 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 271596 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 545 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 189 # number of ReadReq misses system.l2c.ReadReq_misses::total 285289 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2443 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2926 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.259875 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.259877 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.006270 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.005566 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137033 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937428 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.137034 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937452 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.896104 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930344 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.930366 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.562500 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 32932.289205 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -492,7 +492,7 @@ system.iocache.tagsinuse 0.572561 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1746701282000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1746701284000 # Cycle when the warmup percentage was hit. system.iocache.occ_blocks::tsunami.ide 0.572561 # Average occupied blocks per requestor system.iocache.occ_percent::tsunami.ide 0.035785 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.035785 # Average percentage of cache occupancy @@ -506,12 +506,12 @@ system.iocache.overall_misses::tsunami.ide 41726 # system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10674900806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10674900806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10695943804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10695943804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10695943804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10695943804 # 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average overall miss latency +system.iocache.demand_avg_miss_latency::total 256353.920194 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 256353.920194 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 256353.920194 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 286338 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27291 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27305 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.492104 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.486651 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -556,12 +556,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41726 system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8513588925 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8513588925 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8525583174 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8525583174 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8525583174 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8525583174 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -572,12 +572,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204889.991456 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204889.991456 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204323.040167 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204323.040167 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204323.040167 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204323.040167 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -641,8 +641,8 @@ system.cpu0.num_fp_register_writes 146520 # nu system.cpu0.num_mem_refs 14722187 # number of memory refs system.cpu0.num_load_insts 8662865 # Number of load instructions system.cpu0.num_store_insts 6059322 # Number of store instructions -system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles -system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles +system.cpu0.num_idle_cycles 3679287255.686766 # Number of idle cycles +system.cpu0.num_busy_cycles 228924280.313234 # Number of busy cycles system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -660,11 +660,11 @@ system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # nu system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1898301427500 97.14% 97.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 762226000 0.04% 97.19% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 54943825500 2.81% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -730,8 +730,8 @@ system.cpu0.kern.mode_switch_good::kernel 0.175657 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3454635500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1950347158000 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3454773000 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3897 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -766,12 +766,12 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.icache.replacements 915312 # number of replacements -system.cpu0.icache.tagsinuse 509.170565 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 509.170564 # Cycle average of tags in use system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.170565 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.170564 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits @@ -786,12 +786,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 915946 # system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses system.cpu0.icache.overall_misses::total 915946 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645153500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12645153500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12645153500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12645153500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12645153500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12645153500 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645308000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12645308000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12645308000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12645308000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12645308000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12645308000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses @@ -804,12 +804,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940 system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.566595 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.566595 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13805.566595 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13805.566595 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.735273 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.735273 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.735273 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13805.735273 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.735273 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13805.735273 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -824,70 +824,70 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 915946 system.cpu0.icache.demand_mshr_misses::total 915946 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 915946 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 915946 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813261500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813261500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813261500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10813261500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813261500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10813261500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813416000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813416000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813416000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10813416000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813416000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10813416000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.566595 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.735273 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.735273 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.735273 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1337909 # number of replacements -system.cpu0.dcache.tagsinuse 506.537579 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13346950 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338324 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.972884 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337901 # number of replacements +system.cpu0.dcache.tagsinuse 506.537580 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13346958 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1338316 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.972950 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.537579 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 506.537580 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.989331 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.989331 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7419116 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7419116 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5560491 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5560491 # number of WriteReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 7419122 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7419122 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5560492 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5560492 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176356 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 176356 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191669 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 191669 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12979607 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12979607 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12979607 # number of overall hits -system.cpu0.dcache.overall_hits::total 12979607 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1035921 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1035921 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291041 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291041 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 12979614 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12979614 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12979614 # number of overall hits +system.cpu0.dcache.overall_hits::total 12979614 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1035915 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1035915 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291040 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 291040 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16710 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 16710 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 430 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326962 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326962 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326962 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326962 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391252000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 22391252000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190685500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8190685500 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1326955 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326955 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326955 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326955 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391266500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 22391266500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190691500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8190691500 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219165000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 219165000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2509000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 2509000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 30581937500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 30581937500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 30581937500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 30581937500 # number of overall miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 30581958000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 30581958000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 30581958000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 30581958000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 8455037 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8455037 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851532 # number of WriteReq accesses(hits+misses) @@ -900,30 +900,30 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14306569 system.cpu0.dcache.demand_accesses::total 14306569 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 14306569 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14306569 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122521 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122521 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049738 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049738 # miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122520 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122520 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049737 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049737 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086551 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092752 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092752 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092752 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092752 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.825841 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.825841 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.720441 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.720441 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092751 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092751 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092751 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092751 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.965031 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.965031 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.837754 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.837754 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.718238 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23046.718238 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.718238 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23046.718238 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -932,62 +932,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks -system.cpu0.dcache.writebacks::total 789805 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035921 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1035921 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291041 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 291041 # number of WriteReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 789801 # number of writebacks +system.cpu0.dcache.writebacks::total 789801 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035915 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1035915 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291040 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291040 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326962 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1326962 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326962 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1326962 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319410000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319410000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608603500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608603500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326955 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326955 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326955 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326955 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319436500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319436500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608611500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608611500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928013500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 27928013500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928013500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 27928013500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465455500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465455500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092162000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092162000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557617500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928048000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 27928048000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928048000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 27928048000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465347500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465347500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092159000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092159000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557506500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557506500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122520 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122520 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049737 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049737 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092751 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092751 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092751 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092751 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.965031 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.965031 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.837754 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.837754 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.718238 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.718238 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.718238 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.718238 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1045,8 +1045,8 @@ system.cpu1.num_fp_register_writes 21862 # nu system.cpu1.num_mem_refs 1706720 # number of memory refs system.cpu1.num_load_insts 1053093 # Number of load instructions system.cpu1.num_store_insts 653627 # Number of store instructions -system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles +system.cpu1.num_idle_cycles 3890042730.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 19340012.001990 # Number of busy cycles system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -1062,10 +1062,10 @@ system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # nu system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1917858601000 98.12% 98.12% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 36066950000 1.85% 100.00% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1138,12 +1138,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 86916 # system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses system.cpu1.icache.overall_misses::total 86916 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175951500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1175951500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1175951500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1175951500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1175951500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1175951500 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175956500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1175956500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1175956500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1175956500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1175956500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1175956500 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses @@ -1156,12 +1156,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.747112 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.747112 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13529.747112 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13529.747112 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.804639 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.804639 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13529.804639 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13529.804639 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1176,70 +1176,70 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916 system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002119500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002119500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002119500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 1002119500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002119500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 1002119500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002124500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002124500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002124500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1002124500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002124500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1002124500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.747112 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.804639 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.804639 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.804639 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 52807 # number of replacements system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1641018 # Total number of references to valid blocks. +system.cpu1.dcache.total_refs 1641017 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 30.777340 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1001238 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1001238 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 1001237 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1001237 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1617458 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1617458 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1617458 # number of overall hits -system.cpu1.dcache.overall_hits::total 1617458 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 37008 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 37008 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 1617457 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1617457 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1617457 # number of overall hits +system.cpu1.dcache.overall_hits::total 1617457 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 37009 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 37009 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 20401 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 956 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 500 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 500 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 57409 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 57409 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 57409 # number of overall misses -system.cpu1.dcache.overall_misses::total 57409 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463706500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 463706500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 540901000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 540901000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10601500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 10601500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.demand_misses::cpu1.data 57410 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 57410 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 57410 # number of overall misses +system.cpu1.dcache.overall_misses::total 57410 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463717500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 463717500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 540903500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 540903500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10599500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 10599500 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3694000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 3694000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1004607500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1004607500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1004607500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1004607500 # number of overall miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1004621000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1004621000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1004621000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1004621000 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038246 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1038246 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 636621 # number of WriteReq accesses(hits+misses) @@ -1252,8 +1252,8 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1674867 system.cpu1.dcache.demand_accesses::total 1674867 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 1674867 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1674867 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035645 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035645 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035646 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035646 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032046 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.032046 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081279 # miss rate for LoadLockedReq accesses @@ -1264,18 +1264,18 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277 system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.898941 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.455223 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.455223 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11089.435146 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.857602 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.857602 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.577766 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.577766 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11087.343096 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11087.343096 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.059397 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17499.059397 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.059397 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17499.059397 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1286,38 +1286,38 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks system.cpu1.dcache.writebacks::total 30630 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37008 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37009 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 37009 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 57409 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 57409 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 57409 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 57409 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389690500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389690500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500099000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500099000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8689500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57410 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57410 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57410 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57410 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389699500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389699500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500101500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500101500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8687500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8687500 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889789500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 889789500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889789500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 889789500 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889801000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 889801000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889801000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 889801000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035645 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035646 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035646 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses @@ -1328,18 +1328,18 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.898941 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.857602 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.857602 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.577766 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.577766 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9087.343096 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9087.343096 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.059397 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.059397 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.059397 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.059397 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 10a028441..9db64d392 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.913475 # Nu sim_ticks 1913474690000 # Number of ticks simulated final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1324010 # Simulator instruction rate (inst/s) -host_op_rate 1324010 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45134311907 # Simulator tick rate (ticks/s) -host_mem_usage 328328 # Number of bytes of host memory used -host_seconds 42.40 # Real time elapsed on the host +host_inst_rate 960952 # Simulator instruction rate (inst/s) +host_op_rate 960952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32757999490 # Simulator tick rate (ticks/s) +host_mem_usage 329472 # Number of bytes of host memory used +host_seconds 58.41 # Real time elapsed on the host sim_insts 56131527 # Number of instructions simulated sim_ops 56131527 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory @@ -40,7 +40,7 @@ system.physmem.bw_total::tsunami.ide 1386010 # To system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 443158 # Total number of read requests seen system.physmem.writeReqs 115703 # Total number of write requests seen -system.physmem.cpureqs 560726 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 559001 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 28362112 # Total number of bytes read from memory system.physmem.bytesWritten 7404992 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize() @@ -80,7 +80,7 @@ system.physmem.perBankWrReqs::13 7186 # Tr system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry system.physmem.totGap 1913462790000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -96,26 +96,26 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 115703 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 402452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 402453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3684 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1367 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -132,11 +132,11 @@ system.physmem.wrQLenPdf::0 3531 # Wh system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see @@ -155,19 +155,19 @@ system.physmem.wrQLenPdf::23 1500 # Wh system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see -system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::27 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.totQLat 4710239250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13222743000 # Sum of mem lat for all requests system.physmem.totBusLat 2215485000 # Total cycles spent in databus access -system.physmem.totBankLat 6297005000 # Total cycles spent in bank access -system.physmem.avgQLat 10649.88 # Average queueing delay per request -system.physmem.avgBankLat 14211.35 # Average bank access latency per request +system.physmem.totBankLat 6297018750 # Total cycles spent in bank access +system.physmem.avgQLat 10630.27 # Average queueing delay per request +system.physmem.avgBankLat 14211.38 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29861.22 # Average memory access latency +system.physmem.avgMemAccLat 29841.64 # Average memory access latency system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s @@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10661973806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10661973806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10682901804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10682901804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10682901804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10682901804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10653271428 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10653271428 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10674199426 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10674199426 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10674199426 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10674199426 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -224,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256593.516702 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256593.516702 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 256031.199617 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 256031.199617 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285723 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256384.083269 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256384.083269 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255822.634536 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255822.634536 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285520 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27146 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27149 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.525418 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.516778 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8499962078 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8499962078 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8511893327 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8511893327 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8511893327 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8511893327 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8491261949 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8491261949 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8503193198 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8503193198 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8503193198 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8503193198 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204562.044619 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204562.044619 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204352.665311 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204352.665311 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -335,8 +335,8 @@ system.cpu.num_fp_register_writes 166418 # nu system.cpu.num_mem_refs 15461819 # number of memory refs system.cpu.num_load_insts 9093811 # Number of load instructions system.cpu.num_store_insts 6368008 # Number of store instructions -system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles -system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles +system.cpu.num_idle_cycles 3593002703.998122 # Number of idle cycles +system.cpu.num_busy_cycles 233946676.001878 # Number of busy cycles system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles system.cpu.idle_fraction 0.938869 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed @@ -352,10 +352,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1858610730000 97.13% 97.13% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54034649000 2.82% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -420,9 +420,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323898 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 45394332000 2.37% 2.37% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5131699000 0.27% 2.64% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862947923000 97.36% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -476,12 +476,12 @@ system.cpu.icache.demand_misses::cpu.inst 928628 # n system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 928628 # number of overall misses system.cpu.icache.overall_misses::total 928628 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770278000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12770278000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12770278000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12770278000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12770278000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12770278000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770432000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12770432000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12770432000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12770432000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12770432000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12770432000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 56143366 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56143366 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 56143366 # number of demand (read+write) accesses @@ -494,12 +494,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.769277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13751.769277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13751.769277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13751.769277 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.935113 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13751.935113 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13751.935113 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13751.935113 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,53 +514,53 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 928628 system.cpu.icache.demand_mshr_misses::total 928628 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 928628 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 928628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913022000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10913022000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913022000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10913022000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913022000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10913022000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10913176000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10913176000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10913176000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10913176000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10913176000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10913176000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.769277 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.769277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.769277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.769277 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.935113 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.935113 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.935113 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11751.935113 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 336244 # number of replacements -system.cpu.l2cache.tagsinuse 65321.744295 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2445552 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 65321.744334 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2445560 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 401406 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.092465 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 6.092485 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 5250002751 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 55750.890928 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 4786.700552 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 4784.152815 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 55750.890947 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 4786.700562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 4784.152824 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.850691 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.073039 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.073000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.996731 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 915318 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 813981 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1729299 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 834498 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834498 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 813988 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1729306 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 834499 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 834499 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187514 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187514 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 915318 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001495 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 831348000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17296377000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18127725000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 928608 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1085944 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2014552 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 834498 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 834498 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1085951 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2014559 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 834499 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 834499 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304370 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304370 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 928608 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390314 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2318922 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390321 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2318929 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 928608 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390314 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2318922 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390321 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2318929 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014312 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250439 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250438 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.141596 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383927 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.383927 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014312 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279663 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279661 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.173403 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014312 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279663 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279661 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.173403 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62542.814146 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43017.388395 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 43927.082274 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62554.401806 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 43018.557671 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 43928.736946 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14576.923077 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14576.923077 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47896.197029 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47896.197029 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 45080.537864 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62542.814146 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44483.669780 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 45080.537864 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47895.880400 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47895.880400 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62554.401806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44484.392481 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 45081.619660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62554.401806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44484.392481 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 45081.619660 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -651,19 +651,19 @@ system.cpu.l2cache.demand_mshr_misses::total 402109 system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 388819 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 402109 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666266030 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8360156960 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9026422990 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 666421030 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8360475460 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9026896490 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4160193080 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4160193080 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 666266030 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12520350040 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13186616070 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 666266030 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12520350040 # 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number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895853000 # number of WriteReq MSHR uncacheable cycles @@ -671,31 +671,31 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895853000 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229999000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229999000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250438 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141596 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383927 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383927 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279661 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.173403 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279661 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.173403 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50132.884123 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30740.052728 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31643.569007 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50144.547028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30741.223843 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31645.228937 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35601.022455 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35601.022455 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35600.705826 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35600.705826 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -703,47 +703,47 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1389801 # number of replacements +system.cpu.dcache.replacements 1389808 # number of replacements system.cpu.dcache.tagsinuse 511.980871 # Cycle average of tags in use -system.cpu.dcache.total_refs 14037928 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1390313 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.096955 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14037921 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1390320 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.096899 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807394 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807394 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7807387 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807387 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5848285 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848285 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199228 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655679 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655679 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655679 # number of overall hits -system.cpu.dcache.overall_hits::total 13655679 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1068700 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1068700 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 13655672 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655672 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655672 # number of overall hits +system.cpu.dcache.overall_hits::total 13655672 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1068707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1068707 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304387 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304387 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373087 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373087 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373087 # number of overall misses -system.cpu.dcache.overall_misses::total 1373087 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22867911000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22867911000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385686000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8385686000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1373094 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373094 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373094 # number of overall misses +system.cpu.dcache.overall_misses::total 1373094 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22868320000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22868320000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385649000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8385649000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228869000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 228869000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31253597000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31253597000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31253597000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31253597000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31253969000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31253969000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31253969000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31253969000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 8876094 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8876094 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152672 # number of WriteReq accesses(hits+misses) @@ -756,8 +756,8 @@ system.cpu.dcache.demand_accesses::cpu.data 15028766 # system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15028766 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120402 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120402 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120403 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120403 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049472 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049472 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses @@ -766,16 +766,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.091364 system.cpu.dcache.demand_miss_rate::total 0.091364 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091364 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.091364 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21397.876860 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21397.876860 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.422282 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.422282 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21398.119410 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21398.119410 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.300726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.300726 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13272.384598 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22761.711143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22761.711143 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -784,36 +784,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834498 # number of writebacks -system.cpu.dcache.writebacks::total 834498 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068700 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068700 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks +system.cpu.dcache.writebacks::total 834499 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068707 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1068707 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304387 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 304387 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373087 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373087 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373087 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373087 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730511000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730511000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776912000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776912000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1373094 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373094 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373094 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373094 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776875000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776875000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194381000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194381000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507423000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28507423000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507423000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28507423000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507781000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28507781000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507781000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28507781000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120403 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses @@ -822,16 +822,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364 system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19398.119410 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19398.119410 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.300726 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.300726 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 38cfd80e2..2f6691c8d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.195162 # Nu sim_ticks 5195162021000 # Number of ticks simulated final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 926995 # Simulator instruction rate (inst/s) -host_op_rate 1786992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37543942770 # Simulator tick rate (ticks/s) -host_mem_usage 611560 # Number of bytes of host memory used -host_seconds 138.38 # Real time elapsed on the host -sim_insts 128273323 # Number of instructions simulated -sim_ops 247275942 # Number of ops (including micro ops) simulated +host_inst_rate 697576 # Simulator instruction rate (inst/s) +host_op_rate 1344736 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28252317760 # Simulator tick rate (ticks/s) +host_mem_usage 611664 # Number of bytes of host memory used +host_seconds 183.88 # Real time elapsed on the host +sim_insts 128273373 # Number of instructions simulated +sim_ops 247275988 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -48,16 +48,16 @@ system.physmem.bw_total::cpu.data 1734722 # To system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 198400 # Total number of read requests seen system.physmem.writeReqs 126924 # Total number of write requests seen -system.physmem.cpureqs 327581 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 326952 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 12697600 # Total number of bytes read from memory system.physmem.bytesWritten 8123136 # Total number of bytes written to memory system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12234 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis @@ -88,7 +88,7 @@ system.physmem.perBankWrReqs::13 7628 # Tr system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 633 # Number of times wr buffer was full causing retry +system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry system.physmem.totGap 5195161957500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes @@ -104,27 +104,27 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 126924 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 155117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2021 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 155109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -136,15 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5514 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see @@ -159,23 +159,23 @@ system.physmem.wrQLenPdf::19 5518 # Wh system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.totQLat 4073325250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7869155250 # Sum of mem lat for all requests -system.physmem.totBusLat 991710000 # Total cycles spent in databus access -system.physmem.totBankLat 2804120000 # Total cycles spent in bank access -system.physmem.avgQLat 20536.88 # Average queueing delay per request -system.physmem.avgBankLat 14137.80 # Average bank access latency per request +system.physmem.wrQLenPdf::23 1323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.totQLat 4118897499 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7915241249 # Sum of mem lat for all requests +system.physmem.totBusLat 991715000 # Total cycles spent in databus access +system.physmem.totBankLat 2804628750 # Total cycles spent in bank access +system.physmem.avgQLat 20766.54 # Average queueing delay per request +system.physmem.avgBankLat 14140.30 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39674.68 # Average memory access latency +system.physmem.avgMemAccLat 39906.83 # Average memory access latency system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s @@ -184,8 +184,8 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.66 # Average write queue length over time -system.physmem.readRowHits 175586 # Number of row buffer hits during reads -system.physmem.writeRowHits 94818 # Number of row buffer hits during writes +system.physmem.readRowHits 175593 # Number of row buffer hits during reads +system.physmem.writeRowHits 94810 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes system.physmem.avgGap 15969193.66 # Average gap between requests @@ -206,14 +206,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47564 system.iocache.demand_misses::total 47564 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses system.iocache.overall_misses::total 47564 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10699969160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10699969160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10839449092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10839449092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10839449092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10839449092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137986397 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 137986397 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732357682 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10732357682 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10870344079 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10870344079 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10870344079 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10870344079 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -230,19 +230,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229023.312500 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229023.312500 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227891.873938 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227891.873938 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 173195 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163490.991706 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 163490.991706 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.559974 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229716.559974 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228541.419540 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228541.419540 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 175903 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16181 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16290 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.703603 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.798220 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -256,14 +256,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 95570962 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8269165315 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8269165315 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8364736277 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8364736277 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94077427 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 94077427 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301559588 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8301559588 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8395637015 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8395637015 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.736967 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.736967 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176994.120612 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176994.120612 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111466.145735 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 111466.145735 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.491182 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.491182 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -296,72 +296,72 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10390324042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128273323 # Number of instructions committed -system.cpu.committedOps 247275942 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232011652 # Number of integer alu accesses +system.cpu.committedInsts 128273373 # Number of instructions committed +system.cpu.committedOps 247275988 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232011695 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls -system.cpu.num_int_insts 232011652 # number of integer instructions +system.cpu.num_conditional_control_insts 23157364 # number of instructions that are conditional controls +system.cpu.num_int_insts 232011695 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567056066 # number of times the integer registers were read -system.cpu.num_int_register_writes 293242220 # number of times the integer registers were written +system.cpu.num_int_register_reads 567056109 # number of times the integer registers were read +system.cpu.num_int_register_writes 293242196 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22232130 # number of memory refs -system.cpu.num_load_insts 13871776 # Number of load instructions -system.cpu.num_store_insts 8360354 # Number of store instructions -system.cpu.num_idle_cycles 9789674914.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600649127.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942191 # Percentage of idle cycles +system.cpu.num_mem_refs 22232145 # number of memory refs +system.cpu.num_load_insts 13871789 # Number of load instructions +system.cpu.num_store_insts 8360356 # Number of store instructions +system.cpu.num_idle_cycles 9789660715.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600663326.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057810 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942190 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791510 # number of replacements +system.cpu.icache.replacements 791527 # number of replacements system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use -system.cpu.icache.total_refs 144497671 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 792022 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.441486 # Average number of references to valid blocks. +system.cpu.icache.total_refs 144497724 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 792039 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.437638 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144497671 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144497671 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144497671 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144497671 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144497671 # number of overall hits -system.cpu.icache.overall_hits::total 144497671 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792029 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792029 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792029 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792029 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792029 # number of overall misses -system.cpu.icache.overall_misses::total 792029 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10955241500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10955241500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10955241500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10955241500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10955241500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10955241500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145289700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145289700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145289700 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145289700 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145289700 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145289700 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144497724 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144497724 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144497724 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144497724 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144497724 # number of overall hits +system.cpu.icache.overall_hits::total 144497724 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792046 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792046 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792046 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792046 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792046 # number of overall misses +system.cpu.icache.overall_misses::total 792046 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10958971500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10958971500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10958971500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10958971500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10958971500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10958971500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145289770 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145289770 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145289770 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145289770 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145289770 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145289770 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13831.869161 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13831.869161 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13831.869161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13831.869161 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13836.281605 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13836.281605 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13836.281605 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13836.281605 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,40 +370,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792029 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 792029 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 792029 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 792029 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 792029 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 792029 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9371183500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9371183500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9371183500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9371183500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9371183500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9371183500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792046 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 792046 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 792046 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 792046 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 792046 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 792046 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9374879500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9374879500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9374879500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9374879500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9374879500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9374879500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11831.869161 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11831.869161 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11836.281605 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11836.281605 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3425 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.077882 # Cycle average of tags in use +system.cpu.itb_walker_cache.tagsinuse 3.077880 # Cycle average of tags in use system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5164118674000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077882 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192368 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.192368 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.warmup_cycle 5164120857000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077880 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192367 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.192367 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8004 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 8004 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -479,13 +479,13 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7540 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.062515 # Cycle average of tags in use +system.cpu.dtb_walker_cache.replacements 7539 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.062514 # Cycle average of tags in use system.cpu.dtb_walker_cache.total_refs 13178 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7554 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.744506 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7553 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.744737 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062515 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062514 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits @@ -559,63 +559,63 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8554.033922 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1618785 # number of replacements +system.cpu.dcache.replacements 1618797 # number of replacements system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use -system.cpu.dcache.total_refs 20025893 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1619297 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.367029 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20025896 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1619309 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.366939 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11988262 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11988262 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8035470 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8035470 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20023732 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20023732 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20023732 # number of overall hits -system.cpu.dcache.overall_hits::total 20023732 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1306602 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1306602 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 314890 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 314890 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1621492 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1621492 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1621492 # number of overall misses -system.cpu.dcache.overall_misses::total 1621492 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18343104000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18343104000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556691000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8556691000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26899795000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26899795000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26899795000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26899795000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13294864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13294864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350360 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350360 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21645224 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21645224 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21645224 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21645224 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098279 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098279 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11988260 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11988260 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035474 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035474 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20023734 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20023734 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20023734 # number of overall hits +system.cpu.dcache.overall_hits::total 20023734 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1306617 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1306617 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1621505 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1621505 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1621505 # number of overall misses +system.cpu.dcache.overall_misses::total 1621505 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18345510500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18345510500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8557598000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8557598000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26903108500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26903108500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26903108500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26903108500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13294877 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13294877 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8350362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21645239 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21645239 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21645239 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21645239 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098280 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098280 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037710 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.037710 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074912 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074912 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074912 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074912 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.784573 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.784573 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27173.587602 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27173.587602 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16589.532973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16589.532973 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.074913 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074913 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074913 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074913 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14040.465186 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14040.465186 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27176.640583 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27176.640583 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16591.443443 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16591.443443 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,46 +624,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1536047 # number of writebacks -system.cpu.dcache.writebacks::total 1536047 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306602 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1306602 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314890 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 314890 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1621492 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1621492 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1621492 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1621492 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15729900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15729900000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926911000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926911000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23656811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23656811000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23656811000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23656811000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1536058 # number of writebacks +system.cpu.dcache.writebacks::total 1536058 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1306617 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1621505 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1621505 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1621505 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1621505 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15732276500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15732276500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7927822000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7927822000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23660098500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23660098500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23660098500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23660098500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467832500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467832500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613781500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613781500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098279 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098279 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467833000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467833000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613782000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613782000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098280 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098280 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037710 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037710 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074912 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074912 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12038.784573 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12038.784573 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25173.587602 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25173.587602 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074913 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074913 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12040.465186 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12040.465186 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25176.640583 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25176.640583 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -672,17 +672,17 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 86864 # number of replacements -system.cpu.l2cache.tagsinuse 64770.428925 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3484716 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 64770.428854 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3484759 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.981554 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 22.981837 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50336.266909 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 50336.272506 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.007172 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140366 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3358.136526 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11075.877952 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.768070 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140365 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3358.130752 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11075.878059 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.768071 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.051241 # Average percentage of cache occupancy @@ -690,25 +690,25 @@ system.cpu.l2cache.occ_percent::cpu.data 0.169004 # Av system.cpu.l2cache.occ_percent::total 0.988318 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6347 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2754 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779144 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1277462 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2065707 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1539401 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1539401 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779161 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1277476 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2065738 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1539412 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1539412 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 293 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 293 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199367 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199367 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 199364 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 199364 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6347 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2754 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779144 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1476829 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2265074 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 779161 # 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number of ReadReq misses @@ -730,44 +730,44 @@ system.cpu.l2cache.overall_misses::cpu.data 141743 # system.cpu.l2cache.overall_misses::total 154621 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 68500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 787701500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1647921500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2436036500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16174500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16174500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5583363000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5583363000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 791210500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1650142000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2441766000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16179000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 16179000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5584232500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5584232500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 68500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 787701500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7231284500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8019399500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 791210500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7234374500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8025998500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 68500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 787701500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7231284500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8019399500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 791210500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7234374500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8025998500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6348 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2759 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 792016 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1305847 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2106970 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1539401 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1539401 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 792033 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1305861 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2107001 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1539412 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1539412 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1657 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1657 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 312725 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 312725 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 312722 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 312722 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6348 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2759 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 792016 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1618572 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2419695 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792033 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1618583 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2419723 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6348 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2759 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792016 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1618572 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2419695 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792033 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1618583 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2419723 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000158 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001812 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016252 # miss rate for ReadReq accesses @@ -775,37 +775,37 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021737 system.cpu.l2cache.ReadReq_miss_rate::total 0.019584 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823174 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823174 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362485 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.362485 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362488 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.362488 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000158 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001812 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016252 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087573 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063901 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087572 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063900 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000158 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001812 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016252 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087573 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063901 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087572 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063900 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68500 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61194.958048 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58056.068346 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 59036.824758 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11858.137830 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11858.137830 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49254.247605 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49254.247605 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61467.565258 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58134.296283 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 59175.677968 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11861.436950 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11861.436950 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49261.917994 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49261.917994 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51864.879285 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61467.565258 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51038.672104 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51907.557835 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51864.879285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61467.565258 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51038.672104 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51907.557835 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -837,29 +837,29 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 141743 system.cpu.l2cache.overall_mshr_misses::total 154621 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56251 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281255 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 627778857 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1295316957 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6120477841 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56251 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 627778857 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5485728232 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6113844595 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 631288357 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5488851978 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6120477841 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305021500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896197000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896197000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305022500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305022500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896198000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896198000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses @@ -867,37 +867,37 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362485 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362485 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063901 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063900 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063900 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48770.886964 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45633.854395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46613.996074 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36966.171554 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36966.171554 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49043.533017 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45712.487335 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46753.140004 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10716.162023 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10716.162023 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36974.038224 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36974.038224 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 159c48ed1..08d964bc4 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,634 +1,633 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000759 # Number of seconds simulated -sim_ticks 758619000 # Number of ticks simulated -final_tick 758619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000758 # Number of seconds simulated +sim_ticks 758227000 # Number of ticks simulated +final_tick 758227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 45315591 # Simulator tick rate (ticks/s) -host_mem_usage 399988 # Number of bytes of host memory used -host_seconds 16.74 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 93443 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 93419 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 89535 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 90172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 93283 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 92172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 94553 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 91950 # Number of bytes read from this memory -system.physmem.bytes_read::total 738527 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 485568 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5315 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5220 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5162 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5331 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5296 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5419 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5320 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5436 # Number of bytes written to this memory -system.physmem.bytes_written::total 528067 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11015 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11194 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88997 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7587 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5315 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5220 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5162 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5331 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5296 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5419 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5320 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5436 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50086 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 123175138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 123143502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 118023672 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 118863356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 122964228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 121499725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 124638323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 121207088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 973515032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 640068335 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7006152 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6880924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 6804470 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7027243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 6981106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7143243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7012743 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7165652 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 696089869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 640068335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 130181290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 130024426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 124828142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 125890599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 129945335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 128642968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 131651066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 128372740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1669604900 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15559 # number of replacements -system.l2c.tagsinuse 800.707629 # Cycle average of tags in use -system.l2c.total_refs 151038 # Total number of references to valid blocks. -system.l2c.sampled_refs 16357 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.233845 # Average number of references to valid blocks. +host_tick_rate 200763174 # Simulator tick rate (ticks/s) +host_mem_usage 353776 # Number of bytes of host memory used +host_seconds 3.78 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 94296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 93084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 90684 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 91125 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 90329 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 98961 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 91564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 94442 # Number of bytes read from this memory +system.physmem.bytes_read::total 744485 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 495744 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5338 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5288 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5371 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5302 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5445 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5231 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5430 # Number of bytes written to this memory +system.physmem.bytes_written::total 538519 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10932 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11202 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10987 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11345 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89033 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7746 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5338 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5288 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5371 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5302 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5445 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5231 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5430 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50521 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 124363812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 122765346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 119600067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 120181687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 119131869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 130516323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 120760669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 124556366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 981876140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 653820030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7040108 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6974165 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7083631 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6992629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 7181227 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 6898989 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7082312 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7161444 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 710234534 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 653820030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 131403920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 129739511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 126683698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 127174316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 126313096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 137415312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 127842981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 131717810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1692110674 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15709 # number of replacements +system.l2c.tagsinuse 802.621152 # Cycle average of tags in use +system.l2c.total_refs 152986 # Total number of references to valid blocks. +system.l2c.sampled_refs 16508 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.267386 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 736.955948 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.896049 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.875266 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.499139 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.819632 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 8.127236 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 8.346952 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 8.379667 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 7.807741 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.719684 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007711 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007691 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007323 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007636 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007937 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.008151 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.008183 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.007625 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781941 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10425 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10868 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10852 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10879 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10945 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10774 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10623 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86293 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76698 # number of Writeback hits -system.l2c.Writeback_hits::total 76698 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 360 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 388 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 372 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 365 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 360 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 369 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2938 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2007 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1980 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2070 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2061 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1961 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2103 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16299 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12432 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12832 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 13006 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12726 # number of demand (read+write) hits -system.l2c.demand_hits::total 102592 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12432 # number of overall hits -system.l2c.overall_hits::cpu1 12963 # number of overall hits -system.l2c.overall_hits::cpu2 12832 # number of overall hits -system.l2c.overall_hits::cpu3 12949 # number of overall hits -system.l2c.overall_hits::cpu4 12949 # number of overall hits -system.l2c.overall_hits::cpu5 13006 # number of overall hits -system.l2c.overall_hits::cpu6 12735 # number of overall hits -system.l2c.overall_hits::cpu7 12726 # number of overall hits -system.l2c.overall_hits::total 102592 # number of overall hits -system.l2c.ReadReq_misses::cpu0 852 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 872 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 800 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 819 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 876 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 871 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 869 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 848 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6807 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1921 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1804 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1923 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1810 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1803 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1840 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1866 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1868 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14835 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4250 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4373 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4213 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4295 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4281 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4251 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4294 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4308 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34265 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5102 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5245 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5013 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5114 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5157 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5122 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5163 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5156 # number of demand (read+write) misses -system.l2c.demand_misses::total 41072 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5102 # number of overall misses -system.l2c.overall_misses::cpu1 5245 # number of overall misses -system.l2c.overall_misses::cpu2 5013 # number of overall misses -system.l2c.overall_misses::cpu3 5114 # number of overall misses -system.l2c.overall_misses::cpu4 5157 # number of overall misses -system.l2c.overall_misses::cpu5 5122 # number of overall misses -system.l2c.overall_misses::cpu6 5163 # number of overall misses -system.l2c.overall_misses::cpu7 5156 # number of overall misses -system.l2c.overall_misses::total 41072 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 50457953 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 52232944 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 47803944 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 49059449 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 51558931 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 52310430 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 51043945 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 50050941 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 404518537 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 54750899 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 49983404 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 56149902 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 53493906 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 50935912 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 51769923 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 53458903 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 54181398 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 424724247 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 228244633 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 234983117 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 226986626 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 231330611 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 230611636 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 229068598 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 231365116 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 232157113 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1844747450 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 278702586 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 287216061 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 274790570 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 280390060 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 282170567 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 281379028 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 282409061 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 282208054 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2249265987 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 278702586 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 287216061 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 274790570 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 280390060 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 93100 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 76698 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 76698 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2283 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2164 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2311 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2182 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2165 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2205 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2226 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2237 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17773 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6257 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6468 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6193 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6365 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6303 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6255 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6411 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50564 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17534 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18208 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18063 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18106 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18128 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17898 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17882 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143664 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17534 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18208 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17845 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18063 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18106 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18128 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17898 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17882 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143664 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.075552 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.074276 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.068658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.070012 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.074218 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.073714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.074637 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.073926 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.073115 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.841437 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.833641 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.832107 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.829514 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.832794 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.834467 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.838275 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.835047 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.834693 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.679239 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.676098 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.680284 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.674784 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.679200 # 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miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.290978 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.288060 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.280919 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.283120 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.284823 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.282546 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.288468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.288335 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.285889 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 59222.949531 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 59900.165138 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 59754.930000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 59901.647131 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 58857.227169 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 60057.898967 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 58738.716916 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59022.336085 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 59426.845453 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28501.248829 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 27706.986696 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29199.117005 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 29554.644199 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28250.644481 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28135.827717 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28648.929796 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29005.031049 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28629.878463 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53704.619529 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53734.991310 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53877.670544 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.444936 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53868.637234 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53885.814632 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53881.023754 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53889.766249 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53837.660878 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54626.143865 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54759.973499 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54815.593457 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54827.935080 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54716.030056 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54935.382273 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54698.636645 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54733.912723 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54763.975141 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54626.143865 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54759.973499 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54815.593457 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54827.935080 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54716.030056 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54935.382273 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54698.636645 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54733.912723 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54763.975141 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 10793 # number of cycles access was blocked +system.l2c.occ_blocks::writebacks 738.344301 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.856749 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.750709 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 7.581062 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 8.075895 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.623690 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 8.411297 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 8.326520 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 8.650930 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.721039 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007673 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007569 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007403 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007887 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007445 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.008214 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.008131 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.008448 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783810 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 11060 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10905 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10917 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10908 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 11025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10769 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 11003 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 11044 # number of ReadReq hits +system.l2c.ReadReq_hits::total 87631 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77283 # number of Writeback hits +system.l2c.Writeback_hits::total 77283 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 381 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 372 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 389 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 412 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 335 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 347 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 375 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 371 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2982 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2017 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 2086 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1996 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2001 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 2062 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1995 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 2076 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 2009 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16242 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 13077 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12991 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12913 # 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number of overall hits +system.l2c.ReadReq_misses::cpu0 831 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 825 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 807 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 851 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 828 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 911 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 848 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 890 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6791 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1940 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1902 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1837 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1834 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1940 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1893 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1907 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1914 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15167 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4262 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4280 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4275 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4377 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4319 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4433 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4324 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34643 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5093 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5105 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5180 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5126 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5205 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5230 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5281 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5214 # number of demand (read+write) misses +system.l2c.demand_misses::total 41434 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5093 # number of overall misses +system.l2c.overall_misses::cpu1 5105 # number of overall misses +system.l2c.overall_misses::cpu2 5180 # number of overall misses +system.l2c.overall_misses::cpu3 5126 # number of overall misses +system.l2c.overall_misses::cpu4 5205 # number of overall misses +system.l2c.overall_misses::cpu5 5230 # number of overall misses +system.l2c.overall_misses::cpu6 5281 # number of overall misses +system.l2c.overall_misses::cpu7 5214 # number of overall misses +system.l2c.overall_misses::total 41434 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 50386435 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 49587933 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 48886937 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 50664930 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 50580935 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 54458446 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 51430439 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 53097926 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 409093981 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 55854416 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 53852396 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 53210404 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 50920923 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 55308908 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 55911401 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 54499902 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 55745405 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 435303755 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 229815657 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 230400614 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 235881114 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 230703609 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 235441620 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 233239630 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 238696088 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 232987140 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1867165472 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 280202092 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 279988547 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 284768051 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 281368539 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 286022555 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 287698076 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 290126527 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 286085066 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2276259453 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 280202092 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 279988547 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 284768051 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 281368539 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 286022555 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 287698076 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 290126527 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 286085066 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2276259453 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11891 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11730 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11724 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11759 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11853 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11680 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11851 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11934 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 94422 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77283 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77283 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2321 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2274 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2226 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2246 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2275 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2240 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2285 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18149 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6279 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6366 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6369 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6276 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6439 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6314 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6509 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6333 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50885 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18096 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18093 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18035 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18292 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17994 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18360 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18267 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 145307 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18096 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18093 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18035 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18292 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17994 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18360 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18267 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 145307 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.069885 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.070332 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.068833 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.072370 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.069856 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.077997 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.071555 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.074577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.071922 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.835847 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.836412 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.825247 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.816563 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.852747 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.845089 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.835670 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.837637 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.835693 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.678771 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.672322 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.686607 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.681166 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.679764 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.684035 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.681057 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.682773 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.680810 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.280297 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.282107 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.286299 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.284225 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.284551 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.290652 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.287636 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.285433 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.285148 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.280297 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.282107 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.286299 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.284225 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.284551 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.290652 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.287636 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.285433 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.285148 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60633.495788 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 60106.585455 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 60578.608426 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 59535.757932 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61088.085749 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 59778.755214 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 60649.102594 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 59660.591011 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 60240.609778 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28790.936082 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28313.562566 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 28965.924878 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27764.952563 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28509.746392 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29535.869519 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28578.868380 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29125.080982 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28700.715699 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53922.021821 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53831.919159 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53940.341642 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53965.756491 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53790.637423 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54003.155823 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53845.271374 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53882.317299 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53897.337759 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55017.100334 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 54845.944564 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54974.527220 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54890.468006 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54951.499520 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55009.192352 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54937.800985 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54868.635596 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54936.995052 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55017.100334 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 54845.944564 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54974.527220 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54890.468006 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54951.499520 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55009.192352 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54937.800985 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54868.635596 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54936.995052 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 12946 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1480 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1808 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.292568 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.160398 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7587 # number of writebacks -system.l2c.writebacks::total 7587 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 7746 # number of writebacks +system.l2c.writebacks::total 7746 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 3 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu6 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 32 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 29 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 92 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 845 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 865 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 794 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 809 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 871 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 865 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 859 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 839 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6747 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1921 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1804 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1923 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1809 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1803 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1840 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1865 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1868 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14833 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4243 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4367 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4211 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4291 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4278 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4245 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4291 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4307 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34233 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5088 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5232 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5005 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5100 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5149 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5110 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5150 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5146 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40980 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5088 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5232 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5005 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5100 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5149 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5110 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5150 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5146 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40980 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 39952953 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 41536444 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 37955945 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 38925950 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 40835431 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 41565931 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 40269445 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 39637942 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 320680041 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78868808 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 73978329 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78794825 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 74230834 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 74073835 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 75455362 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76452812 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 76637320 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 608492125 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 176592133 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 181884117 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 175861127 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 179102612 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 178683137 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 177427598 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 179259117 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 179911613 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1428721454 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 216545086 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 223420561 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 213817072 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 218028562 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 219518568 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 218993529 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 219528562 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 219549555 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1749401495 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 216545086 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 223420561 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 213817072 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 218028562 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 219518568 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 218993529 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 219528562 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 219549555 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1749401495 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 402081632 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 400575089 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 409123618 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 408517090 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 408283130 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 406615614 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 405150633 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 405778615 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3246125421 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 225621486 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222590493 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 219789492 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 227766486 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225717983 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 229461987 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226436485 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 231064489 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1808448901 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 627703118 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 623165582 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 628913110 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 636283576 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 634001113 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 636077601 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 631587118 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 636843104 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5054574322 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.074931 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.073680 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068143 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.069157 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.073795 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.073206 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.073778 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073141 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.072470 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.841437 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.833641 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.832107 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.829056 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.832794 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.834467 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.837826 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.835047 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.834581 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.678121 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.675170 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679961 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.674156 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678724 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672529 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.686011 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.671814 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.677023 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285249 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285249 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 47281.601183 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48019.010405 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 47803.457179 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 48116.131026 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46883.388060 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48053.099422 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46879.447031 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47244.269368 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 47529.278346 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.120770 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41007.942905 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40974.947998 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41034.181316 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41083.657793 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41008.348913 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40993.464879 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41026.402570 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41022.862873 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41619.640113 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41649.671857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41762.319402 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41739.131205 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41767.914212 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41796.842874 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41775.604055 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41771.909218 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41735.210294 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 828 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 815 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 804 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 844 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 824 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 909 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 843 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 883 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6750 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1940 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1901 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1837 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1834 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1940 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1892 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1907 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1914 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15165 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4255 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4276 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4373 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4271 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4372 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4316 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4430 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4321 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34614 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5083 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5091 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5177 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5115 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5196 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5225 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5273 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5204 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 41364 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5083 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5091 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5177 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5115 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5196 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5225 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5273 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5204 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 41364 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 40211435 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 39357435 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 39064937 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 40158430 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 40512435 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 43385946 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 40969439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 42146427 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 325806484 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 79643349 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78062835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 75255324 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 75287345 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79635834 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77713835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78284820 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 78593341 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 622476683 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 178045657 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 178454114 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 182867114 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 178794609 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 182240620 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 180819630 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 184924089 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 180516140 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1446661973 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 218257092 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 217811549 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 221932051 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 218953039 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 222753055 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 224205576 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 225893528 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 222662567 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1772468457 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 218257092 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 217811549 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 221932051 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 218953039 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 222753055 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 224205576 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 225893528 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 222662567 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1772468457 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 410453631 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 397457157 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 406979111 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 406829637 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 405432120 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405171118 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 400882109 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 414057617 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3247262500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 226073488 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 225167477 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 228704981 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 225137481 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230851979 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 222187990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 228117990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230091986 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1816333372 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 636527119 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 622624634 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 635684092 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 631967118 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 636284099 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 627359108 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 629000099 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 644149603 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5063595872 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.069632 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.069480 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.071775 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069518 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.077825 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.071133 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073990 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.071488 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.835847 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.835972 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.825247 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.816563 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.852747 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844643 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.835670 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.837637 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.835583 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.677656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.671693 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.686607 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680529 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678987 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.683560 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680596 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.682299 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.680240 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.284666 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.284666 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48564.535024 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48291.331288 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48588.230100 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47581.078199 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49165.576456 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47729.313531 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 48599.571767 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47730.947905 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 48267.627259 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41053.272680 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41064.089953 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40966.425694 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41050.896947 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41049.398969 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41074.965645 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41051.295228 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41062.351620 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41046.929311 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41843.867685 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41733.890084 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41817.313972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41862.469913 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41683.581885 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41895.187674 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41743.586682 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41776.473039 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41794.128763 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -657,114 +656,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 97622 # number of read accesses completed -system.cpu0.num_writes 53016 # number of write accesses completed +system.cpu0.num_reads 98877 # number of read accesses completed +system.cpu0.num_writes 53303 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 21387 # number of replacements -system.cpu0.l1c.tagsinuse 393.959213 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13124 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 21798 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.602074 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22594 # number of replacements +system.cpu0.l1c.tagsinuse 395.326045 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13097 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 23010 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.569187 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 393.959213 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.769452 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.769452 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8513 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8513 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1098 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9611 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9611 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9611 # number of overall hits -system.cpu0.l1c.overall_hits::total 9611 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35379 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35379 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 22892 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 22892 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58271 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58271 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58271 # number of overall misses -system.cpu0.l1c.overall_misses::total 58271 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1332854037 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1332854037 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1090035309 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1090035309 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2422889346 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2422889346 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2422889346 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2422889346 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 43892 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 43892 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 23990 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 23990 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 67882 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 67882 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 67882 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 67882 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806047 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.806047 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954231 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954231 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858416 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858416 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858416 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858416 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37673.592724 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 37673.592724 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 47616.429713 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 47616.429713 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 41579.676786 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 41579.676786 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 41579.676786 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 41579.676786 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1432667 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 395.326045 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.772121 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.772121 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8525 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8525 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9567 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9567 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9567 # number of overall hits +system.cpu0.l1c.overall_hits::total 9567 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36170 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36170 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23033 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59203 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59203 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59203 # number of overall misses +system.cpu0.l1c.overall_misses::total 59203 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1338428684 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1338428684 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1081120140 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1081120140 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2419548824 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2419548824 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2419548824 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2419548824 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44695 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44695 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24075 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24075 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68770 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68770 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68770 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68770 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809263 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809263 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956719 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956719 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860884 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860884 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860884 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860884 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37003.834227 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 37003.834227 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 46937.877827 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 46937.877827 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 40868.686114 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 40868.686114 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 40868.686114 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 40868.686114 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1431079 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66221 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 67309 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.634633 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.261332 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9284 # number of writebacks -system.cpu0.l1c.writebacks::total 9284 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35379 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35379 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22892 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 22892 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58271 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58271 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58271 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58271 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1262100037 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1262100037 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1044251309 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1044251309 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2306351346 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2306351346 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2306351346 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2306351346 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 709848172 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 709848172 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 441878494 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 441878494 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1151726666 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1151726666 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806047 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806047 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954231 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954231 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858416 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858416 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35673.705786 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35673.705786 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 45616.429713 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 45616.429713 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9829 # number of writebacks +system.cpu0.l1c.writebacks::total 9829 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36170 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23033 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59203 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59203 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59203 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59203 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1266094684 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1266094684 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1035054140 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1035054140 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2301148824 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2301148824 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2301148824 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2301148824 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 713940998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 713940998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 425679500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 425679500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1139620498 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1139620498 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809263 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809263 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956719 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956719 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860884 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860884 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35004.000111 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35004.000111 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 44937.877827 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 44937.877827 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -772,114 +771,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98743 # number of read accesses completed -system.cpu1.num_writes 53079 # number of write accesses completed +system.cpu1.num_reads 98330 # number of read accesses completed +system.cpu1.num_writes 53283 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 22269 # number of replacements -system.cpu1.l1c.tagsinuse 395.693103 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13156 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22645 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.580967 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 22413 # number of replacements +system.cpu1.l1c.tagsinuse 397.274781 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13337 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22810 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.584700 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 395.693103 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.772838 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.772838 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8677 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8677 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1112 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1112 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9789 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9789 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9789 # number of overall hits -system.cpu1.l1c.overall_hits::total 9789 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 35979 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 35979 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22841 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22841 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 58820 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 58820 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 58820 # number of overall misses -system.cpu1.l1c.overall_misses::total 58820 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1346712982 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1346712982 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1084415887 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1084415887 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2431128869 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2431128869 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2431128869 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2431128869 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44656 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44656 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23953 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23953 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68609 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68609 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68609 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68609 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805692 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805692 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953576 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.953576 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857322 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857322 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857322 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857322 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37430.528419 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 37430.528419 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47476.725494 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 47476.725494 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 41331.670673 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 41331.670673 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 41331.670673 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 41331.670673 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1432282 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 397.274781 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.775927 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.775927 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8758 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8758 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1087 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1087 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9845 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9845 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9845 # number of overall hits +system.cpu1.l1c.overall_hits::total 9845 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35763 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35763 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23060 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23060 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58823 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58823 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58823 # number of overall misses +system.cpu1.l1c.overall_misses::total 58823 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1339256827 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1339256827 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1098702208 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1098702208 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2437959035 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2437959035 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2437959035 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2437959035 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44521 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24147 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24147 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68668 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68668 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68668 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68668 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803284 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.803284 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954984 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954984 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.856629 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.856629 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.856629 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.856629 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37448.111931 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 37448.111931 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47645.368951 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 47645.368951 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 41445.676606 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 41445.676606 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 41445.676606 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 41445.676606 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1431601 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66708 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66652 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.470918 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.478740 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9759 # number of writebacks -system.cpu1.l1c.writebacks::total 9759 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35979 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22841 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22841 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 58820 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 58820 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 58820 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 58820 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1274756982 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1274756982 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1038739887 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1038739887 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2313496869 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2313496869 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2313496869 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2313496869 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 702867762 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 702867762 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 426288670 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 426288670 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1129156432 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1129156432 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805692 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805692 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953576 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953576 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857322 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857322 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35430.584007 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35430.584007 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45476.988179 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45476.988179 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9847 # number of writebacks +system.cpu1.l1c.writebacks::total 9847 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23060 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58823 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58823 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58823 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58823 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1267732827 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1267732827 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1052584208 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1052584208 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2320317035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2320317035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2320317035 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2320317035 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 694424746 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 694424746 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 428704098 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 428704098 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1123128844 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1123128844 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803284 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803284 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954984 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954984 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.856629 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.856629 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35448.167855 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35448.167855 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45645.455681 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45645.455681 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -887,114 +886,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 98534 # number of read accesses completed -system.cpu2.num_writes 52787 # number of write accesses completed +system.cpu2.num_reads 98918 # number of read accesses completed +system.cpu2.num_writes 53026 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 21873 # number of replacements -system.cpu2.l1c.tagsinuse 394.149978 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13285 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22270 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.596542 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22091 # number of replacements +system.cpu2.l1c.tagsinuse 394.122068 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13053 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22474 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.580804 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 394.149978 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.769824 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.769824 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8620 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8620 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1112 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1112 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9732 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9732 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9732 # number of overall hits -system.cpu2.l1c.overall_hits::total 9732 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 35901 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 35901 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22666 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22666 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 58567 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 58567 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 58567 # number of overall misses -system.cpu2.l1c.overall_misses::total 58567 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1333102057 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1333102057 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1080309021 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1080309021 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2413411078 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2413411078 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2413411078 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2413411078 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44521 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23778 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23778 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68299 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68299 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68299 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68299 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806384 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806384 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953234 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953234 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.857509 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.857509 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.857509 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.857509 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37132.727696 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 37132.727696 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47662.093929 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 47662.093929 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 41207.695084 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 41207.695084 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 41207.695084 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 41207.695084 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1432337 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 394.122068 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.769770 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.769770 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1062 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9719 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9719 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9719 # number of overall hits +system.cpu2.l1c.overall_hits::total 9719 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35792 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35792 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22782 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22782 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58574 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58574 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58574 # number of overall misses +system.cpu2.l1c.overall_misses::total 58574 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1334540137 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1334540137 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1086319531 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1086319531 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2420859668 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2420859668 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2420859668 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2420859668 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23844 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23844 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68293 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68293 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68293 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68293 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805237 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805237 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955460 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955460 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.857687 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.857687 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.857687 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.857687 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37285.989523 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 37285.989523 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47683.238127 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 47683.238127 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 41329.935944 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 41329.935944 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 41329.935944 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 41329.935944 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1431481 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66669 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66558 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.484303 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.507272 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9470 # number of writebacks -system.cpu2.l1c.writebacks::total 9470 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35901 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35901 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22666 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22666 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58567 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58567 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58567 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58567 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1261304057 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1261304057 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1034981021 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1034981021 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2296285078 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2296285078 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2296285078 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2296285078 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 719957534 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 719957534 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 417914602 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 417914602 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1137872136 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1137872136 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806384 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806384 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953234 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953234 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.857509 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.857509 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35132.839113 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35132.839113 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45662.270405 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45662.270405 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9590 # number of writebacks +system.cpu2.l1c.writebacks::total 9590 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22782 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22782 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58574 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58574 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58574 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58574 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1262960137 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1262960137 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040755531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040755531 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2303715668 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2303715668 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2303715668 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2303715668 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 710805276 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 710805276 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 431026471 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 431026471 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1141831747 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1141831747 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805237 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805237 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955460 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955460 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.857687 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.857687 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35286.101280 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35286.101280 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45683.238127 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45683.238127 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1002,114 +1001,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99583 # number of read accesses completed -system.cpu3.num_writes 53448 # number of write accesses completed +system.cpu3.num_reads 98879 # number of read accesses completed +system.cpu3.num_writes 53514 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22221 # number of replacements -system.cpu3.l1c.tagsinuse 395.683952 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13227 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22614 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.584903 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 22321 # number of replacements +system.cpu3.l1c.tagsinuse 395.059941 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13052 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22702 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.574927 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.683952 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.772820 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.772820 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8699 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8699 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1092 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1092 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9791 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9791 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9791 # number of overall hits -system.cpu3.l1c.overall_hits::total 9791 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35935 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35935 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23086 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23086 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 59021 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 59021 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 59021 # number of overall misses -system.cpu3.l1c.overall_misses::total 59021 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1329205475 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1329205475 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1090244238 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1090244238 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2419449713 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2419449713 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2419449713 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2419449713 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44634 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44634 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24178 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24178 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68812 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68812 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68812 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68812 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805104 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.805104 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954835 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954835 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.857714 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.857714 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.857714 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.857714 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 36989.160289 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 36989.160289 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47225.341679 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 47225.341679 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 40993.031514 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 40993.031514 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 40993.031514 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 40993.031514 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1431757 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 395.059941 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.771601 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.771601 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1034 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1034 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9596 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9596 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9596 # number of overall hits +system.cpu3.l1c.overall_hits::total 9596 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35946 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35946 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22965 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22965 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58911 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58911 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58911 # number of overall misses +system.cpu3.l1c.overall_misses::total 58911 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1334193508 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1334193508 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1085703243 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1085703243 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2419896751 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2419896751 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2419896751 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2419896751 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44508 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44508 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 23999 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 23999 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68507 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68507 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68507 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68507 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807630 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807630 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956915 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.956915 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859927 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859927 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859927 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859927 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 37116.605686 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 37116.605686 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47276.431221 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 47276.431221 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 41077.163026 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 41077.163026 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 41077.163026 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 41077.163026 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1431288 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 67125 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66945 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.329713 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.380058 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9875 # number of writebacks -system.cpu3.l1c.writebacks::total 9875 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35935 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35935 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23086 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23086 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 59021 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 59021 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 59021 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 59021 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1257339475 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1257339475 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1044074238 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1044074238 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2301413713 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2301413713 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2301413713 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2301413713 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 714868620 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 714868620 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 436247033 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 436247033 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1151115653 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1151115653 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805104 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805104 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954835 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954835 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.857714 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.857714 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34989.271602 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34989.271602 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45225.428312 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45225.428312 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9751 # number of writebacks +system.cpu3.l1c.writebacks::total 9751 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35946 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35946 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22965 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58911 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58911 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58911 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58911 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1262305508 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1262305508 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1039775243 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1039775243 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2302080751 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2302080751 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2302080751 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2302080751 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 712475632 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 712475632 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 424398019 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 424398019 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1136873651 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1136873651 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807630 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807630 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956915 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956915 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859927 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859927 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 35116.716964 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35116.716964 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45276.518310 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45276.518310 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1117,114 +1116,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53418 # number of write accesses completed +system.cpu4.num_reads 99302 # number of read accesses completed +system.cpu4.num_writes 53818 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22068 # number of replacements -system.cpu4.l1c.tagsinuse 394.143159 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13375 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22471 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.595212 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22353 # number of replacements +system.cpu4.l1c.tagsinuse 396.021323 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13287 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22757 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.583864 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 394.143159 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.769811 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.769811 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8810 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8810 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1141 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1141 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9951 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9951 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9951 # number of overall hits -system.cpu4.l1c.overall_hits::total 9951 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36179 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36179 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22735 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22735 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 58914 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 58914 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 58914 # number of overall misses -system.cpu4.l1c.overall_misses::total 58914 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1352891584 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1352891584 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1067419012 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1067419012 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2420310596 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2420310596 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2420310596 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2420310596 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44989 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44989 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 23876 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 23876 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68865 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68865 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68865 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68865 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804174 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804174 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952211 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952211 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.855500 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.855500 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.855500 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.855500 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 37394.388568 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 37394.388568 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 46950.473367 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 46950.473367 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 41082.095869 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 41082.095869 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 41082.095869 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 41082.095869 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1431267 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 396.021323 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.773479 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.773479 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8768 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8768 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1075 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1075 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9843 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9843 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9843 # number of overall hits +system.cpu4.l1c.overall_hits::total 9843 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36125 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36125 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22981 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22981 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59106 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59106 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59106 # number of overall misses +system.cpu4.l1c.overall_misses::total 59106 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1336431585 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1336431585 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1085022253 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1085022253 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2421453838 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2421453838 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2421453838 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2421453838 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44893 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44893 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24056 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24056 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68949 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68949 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68949 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68949 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804691 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.804691 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955313 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.955313 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857242 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857242 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857242 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857242 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 36994.645952 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 36994.645952 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 47213.883338 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 47213.883338 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 40967.986973 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 40967.986973 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 40967.986973 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 40967.986973 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1430986 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66934 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 67143 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.383258 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.312512 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9521 # number of writebacks -system.cpu4.l1c.writebacks::total 9521 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36179 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36179 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22735 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22735 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 58914 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 58914 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1280533584 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1280533584 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1021953012 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1021953012 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2302486596 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2302486596 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2302486596 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2302486596 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 712917081 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 712917081 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 441958565 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 441958565 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1154875646 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1154875646 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804174 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804174 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952211 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952211 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.855500 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.855500 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35394.388568 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35394.388568 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 44950.649307 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 44950.649307 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9680 # number of writebacks +system.cpu4.l1c.writebacks::total 9680 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36125 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36125 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22981 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22981 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59106 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59106 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59106 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59106 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1264183585 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1264183585 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1039060253 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1039060253 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2303243838 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2303243838 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2303243838 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2303243838 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 711442657 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 711442657 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 433569420 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 433569420 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1145012077 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1145012077 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804691 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804691 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955313 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955313 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857242 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857242 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 34994.701315 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 34994.701315 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45213.883338 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45213.883338 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1232,114 +1231,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99061 # number of read accesses completed -system.cpu5.num_writes 53322 # number of write accesses completed +system.cpu5.num_reads 98038 # number of read accesses completed +system.cpu5.num_writes 52677 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22382 # number of replacements -system.cpu5.l1c.tagsinuse 394.919460 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13094 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22775 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.574929 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 21614 # number of replacements +system.cpu5.l1c.tagsinuse 395.041478 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13218 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22030 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.600000 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 394.919460 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.771327 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.771327 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8623 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8623 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1083 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1083 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9706 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9706 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9706 # number of overall hits -system.cpu5.l1c.overall_hits::total 9706 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 35968 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 35968 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 22960 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 22960 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 58928 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 58928 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 58928 # number of overall misses -system.cpu5.l1c.overall_misses::total 58928 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1339036093 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1339036093 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1083656826 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1083656826 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2422692919 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2422692919 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2422692919 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2422692919 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44591 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44591 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24043 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24043 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68634 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68634 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68634 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68634 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806620 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806620 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954956 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954956 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.858583 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.858583 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.858583 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.858583 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37228.539062 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 37228.539062 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47197.596951 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 47197.596951 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 41112.763355 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 41112.763355 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 41112.763355 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 41112.763355 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1432391 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 395.041478 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.771565 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.771565 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8654 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8654 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1143 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9797 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9797 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9797 # number of overall hits +system.cpu5.l1c.overall_hits::total 9797 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 35607 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 35607 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22649 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22649 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 58256 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 58256 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 58256 # number of overall misses +system.cpu5.l1c.overall_misses::total 58256 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1343353904 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1343353904 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1075550971 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1075550971 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2418904875 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2418904875 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2418904875 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2418904875 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44261 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44261 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 23792 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 23792 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68053 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68053 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68053 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68053 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804478 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.804478 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951959 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.951959 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.856039 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.856039 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.856039 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.856039 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37727.241947 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 37727.241947 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47487.790675 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 47487.790675 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 41521.987006 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 41521.987006 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 41521.987006 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 41521.987006 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1431933 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66951 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66282 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.394617 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.603648 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9691 # number of writebacks -system.cpu5.l1c.writebacks::total 9691 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35968 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35968 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22960 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22960 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58928 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58928 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58928 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58928 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1267104093 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1267104093 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1037740826 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1037740826 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2304844919 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2304844919 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2304844919 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2304844919 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 711626590 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 711626590 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 438340423 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 438340423 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1149967013 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1149967013 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806620 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806620 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954956 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954956 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.858583 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.858583 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35228.650272 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35228.650272 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45197.771167 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45197.771167 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9279 # number of writebacks +system.cpu5.l1c.writebacks::total 9279 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35607 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 35607 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22649 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22649 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 58256 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 58256 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 58256 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 58256 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1272141904 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1272141904 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1030256971 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1030256971 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2302398875 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2302398875 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2302398875 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2302398875 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 712509152 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 712509152 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 420356599 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 420356599 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1132865751 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1132865751 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804478 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804478 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951959 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951959 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.856039 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.856039 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35727.298116 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35727.298116 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45487.967283 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45487.967283 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1347,114 +1346,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 98175 # number of read accesses completed -system.cpu6.num_writes 52998 # number of write accesses completed +system.cpu6.num_reads 98486 # number of read accesses completed +system.cpu6.num_writes 53296 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21915 # number of replacements -system.cpu6.l1c.tagsinuse 395.370816 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13077 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22297 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.586491 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22107 # number of replacements +system.cpu6.l1c.tagsinuse 394.242179 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13254 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22518 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.588596 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 395.370816 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.772209 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.772209 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8591 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8591 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1078 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1078 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9669 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9669 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9669 # number of overall hits -system.cpu6.l1c.overall_hits::total 9669 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35673 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35673 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22773 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22773 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 58446 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 58446 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 58446 # number of overall misses -system.cpu6.l1c.overall_misses::total 58446 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1336174857 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1336174857 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1084897863 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1084897863 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2421072720 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2421072720 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2421072720 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2421072720 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44264 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44264 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23851 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23851 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68115 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68115 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68115 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68115 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805915 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805915 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954803 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954803 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858049 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858049 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858049 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858049 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37456.195358 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 37456.195358 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47639.654986 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 47639.654986 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 41424.096089 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 41424.096089 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 41424.096089 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 41424.096089 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1432460 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 394.242179 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.770004 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.770004 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8629 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8629 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1104 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1104 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9733 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9733 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9733 # number of overall hits +system.cpu6.l1c.overall_hits::total 9733 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35833 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35833 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23033 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58866 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58866 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58866 # number of overall misses +system.cpu6.l1c.overall_misses::total 58866 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1334639245 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1334639245 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1095786214 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1095786214 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2430425459 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2430425459 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2430425459 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2430425459 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44462 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44462 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24137 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68599 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68599 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68599 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68599 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805924 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805924 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954261 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954261 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858117 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858117 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858117 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858117 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37246.092847 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 37246.092847 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47574.619633 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 47574.619633 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 41287.423283 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 41287.423283 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 41287.423283 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 41287.423283 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1431647 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66523 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66759 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.533304 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.445004 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9553 # number of writebacks -system.cpu6.l1c.writebacks::total 9553 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35673 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35673 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22773 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22773 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 58446 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 58446 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 58446 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 58446 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1264832857 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1264832857 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1039353863 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1039353863 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2304186720 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2304186720 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2304186720 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2304186720 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 711871628 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 711871628 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 446494550 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 446494550 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1158366178 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1158366178 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954803 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954803 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858049 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858049 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35456.307487 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35456.307487 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45639.742809 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45639.742809 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9651 # number of writebacks +system.cpu6.l1c.writebacks::total 9651 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35833 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35833 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58866 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58866 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58866 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58866 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1262977245 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1262977245 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1049724214 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1049724214 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2312701459 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2312701459 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2312701459 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2312701459 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702275141 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702275141 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 427671023 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 427671023 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1129946164 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1129946164 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805924 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805924 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954261 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954261 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858117 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858117 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35246.204476 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35246.204476 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45574.793297 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45574.793297 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1462,114 +1461,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98453 # number of read accesses completed -system.cpu7.num_writes 53303 # number of write accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 53815 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22126 # number of replacements -system.cpu7.l1c.tagsinuse 394.997672 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13256 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22544 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.588006 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22563 # number of replacements +system.cpu7.l1c.tagsinuse 397.316418 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13400 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22950 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.583878 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 394.997672 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.771480 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.771480 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8720 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8720 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1098 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9818 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9818 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9818 # number of overall hits -system.cpu7.l1c.overall_hits::total 9818 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35443 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35443 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23039 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23039 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58482 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58482 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58482 # number of overall misses -system.cpu7.l1c.overall_misses::total 58482 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1325635544 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1325635544 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1095033308 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1095033308 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2420668852 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2420668852 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2420668852 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2420668852 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44163 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44163 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24137 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68300 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68300 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68300 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68300 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.802550 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.802550 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954510 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954510 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.856252 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.856252 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.856252 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.856252 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37401.900065 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 37401.900065 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47529.550241 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 47529.550241 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 41391.690640 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 41391.690640 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 41391.690640 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 41391.690640 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1432038 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 397.316418 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.776009 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.776009 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8738 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8738 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1123 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1123 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9861 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9861 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9861 # number of overall hits +system.cpu7.l1c.overall_hits::total 9861 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36561 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36561 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22883 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22883 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59444 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59444 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59444 # number of overall misses +system.cpu7.l1c.overall_misses::total 59444 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1338317183 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1338317183 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1076026419 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1076026419 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2414343602 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2414343602 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2414343602 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2414343602 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69305 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69305 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69305 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69305 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807104 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807104 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953220 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953220 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857716 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857716 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857716 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857716 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 36605.048631 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 36605.048631 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47022.961106 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 47022.961106 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 40615.429682 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 40615.429682 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 40615.429682 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 40615.429682 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1430407 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 66517 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 67553 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.528902 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.174589 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9733 # number of writebacks -system.cpu7.l1c.writebacks::total 9733 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35443 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35443 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23039 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23039 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58482 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58482 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58482 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58482 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1254751544 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1254751544 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1048957308 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1048957308 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2303708852 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2303708852 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2303708852 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2303708852 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 712119692 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 712119692 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 450587409 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 450587409 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1162707101 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1162707101 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.802550 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.802550 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954510 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954510 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.856252 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.856252 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35401.956494 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35401.956494 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45529.637050 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45529.637050 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9844 # number of writebacks +system.cpu7.l1c.writebacks::total 9844 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36561 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36561 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22883 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22883 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59444 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59444 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59444 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59444 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1265201183 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1265201183 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1030262419 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1030262419 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2295463602 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2295463602 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2295463602 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2295463602 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 718920000 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 718920000 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432823408 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432823408 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1151743408 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1151743408 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807104 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807104 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953220 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953220 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857716 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857716 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 34605.212740 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 34605.212740 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45023.048508 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45023.048508 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt index fd1ec361f..3f17aa9b6 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 31243111314 # Simulator tick rate (ticks/s) -host_mem_usage 230668 # Number of bytes of host memory used -host_seconds 3.20 # Real time elapsed on the host +host_tick_rate 15527580566 # Simulator tick rate (ticks/s) +host_mem_usage 226756 # Number of bytes of host memory used +host_seconds 6.44 # Real time elapsed on the host system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory system.physmem.bytes_read::total 64 # Number of bytes read from this memory system.physmem.bytes_written::cpu 213335552 # Number of bytes written to this memory @@ -151,9 +151,9 @@ system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% # system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1 # Read request-response latency system.monitor.writeLatencyHist::samples 3333367 # Write request-response latency -system.monitor.writeLatencyHist::mean 30000 # Write request-response latency -system.monitor.writeLatencyHist::gmean 29999.999984 # Write request-response latency -system.monitor.writeLatencyHist::stdev 0 # Write request-response latency +system.monitor.writeLatencyHist::mean 30000.000098 # Write request-response latency +system.monitor.writeLatencyHist::gmean 30000.000081 # Write request-response latency +system.monitor.writeLatencyHist::stdev 0.179652 # Write request-response latency system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency @@ -204,8 +204,8 @@ system.monitor.ittReadRead::min_value 0 # Re system.monitor.ittReadRead::max_value 0 # Read-to-read inter transaction time system.monitor.ittReadRead::total 0 # Read-to-read inter transaction time system.monitor.ittWriteWrite::samples 3333367 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::mean 29999.695203 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::stdev 539.134360 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::mean 29999.695301 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::stdev 539.310304 # Write-to-write inter transaction time system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::5001-10000 99 0.00% 0.00% # Write-to-write inter transaction time @@ -229,11 +229,11 @@ system.monitor.ittWriteWrite::90001-95000 0 0.00% 100.00% # W system.monitor.ittWriteWrite::95001-100000 0 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::overflows 1 0.00% 100.00% # Write-to-write inter transaction time system.monitor.ittWriteWrite::min_value 10000 # Write-to-write inter transaction time -system.monitor.ittWriteWrite::max_value 994000 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::max_value 994328 # Write-to-write inter transaction time system.monitor.ittWriteWrite::total 3333367 # Write-to-write inter transaction time system.monitor.ittReqReq::samples 3333368 # Request-to-request inter transaction time system.monitor.ittReqReq::mean 29999.687703 # Request-to-request inter transaction time -system.monitor.ittReqReq::stdev 539.308135 # Request-to-request inter transaction time +system.monitor.ittReqReq::stdev 539.488612 # Request-to-request inter transaction time system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::1-5000 1 0.00% 0.00% # Request-to-request inter transaction time system.monitor.ittReqReq::5001-10000 99 0.00% 0.00% # Request-to-request inter transaction time @@ -256,8 +256,8 @@ system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Re system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time -system.monitor.ittReqReq::min_value 5000 # Request-to-request inter transaction time -system.monitor.ittReqReq::max_value 994000 # Request-to-request inter transaction time +system.monitor.ittReqReq::min_value 4672 # Request-to-request inter transaction time +system.monitor.ittReqReq::max_value 994328 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333368 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions system.monitor.outstandingReadsHist::mean 0 # Outstanding read transactions |