diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
| commit | 3ebfe2eb0124b0524952c59f04580a55eb36edff (patch) | |
| tree | 3d48c5d7bddaa51413b4504b7bc17635e67e14a7 /tests | |
| parent | 3396fd9e84358346b60437a7635c9cc5f331017f (diff) | |
| download | gem5-3ebfe2eb0124b0524952c59f04580a55eb36edff.tar.xz | |
O3: Update stats for fetch and bp changes.
Diffstat (limited to 'tests')
137 files changed, 16724 insertions, 16680 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini index 23a53cd4f..b6c1d1a1d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout index 52e5d9fa3..9da502021 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:12:22 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/inorder-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:24 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 279017416500 because target called exit() +Exiting @ tick 274500333500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index a0423dfde..ec1428295 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279017 # Number of seconds simulated -sim_ticks 279017416500 # Number of ticks simulated +sim_seconds 0.274500 # Number of seconds simulated +sim_ticks 274500333500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128000 # Simulator instruction rate (inst/s) -host_tick_rate 59339940 # Simulator tick rate (ticks/s) -host_mem_usage 192984 # Number of bytes of host memory used -host_seconds 4702.02 # Real time elapsed on the host +host_inst_rate 56944 # Simulator instruction rate (inst/s) +host_tick_rate 25971361 # Simulator tick rate (ticks/s) +host_mem_usage 245756 # Number of bytes of host memory used +host_seconds 10569.35 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517555 # DTB read hits +system.cpu.dtb.read_hits 114517568 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520186 # DTB read accesses -system.cpu.dtb.write_hits 39666604 # DTB write hits +system.cpu.dtb.read_accesses 114520199 # DTB read accesses +system.cpu.dtb.write_hits 39666597 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39668906 # DTB write accesses -system.cpu.dtb.data_hits 154184159 # DTB hits +system.cpu.dtb.write_accesses 39668899 # DTB write accesses +system.cpu.dtb.data_hits 154184165 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154189092 # DTB accesses -system.cpu.itb.fetch_hits 29078095 # ITB hits +system.cpu.dtb.data_accesses 154189098 # DTB accesses +system.cpu.itb.fetch_hits 27986226 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 29078117 # ITB accesses +system.cpu.itb.fetch_accesses 27986248 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 558034834 # number of cpu cycles simulated +system.cpu.numCycles 549000668 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 547808694 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 538772486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 412073 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 61249901 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 496784933 # Number of cycles cpu stages are processed. -system.cpu.activity 89.024000 # Percentage of cycles cpu is active +system.cpu.timesIdled 412059 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59486579 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489514089 # Number of cycles cpu stages are processed. +system.cpu.activity 89.164571 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -61,79 +61,79 @@ system.cpu.comFloats 24 # Nu system.cpu.committedInsts 601856964 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions Simulated (Total) -system.cpu.cpi 0.927188 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.927188 # CPI: Total CPI of All Threads -system.cpu.ipc 1.078529 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads +system.cpu.ipc 1.096277 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.078529 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 90037625 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 84897563 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 39773148 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 49497029 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 39091844 # Number of BTB hits +system.cpu.ipc_total 1.096277 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 86959577 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 82118654 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 36581334 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 45689066 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 35726566 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 78.978163 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 41686827 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 48350798 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541420411 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 78.195002 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 38245021 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 48714556 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 540577865 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005275257 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1004432711 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 257533113 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 154627572 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 38276366 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 1491795 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 39768161 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 22779717 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 63.580352 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 411890550 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 255585026 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 154582342 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 35142167 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 1434180 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 36576347 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 25971564 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 58.477328 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 411886396 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 210144173 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 347890661 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.342105 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 246346046 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 311688788 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 55.854719 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 214904658 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 343130176 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 61.489025 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 446207500 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111827334 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.039490 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 210384695 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347650139 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 62.299003 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 209828742 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 339171926 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.779875 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 238624991 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310375677 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.534663 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 207052073 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341948595 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.285643 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 437467887 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111532781 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.315600 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201947249 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347053419 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.215482 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 726.393228 # Cycle average of tags in use -system.cpu.icache.total_refs 29077078 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 852 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 34128.025822 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 728.259897 # Cycle average of tags in use +system.cpu.icache.total_refs 27985205 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 32731.233918 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 726.393228 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.354684 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 29077078 # number of ReadReq hits -system.cpu.icache.demand_hits 29077078 # number of demand (read+write) hits -system.cpu.icache.overall_hits 29077078 # number of overall hits -system.cpu.icache.ReadReq_misses 1015 # number of ReadReq misses -system.cpu.icache.demand_misses 1015 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1015 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 56421500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 56421500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 56421500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 29078093 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 29078093 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 29078093 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55587.684729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55587.684729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55587.684729 # average overall miss latency +system.cpu.icache.occ_blocks::0 728.259897 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.355596 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 27985205 # number of ReadReq hits +system.cpu.icache.demand_hits 27985205 # number of demand (read+write) hits +system.cpu.icache.overall_hits 27985205 # number of overall hits +system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses +system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 56646500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 56646500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 56646500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 27986224 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 27986224 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 27986224 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000036 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000036 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000036 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55590.284593 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55590.284593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55590.284593 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 43500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -143,159 +143,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets 21750 system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 163 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 163 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 163 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 852 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 852 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 852 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 855 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 855 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45615500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45615500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45615500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45774000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45774000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45774000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53539.319249 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53539.319249 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4094.156589 # Cycle average of tags in use -system.cpu.dcache.total_refs 152394384 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.126386 # Cycle average of tags in use +system.cpu.dcache.total_refs 152394244 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 334.642199 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267634000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.156589 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999550 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 114120508 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38273876 # number of WriteReq hits -system.cpu.dcache.demand_hits 152394384 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 152394384 # number of overall hits -system.cpu.dcache.ReadReq_misses 393534 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1177445 # number of WriteReq misses -system.cpu.dcache.demand_misses 1570979 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1570979 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 8150455500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25241828500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 33392284000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 33392284000 # number of overall miss cycles +system.cpu.dcache.avg_refs 334.641891 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 267624000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.126386 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999543 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 114120509 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38273735 # number of WriteReq hits +system.cpu.dcache.demand_hits 152394244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 152394244 # number of overall hits +system.cpu.dcache.ReadReq_misses 393533 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1177586 # number of WriteReq misses +system.cpu.dcache.demand_misses 1571119 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1571119 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 8150453500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25245531000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 33395984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 33395984500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.003437 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.029846 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010203 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 20710.930949 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 21437.798369 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 21255.716340 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 21255.716340 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12054000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3423892000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2783 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 216217 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4331.297161 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15835.443097 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate 0.029849 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 21256.177603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 21256.177603 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12016500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3424460500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2770 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 216245 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4338.086643 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 408187 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 192302 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 923282 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1115584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1115584 # number of overall MSHR hits +system.cpu.dcache.writebacks 408188 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 192301 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 923423 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1115724 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1115724 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3562178000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5466807000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9028985000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9028985000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3562138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5466740000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9028878000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9028878000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.846625 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21509.059147 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19826.710877 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73794 # number of replacements -system.cpu.l2cache.tagsinuse 17696.077368 # Cycle average of tags in use -system.cpu.l2cache.total_refs 445682 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89681 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.969637 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73797 # number of replacements +system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use +system.cpu.l2cache.total_refs 445688 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1642.043968 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16054.033399 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.050111 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.489930 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 170050 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 408187 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 364155 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 364155 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32017 # number of ReadReq misses +system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 364156 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92092 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92092 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1674832000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3134450000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4809282000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4809282000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 202067 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 408187 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92094 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 456247 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 456247 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.158447 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.201847 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.201847 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52310.709935 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.613816 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52222.581766 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52222.581766 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1314000 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10346.456693 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59344 # number of writebacks +system.cpu.l2cache.writebacks 59345 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32017 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92092 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92092 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1280946000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406895000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 3687841000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 3687841000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.201847 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.201847 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.308086 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.835622 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.183078 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 2c97093b4..55c96d241 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 8c9b1bbab..ac32dbe3f 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:20:02 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:24 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -39,4 +39,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 162342217500 because target called exit() +Exiting @ tick 145300717500 because target called exit() diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 9bb344c89..339674edd 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.162342 # Number of seconds simulated -sim_ticks 162342217500 # Number of ticks simulated +sim_seconds 0.145301 # Number of seconds simulated +sim_ticks 145300717500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 248957 # Simulator instruction rate (inst/s) -host_tick_rate 71463217 # Simulator tick rate (ticks/s) -host_mem_usage 193608 # Number of bytes of host memory used -host_seconds 2271.69 # Real time elapsed on the host +host_inst_rate 109615 # Simulator instruction rate (inst/s) +host_tick_rate 28162171 # Simulator tick rate (ticks/s) +host_mem_usage 246532 # Number of bytes of host memory used +host_seconds 5159.43 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122220880 # DTB read hits -system.cpu.dtb.read_misses 24742 # DTB read misses +system.cpu.dtb.read_hits 125840781 # DTB read hits +system.cpu.dtb.read_misses 26740 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122245622 # DTB read accesses -system.cpu.dtb.write_hits 40876425 # DTB write hits -system.cpu.dtb.write_misses 28211 # DTB write misses +system.cpu.dtb.read_accesses 125867521 # DTB read accesses +system.cpu.dtb.write_hits 41455603 # DTB write hits +system.cpu.dtb.write_misses 32148 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40904636 # DTB write accesses -system.cpu.dtb.data_hits 163097305 # DTB hits -system.cpu.dtb.data_misses 52953 # DTB misses +system.cpu.dtb.write_accesses 41487751 # DTB write accesses +system.cpu.dtb.data_hits 167296384 # DTB hits +system.cpu.dtb.data_misses 58888 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 163150258 # DTB accesses -system.cpu.itb.fetch_hits 65447834 # ITB hits -system.cpu.itb.fetch_misses 37 # ITB misses +system.cpu.dtb.data_accesses 167355272 # DTB accesses +system.cpu.itb.fetch_hits 71694847 # ITB hits +system.cpu.itb.fetch_misses 40 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65447871 # ITB accesses +system.cpu.itb.fetch_accesses 71694887 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 324684436 # number of cpu cycles simulated +system.cpu.numCycles 290601436 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 76158972 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 70244988 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 4119052 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 71175082 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 63645886 # Number of BTB hits +system.cpu.BPredUnit.lookups 82480135 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 75938237 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 4123227 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 78114904 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 69862682 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1672188 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 199 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 65447834 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 697103085 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76158972 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65318074 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129743678 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4139889 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 65447834 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1277663 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 324617336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.147461 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.098162 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1959581 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 207 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 74561330 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 742166836 # Number of instructions fetch has processed +system.cpu.fetch.Branches 82480135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71822263 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 139513131 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17330809 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 63439148 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 978 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 71694847 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1192151 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 290532092 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.554509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.199356 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 194873658 60.03% 60.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10240367 3.15% 63.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15840170 4.88% 68.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13915379 4.29% 72.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11968140 3.69% 76.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13832570 4.26% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5877215 1.81% 82.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3421155 1.05% 83.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 54648682 16.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151018961 51.98% 51.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11571435 3.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15893812 5.47% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 16015901 5.51% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13154387 4.53% 71.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15895840 5.47% 76.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6797382 2.34% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3595958 1.24% 80.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 56588416 19.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 324617336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.234563 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.147017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 142213399 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 44833716 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122593858 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5374385 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9601978 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4163323 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 844 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 687863087 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3402 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9601978 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 149604933 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12564419 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 695 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 115293181 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 37552130 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 678776451 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 101 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 31522766 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 659383 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 517767610 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 894089158 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 894087193 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1965 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 290532092 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.283826 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.553899 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 90749428 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 49730662 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 127248783 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9786563 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13016656 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4449520 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 868 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 730230726 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3285 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 13016656 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 99035242 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12652833 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 552 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 123482350 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 42344459 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 716220339 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 269 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32893905 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3996747 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 545787696 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 940589265 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 940587099 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2166 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 53912721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 73444449 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 125962189 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42585734 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11874393 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4773328 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 618660755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 605609121 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 11391 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 51673321 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 26894119 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 324617336 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.865609 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.727719 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 81932807 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 82656426 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 131826399 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43887979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16660025 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7232836 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 645179442 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 621649928 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 372243 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 78544400 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 43423824 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 290532092 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.139695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.881267 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 90473429 27.87% 27.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 62743019 19.33% 47.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 78570143 24.20% 71.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 32526937 10.02% 81.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31455135 9.69% 91.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13029774 4.01% 95.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 14124566 4.35% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1126465 0.35% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 567868 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 71097940 24.47% 24.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 58395265 20.10% 44.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 55676712 19.16% 63.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 31603347 10.88% 74.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 33236000 11.44% 86.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23958494 8.25% 94.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12196902 4.20% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3766140 1.30% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 601292 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 324617336 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 290532092 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5228922 88.18% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 48 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 403247 6.80% 94.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 297449 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4587811 88.39% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 54 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 88.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 424179 8.17% 96.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 178446 3.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439577743 72.58% 72.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6656 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124281005 20.52% 93.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41743673 6.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 451150539 72.57% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7830 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 5 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 5 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 128375845 20.65% 93.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 42115665 6.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 605609121 # Type of FU issued -system.cpu.iq.rate 1.865224 # Inst issue rate -system.cpu.iq.fu_busy_cnt 5929666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009791 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1541773318 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 670348766 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 595947084 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3317 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1802 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1594 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 611537118 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1669 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10009719 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 621649928 # Type of FU issued +system.cpu.iq.rate 2.139184 # Inst issue rate +system.cpu.iq.fu_busy_cnt 5190490 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008350 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1539391263 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 723910400 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 609602063 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3418 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1948 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1597 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 626838696 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11620337 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11448147 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9957 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 24101 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3134413 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 17312357 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 134964 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 365628 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4436658 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6020 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 733 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5886 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 50751 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9601978 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1354512 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 64907 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 661873499 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3111469 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 125962189 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42585734 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 24101 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3653189 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 952315 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4605504 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599183867 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122245685 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6425254 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13016656 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1515186 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 101274 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 690779591 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2446688 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 131826399 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 43887979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 41001 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13794 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 365628 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4028203 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 602481 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4630684 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 613929253 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 125867602 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7720675 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 43212719 # number of nop insts executed -system.cpu.iew.exec_refs 163178153 # number of memory reference insts executed -system.cpu.iew.exec_branches 67449018 # Number of branches executed -system.cpu.iew.exec_stores 40932468 # Number of stores executed -system.cpu.iew.exec_rate 1.845435 # Inst execution rate -system.cpu.iew.wb_sent 597097102 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 595948678 # cumulative count of insts written-back -system.cpu.iew.wb_producers 395837342 # num instructions producing a value -system.cpu.iew.wb_consumers 486897348 # num instructions consuming a value +system.cpu.iew.exec_nop 45600120 # number of nop insts executed +system.cpu.iew.exec_refs 167374804 # number of memory reference insts executed +system.cpu.iew.exec_branches 68499674 # Number of branches executed +system.cpu.iew.exec_stores 41507202 # Number of stores executed +system.cpu.iew.exec_rate 2.112616 # Inst execution rate +system.cpu.iew.wb_sent 611080780 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 609603660 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419952220 # num instructions producing a value +system.cpu.iew.wb_consumers 531843575 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.835470 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.812979 # average fanout of values written-back +system.cpu.iew.wb_rate 2.097731 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789616 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 59876142 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 88769206 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4118243 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 315015358 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.910564 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.344745 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4122409 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 277515436 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.168733 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.607930 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102187516 32.44% 32.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 100337503 31.85% 64.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 36333939 11.53% 75.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9834278 3.12% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 9585018 3.04% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21675104 6.88% 88.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 13171126 4.18% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1520592 0.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20370282 6.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91720629 33.05% 33.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 75337959 27.15% 60.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31629889 11.40% 71.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9762168 3.52% 75.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10089201 3.64% 78.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 21364718 7.70% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5897222 2.13% 88.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2300204 0.83% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29413446 10.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 315015358 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 277515436 # Number of insts commited each cycle system.cpu.commit.count 601856963 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 153965363 # Number of memory references committed @@ -288,50 +290,50 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20370282 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29413446 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 956313792 # The number of ROB reads -system.cpu.rob.rob_writes 1333072216 # The number of ROB writes -system.cpu.timesIdled 2037 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 67100 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 938663770 # The number of ROB reads +system.cpu.rob.rob_writes 1394275800 # The number of ROB writes +system.cpu.timesIdled 2250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 69344 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.574101 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.574101 # CPI: Total CPI of All Threads -system.cpu.ipc 1.741853 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.741853 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 844972523 # number of integer regfile reads -system.cpu.int_regfile_writes 489243634 # number of integer regfile writes -system.cpu.fp_regfile_reads 253 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cpi 0.513836 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.513836 # CPI: Total CPI of All Threads +system.cpu.ipc 1.946145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.946145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 864545189 # number of integer regfile reads +system.cpu.int_regfile_writes 501712619 # number of integer regfile writes +system.cpu.fp_regfile_reads 277 # number of floating regfile reads +system.cpu.fp_regfile_writes 57 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 32 # number of replacements -system.cpu.icache.tagsinuse 774.695980 # Cycle average of tags in use -system.cpu.icache.total_refs 65446683 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 71998.551155 # Average number of references to valid blocks. +system.cpu.icache.replacements 36 # number of replacements +system.cpu.icache.tagsinuse 798.939045 # Cycle average of tags in use +system.cpu.icache.total_refs 71693570 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 940 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 76269.755319 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 774.695980 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.378270 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 65446683 # number of ReadReq hits -system.cpu.icache.demand_hits 65446683 # number of demand (read+write) hits -system.cpu.icache.overall_hits 65446683 # number of overall hits -system.cpu.icache.ReadReq_misses 1151 # number of ReadReq misses -system.cpu.icache.demand_misses 1151 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1151 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 42013000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 42013000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 42013000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 65447834 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 65447834 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 65447834 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 798.939045 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.390107 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 71693570 # number of ReadReq hits +system.cpu.icache.demand_hits 71693570 # number of demand (read+write) hits +system.cpu.icache.overall_hits 71693570 # number of overall hits +system.cpu.icache.ReadReq_misses 1277 # number of ReadReq misses +system.cpu.icache.demand_misses 1277 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1277 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 46025000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 46025000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 46025000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 71694847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 71694847 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 71694847 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36501.303215 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36501.303215 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36501.303215 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36041.503524 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36041.503524 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36041.503524 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,161 +343,161 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 242 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 242 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 242 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 940 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 940 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 940 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32280000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32280000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32280000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33513000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33513000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33513000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35511.551155 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35511.551155 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35652.127660 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35652.127660 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 471038 # number of replacements -system.cpu.dcache.tagsinuse 4094.151824 # Cycle average of tags in use -system.cpu.dcache.total_refs 149582206 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 475134 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 314.821095 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126677000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.151824 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999549 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 111416977 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 38165226 # number of WriteReq hits +system.cpu.dcache.replacements 470805 # number of replacements +system.cpu.dcache.tagsinuse 4093.951768 # Cycle average of tags in use +system.cpu.dcache.total_refs 151630549 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 474901 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 319.288755 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126064000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4093.951768 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999500 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 113482808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 38147738 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 149582203 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 149582203 # number of overall hits -system.cpu.dcache.ReadReq_misses 787554 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1286095 # number of WriteReq misses -system.cpu.dcache.demand_misses 2073649 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2073649 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11948365500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 18377052890 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 30325418390 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 30325418390 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 112204531 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits 151630546 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 151630546 # number of overall hits +system.cpu.dcache.ReadReq_misses 730789 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1303583 # number of WriteReq misses +system.cpu.dcache.demand_misses 2034372 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2034372 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11799719000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 19632109224 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 31431828224 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 31431828224 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 114213597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 151655852 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 151655852 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.007019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.032600 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.013673 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013673 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14624.181040 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14624.181040 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 778498 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 153664918 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 153664918 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.006398 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.033043 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.013239 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013239 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16146.547088 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15060.114488 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 15450.383816 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15450.383816 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 917496 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 236500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 119 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7710.050420 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 423176 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 569368 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1029147 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1598515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1598515 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 218186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 256948 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 475134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 475134 # number of overall MSHR misses +system.cpu.dcache.writebacks 423137 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 511918 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1047553 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1559471 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1559471 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 218871 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 256030 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 474901 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 474901 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4510496494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4510496494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1640511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3027783994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4668295494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4668295494 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003133 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003133 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001916 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006490 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003090 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003090 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7495.335152 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.895379 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9830.039301 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 74455 # number of replacements -system.cpu.l2cache.tagsinuse 17721.214963 # Cycle average of tags in use -system.cpu.l2cache.total_refs 477367 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 90353 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.283355 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 74456 # number of replacements +system.cpu.l2cache.tagsinuse 17669.602101 # Cycle average of tags in use +system.cpu.l2cache.total_refs 478138 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 90356 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.291713 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1734.245593 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15986.969370 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.052925 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487884 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 186178 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 423176 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 197108 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 383286 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 383286 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32917 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 59840 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 92757 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 92757 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1132170000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2063110500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3195280500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3195280500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 219095 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 423176 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 256948 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 476043 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 476043 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.150241 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.232888 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194850 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194850 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34394.689674 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34477.113971 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34447.863773 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34447.863773 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1747.606056 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15921.996045 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.053333 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485901 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 186860 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 423137 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 196226 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 383086 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 383086 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32951 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92755 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92755 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1133426500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2066052500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3199479000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3199479000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 219811 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 423137 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 256030 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 475841 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 475841 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.149906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.233582 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.194929 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.194929 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34397.332403 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.062069 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34493.870950 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34493.870950 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 468000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 80 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5145.833333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5850 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59322 # number of writebacks +system.cpu.l2cache.writebacks 59325 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32917 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 59840 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 92757 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 92757 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 32951 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92755 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1020989500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876396000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2897385500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2897385500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1022116000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877697000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2899813000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2899813000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150241 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232888 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194850 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194850 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31017.088435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31356.885027 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31236.300225 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.149906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.194929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.194929 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.271039 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31397.515216 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31263.144844 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini index 07f2d92be..485873d05 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr b/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout index 7084f92e2..f34e7fb17 100755 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 16:32:58 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 00:29:29 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -44,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 189745250000 because target called exit() +Exiting @ tick 182546630500 because target called exit() diff --git a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt index 1e34e6b02..79eb9dffa 100644 --- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.189745 # Number of seconds simulated -sim_ticks 189745250000 # Number of ticks simulated +sim_seconds 0.182547 # Number of seconds simulated +sim_ticks 182546630500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57706 # Simulator instruction rate (inst/s) -host_tick_rate 18177630 # Simulator tick rate (ticks/s) -host_mem_usage 255472 # Number of bytes of host memory used -host_seconds 10438.39 # Real time elapsed on the host -sim_insts 602359840 # Number of instructions simulated +host_inst_rate 66837 # Simulator instruction rate (inst/s) +host_tick_rate 20255145 # Simulator tick rate (ticks/s) +host_mem_usage 257744 # Number of bytes of host memory used +host_seconds 9012.36 # Real time elapsed on the host +sim_insts 602359825 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,297 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 379490501 # number of cpu cycles simulated +system.cpu.numCycles 365093262 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 86928352 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80528545 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3884028 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 80092626 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 74490175 # Number of BTB hits +system.cpu.BPredUnit.lookups 94055134 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 86414920 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3979081 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 88956702 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 82512166 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1400314 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1695 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 70199329 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 678993278 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86928352 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 75890489 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 151223447 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4473449 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 70199329 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 924096 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 378585601 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.910199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.920341 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1838122 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1832 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 80667890 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 724099412 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94055134 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 84350288 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 163986224 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 21484785 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 102787887 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 614 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 78002853 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1602878 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 364227401 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.127111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.977166 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 227362317 60.06% 60.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25157685 6.65% 66.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 17486331 4.62% 71.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 21712752 5.74% 77.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11244311 2.97% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11955687 3.16% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4446495 1.17% 84.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7289466 1.93% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 51930557 13.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 200241339 54.98% 54.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25976483 7.13% 62.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 20067114 5.51% 67.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25160816 6.91% 74.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12370660 3.40% 77.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13978922 3.84% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4846811 1.33% 83.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7981089 2.19% 85.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53604167 14.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 378585601 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.229066 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.789223 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 160153181 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 58093543 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 140600980 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8092430 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11645467 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 5860940 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1284 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 711110342 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4730 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11645467 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 169808793 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7731895 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 102804 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 138994558 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50302084 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 699378515 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 44454073 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4930432 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 610 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723286205 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3254558347 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3254558219 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 364227401 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257619 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.983327 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 103328819 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 82990379 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 141956916 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19169051 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16782236 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6955768 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 2559 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 762233872 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 7095 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 16782236 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 116716310 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10162193 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109463 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 147645122 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72812077 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 747464015 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 176 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 58909213 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10051058 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 590 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 771173910 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3477020106 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3477019978 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627417450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 95868750 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6063 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6060 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 83251971 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172882787 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80813690 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 15992884 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23084405 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 678074240 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7046 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 648954836 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 321485 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 74818706 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 185294154 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 741 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 378585601 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.714156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.635088 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627417426 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 143756479 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6432 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6428 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 129949589 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 185066010 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85818254 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 23013256 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30486769 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 718960040 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7404 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 670280843 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 854799 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 116155760 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 288576013 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 364227401 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.840281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.715695 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 99002495 26.15% 26.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 107489876 28.39% 54.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 72418873 19.13% 73.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 48797355 12.89% 86.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 22456398 5.93% 92.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 17049752 4.50% 97.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6015477 1.59% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3775065 1.00% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1580310 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 91766913 25.19% 25.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93871528 25.77% 50.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 74118513 20.35% 71.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 44924126 12.33% 83.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 26194132 7.19% 90.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19078510 5.24% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7890026 2.17% 98.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 5178547 1.42% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1205106 0.33% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 378585601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 364227401 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 164864 5.19% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2380738 74.98% 80.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 629773 19.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 168001 4.86% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2622016 75.82% 80.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 668303 19.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 405017368 62.41% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6545 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 167786137 25.85% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76144783 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 415768758 62.03% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 175425484 26.17% 88.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79080039 11.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 648954836 # Type of FU issued -system.cpu.iq.rate 1.710069 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3175375 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004893 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1679992097 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 753424475 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 636613588 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 670280843 # Type of FU issued +system.cpu.iq.rate 1.835917 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3458320 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005160 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1709102170 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 835787693 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 655814402 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 652130191 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 673739143 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 25625639 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 28975081 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23930184 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 271058 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 524844 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10592669 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 36113410 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 129451 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 665732 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 15597236 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15888 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12323 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 16028 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12631 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11645467 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 694588 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38667 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 678142321 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3267373 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172882787 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80813690 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5710 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7359 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3854 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 524844 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3752039 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 638545 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 4390584 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642328929 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 165615332 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6625907 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16782236 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 788804 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 51690 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 719036936 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2011497 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 185066010 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85818254 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6071 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13145 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5072 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 665732 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4120759 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 486329 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4607088 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 662401467 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 171983852 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7879376 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 61035 # number of nop insts executed -system.cpu.iew.exec_refs 240294143 # number of memory reference insts executed -system.cpu.iew.exec_branches 74636278 # Number of branches executed -system.cpu.iew.exec_stores 74678811 # Number of stores executed -system.cpu.iew.exec_rate 1.692609 # Inst execution rate -system.cpu.iew.wb_sent 637663585 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 636613604 # cumulative count of insts written-back -system.cpu.iew.wb_producers 410591202 # num instructions producing a value -system.cpu.iew.wb_consumers 620919251 # num instructions consuming a value +system.cpu.iew.exec_nop 69492 # number of nop insts executed +system.cpu.iew.exec_refs 249361026 # number of memory reference insts executed +system.cpu.iew.exec_branches 77022435 # Number of branches executed +system.cpu.iew.exec_stores 77377174 # Number of stores executed +system.cpu.iew.exec_rate 1.814335 # Inst execution rate +system.cpu.iew.wb_sent 657949131 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 655814418 # cumulative count of insts written-back +system.cpu.iew.wb_producers 425644511 # num instructions producing a value +system.cpu.iew.wb_consumers 661906658 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.677548 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661263 # average fanout of values written-back +system.cpu.iew.wb_rate 1.796293 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.643058 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 602359891 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 75781554 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 6305 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3943142 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 366940135 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.641575 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.021399 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 602359876 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 116686609 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 6302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 4038424 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 347445166 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.733683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.123903 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 118738354 32.36% 32.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 123466865 33.65% 66.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 52180899 14.22% 80.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12560554 3.42% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 20975428 5.72% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13806386 3.76% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7633759 2.08% 95.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2509750 0.68% 95.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15068140 4.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113764130 32.74% 32.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 109130175 31.41% 64.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 49680788 14.30% 78.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10344875 2.98% 81.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23361064 6.72% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14153772 4.07% 92.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8154815 2.35% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1152882 0.33% 94.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 17702665 5.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366940135 # Number of insts commited each cycle -system.cpu.commit.count 602359891 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 347445166 # Number of insts commited each cycle +system.cpu.commit.count 602359876 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219173623 # Number of memory references committed -system.cpu.commit.loads 148952602 # Number of loads committed +system.cpu.commit.refs 219173617 # Number of memory references committed +system.cpu.commit.loads 148952599 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828609 # Number of branches committed +system.cpu.commit.branches 70828606 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533522671 # Number of committed integer instructions. +system.cpu.commit.int_insts 533522659 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15068140 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 17702665 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1030012828 # The number of ROB reads -system.cpu.rob.rob_writes 1367937117 # The number of ROB writes -system.cpu.timesIdled 36799 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 904900 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 602359840 # Number of Instructions Simulated -system.cpu.committedInsts_total 602359840 # Number of Instructions Simulated -system.cpu.cpi 0.630006 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.630006 # CPI: Total CPI of All Threads -system.cpu.ipc 1.587286 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.587286 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3206207435 # number of integer regfile reads -system.cpu.int_regfile_writes 661050575 # number of integer regfile writes +system.cpu.rob.rob_reads 1048788374 # The number of ROB reads +system.cpu.rob.rob_writes 1454922610 # The number of ROB writes +system.cpu.timesIdled 36904 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 865861 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 602359825 # Number of Instructions Simulated +system.cpu.committedInsts_total 602359825 # Number of Instructions Simulated +system.cpu.cpi 0.606105 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.606105 # CPI: Total CPI of All Threads +system.cpu.ipc 1.649879 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.649879 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3307885763 # number of integer regfile reads +system.cpu.int_regfile_writes 680907350 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 912573919 # number of misc regfile reads -system.cpu.misc_regfile_writes 2672 # number of misc regfile writes -system.cpu.icache.replacements 41 # number of replacements -system.cpu.icache.tagsinuse 627.011637 # Cycle average of tags in use -system.cpu.icache.total_refs 70198409 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 729 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 96294.113855 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 966917605 # number of misc regfile reads +system.cpu.misc_regfile_writes 2666 # number of misc regfile writes +system.cpu.icache.replacements 48 # number of replacements +system.cpu.icache.tagsinuse 654.116997 # Cycle average of tags in use +system.cpu.icache.total_refs 78001834 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 767 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 101697.306389 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 627.011637 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.306158 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 70198409 # number of ReadReq hits -system.cpu.icache.demand_hits 70198409 # number of demand (read+write) hits -system.cpu.icache.overall_hits 70198409 # number of overall hits -system.cpu.icache.ReadReq_misses 920 # number of ReadReq misses -system.cpu.icache.demand_misses 920 # number of demand (read+write) misses -system.cpu.icache.overall_misses 920 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32585000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32585000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32585000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 70199329 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 70199329 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 70199329 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 654.116997 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.319393 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 78001834 # number of ReadReq hits +system.cpu.icache.demand_hits 78001834 # number of demand (read+write) hits +system.cpu.icache.overall_hits 78001834 # number of overall hits +system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses +system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 35576500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 35576500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 35576500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 78002853 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 78002853 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 78002853 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35418.478261 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35418.478261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35418.478261 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34913.150147 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34913.150147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34913.150147 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,143 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 189 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 189 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 189 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 731 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 731 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 731 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 252 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 252 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 252 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 767 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 767 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 767 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 25045500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 25045500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 25045500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 26271000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 26271000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 26271000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34261.969904 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34261.969904 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34251.629726 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34251.629726 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34251.629726 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 440236 # number of replacements -system.cpu.dcache.tagsinuse 4094.816019 # Cycle average of tags in use -system.cpu.dcache.total_refs 206409236 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 444332 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 464.538309 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 88952000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.816019 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999711 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 138485254 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 67921309 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1329 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1335 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 206406563 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 206406563 # number of overall hits -system.cpu.dcache.ReadReq_misses 243961 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1496222 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1740183 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1740183 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3253587000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 26715936018 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 152000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 29969523018 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 29969523018 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 138729215 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 440983 # number of replacements +system.cpu.dcache.tagsinuse 4094.790768 # Cycle average of tags in use +system.cpu.dcache.total_refs 209375241 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 445079 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 470.422646 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 87857000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.790768 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999705 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 141476381 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 67896188 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 1340 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 1332 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 209372569 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 209372569 # number of overall hits +system.cpu.dcache.ReadReq_misses 248779 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1521343 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 10 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 1770122 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1770122 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3280245000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 26835404025 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 198500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 30115649025 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 30115649025 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 141725160 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1344 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1335 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 208146746 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 208146746 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001759 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.021554 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.011161 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.008360 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.008360 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 13336.504605 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17855.596307 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 10133.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 17222.052519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 17222.052519 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9582528 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 1350 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 1332 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 211142691 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 211142691 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.001755 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.021916 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.007407 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.008384 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.008384 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 13185.377383 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17639.285832 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 19850 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 17013.318305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 17013.318305 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9583027 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2185 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.596339 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4385.824714 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 394716 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 46944 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1248905 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1295849 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1295849 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 197017 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 247317 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 444334 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 444334 # number of overall MSHR misses +system.cpu.dcache.writebacks 395060 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 51069 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1273974 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 10 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1325043 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1325043 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 197710 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 247369 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 445079 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 445079 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1620169000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2562065527 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4182234527 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4182234527 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1624301000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2561171527 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4185472527 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4185472527 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001420 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001395 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003563 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002135 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002135 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8223.498480 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10359.439614 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9412.366659 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.002108 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002108 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8215.573314 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10353.647898 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9403.886786 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9403.886786 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 72895 # number of replacements -system.cpu.l2cache.tagsinuse 17837.050931 # Cycle average of tags in use -system.cpu.l2cache.total_refs 420745 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 88410 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.759020 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 72980 # number of replacements +system.cpu.l2cache.tagsinuse 17828.973663 # Cycle average of tags in use +system.cpu.l2cache.total_refs 421802 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 88512 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.765478 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1909.078024 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15927.972907 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058260 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.486083 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 165017 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 394716 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 188953 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 353970 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 353970 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32728 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 58363 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91091 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91091 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1124545500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2003459500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3128005000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3128005000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 197745 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 394716 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 247316 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 445061 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 445061 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.165506 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235986 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.204671 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.204671 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34360.348937 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34327.561983 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34339.341977 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34339.341977 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1911.988295 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15916.985368 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058349 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.485748 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 165669 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 395060 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 188996 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 354665 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 354665 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32802 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58379 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91181 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91181 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1126009000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2004629500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3130638500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3130638500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 198471 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 395060 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 247375 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 445846 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 445846 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.165274 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235994 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.204512 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.204512 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34327.449546 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34338.195241 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34334.329520 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34334.329520 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked @@ -496,32 +494,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5845.170455 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58107 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32722 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58363 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91085 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91085 # number of overall MSHR misses +system.cpu.l2cache.writebacks 58140 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 9 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32793 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58379 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91172 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91172 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1018131500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 32000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1823239000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2841370500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2841370500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1019413500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1823005500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2842419000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2842419000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.204657 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.204657 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31114.586517 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 32000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31239.638127 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.713729 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235994 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.204492 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.204492 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31086.314152 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31227.076517 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.446716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.446716 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index d070843b4..d391b02a1 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index e45361957..589c8ec4c 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout -Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 12 2011 07:14:44 -gem5 started Jun 12 2011 07:18:15 -gem5 executing on zizzer +gem5 compiled Jul 8 2011 15:08:13 +gem5 started Jul 8 2011 18:26:23 +gem5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -40,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 573907140000 because target called exit() +Exiting @ tick 563588156500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 783dcd8cf..d52982e26 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,250 +1,252 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.573907 # Number of seconds simulated -sim_ticks 573907140000 # Number of ticks simulated +sim_seconds 0.563588 # Number of seconds simulated +sim_ticks 563588156500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108575 # Simulator instruction rate (inst/s) -host_tick_rate 44331146 # Simulator tick rate (ticks/s) -host_mem_usage 230156 # Number of bytes of host memory used -host_seconds 12945.91 # Real time elapsed on the host +host_inst_rate 64765 # Simulator instruction rate (inst/s) +host_tick_rate 25968064 # Simulator tick rate (ticks/s) +host_mem_usage 251156 # Number of bytes of host memory used +host_seconds 21703.13 # Real time elapsed on the host sim_insts 1405604152 # Number of instructions simulated system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 1147814281 # number of cpu cycles simulated +system.cpu.numCycles 1127176314 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 103831607 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 92935748 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 5327690 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 99212201 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 97835702 # Number of BTB hits +system.cpu.BPredUnit.lookups 108002078 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 96458356 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 5419443 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 104845979 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 103526655 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1143 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 1233 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 171000623 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1733021012 # Number of instructions fetch has processed -system.cpu.fetch.Branches 103831607 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 97836845 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371038275 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5780781 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 171000623 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1213723 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1147443356 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.514308 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.728632 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 182291160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1787208152 # Number of instructions fetch has processed +system.cpu.fetch.Branches 108002078 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103527888 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 384452467 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 39306331 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 526780202 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 13 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1622 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 177554256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1007248 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1126809005 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.590132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.768689 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 776405081 67.66% 67.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82050380 7.15% 74.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 44983062 3.92% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 23090909 2.01% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 33504477 2.92% 83.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 33278378 2.90% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14847881 1.29% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7468781 0.65% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 131814407 11.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 742356538 65.88% 65.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 85341479 7.57% 73.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 46929286 4.16% 77.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24554385 2.18% 79.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 34670829 3.08% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 34912206 3.10% 85.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 15372705 1.36% 87.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7941055 0.70% 88.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 134730522 11.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1147443356 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090460 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.509844 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 395037433 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 355619175 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 349843694 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18917144 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 28025910 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1728452454 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 28025910 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 431217240 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 109925159 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53352046 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 328971918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 195951083 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1711590764 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 114289761 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 41137293 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 28197975 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1428307054 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2890539960 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2856856842 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 33683118 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1126809005 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.095816 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.585562 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 243483307 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 469211226 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 329903735 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50927196 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 33283541 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1773785354 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 33283541 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 303199519 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 121005551 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 66378557 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 319425533 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 283516304 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1755376544 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 158155356 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 64460520 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 40367810 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1464774447 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2963679380 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2929648556 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34030824 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770452 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 183536602 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3097987 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3097933 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 355739263 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 461589654 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 187242454 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 391441071 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 159185807 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1587145158 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3113475 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1482560203 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 270761 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 184202886 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 243216207 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 869804 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1147443356 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.292055 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.157896 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 220003995 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3335169 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3335909 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 507197291 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 473956598 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 190918944 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 402921595 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 162419763 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1626020867 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3211854 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1494042135 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 206172 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 223169277 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 302404283 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 968183 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1126809005 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.325905 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.154571 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 300845237 26.22% 26.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 453630203 39.53% 65.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 228516175 19.92% 85.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 106998909 9.32% 94.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 42740064 3.72% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8913516 0.78% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5375020 0.47% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 270889 0.02% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 153343 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 292007700 25.91% 25.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 411780858 36.54% 62.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 263168713 23.36% 85.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 101528512 9.01% 94.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 43990451 3.90% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 11374555 1.01% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2356617 0.21% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 448758 0.04% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152841 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1147443356 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1126809005 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 201164 6.38% 6.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 172993 5.49% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2493416 79.12% 90.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 283893 9.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 276548 8.36% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 151088 4.56% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2447279 73.94% 86.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 434986 13.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 884414368 59.65% 59.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2630713 0.18% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 423843345 28.59% 88.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171671777 11.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 893364457 59.80% 59.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2623126 0.18% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 426278234 28.53% 88.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171776318 11.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1482560203 # Type of FU issued -system.cpu.iq.rate 1.291638 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3151466 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002126 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4098230852 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1765766096 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1465086286 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17755137 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9173728 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8521133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1476573323 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9138346 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 135220708 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1494042135 # Type of FU issued +system.cpu.iq.rate 1.325473 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3309901 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002215 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4100596899 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1843738328 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1474876541 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17812449 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9274219 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8514769 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1488163197 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9188839 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 140932048 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 59076810 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33855 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 480180 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 20394312 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 71443754 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20242 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 695476 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24070802 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 270 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 40283 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 267 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39866 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 28025910 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2504854 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 128582 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1690773630 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4528845 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 461589654 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 187242454 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3013900 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66564 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8476 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 480180 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5013682 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 651351 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 5665033 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1476197681 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 421021999 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6362522 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 33283541 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2642816 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 166342 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1732819113 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4184603 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 473956598 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 190918944 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3110022 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 73740 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9229 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 695476 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5255230 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 461002 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 5716232 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1486789752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 422968775 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7252383 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 100514997 # number of nop insts executed -system.cpu.iew.exec_refs 591171698 # number of memory reference insts executed -system.cpu.iew.exec_branches 89599986 # Number of branches executed -system.cpu.iew.exec_stores 170149699 # Number of stores executed -system.cpu.iew.exec_rate 1.286095 # Inst execution rate -system.cpu.iew.wb_sent 1474639839 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1473607419 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1163432060 # num instructions producing a value -system.cpu.iew.wb_consumers 1211671971 # num instructions consuming a value +system.cpu.iew.exec_nop 103586392 # number of nop insts executed +system.cpu.iew.exec_refs 593427321 # number of memory reference insts executed +system.cpu.iew.exec_branches 90250072 # Number of branches executed +system.cpu.iew.exec_stores 170458546 # Number of stores executed +system.cpu.iew.exec_rate 1.319039 # Inst execution rate +system.cpu.iew.wb_sent 1484841678 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1483391310 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1170940676 # num instructions producing a value +system.cpu.iew.wb_consumers 1222219030 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.283838 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.960187 # average fanout of values written-back +system.cpu.iew.wb_rate 1.316024 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.958045 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 201157053 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 243200723 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5327690 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1119418057 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.330623 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.777335 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5419443 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1093526075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.362129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.820328 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 396150099 35.39% 35.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 467476114 41.76% 77.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 53942653 4.82% 81.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 96590276 8.63% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 32582647 2.91% 93.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8533715 0.76% 94.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 26013211 2.32% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9722118 0.87% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 28407224 2.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 386645364 35.36% 35.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 450467032 41.19% 76.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 52266567 4.78% 81.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 95504499 8.73% 90.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 32424023 2.97% 93.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8856558 0.81% 93.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 27482733 2.51% 96.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9900040 0.91% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29979259 2.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1119418057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1093526075 # Number of insts commited each cycle system.cpu.commit.count 1489523295 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 569360986 # Number of memory references committed @@ -254,50 +256,50 @@ system.cpu.commit.branches 86248929 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476388 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 28407224 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29979259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2781626311 # The number of ROB reads -system.cpu.rob.rob_writes 3409421269 # The number of ROB writes -system.cpu.timesIdled 11496 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 370925 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2796205964 # The number of ROB reads +system.cpu.rob.rob_writes 3498772696 # The number of ROB writes +system.cpu.timesIdled 11331 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 367309 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.816599 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.816599 # CPI: Total CPI of All Threads -system.cpu.ipc 1.224592 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.224592 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1997677714 # number of integer regfile reads -system.cpu.int_regfile_writes 1296953173 # number of integer regfile writes -system.cpu.fp_regfile_reads 16960308 # number of floating regfile reads -system.cpu.fp_regfile_writes 10460736 # number of floating regfile writes -system.cpu.misc_regfile_reads 596972028 # number of misc regfile reads +system.cpu.cpi 0.801916 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.801916 # CPI: Total CPI of All Threads +system.cpu.ipc 1.247014 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.247014 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2006108330 # number of integer regfile reads +system.cpu.int_regfile_writes 1306606440 # number of integer regfile writes +system.cpu.fp_regfile_reads 16974388 # number of floating regfile reads +system.cpu.fp_regfile_writes 10441040 # number of floating regfile writes +system.cpu.misc_regfile_reads 599300610 # number of misc regfile reads system.cpu.misc_regfile_writes 2258933 # number of misc regfile writes -system.cpu.icache.replacements 152 # number of replacements -system.cpu.icache.tagsinuse 1026.516875 # Cycle average of tags in use -system.cpu.icache.total_refs 170998889 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1268 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 134857.167981 # Average number of references to valid blocks. +system.cpu.icache.replacements 162 # number of replacements +system.cpu.icache.tagsinuse 1043.489653 # Cycle average of tags in use +system.cpu.icache.total_refs 177552476 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1297 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 136894.738628 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1026.516875 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.501229 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 170998889 # number of ReadReq hits -system.cpu.icache.demand_hits 170998889 # number of demand (read+write) hits -system.cpu.icache.overall_hits 170998889 # number of overall hits -system.cpu.icache.ReadReq_misses 1734 # number of ReadReq misses -system.cpu.icache.demand_misses 1734 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1734 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 61087500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 61087500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 61087500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 171000623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 171000623 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 171000623 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1043.489653 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.509516 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 177552476 # number of ReadReq hits +system.cpu.icache.demand_hits 177552476 # number of demand (read+write) hits +system.cpu.icache.overall_hits 177552476 # number of overall hits +system.cpu.icache.ReadReq_misses 1780 # number of ReadReq misses +system.cpu.icache.demand_misses 1780 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 62084000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 62084000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 62084000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 177554256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 177554256 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 177554256 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35229.238754 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35229.238754 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35229.238754 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34878.651685 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34878.651685 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34878.651685 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,140 +309,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 465 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 465 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 465 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1269 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1269 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1269 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 482 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 482 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 482 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1298 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 44480000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 44480000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 44480000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45208500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45208500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45208500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35051.221434 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35051.221434 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35051.221434 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34829.352851 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34829.352851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34829.352851 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 477525 # number of replacements -system.cpu.dcache.tagsinuse 4095.396718 # Cycle average of tags in use -system.cpu.dcache.total_refs 449986913 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 481621 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 934.317467 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 132284000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.396718 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999853 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 284949611 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 165035983 # number of WriteReq hits +system.cpu.dcache.replacements 475456 # number of replacements +system.cpu.dcache.tagsinuse 4095.394464 # Cycle average of tags in use +system.cpu.dcache.total_refs 446158150 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 479552 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 930.364486 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 131008000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.394464 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999852 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 281189388 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 164967443 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits 449985594 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 449985594 # number of overall hits -system.cpu.dcache.ReadReq_misses 816129 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1810833 # number of WriteReq misses +system.cpu.dcache.demand_hits 446156831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 446156831 # number of overall hits +system.cpu.dcache.ReadReq_misses 816269 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1879373 # number of WriteReq misses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.demand_misses 2626962 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2626962 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11967941500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 27822628145 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2695642 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2695642 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 11972698500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 28858348258 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency 267000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency 39790569645 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39790569645 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 285765740 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 40831046758 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 40831046758 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 282005657 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 452612556 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 452612556 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002856 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010853 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 448852473 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 448852473 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.002895 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011264 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate 0.005804 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.005804 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14664.276726 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 15364.546673 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.006006 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.006006 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 14667.589361 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15355.306402 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency 38142.857143 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency 15146.990952 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 15146.990952 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency 15147.058385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 15147.058385 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 3000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 428389 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 602603 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1542745 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2145348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2145348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213526 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 268088 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 426829 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 604140 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1611957 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2216097 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2216097 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 212129 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 267416 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses 481614 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 481614 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 479545 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 479545 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1594631500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3466876734 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1590330500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3553768773 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency 246000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5061508234 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5061508234 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5144099273 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5144099273 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000747 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000752 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001603 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001064 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001064 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7468.090537 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12931.860934 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001068 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001068 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7496.997110 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13289.289994 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35142.857143 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10509.470726 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10509.470726 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10727.041827 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10727.041827 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 75907 # number of replacements -system.cpu.l2cache.tagsinuse 17672.498181 # Cycle average of tags in use -system.cpu.l2cache.total_refs 467533 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 91416 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.114345 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 75860 # number of replacements +system.cpu.l2cache.tagsinuse 17695.918496 # Cycle average of tags in use +system.cpu.l2cache.total_refs 464712 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 91372 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.085934 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1962.738670 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15709.759511 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.059898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.479424 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181118 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 428389 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 207636 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 388754 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 388754 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33668 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 60468 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 94136 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 94136 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1145944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2080516000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3226460000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3226460000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214786 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 428389 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 268104 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 482890 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 482890 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.156751 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.225539 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.194943 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.194943 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34036.592610 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34406.892902 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34274.453981 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34274.453981 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 1941.337449 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15754.581047 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.059245 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.480792 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 179775 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 426829 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 206986 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 386761 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 386761 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33652 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 60437 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 94089 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 94089 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1145407000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2080656500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3226063500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3226063500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 213427 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 426829 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 267423 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 480850 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 480850 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.157675 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.225998 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.195672 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.195672 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34036.818020 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34426.865993 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34287.360903 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34287.360903 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,27 +451,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 59288 # number of writebacks +system.cpu.l2cache.writebacks 59276 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33668 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 60468 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 94136 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 94136 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33652 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60437 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 94089 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 94089 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1043871500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893875000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2937746500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2937746500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1043368500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893759500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2937128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2937128000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156751 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225539 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.194943 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.194943 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.856243 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31320.285109 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31207.471106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31207.471106 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225998 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.195672 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.195672 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.650541 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31334.439168 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.486518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.486518 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 21fe896ca..29b391479 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index f693063ef..621f09656 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 8 2011 19:12:13 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -1062,4 +1062,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 750278436000 because target called exit() +Exiting @ tick 746999805000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 8f8873cca..b33faa135 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,249 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.750278 # Number of seconds simulated -sim_ticks 750278436000 # Number of ticks simulated +sim_seconds 0.747000 # Number of seconds simulated +sim_ticks 746999805000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 214715 # Simulator instruction rate (inst/s) -host_tick_rate 99350353 # Simulator tick rate (ticks/s) -host_mem_usage 230596 # Number of bytes of host memory used -host_seconds 7551.84 # Real time elapsed on the host +host_inst_rate 52755 # Simulator instruction rate (inst/s) +host_tick_rate 24303440 # Simulator tick rate (ticks/s) +host_mem_usage 253604 # Number of bytes of host memory used +host_seconds 30736.38 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1500556873 # number of cpu cycles simulated +system.cpu.numCycles 1493999611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 179206646 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 179206646 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 8463551 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 169776881 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 168588435 # Number of BTB hits +system.cpu.BPredUnit.lookups 183981284 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 183981284 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7273832 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 175979129 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 174823422 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 168643185 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1398775423 # Number of instructions fetch has processed -system.cpu.fetch.Branches 179206646 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 168588435 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 401459368 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14868125 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 168643185 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 821564 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1500265844 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.692515 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.050179 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 199101325 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1418187336 # Number of instructions fetch has processed +system.cpu.fetch.Branches 183981284 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 174823422 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 411931747 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 120581871 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 775842898 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 439 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 187933146 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1412014 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1493732032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.734289 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.070436 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1101846908 73.44% 73.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25629201 1.71% 75.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 17503252 1.17% 76.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17259352 1.15% 77.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 30203070 2.01% 79.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16882652 1.13% 80.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 34105222 2.27% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37737433 2.52% 85.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 219098754 14.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1084944891 72.63% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 27695152 1.85% 74.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18612240 1.25% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 16931022 1.13% 76.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30747713 2.06% 78.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 17254642 1.16% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38005540 2.54% 82.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 38774045 2.60% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 220766787 14.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1500265844 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119427 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.932171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 426619882 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 588582259 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 331774062 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 54890410 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 98399231 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2463603655 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 98399231 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 490140995 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 167797271 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 309381141 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 434544169 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2390094348 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 68 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 298397694 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 109374277 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2388910462 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5790943512 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5790943448 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 64 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1493732032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123147 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.949255 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 299784199 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 683008972 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 314849688 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 89233622 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 106855551 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2563435147 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 106855551 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 360599256 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 188215169 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3353 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 328972953 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 509085750 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2506842740 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 353300714 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 135977984 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2507364398 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6062894034 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6062889786 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4248 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 770915812 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 87 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 713558954 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 613723437 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250366407 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 539421468 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 206415389 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2337617045 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1854722734 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 196953 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 715983429 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1505792864 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1500265844 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.236263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.216770 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 889369748 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 162 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 162 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 860776772 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 644217579 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 260359160 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 564219162 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 219825369 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2437807916 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 95 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1879814445 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 473311 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 816283522 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1731057121 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1493732032 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.258468 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.208875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 461494018 30.76% 30.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 582014055 38.79% 69.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 214930558 14.33% 83.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153972669 10.26% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 64799231 4.32% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 17691341 1.18% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4397619 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 840611 0.06% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125742 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 432191127 28.93% 28.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 591005322 39.57% 68.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 246823296 16.52% 85.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 135579868 9.08% 94.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 59328852 3.97% 98.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 22913004 1.53% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4862881 0.33% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 856243 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 171439 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1500265844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1493732032 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 159647 3.75% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3486871 81.91% 85.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 610438 14.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 145103 3.04% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3853337 80.69% 83.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 777052 16.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 27575645 1.49% 1.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1184540758 63.87% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 450487645 24.29% 89.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192118686 10.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 26397138 1.40% 1.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212079345 64.48% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 449002654 23.89% 89.77% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192335308 10.23% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1854722734 # Type of FU issued -system.cpu.iq.rate 1.236023 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4256956 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002295 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5214165186 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3059990835 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1837811563 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 1879814445 # Type of FU issued +system.cpu.iq.rate 1.258243 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4775492 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002540 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5258609690 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3260533161 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1853774167 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 1274 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1831404026 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1858192780 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 19 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 117971084 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 120571651 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 194681312 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 16091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6391116 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 62180350 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 225175454 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6636 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6448917 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 72173103 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30252 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 67 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30868 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 98399231 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1363305 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 110880 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2337617123 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 338195 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 613723437 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 250366407 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 56702 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6391116 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4450206 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4153743 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8603949 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1842187665 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 444314021 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12535069 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 106855551 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4276997 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 154006 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2437808011 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3809571 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 644217579 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 260359160 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 95 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 92996 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6448917 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4522013 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2931532 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7453545 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1858657499 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 444749829 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21156946 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 636013673 # number of memory reference insts executed -system.cpu.iew.exec_branches 111427506 # Number of branches executed -system.cpu.iew.exec_stores 191699652 # Number of stores executed -system.cpu.iew.exec_rate 1.227669 # Inst execution rate -system.cpu.iew.wb_sent 1840965230 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1837811575 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1424401809 # num instructions producing a value -system.cpu.iew.wb_consumers 2083960582 # num instructions consuming a value +system.cpu.iew.exec_refs 636612361 # number of memory reference insts executed +system.cpu.iew.exec_branches 111987428 # Number of branches executed +system.cpu.iew.exec_stores 191862532 # Number of stores executed +system.cpu.iew.exec_rate 1.244082 # Inst execution rate +system.cpu.iew.wb_sent 1856615108 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1853774179 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1441885120 # num instructions producing a value +system.cpu.iew.wb_consumers 2107634936 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.224753 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.683507 # average fanout of values written-back +system.cpu.iew.wb_rate 1.240813 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.684125 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 716132515 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 816323432 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8463578 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1401866613 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.156668 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.378442 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7273892 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1386876481 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.169170 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.394530 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 520031376 37.10% 37.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 533018726 38.02% 75.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 125308330 8.94% 84.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 139235246 9.93% 93.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 43288203 3.09% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 23453801 1.67% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4331063 0.31% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1854281 0.13% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11345587 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 510181205 36.79% 36.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 529583219 38.19% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 122943422 8.86% 83.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 138376651 9.98% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 42654329 3.08% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24144434 1.74% 98.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5177613 0.37% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2036062 0.15% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11779546 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1401866613 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1386876481 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -253,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 11345587 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11779546 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3728147523 # The number of ROB reads -system.cpu.rob.rob_writes 4773653528 # The number of ROB writes -system.cpu.timesIdled 43666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 291029 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3812914349 # The number of ROB reads +system.cpu.rob.rob_writes 4982493999 # The number of ROB writes +system.cpu.timesIdled 44138 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 267579 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.925416 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.925416 # CPI: Total CPI of All Threads -system.cpu.ipc 1.080595 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.080595 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3235784294 # number of integer regfile reads -system.cpu.int_regfile_writes 1830729236 # number of integer regfile writes +system.cpu.cpi 0.921372 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.921372 # CPI: Total CPI of All Threads +system.cpu.ipc 1.085338 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.085338 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3240601354 # number of integer regfile reads +system.cpu.int_regfile_writes 1846777221 # number of integer regfile writes system.cpu.fp_regfile_reads 12 # number of floating regfile reads -system.cpu.misc_regfile_reads 930213220 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 793.330591 # Cycle average of tags in use -system.cpu.icache.total_refs 168641986 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 875 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 192733.698286 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 936479302 # number of misc regfile reads +system.cpu.icache.replacements 14 # number of replacements +system.cpu.icache.tagsinuse 820.004984 # Cycle average of tags in use +system.cpu.icache.total_refs 187931883 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 908 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 206973.439427 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 793.330591 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.387368 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 168641986 # number of ReadReq hits -system.cpu.icache.demand_hits 168641986 # number of demand (read+write) hits -system.cpu.icache.overall_hits 168641986 # number of overall hits -system.cpu.icache.ReadReq_misses 1199 # number of ReadReq misses -system.cpu.icache.demand_misses 1199 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1199 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 42201000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 42201000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 42201000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 168643185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 168643185 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 168643185 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 820.004984 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.400393 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 187931883 # number of ReadReq hits +system.cpu.icache.demand_hits 187931883 # number of demand (read+write) hits +system.cpu.icache.overall_hits 187931883 # number of overall hits +system.cpu.icache.ReadReq_misses 1263 # number of ReadReq misses +system.cpu.icache.demand_misses 1263 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1263 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 44191500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 44191500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 44191500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 187933146 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 187933146 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 187933146 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35196.830692 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35196.830692 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35196.830692 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34989.311164 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34989.311164 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34989.311164 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,159 +306,159 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 324 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 324 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 324 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 875 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 875 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 875 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 355 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 355 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 355 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 908 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 908 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 908 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 30921000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 30921000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 30921000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 32070500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 32070500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 32070500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35338.285714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35338.285714 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35319.933921 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35319.933921 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460957 # number of replacements -system.cpu.dcache.tagsinuse 4095.145869 # Cycle average of tags in use -system.cpu.dcache.total_refs 513034277 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 465053 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 1103.173782 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317696000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.145869 # Average occupied blocks per context +system.cpu.dcache.replacements 459464 # number of replacements +system.cpu.dcache.tagsinuse 4095.142322 # Cycle average of tags in use +system.cpu.dcache.total_refs 510865684 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463560 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1102.048675 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317747000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.142322 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999791 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 326108931 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 186925346 # number of WriteReq hits -system.cpu.dcache.demand_hits 513034277 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 513034277 # number of overall hits -system.cpu.dcache.ReadReq_misses 218266 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1260711 # number of WriteReq misses -system.cpu.dcache.demand_misses 1478977 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1478977 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2205272500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 24390827496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 26596099996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 26596099996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 326327197 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 323944700 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186920984 # number of WriteReq hits +system.cpu.dcache.demand_hits 510865684 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 510865684 # number of overall hits +system.cpu.dcache.ReadReq_misses 217118 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1265073 # number of WriteReq misses +system.cpu.dcache.demand_misses 1482191 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1482191 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2201155000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24662905498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 26864060498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 26864060498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 324161818 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 514513254 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 514513254 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000669 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006699 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.002875 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002875 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10103.600652 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19346.882431 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 17982.767816 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 17982.767816 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 504500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 474736000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 214 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29560 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2357.476636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16060.081191 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses 512347875 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 512347875 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000670 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006722 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.002893 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.002893 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10138.058567 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19495.242961 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18124.560531 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18124.560531 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1608500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 471924500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 447 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29514 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3598.434004 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15989.852273 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 411400 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3331 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1010593 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1013924 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1013924 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 214935 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 250118 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 465053 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 465053 # number of overall MSHR misses +system.cpu.dcache.writebacks 410359 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3236 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1015395 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1018631 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1018631 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213882 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249678 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463560 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463560 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1536673000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2518183497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4054856497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4054856497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1535369000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2499634500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4035003500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4035003500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000659 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000904 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000904 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7149.477749 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10067.981901 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8719.127706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000660 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001327 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000905 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000905 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7178.579778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10011.432725 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8704.382388 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73679 # number of replacements -system.cpu.l2cache.tagsinuse 18021.980204 # Cycle average of tags in use -system.cpu.l2cache.total_refs 455469 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89282 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.101465 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73641 # number of replacements +system.cpu.l2cache.tagsinuse 18052.437933 # Cycle average of tags in use +system.cpu.l2cache.total_refs 453217 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89251 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.078005 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1918.737195 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16103.243009 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.058555 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.491432 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 182682 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 411400 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 191297 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 373979 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 373979 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33118 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58831 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91949 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91949 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1130130500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2026415500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3156546000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3156546000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 215800 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 411400 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 250128 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 465928 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 465928 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.153466 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235204 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.197346 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.197346 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34124.358355 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34444.689024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34329.312989 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34329.312989 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 1921.052649 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16131.385284 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058626 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.492291 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181658 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 410359 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 190902 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 372560 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 372560 # number of overall hits +system.cpu.l2cache.ReadReq_misses 33126 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58782 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91908 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91908 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1130437500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2022399000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3152836500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3152836500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214784 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 410359 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249684 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464468 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464468 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154229 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235426 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.197878 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.197878 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34125.384894 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.072982 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34304.266223 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34304.266223 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1076.388889 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58539 # number of writebacks +system.cpu.l2cache.writebacks 58527 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33118 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58831 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91949 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91949 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33126 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58782 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91908 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91908 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1026873000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1832918500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2859791500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2859791500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1027129500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1831638000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2858767500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2858767500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153466 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235204 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.197346 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.197346 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.491938 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31155.657731 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.931506 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154229 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235426 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.197878 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.197878 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31006.746966 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31159.844850 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31104.664447 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 674bf0325..085ebcfb6 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -10,12 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +memories=system.physmem +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -930,7 +931,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -950,7 +951,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1046,6 +1047,7 @@ port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system. [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -1078,7 +1080,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -1197,6 +1199,7 @@ pio=system.iobus.port[27] [system.tsunami.fake_OROM] type=IsaFake +fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 @@ -1213,6 +1216,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake +fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 @@ -1229,6 +1233,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake +fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 @@ -1245,6 +1250,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake +fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 @@ -1261,6 +1267,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake +fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 @@ -1277,6 +1284,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake +fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 @@ -1293,6 +1301,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake +fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 @@ -1309,6 +1318,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake +fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 @@ -1325,6 +1335,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake +fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 @@ -1341,6 +1352,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake +fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 @@ -1357,6 +1369,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake +fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 @@ -1373,6 +1386,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake +fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 @@ -1389,6 +1403,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake +fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 @@ -1405,6 +1420,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake +fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 @@ -1421,6 +1437,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake +fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 @@ -1437,6 +1454,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake +fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 @@ -1453,6 +1471,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake +fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 @@ -1469,6 +1488,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake +fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 @@ -1485,6 +1505,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake +fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index 0372a3b05..0bcb6e870 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -1,9 +1,5 @@ warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 6aab5269d..9c91bbd4a 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,17 +1,13 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:02:59 -M5 started Apr 21 2011 13:21:52 -M5 executing on maize -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Jul 8 2011 15:02:59 +gem5 started Jul 8 2011 18:23:45 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 109002500 -Exiting @ tick 1901725056500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107915000 +Exiting @ tick 1898652239500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index a973eefe5..049977b68 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,1563 +1,1573 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146685 # Simulator instruction rate (inst/s) -host_mem_usage 297796 # Number of bytes of host memory used -host_seconds 389.14 # Real time elapsed on the host -host_tick_rate 4887032789 # Simulator tick rate (ticks/s) +sim_seconds 1.898652 # Number of seconds simulated +sim_ticks 1898652239500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 57080594 # Number of instructions simulated -sim_seconds 1.901725 # Number of seconds simulated -sim_ticks 1901725056500 # Number of ticks simulated +host_inst_rate 56630 # Simulator instruction rate (inst/s) +host_tick_rate 1915374267 # Simulator tick rate (ticks/s) +host_mem_usage 336120 # Number of bytes of host memory used +host_seconds 991.27 # Real time elapsed on the host +sim_insts 56136028 # Number of instructions simulated +system.l2c.replacements 398212 # number of replacements +system.l2c.tagsinuse 35264.339871 # Cycle average of tags in use +system.l2c.total_refs 2531779 # Total number of references to valid blocks. +system.l2c.sampled_refs 433064 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.846201 # Average number of references to valid blocks. +system.l2c.warmup_cycle 9253572000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 10247.642027 # Average occupied blocks per context +system.l2c.occ_blocks::1 2471.458479 # Average occupied blocks per context +system.l2c.occ_blocks::2 22545.239365 # Average occupied blocks per context +system.l2c.occ_percent::0 0.156367 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.037711 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.344013 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 988451 # number of ReadReq hits +system.l2c.ReadReq_hits::1 903729 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1892180 # number of ReadReq hits +system.l2c.Writeback_hits::0 854494 # number of Writeback hits +system.l2c.Writeback_hits::total 854494 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 118 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 98 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 216 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 35 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 33 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 107958 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 83389 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 191347 # number of ReadExReq hits +system.l2c.demand_hits::0 1096409 # number of demand (read+write) hits +system.l2c.demand_hits::1 987118 # number of demand (read+write) hits +system.l2c.demand_hits::2 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 2083527 # number of demand (read+write) hits +system.l2c.overall_hits::0 1096409 # number of overall hits +system.l2c.overall_hits::1 987118 # number of overall hits +system.l2c.overall_hits::2 0 # number of overall hits +system.l2c.overall_hits::total 2083527 # number of overall hits +system.l2c.ReadReq_misses::0 301714 # number of ReadReq misses +system.l2c.ReadReq_misses::1 8229 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309943 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 2585 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 556 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3141 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 58 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 106 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 164 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 104499 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 19805 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124304 # number of ReadExReq misses +system.l2c.demand_misses::0 406213 # number of demand (read+write) misses +system.l2c.demand_misses::1 28034 # number of demand (read+write) misses +system.l2c.demand_misses::2 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 434247 # number of demand (read+write) misses +system.l2c.overall_misses::0 406213 # number of overall misses +system.l2c.overall_misses::1 28034 # number of overall misses +system.l2c.overall_misses::2 0 # number of overall misses +system.l2c.overall_misses::total 434247 # number of overall misses +system.l2c.ReadReq_miss_latency 16115869500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 5950500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 996000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6519390500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22635260000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22635260000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1290165 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 911958 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2202123 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 854494 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 854494 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 2703 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 654 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 93 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 139 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 232 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 212457 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 103194 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 315651 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 1502622 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 1015152 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2517774 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1502622 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 1015152 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2517774 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.233857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.009023 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.956345 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.850153 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.623656 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.762590 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.491860 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.191920 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.270336 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.027616 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.270336 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.027616 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 53414.390781 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1958423.806052 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 2301.934236 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 10702.338129 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 17172.413793 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 9396.226415 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 62387.108968 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 329179.020449 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::0 55722.638123 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 807421.702219 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency +system.l2c.demand_avg_miss_latency::total inf # average overall miss latency +system.l2c.overall_avg_miss_latency::0 55722.638123 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 807421.702219 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency +system.l2c.overall_avg_miss_latency::total inf # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 122541 # number of writebacks +system.l2c.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 22 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 22 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 309921 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3141 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 164 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 124304 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 434225 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 434225 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency 12396913500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 125650000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 6563500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5007569500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17404483000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17404483000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 838548000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1423652498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 2262200498 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.240218 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.339841 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.162042 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 4.802752 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.763441 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.179856 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.585078 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 1.204566 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::0 0.288978 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.427744 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.288978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.427744 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40000.237157 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40003.183699 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40021.341463 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40284.862112 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40081.715700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40081.715700 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 41701 # number of replacements +system.iocache.tagsinuse 0.379408 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.warmup_cycle 1709327692000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.379408 # Average occupied blocks per context +system.iocache.occ_percent::1 0.023713 # Average percentage of cache occupancy +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.ReadReq_misses::1 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41731 # number of demand (read+write) misses +system.iocache.demand_misses::total 41731 # number of demand (read+write) misses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41731 # number of overall misses +system.iocache.overall_misses::total 41731 # number of overall misses +system.iocache.ReadReq_miss_latency 20617998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5720950806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5741568804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5741568804 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41731 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41731 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115184.346369 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137681.719436 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137585.219717 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137585.219717 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64667028 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6183.498566 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 41522 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.ReadReq_mshr_misses 179 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses 41731 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 41731 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.ReadReq_mshr_miss_latency 11309998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560091958 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571401956 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571401956 # number of overall MSHR miss cycles +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency 63184.346369 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85677.992828 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85581.509094 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85581.509094 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu0.dtb.fetch_hits 0 # ITB hits +system.cpu0.dtb.fetch_misses 0 # ITB misses +system.cpu0.dtb.fetch_acv 0 # ITB acv +system.cpu0.dtb.fetch_accesses 0 # ITB accesses +system.cpu0.dtb.read_hits 6880123 # DTB read hits +system.cpu0.dtb.read_misses 27029 # DTB read misses +system.cpu0.dtb.read_acv 463 # DTB read access violations +system.cpu0.dtb.read_accesses 649764 # DTB read accesses +system.cpu0.dtb.write_hits 4434059 # DTB write hits +system.cpu0.dtb.write_misses 4980 # DTB write misses +system.cpu0.dtb.write_acv 206 # DTB write access violations +system.cpu0.dtb.write_accesses 207730 # DTB write accesses +system.cpu0.dtb.data_hits 11314182 # DTB hits +system.cpu0.dtb.data_misses 32009 # DTB misses +system.cpu0.dtb.data_acv 669 # DTB access violations +system.cpu0.dtb.data_accesses 857494 # DTB accesses +system.cpu0.itb.fetch_hits 880445 # ITB hits +system.cpu0.itb.fetch_misses 30276 # ITB misses +system.cpu0.itb.fetch_acv 796 # ITB acv +system.cpu0.itb.fetch_accesses 910721 # ITB accesses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.read_acv 0 # DTB read access violations +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.write_acv 0 # DTB write access violations +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.data_hits 0 # DTB hits +system.cpu0.itb.data_misses 0 # DTB misses +system.cpu0.itb.data_acv 0 # DTB access violations +system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.numCycles 86706401 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.BPredUnit.lookups 9688854 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 8181343 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 315076 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8774584 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 4716459 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 5478793 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 10568954 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 28086 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 455851 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 9912652 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 11764241 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 785162 # Number of times the RAS was used to get a target. -system.cpu0.commit.branchMispredicts 606344 # The number of times a branch was mispredicted -system.cpu0.commit.branches 7026012 # Number of branches committed -system.cpu0.commit.bw_lim_events 938799 # number cycles where commit BW limit reached -system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.commitCommittedInsts 47025846 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 585526 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 5969393 # The number of squashed insts skipped by commit -system.cpu0.commit.committed_per_cycle::samples 72953049 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.644604 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.459058 # Number of insts commited each cycle +system.cpu0.BPredUnit.usedRAS 623303 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 24682 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 18567041 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 50425492 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 9688854 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5339762 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 9915303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1544367 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 26514797 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 7883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 184619 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 223130 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6371925 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 198240 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 56424843 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.893675 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.198082 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 46509540 82.43% 82.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 722585 1.28% 83.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1421448 2.52% 86.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 628845 1.11% 87.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2255580 4.00% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 483816 0.86% 92.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 510012 0.90% 93.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 672132 1.19% 94.29% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3220885 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 56424843 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.111743 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.581566 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19801968 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 25882509 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8989466 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 763548 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 987351 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 383922 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 24849 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 49347154 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 75527 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 987351 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 20629203 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 9499998 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13447452 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8452255 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3408582 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 46738624 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3619 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 624032 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1191344 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 31596053 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 57298293 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 57042075 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 256218 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 26711174 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4884879 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1120422 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 175328 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8812934 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7283662 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4733758 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1431112 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1440543 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 41212860 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1406639 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 39893176 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 57069 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5631702 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3133217 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 960480 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 56424843 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.707014 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.300043 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 37805881 67.00% 67.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8674612 15.37% 82.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4282035 7.59% 89.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2440705 4.33% 94.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1659937 2.94% 97.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 878759 1.56% 98.79% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 516481 0.92% 99.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 131514 0.23% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 34919 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 56424843 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 44960 12.13% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 207193 55.91% 68.04% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 118450 31.96% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.FU_type_0::No_OpClass 4482 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 27545306 69.05% 69.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42376 0.11% 69.17% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.17% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14767 0.04% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 2231 0.01% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7173118 17.98% 87.19% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4487292 11.25% 98.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 623604 1.56% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 39893176 # Type of FU issued +system.cpu0.iq.rate 0.460095 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 370605 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.009290 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 136270898 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 48090698 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38918381 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 367971 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 179542 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 176099 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 40067792 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 191507 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 416583 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 1090641 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 12429 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20965 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 441226 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 12240 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 165915 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 987351 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6354184 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 491419 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 45032066 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 578341 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7283662 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 4733758 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1245675 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 448555 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 7135 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20965 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 225122 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 243860 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 468982 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 39459085 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 6924497 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 434091 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 2412567 # number of nop insts executed +system.cpu0.iew.exec_refs 11372805 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6223343 # Number of branches executed +system.cpu0.iew.exec_stores 4448308 # Number of stores executed +system.cpu0.iew.exec_rate 0.455088 # Inst execution rate +system.cpu0.iew.wb_sent 39184807 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 39094480 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 19569580 # num instructions producing a value +system.cpu0.iew.wb_consumers 25865337 # num instructions consuming a value +system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.wb_rate 0.450883 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.756595 # average fanout of values written-back +system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.commit.commitCommittedInsts 38900399 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6019570 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 446159 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 429799 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 55437492 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.701698 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560671 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 53597246 73.47% 73.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8417746 11.54% 85.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4840163 6.63% 91.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2111570 2.89% 94.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1587453 2.18% 96.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575078 0.79% 97.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 337488 0.46% 97.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 547506 0.75% 98.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 938799 1.29% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 40051862 72.25% 72.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6559971 11.83% 84.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3806221 6.87% 90.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1668838 3.01% 93.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1194660 2.15% 96.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 396856 0.72% 96.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 307618 0.55% 97.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 498884 0.90% 98.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 952582 1.72% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 72953049 # Number of insts commited each cycle -system.cpu0.commit.count 47025846 # Number of instructions committed -system.cpu0.commit.fp_insts 287589 # Number of committed floating point instructions. -system.cpu0.commit.function_calls 606692 # Number of function calls committed. -system.cpu0.commit.int_insts 43528406 # Number of committed integer instructions. -system.cpu0.commit.loads 7569996 # Number of loads committed -system.cpu0.commit.membars 198353 # Number of memory barriers committed -system.cpu0.commit.refs 12959088 # Number of memory references committed +system.cpu0.commit.committed_per_cycle::total 55437492 # Number of insts commited each cycle +system.cpu0.commit.count 38900399 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.committedInsts 44336308 # Number of Instructions Simulated -system.cpu0.committedInsts_total 44336308 # Number of Instructions Simulated -system.cpu0.cpi 2.365714 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.365714 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 187921 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 187921 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 13445.030972 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10250.543228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 169356 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 169356 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 249607000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.098792 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 18565 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18565 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3378 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 155675000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.080816 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 15187 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 7569121 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7569121 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 24067.489407 # average ReadReq miss latency +system.cpu0.commit.refs 10485553 # Number of memory references committed +system.cpu0.commit.loads 6193021 # Number of loads committed +system.cpu0.commit.membars 147117 # Number of memory barriers committed +system.cpu0.commit.branches 5834794 # Number of branches committed +system.cpu0.commit.fp_insts 173443 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 36122415 # Number of committed integer instructions. +system.cpu0.commit.function_calls 477666 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 952582 # number cycles where commit BW limit reached +system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.rob.rob_reads 99224913 # The number of ROB reads +system.cpu0.rob.rob_writes 90827622 # The number of ROB writes +system.cpu0.timesIdled 838575 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 30281558 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 36751342 # Number of Instructions Simulated +system.cpu0.committedInsts_total 36751342 # Number of Instructions Simulated +system.cpu0.cpi 2.359272 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.359272 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.423860 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.423860 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 52035955 # number of integer regfile reads +system.cpu0.int_regfile_writes 28508894 # number of integer regfile writes +system.cpu0.fp_regfile_reads 87486 # number of floating regfile reads +system.cpu0.fp_regfile_writes 87606 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1265189 # number of misc regfile reads +system.cpu0.misc_regfile_writes 638472 # number of misc regfile writes +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.cpu0.icache.replacements 604064 # number of replacements +system.cpu0.icache.tagsinuse 509.990240 # Cycle average of tags in use +system.cpu0.icache.total_refs 5734171 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 604576 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.484616 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 23368350000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 509.990240 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.996075 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 5734171 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5734171 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 5734171 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5734171 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 5734171 # number of overall hits +system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::total 5734171 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 637754 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 637754 # number of ReadReq misses +system.cpu0.icache.demand_misses::0 637754 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 637754 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::0 637754 # number of overall misses +system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::total 637754 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 9712599996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 9712599996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 9712599996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::0 6371925 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6371925 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::0 6371925 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6371925 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::0 6371925 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6371925 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::0 0.100088 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::0 0.100088 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::0 0.100088 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::0 15229.383110 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::0 15229.383110 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 15229.383110 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1053998 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 101 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 10435.623762 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks 253 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits 33035 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 33035 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 33035 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 604719 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 604719 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 604719 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency 7372056498 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 7372056498 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 7372056498 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.094904 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.094904 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.094904 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12190.879562 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 12190.879562 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12190.879562 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 899634 # number of replacements +system.cpu0.dcache.tagsinuse 446.158722 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8155860 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 900023 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.061835 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::0 447.158722 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.873357 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::0 5166195 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5166195 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::0 2708345 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2708345 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 133652 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 133652 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::0 151966 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 151966 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::0 7874540 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7874540 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::0 7874540 # number of overall hits +system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::total 7874540 # number of overall hits +system.cpu0.dcache.ReadReq_misses::0 1064203 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1064203 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::0 1419249 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1419249 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::0 11793 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11793 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::0 744 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 744 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::0 2483452 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2483452 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::0 2483452 # number of overall misses +system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::total 2483452 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 27896641000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 47260927840 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency 183691500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency 7368500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency 75157568840 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 75157568840 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::0 6230398 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6230398 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 4127594 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4127594 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 145445 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 145445 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 152710 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 152710 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 10357992 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10357992 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::0 10357992 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10357992 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::0 0.170808 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::0 0.343844 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.081082 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.004872 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::0 0.239762 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::0 0.239762 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::0 26213.646269 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26547.034409 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 6281230 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6281230 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 30996303000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.170151 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1287891 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1287891 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 494238 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 21069133500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.104854 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 793653 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 636739500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 196148 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 196148 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 12580.258745 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 9578.581696 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 191974 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191974 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 52510000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.021280 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 4174 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4174 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 39981000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.021280 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 4174 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5179136 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5179136 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 31904.477186 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 33299.955004 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30396.485851 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3600390 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3600390 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 50369065740 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.304828 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1578746 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1578746 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1328268 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 7613650983 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.048363 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 250478 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1111159498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8752.803276 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.840448 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 95418 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 835174983 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 12748257 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12748257 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 28383.561902 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15576.316459 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 9903.897849 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 30263.346680 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 27470.484530 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 9881620 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9881620 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 81365368740 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.224865 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2866637 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2866637 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1822506 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 28682784483 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.081904 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1044131 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_blocks::0 489.863061 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.956764 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.overall_accesses::0 12748257 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12748257 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 28383.561902 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 30263.346680 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 27470.484530 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 9881620 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 9881620 # number of overall hits -system.cpu0.dcache.overall_miss_latency 81365368740 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.224865 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2866637 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2866637 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1822506 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 28682784483 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.081904 # mshr miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 831922069 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 188000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 93842 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8865.135749 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks 419465 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 382209 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1203298 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 2986 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1585507 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1585507 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 681994 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 215951 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 8807 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 744 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 897945 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 897945 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 19802710500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 7045833069 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 103680500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 5132500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 5001 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 26848543569 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 26848543569 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 634638000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1036991998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 1671629998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109462 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.052319 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.060552 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.004872 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.086691 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.086691 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1044131 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1747898998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1041325 # number of replacements -system.cpu0.dcache.sampled_refs 1041715 # Sample count of references to valid blocks. +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 29036.487858 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 32626.999037 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11772.510503 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 6898.521505 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 29899.986713 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 29899.986713 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 488.863062 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10250942 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 532971 # number of writebacks -system.cpu0.decode.BlockedCycles 30335443 # Number of cycles decode is blocked -system.cpu0.decode.BranchMispred 32433 # Number of times decode detected a branch misprediction -system.cpu0.decode.BranchResolved 467445 # Number of times decode resolved a branch -system.cpu0.decode.DecodedInsts 58302731 # Number of instructions handled by decode -system.cpu0.decode.IdleCycles 31236137 # Number of cycles decode is idle -system.cpu0.decode.RunCycles 10506640 # Number of cycles decode is running -system.cpu0.decode.SquashCycles 1085015 # Number of cycles decode is squashing -system.cpu0.decode.SquashedInsts 96992 # Number of squashed instructions handled by decode -system.cpu0.decode.UnblockCycles 874828 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 755162 # DTB accesses -system.cpu0.dtb.data_acv 768 # DTB access violations -system.cpu0.dtb.data_hits 13777358 # DTB hits -system.cpu0.dtb.data_misses 33542 # DTB misses -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 569569 # DTB read accesses -system.cpu0.dtb.read_acv 514 # DTB read access violations -system.cpu0.dtb.read_hits 8255195 # DTB read hits -system.cpu0.dtb.read_misses 26791 # DTB read misses -system.cpu0.dtb.write_accesses 185593 # DTB write accesses -system.cpu0.dtb.write_acv 254 # DTB write access violations -system.cpu0.dtb.write_hits 5522163 # DTB write hits -system.cpu0.dtb.write_misses 6751 # DTB write misses -system.cpu0.fetch.Branches 11764241 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 7276849 # Number of cache lines fetched -system.cpu0.fetch.Cycles 11546182 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 354114 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 59401999 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 28935 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 709322 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.112161 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 7276849 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 6263955 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.566343 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 74038064 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.802317 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.109343 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62491882 84.41% 84.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 859667 1.16% 85.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1580756 2.14% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 707840 0.96% 88.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2540715 3.43% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 543724 0.73% 92.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 599348 0.81% 93.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 933324 1.26% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3780808 5.11% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 74038064 # Number of instructions fetched each cycle (Total) -system.cpu0.fp_regfile_reads 141418 # number of floating regfile reads -system.cpu0.fp_regfile_writes 143630 # number of floating regfile writes -system.cpu0.icache.ReadReq_accesses::0 7276849 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7276849 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 14969.786485 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11880.005982 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 6407354 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6407354 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 13016154500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.119488 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 869495 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 869495 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 30374 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 9968762500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.115314 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 839121 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11944.444444 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 7.637231 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 36 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 430000 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 7276849 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7276849 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 14969.786485 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11880.005982 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 6407354 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6407354 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 13016154500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.119488 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 869495 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 869495 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 30374 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 9968762500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.115314 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 839121 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_blocks::0 509.875783 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.995851 # Average percentage of cache occupancy -system.cpu0.icache.overall_accesses::0 7276849 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7276849 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 14969.786485 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11880.005982 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 6407354 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6407354 # number of overall hits -system.cpu0.icache.overall_miss_latency 13016154500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.119488 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 869495 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 869495 # number of overall misses -system.cpu0.icache.overall_mshr_hits 30374 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 9968762500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.115314 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 839121 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 838452 # number of replacements -system.cpu0.icache.sampled_refs 838963 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.875783 # Cycle average of tags in use -system.cpu0.icache.total_refs 6407354 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 23816238000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 147 # number of writebacks -system.cpu0.idleCycles 30848962 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.branchMispredicts 654991 # Number of branch mispredicts detected at execute -system.cpu0.iew.exec_branches 7463719 # Number of branches executed -system.cpu0.iew.exec_nop 2952874 # number of nop insts executed -system.cpu0.iew.exec_rate 0.449724 # Inst execution rate -system.cpu0.iew.exec_refs 13848442 # number of memory reference insts executed -system.cpu0.iew.exec_stores 5542976 # Number of stores executed -system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.iewBlockCycles 7417251 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 8574378 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1551984 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 727686 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5707393 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 53103916 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 8305466 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 392048 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 47170169 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 90492 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 5675 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1085015 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 526785 # Number of cycles IEW is unblocking -system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.cacheBlocked 157871 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread0.forwLoads 427137 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread0.ignoredResponses 7542 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread0.memOrderViolation 14768 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.rescheduledLoads 12869 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.squashedLoads 1004382 # Number of loads squashed -system.cpu0.iew.lsq.thread0.squashedStores 318301 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 14768 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 331464 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 323527 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.wb_consumers 29600256 # num instructions consuming a value -system.cpu0.iew.wb_count 46794498 # cumulative count of insts written-back -system.cpu0.iew.wb_fanout 0.755402 # average fanout of values written-back -system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.wb_producers 22360092 # num instructions producing a value -system.cpu0.iew.wb_rate 0.446142 # insts written-back per cycle -system.cpu0.iew.wb_sent 46875004 # cumulative count of insts sent to commit -system.cpu0.int_regfile_reads 61873527 # number of integer regfile reads -system.cpu0.int_regfile_writes 33807346 # number of integer regfile writes -system.cpu0.ipc 0.422705 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.422705 # IPC: Total IPC of All Threads -system.cpu0.iq.FU_type_0::No_OpClass 3310 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 32518161 68.37% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 52150 0.11% 68.49% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15557 0.03% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1653 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8591465 18.06% 86.59% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5582440 11.74% 98.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 797481 1.68% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 47562217 # Type of FU issued -system.cpu0.iq.fp_alu_accesses 318343 # Number of floating point alu accesses -system.cpu0.iq.fp_inst_queue_reads 608219 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_wakeup_accesses 289004 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_writes 292979 # Number of floating instruction queue writes -system.cpu0.iq.fu_busy_cnt 465945 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.009797 # FU busy rate (busy events/executed inst) -system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 32168 6.90% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 239318 51.36% 58.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 194459 41.73% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.int_alu_accesses 47706509 # Number of integer alu accesses -system.cpu0.iq.int_inst_queue_reads 169046393 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_wakeup_accesses 46505494 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.int_inst_queue_writes 55364625 # Number of integer instruction queue writes -system.cpu0.iq.iqInstsAdded 48386629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 47562217 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1764413 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 5493402 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 26169 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1178887 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 2580822 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.issued_per_cycle::samples 74038064 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.642402 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.245120 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 51535584 69.61% 69.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10789742 14.57% 84.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4855288 6.56% 90.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3076859 4.16% 94.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2068166 2.79% 97.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 951116 1.28% 98.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 576531 0.78% 99.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 134332 0.18% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 50446 0.07% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 74038064 # Number of insts issued each cycle -system.cpu0.iq.rate 0.453461 # Inst issue rate -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 933233 # ITB accesses -system.cpu0.itb.fetch_acv 717 # ITB acv -system.cpu0.itb.fetch_hits 905545 # ITB hits -system.cpu0.itb.fetch_misses 27688 # ITB misses -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 371 0.22% 0.22% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3671 2.19% 2.42% # number of callpals executed -system.cpu0.kern.callpal::tbi 42 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 151594 90.58% 93.02% # number of callpals executed -system.cpu0.kern.callpal::rdps 6330 3.78% 96.81% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::wrusp 2 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::rti 4884 2.92% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 315 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 135 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167365 # number of callpals executed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 180838 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 63498 39.95% 39.95% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 238 0.15% 40.10% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.21% 41.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 288 0.18% 41.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92981 58.50% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 158931 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 62140 49.14% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 238 0.19% 49.33% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.52% 50.86% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 288 0.23% 51.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 61852 48.92% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 126444 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864722249000 98.07% 98.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96095500 0.01% 98.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 397148000 0.02% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 112025000 0.01% 98.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 36054288500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901381806000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.978613 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.665211 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1076 -system.cpu0.kern.mode_good::user 1076 -system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 7211 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1076 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.149216 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899282367000 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1748332500 0.09% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3672 # number of times the context was actually changed -system.cpu0.kern.syscall::2 6 3.17% 3.17% # number of syscalls executed -system.cpu0.kern.syscall::3 16 8.47% 11.64% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.59% 13.23% # number of syscalls executed -system.cpu0.kern.syscall::6 26 13.76% 26.98% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.53% 27.51% # number of syscalls executed -system.cpu0.kern.syscall::17 8 4.23% 31.75% # number of syscalls executed -system.cpu0.kern.syscall::19 6 3.17% 34.92% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.12% 37.04% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.53% 37.57% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.59% 39.15% # number of syscalls executed -system.cpu0.kern.syscall::33 6 3.17% 42.33% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.06% 43.39% # number of syscalls executed -system.cpu0.kern.syscall::45 33 17.46% 60.85% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.59% 62.43% # number of syscalls executed -system.cpu0.kern.syscall::48 7 3.70% 66.14% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.76% 70.90% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.53% 71.43% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.65% 74.07% # number of syscalls executed -system.cpu0.kern.syscall::71 23 12.17% 86.24% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.59% 87.83% # number of syscalls executed -system.cpu0.kern.syscall::74 6 3.17% 91.01% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.53% 91.53% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.53% 92.06% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.70% 95.77% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.06% 96.83% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.06% 97.88% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.53% 98.41% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.53% 98.94% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.06% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 189 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 1239149 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1190008 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 8574378 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5707393 # Number of stores inserted to the mem dependence unit. -system.cpu0.misc_regfile_reads 1734015 # number of misc regfile reads -system.cpu0.misc_regfile_writes 822223 # number of misc regfile writes -system.cpu0.numCycles 104887026 # number of cpu cycles simulated -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.rename.BlockCycles 10226952 # Number of cycles rename is blocking -system.cpu0.rename.CommittedMaps 32010277 # Number of HB maps that are committed -system.cpu0.rename.IQFullEvents 742771 # Number of times rename has blocked due to IQ full -system.cpu0.rename.IdleCycles 32554760 # Number of cycles rename is idle -system.cpu0.rename.LSQFullEvents 1133948 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RenameLookups 67011150 # Number of register rename lookups that rename has made -system.cpu0.rename.RenamedInsts 55116446 # Number of instructions processed by rename -system.cpu0.rename.RenamedOperands 36911598 # Number of destination operands rename has renamed -system.cpu0.rename.RunCycles 10340148 # Number of cycles rename is running -system.cpu0.rename.SquashCycles 1085015 # Number of cycles rename is squashing -system.cpu0.rename.UnblockCycles 3374476 # Number of cycles rename is unblocking -system.cpu0.rename.UndoneMaps 4901321 # Number of HB maps that are undone due to squashing -system.cpu0.rename.fp_rename_lookups 420638 # Number of floating rename lookups -system.cpu0.rename.int_rename_lookups 66590512 # Number of integer rename lookups -system.cpu0.rename.serializeStallCycles 16456711 # count of cycles rename stalled for serializing inst -system.cpu0.rename.serializingInsts 1432211 # count of serializing insts renamed -system.cpu0.rename.skidInsts 8924178 # count of insts added to the skid buffer -system.cpu0.rename.tempSerializingInsts 217463 # count of temporary serializing insts renamed -system.cpu0.rob.rob_reads 124831913 # The number of ROB reads -system.cpu0.rob.rob_writes 107074537 # The number of ROB writes -system.cpu0.timesIdled 1083848 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dtb.fetch_hits 0 # ITB hits +system.cpu1.dtb.fetch_misses 0 # ITB misses +system.cpu1.dtb.fetch_acv 0 # ITB acv +system.cpu1.dtb.fetch_accesses 0 # ITB accesses +system.cpu1.dtb.read_hits 4024884 # DTB read hits +system.cpu1.dtb.read_misses 17321 # DTB read misses +system.cpu1.dtb.read_acv 119 # DTB read access violations +system.cpu1.dtb.read_accesses 318700 # DTB read accesses +system.cpu1.dtb.write_hits 2545920 # DTB write hits +system.cpu1.dtb.write_misses 4459 # DTB write misses +system.cpu1.dtb.write_acv 131 # DTB write access violations +system.cpu1.dtb.write_accesses 133305 # DTB write accesses +system.cpu1.dtb.data_hits 6570804 # DTB hits +system.cpu1.dtb.data_misses 21780 # DTB misses +system.cpu1.dtb.data_acv 250 # DTB access violations +system.cpu1.dtb.data_accesses 452005 # DTB accesses +system.cpu1.itb.fetch_hits 565000 # ITB hits +system.cpu1.itb.fetch_misses 8360 # ITB misses +system.cpu1.itb.fetch_acv 355 # ITB acv +system.cpu1.itb.fetch_accesses 573360 # ITB accesses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.read_acv 0 # DTB read access violations +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.write_acv 0 # DTB write access violations +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.data_hits 0 # DTB hits +system.cpu1.itb.data_misses 0 # DTB misses +system.cpu1.itb.data_acv 0 # DTB access violations +system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.numCycles 36324508 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.BPredUnit.lookups 5837794 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 4807752 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 236405 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 5114419 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 2355373 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1509705 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 3127444 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 7361 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 156935 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 2982175 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 3622579 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 265553 # Number of times the RAS was used to get a target. -system.cpu1.commit.branchMispredicts 207236 # The number of times a branch was mispredicted -system.cpu1.commit.branches 2030517 # Number of branches committed -system.cpu1.commit.bw_lim_events 301379 # number cycles where commit BW limit reached -system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.commitCommittedInsts 13448285 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 143621 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 2329974 # The number of squashed insts skipped by commit -system.cpu1.commit.committed_per_cycle::samples 21012360 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.640018 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.474919 # Number of insts commited each cycle +system.cpu1.BPredUnit.usedRAS 425756 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 18870 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 12975380 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 28382917 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 5837794 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2781129 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 5303525 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 1029370 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 12998724 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 3277 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 80064 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 157005 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 3308770 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 142735 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 32191429 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.881692 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.232987 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 26887904 83.53% 83.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 353233 1.10% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 711039 2.21% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 413904 1.29% 88.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 842441 2.62% 90.73% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 260322 0.81% 91.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 338125 1.05% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 409918 1.27% 93.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1974543 6.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 32191429 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.160712 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.781371 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 12951837 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 13394594 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 4901613 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 288063 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 655321 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 259847 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 18216 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 27639459 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 54136 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 655321 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13441589 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3341745 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 8668513 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 4556322 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1527937 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 25800670 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 384 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 324513 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 337358 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 16998396 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 30868000 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 30637033 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 230967 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 13782341 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 3216047 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 763704 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 85939 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4786247 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4278315 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2704053 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 527948 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 347634 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 22339353 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 928348 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 21581640 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 44138 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3694956 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1842331 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 660792 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 32191429 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.670416 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.349411 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 23032002 71.55% 71.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 3880534 12.05% 83.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1841751 5.72% 89.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1343655 4.17% 93.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 1100926 3.42% 96.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 572017 1.78% 98.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 269219 0.84% 99.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 103064 0.32% 99.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 48261 0.15% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 32191429 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 27325 8.19% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.19% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 173483 52.02% 60.21% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 132688 39.79% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 2823 0.01% 0.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 14285140 66.19% 66.20% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 29916 0.14% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11006 0.05% 66.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1411 0.01% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4218514 19.55% 85.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 2587729 11.99% 97.94% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 445101 2.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 21581640 # Type of FU issued +system.cpu1.iq.rate 0.594134 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 333496 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.015453 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 75401338 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 26810016 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20892220 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 331004 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 159326 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 156915 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 21738437 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 173876 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 181996 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 722762 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 9242 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 8212 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 265030 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 7445 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 45661 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 655321 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2533054 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 130038 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 24654122 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 348083 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 4278315 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 2704053 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 831283 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 42195 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6811 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 8212 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 170867 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 176891 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 347758 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 21288201 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4056224 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 293438 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 1386421 # number of nop insts executed +system.cpu1.iew.exec_refs 6615012 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3371082 # Number of branches executed +system.cpu1.iew.exec_stores 2558788 # Number of stores executed +system.cpu1.iew.exec_rate 0.586056 # Inst execution rate +system.cpu1.iew.wb_sent 21107487 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 21049135 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10120752 # num instructions producing a value +system.cpu1.iew.wb_consumers 14228146 # num instructions consuming a value +system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.wb_rate 0.579475 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.711319 # average fanout of values written-back +system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.commit.commitCommittedInsts 20574037 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 4003646 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 267556 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 316871 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 31536108 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.652396 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.582786 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 15563519 74.07% 74.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2436778 11.60% 85.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1200178 5.71% 91.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 640529 3.05% 94.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 421093 2.00% 96.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 209093 1.00% 97.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 129842 0.62% 98.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 109949 0.52% 98.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 301379 1.43% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 23929669 75.88% 75.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 3216209 10.20% 86.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1611477 5.11% 91.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 871112 2.76% 93.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 572339 1.81% 95.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 274054 0.87% 96.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 208667 0.66% 97.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 210738 0.67% 97.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 641843 2.04% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 21012360 # Number of insts commited each cycle -system.cpu1.commit.count 13448285 # Number of instructions committed -system.cpu1.commit.fp_insts 77652 # Number of committed floating point instructions. -system.cpu1.commit.function_calls 196980 # Number of function calls committed. -system.cpu1.commit.int_insts 12472477 # Number of committed integer instructions. -system.cpu1.commit.loads 2329401 # Number of loads committed -system.cpu1.commit.membars 46552 # Number of memory barriers committed -system.cpu1.commit.refs 3759357 # Number of memory references committed +system.cpu1.commit.committed_per_cycle::total 31536108 # Number of insts commited each cycle +system.cpu1.commit.count 20574037 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.committedInsts 12744286 # Number of Instructions Simulated -system.cpu1.committedInsts_total 12744286 # Number of Instructions Simulated -system.cpu1.cpi 1.922547 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.922547 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 34084 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 34084 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 12032.319953 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7746.929907 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 27308 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 27308 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 81531000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.198803 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 6776 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 6776 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 1483 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 41004500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.155293 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 5293 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 2478047 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2478047 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15160.837325 # average ReadReq miss latency +system.cpu1.commit.refs 5994576 # Number of memory references committed +system.cpu1.commit.loads 3555553 # Number of loads committed +system.cpu1.commit.membars 91088 # Number of memory barriers committed +system.cpu1.commit.branches 3081632 # Number of branches committed +system.cpu1.commit.fp_insts 155618 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 18958031 # Number of committed integer instructions. +system.cpu1.commit.function_calls 316244 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 641843 # number cycles where commit BW limit reached +system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.rob.rob_reads 55370614 # The number of ROB reads +system.cpu1.rob.rob_writes 49810796 # The number of ROB writes +system.cpu1.timesIdled 461933 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4133079 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 19384686 # Number of Instructions Simulated +system.cpu1.committedInsts_total 19384686 # Number of Instructions Simulated +system.cpu1.cpi 1.873877 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.873877 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.533653 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.533653 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 27536671 # number of integer regfile reads +system.cpu1.int_regfile_writes 15012037 # number of integer regfile writes +system.cpu1.fp_regfile_reads 81305 # number of floating regfile reads +system.cpu1.fp_regfile_writes 82180 # number of floating regfile writes +system.cpu1.misc_regfile_reads 884105 # number of misc regfile reads +system.cpu1.misc_regfile_writes 384773 # number of misc regfile writes +system.cpu1.icache.replacements 474445 # number of replacements +system.cpu1.icache.tagsinuse 505.356684 # Cycle average of tags in use +system.cpu1.icache.total_refs 2809266 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 474955 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.914805 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 46541421000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 505.356684 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.987025 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::0 2809266 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2809266 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 2809266 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2809266 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 2809266 # number of overall hits +system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::total 2809266 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 499504 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 499504 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 499504 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 499504 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 499504 # number of overall misses +system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::total 499504 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7358434998 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7358434998 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7358434998 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 3308770 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 3308770 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 3308770 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 3308770 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 3308770 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 3308770 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.150964 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.150964 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::0 0.150964 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::0 14731.483628 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::0 14731.483628 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 14731.483628 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 428499 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 44 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 9738.613636 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks 33 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 24498 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 24498 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 24498 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 475006 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 475006 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 475006 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency 5595943999 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5595943999 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5595943999 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.143560 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.143560 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.143560 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11780.785925 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11780.785925 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11780.785925 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.replacements 557180 # number of replacements +system.cpu1.dcache.tagsinuse 488.553100 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4834021 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 557692 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 8.667905 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 34444090000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 488.553100 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.954205 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 2945256 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2945256 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 1749855 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1749855 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 63493 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 63493 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 71374 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71374 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 4695111 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4695111 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 4695111 # number of overall hits +system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::total 4695111 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 787154 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 787154 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 609216 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 609216 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 13718 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13718 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 830 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 830 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 1396370 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1396370 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 1396370 # number of overall misses +system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::total 1396370 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 11151181000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 13606670637 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 199877000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 10316000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 24757851637 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 24757851637 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 3732410 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3732410 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 2359071 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2359071 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 77211 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 77211 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 72204 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 72204 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 6091481 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6091481 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 6091481 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6091481 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.210897 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.258244 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.177669 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.011495 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.229233 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::0 0.229233 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::0 14166.454086 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12203.806584 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 2047581 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2047581 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 6526225000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.173712 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 430466 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 430466 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 150924 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 3411476500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.112807 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 279542 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 299904000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 32610 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32610 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13453.081410 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10450.798884 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 28667 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 28667 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 53045500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.120914 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 3943 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3943 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 41207500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.120914 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 3943 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 1389552 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1389552 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 29195.465224 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 22334.723049 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26358.387662 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1086825 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1086825 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 8838255601 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.217859 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 302727 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 302727 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 250029 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1389034313 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.037924 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 52698 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 600087500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12134.424364 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 11000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 9.983135 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 9506 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 115349838 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 11000 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 3867599 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3867599 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 20955.574591 # average overall miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14570.418428 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12428.915663 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 17730.151491 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14448.924913 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 3134406 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3134406 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 15364480601 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.189573 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 733193 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 733193 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 400953 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 4800510813 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.085903 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 332240 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_blocks::0 478.607338 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.934780 # Average percentage of cache occupancy -system.cpu1.dcache.overall_accesses::0 3867599 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3867599 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 20955.574591 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 17730.151491 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14448.924913 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 3134406 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 3134406 # number of overall hits -system.cpu1.dcache.overall_miss_latency 15364480601 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.189573 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 733193 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 733193 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 400953 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 4800510813 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.085903 # mshr miss rate for overall accesses +system.cpu1.dcache.blocked_cycles::no_mshrs 143111212 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 13232 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10815.538996 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks 434743 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 338033 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 504690 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 2893 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 842723 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 842723 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 449121 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 104526 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 10825 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 830 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 553647 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 553647 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 5367032500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 2133420198 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 121712000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 7814500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 7500452698 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 7500452698 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 301848000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 539476500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 841324500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.120330 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.044308 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.140200 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.011495 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.090889 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.090889 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 332240 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 899991500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 320146 # number of replacements -system.cpu1.dcache.sampled_refs 320658 # Sample count of references to valid blocks. +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11950.081381 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 20410.426095 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11243.602771 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9415.060241 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 13547.355441 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 13547.355441 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 478.607338 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3201172 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 38945924000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 258747 # number of writebacks -system.cpu1.decode.BlockedCycles 8810954 # Number of cycles decode is blocked -system.cpu1.decode.BranchMispred 10399 # Number of times decode detected a branch misprediction -system.cpu1.decode.BranchResolved 165542 # Number of times decode resolved a branch -system.cpu1.decode.DecodedInsts 17654641 # Number of instructions handled by decode -system.cpu1.decode.IdleCycles 8825966 # Number of cycles decode is idle -system.cpu1.decode.RunCycles 3267842 # Number of cycles decode is running -system.cpu1.decode.SquashCycles 401676 # Number of cycles decode is squashing -system.cpu1.decode.SquashedInsts 25654 # Number of squashed instructions handled by decode -system.cpu1.decode.UnblockCycles 107597 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 513633 # DTB accesses -system.cpu1.dtb.data_acv 185 # DTB access violations -system.cpu1.dtb.data_hits 4112878 # DTB hits -system.cpu1.dtb.data_misses 16265 # DTB misses -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 363334 # DTB read accesses -system.cpu1.dtb.read_acv 74 # DTB read access violations -system.cpu1.dtb.read_hits 2619291 # DTB read hits -system.cpu1.dtb.read_misses 12612 # DTB read misses -system.cpu1.dtb.write_accesses 150299 # DTB write accesses -system.cpu1.dtb.write_acv 111 # DTB write access violations -system.cpu1.dtb.write_hits 1493587 # DTB write hits -system.cpu1.dtb.write_misses 3653 # DTB write misses -system.cpu1.fetch.Branches 3622579 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 2099932 # Number of cache lines fetched -system.cpu1.fetch.Cycles 3426887 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 116518 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 18019858 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 11061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 232369 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.147851 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 2099931 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 1775258 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.735460 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 21414036 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.841498 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.178120 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 17987149 84.00% 84.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 213365 1.00% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 513318 2.40% 87.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 281609 1.32% 88.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 570957 2.67% 91.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 173244 0.81% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 240049 1.12% 93.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 130072 0.61% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1304273 6.09% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 21414036 # Number of instructions fetched each cycle (Total) -system.cpu1.fp_regfile_reads 44611 # number of floating regfile reads -system.cpu1.fp_regfile_writes 43862 # number of floating regfile writes -system.cpu1.icache.ReadReq_accesses::0 2099932 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2099932 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 15131.623612 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12110.189366 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 1856598 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1856598 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 3682038500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.115877 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 243334 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 243334 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 9659 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 2829848500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.111277 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 233675 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 10681.818182 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 7.947119 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 22 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 235000 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 2099932 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2099932 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 15131.623612 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12110.189366 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 1856598 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1856598 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 3682038500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.115877 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 243334 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 243334 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 9659 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 2829848500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.111277 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 233675 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_blocks::0 501.781584 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.980042 # Average percentage of cache occupancy -system.cpu1.icache.overall_accesses::0 2099932 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2099932 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 15131.623612 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12110.189366 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 1856598 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1856598 # number of overall hits -system.cpu1.icache.overall_miss_latency 3682038500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.115877 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 243334 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 243334 # number of overall misses -system.cpu1.icache.overall_mshr_hits 9659 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 2829848500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.111277 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 233675 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 233107 # number of replacements -system.cpu1.icache.sampled_refs 233619 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 501.781584 # Cycle average of tags in use -system.cpu1.icache.total_refs 1856598 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1710247615000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 27 # number of writebacks -system.cpu1.idleCycles 3087450 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.branchMispredicts 229368 # Number of branch mispredicts detected at execute -system.cpu1.iew.exec_branches 2215124 # Number of branches executed -system.cpu1.iew.exec_nop 807214 # number of nop insts executed -system.cpu1.iew.exec_rate 0.568172 # Inst execution rate -system.cpu1.iew.exec_refs 4143059 # number of memory reference insts executed -system.cpu1.iew.exec_stores 1503378 # Number of stores executed -system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.iewBlockCycles 1971298 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 2745592 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 455487 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 238559 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 1578351 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 15868399 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 2639681 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 166261 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 13921060 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 10672 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 5665 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 401676 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 76714 # Number of cycles IEW is unblocking -system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.cacheBlocked 25188 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread0.forwLoads 88996 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread0.ignoredResponses 4435 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread0.memOrderViolation 4299 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.rescheduledLoads 5923 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.squashedLoads 416191 # Number of loads squashed -system.cpu1.iew.lsq.thread0.squashedStores 148395 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 4299 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 105547 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 123821 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.wb_consumers 9185033 # num instructions consuming a value -system.cpu1.iew.wb_count 13765716 # cumulative count of insts written-back -system.cpu1.iew.wb_fanout 0.723664 # average fanout of values written-back -system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.wb_producers 6646874 # num instructions producing a value -system.cpu1.iew.wb_rate 0.561832 # insts written-back per cycle -system.cpu1.iew.wb_sent 13802747 # cumulative count of insts sent to commit -system.cpu1.int_regfile_reads 18282773 # number of integer regfile reads -system.cpu1.int_regfile_writes 9947337 # number of integer regfile writes -system.cpu1.ipc 0.520143 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.520143 # IPC: Total IPC of All Threads -system.cpu1.iq.FU_type_0::No_OpClass 3979 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 9510353 67.51% 67.54% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 21826 0.15% 67.69% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11300 0.08% 67.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1989 0.01% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2724274 19.34% 87.13% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1523321 10.81% 97.94% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 290281 2.06% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 14087323 # Type of FU issued -system.cpu1.iq.fp_alu_accesses 84267 # Number of floating point alu accesses -system.cpu1.iq.fp_inst_queue_reads 163543 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_wakeup_accesses 78913 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_writes 80927 # Number of floating instruction queue writes -system.cpu1.iq.fu_busy_cnt 199599 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014169 # FU busy rate (busy events/executed inst) -system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 10735 5.38% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 110682 55.45% 60.83% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 78182 39.17% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.int_alu_accesses 14198676 # Number of integer alu accesses -system.cpu1.iq.int_inst_queue_reads 49640351 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_wakeup_accesses 13686803 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.int_inst_queue_writes 17182956 # Number of integer instruction queue writes -system.cpu1.iq.iqInstsAdded 14556864 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 14087323 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 504321 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 2199611 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 15615 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 360700 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1165068 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.issued_per_cycle::samples 21414036 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.657855 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.314285 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 15246065 71.20% 71.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2762432 12.90% 84.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1149877 5.37% 89.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 942390 4.40% 93.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 699267 3.27% 97.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 379191 1.77% 98.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 160390 0.75% 99.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 52788 0.25% 99.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 21636 0.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 21414036 # Number of insts issued each cycle -system.cpu1.iq.rate 0.574958 # Inst issue rate -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 456053 # ITB accesses -system.cpu1.itb.fetch_acv 249 # ITB acv -system.cpu1.itb.fetch_hits 445822 # ITB hits -system.cpu1.itb.fetch_misses 10231 # ITB misses -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 288 0.55% 0.56% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.56% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.56% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1111 2.14% 2.70% # number of callpals executed -system.cpu1.kern.callpal::tbi 11 0.02% 2.72% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.73% # number of callpals executed -system.cpu1.kern.callpal::swpipl 44860 86.39% 89.12% # number of callpals executed -system.cpu1.kern.callpal::rdps 2426 4.67% 93.79% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.79% # number of callpals executed -system.cpu1.kern.callpal::wrusp 5 0.01% 93.80% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 93.81% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.81% # number of callpals executed -system.cpu1.kern.callpal::rti 2967 5.71% 99.53% # number of callpals executed -system.cpu1.kern.callpal::callsys 200 0.39% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 45 0.09% 100.00% # number of callpals executed -system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 51930 # number of callpals executed +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 139328 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 46150 38.89% 38.89% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 238 0.20% 39.09% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1923 1.62% 40.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 40.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 70336 59.27% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 118663 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 45525 48.84% 48.84% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 238 0.26% 49.10% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1923 2.06% 51.16% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 45509 48.82% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 93211 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865602561500 98.27% 98.27% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91021500 0.00% 98.28% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 389859500 0.02% 98.30% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 7895500 0.00% 98.30% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 32350102500 1.70% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1898441440500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.986457 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.647023 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 5 2.39% 2.39% # number of syscalls executed +system.cpu0.kern.syscall::3 17 8.13% 10.53% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.44% 11.96% # number of syscalls executed +system.cpu0.kern.syscall::6 28 13.40% 25.36% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.48% 25.84% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.48% 26.32% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.31% 30.62% # number of syscalls executed +system.cpu0.kern.syscall::19 5 2.39% 33.01% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.91% 34.93% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.96% 35.89% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.91% 37.80% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.35% 41.15% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.96% 42.11% # number of syscalls executed +system.cpu0.kern.syscall::45 35 16.75% 58.85% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.91% 60.77% # number of syscalls executed +system.cpu0.kern.syscall::48 6 2.87% 63.64% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.31% 67.94% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.48% 68.42% # number of syscalls executed +system.cpu0.kern.syscall::59 4 1.91% 70.33% # number of syscalls executed +system.cpu0.kern.syscall::71 32 15.31% 85.65% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.44% 87.08% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.31% 91.39% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.48% 92.34% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.35% 95.69% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.96% 96.65% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.96% 97.61% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.96% 98.56% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 209 # number of syscalls executed +system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal::wripir 105 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2219 1.77% 1.85% # number of callpals executed +system.cpu0.kern.callpal::tbi 37 0.03% 1.88% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.89% # number of callpals executed +system.cpu0.kern.callpal::swpipl 112588 89.60% 91.49% # number of callpals executed +system.cpu0.kern.callpal::rdps 6309 5.02% 96.51% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.51% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.52% # number of callpals executed +system.cpu0.kern.callpal::rdusp 6 0.00% 96.52% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.52% # number of callpals executed +system.cpu0.kern.callpal::rti 3897 3.10% 99.62% # number of callpals executed +system.cpu0.kern.callpal::callsys 326 0.26% 99.88% # number of callpals executed +system.cpu0.kern.callpal::imb 146 0.12% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 125650 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5507 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1097 +system.cpu0.kern.mode_good::user 1097 +system.cpu0.kern.mode_good::idle 0 +system.cpu0.kern.mode_switch_good::kernel 0.199201 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1896108272000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1865257500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 2220 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 60321 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 4094 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 19374 38.65% 38.65% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.84% 42.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 371 0.74% 43.23% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28454 56.77% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 50123 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 19355 47.63% 47.63% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 4.73% 52.37% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 371 0.91% 53.28% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18984 46.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 40634 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871185338500 98.39% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 350210000 0.02% 98.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 149885000 0.01% 98.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30038792500 1.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1901724226000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999019 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3828 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 98562 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 35646 40.41% 40.41% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1921 2.18% 42.59% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 105 0.12% 42.71% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 50532 57.29% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 88204 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 34894 48.66% 48.66% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1921 2.68% 51.34% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 105 0.15% 51.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 34789 48.51% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 71709 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1866332283500 98.30% 98.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 346173000 0.02% 98.32% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 42378500 0.00% 98.32% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31930549500 1.68% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1898651384500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978904 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.667182 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 994 -system.cpu1.kern.mode_good::user 661 -system.cpu1.kern.mode_good::idle 333 -system.cpu1.kern.mode_switch::kernel 1487 # number of protection mode switches -system.cpu1.kern.mode_switch::user 661 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2593 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.668460 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used::31 0.688455 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 3 2.56% 2.56% # number of syscalls executed +system.cpu1.kern.syscall::3 13 11.11% 13.68% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.85% 14.53% # number of syscalls executed +system.cpu1.kern.syscall::6 14 11.97% 26.50% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.13% 31.62% # number of syscalls executed +system.cpu1.kern.syscall::19 5 4.27% 35.90% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.71% 37.61% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.71% 39.32% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.71% 41.03% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.42% 44.44% # number of syscalls executed +system.cpu1.kern.syscall::45 19 16.24% 60.68% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.71% 62.39% # number of syscalls executed +system.cpu1.kern.syscall::48 4 3.42% 65.81% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.85% 66.67% # number of syscalls executed +system.cpu1.kern.syscall::59 3 2.56% 69.23% # number of syscalls executed +system.cpu1.kern.syscall::71 22 18.80% 88.03% # number of syscalls executed +system.cpu1.kern.syscall::74 7 5.98% 94.02% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.71% 95.73% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.71% 97.44% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.71% 99.15% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 117 # number of syscalls executed +system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2023 2.23% 2.25% # number of callpals executed +system.cpu1.kern.callpal::tbi 16 0.02% 2.26% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.27% # number of callpals executed +system.cpu1.kern.callpal::swpipl 82767 91.03% 93.30% # number of callpals executed +system.cpu1.kern.callpal::rdps 2444 2.69% 95.99% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.99% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 96.00% # number of callpals executed +system.cpu1.kern.callpal::rdusp 3 0.00% 96.00% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.00% # number of callpals executed +system.cpu1.kern.callpal::rti 3410 3.75% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 189 0.21% 99.96% # number of callpals executed +system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.callpal::total 90921 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2651 # number of protection mode switches +system.cpu1.kern.mode_switch::user 640 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2049 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 706 +system.cpu1.kern.mode_good::user 640 +system.cpu1.kern.mode_good::idle 66 +system.cpu1.kern.mode_switch_good::kernel 0.266315 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.128423 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.796883 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 37276082000 1.96% 1.96% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1059454000 0.06% 2.02% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1863388682000 97.98% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1112 # number of times the context was actually changed -system.cpu1.kern.syscall::2 2 1.46% 1.46% # number of syscalls executed -system.cpu1.kern.syscall::3 14 10.22% 11.68% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.73% 12.41% # number of syscalls executed -system.cpu1.kern.syscall::6 16 11.68% 24.09% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.73% 24.82% # number of syscalls executed -system.cpu1.kern.syscall::17 7 5.11% 29.93% # number of syscalls executed -system.cpu1.kern.syscall::19 4 2.92% 32.85% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.46% 34.31% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.19% 36.50% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.19% 38.69% # number of syscalls executed -system.cpu1.kern.syscall::33 5 3.65% 42.34% # number of syscalls executed -system.cpu1.kern.syscall::45 21 15.33% 57.66% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.19% 59.85% # number of syscalls executed -system.cpu1.kern.syscall::48 3 2.19% 62.04% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.73% 62.77% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.46% 64.23% # number of syscalls executed -system.cpu1.kern.syscall::71 31 22.63% 86.86% # number of syscalls executed -system.cpu1.kern.syscall::74 10 7.30% 94.16% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.46% 95.62% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.46% 97.08% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.19% 99.27% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.73% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 137 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 315526 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 194379 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 2745592 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1578351 # Number of stores inserted to the mem dependence unit. -system.cpu1.misc_regfile_reads 493874 # number of misc regfile reads -system.cpu1.misc_regfile_writes 221749 # number of misc regfile writes -system.cpu1.numCycles 24501486 # number of cpu cycles simulated -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.rename.BlockCycles 2575160 # Number of cycles rename is blocking -system.cpu1.rename.CommittedMaps 9194083 # Number of HB maps that are committed -system.cpu1.rename.IQFullEvents 253610 # Number of times rename has blocked due to IQ full -system.cpu1.rename.IdleCycles 9125188 # Number of cycles rename is idle -system.cpu1.rename.LSQFullEvents 96900 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.ROBFullEvents 103 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RenameLookups 20382349 # Number of register rename lookups that rename has made -system.cpu1.rename.RenamedInsts 16583054 # Number of instructions processed by rename -system.cpu1.rename.RenamedOperands 11154403 # Number of destination operands rename has renamed -system.cpu1.rename.RunCycles 2970670 # Number of cycles rename is running -system.cpu1.rename.SquashCycles 401676 # Number of cycles rename is squashing -system.cpu1.rename.UnblockCycles 911632 # Number of cycles rename is unblocking -system.cpu1.rename.UndoneMaps 1960318 # Number of HB maps that are undone due to squashing -system.cpu1.rename.fp_rename_lookups 113596 # Number of floating rename lookups -system.cpu1.rename.int_rename_lookups 20268753 # Number of integer rename lookups -system.cpu1.rename.serializeStallCycles 5429708 # count of cycles rename stalled for serializing inst -system.cpu1.rename.serializingInsts 475094 # count of serializing insts renamed -system.cpu1.rename.skidInsts 2839642 # count of insts added to the skid buffer -system.cpu1.rename.tempSerializingInsts 40509 # count of temporary serializing insts renamed -system.cpu1.rob.rob_reads 36377887 # The number of ROB reads -system.cpu1.rob.rob_writes 31956605 # The number of ROB writes -system.cpu1.timesIdled 286877 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115257.131429 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63257.131429 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20169998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11069998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137655.487245 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85651.857817 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5719860806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3559005996 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6179.103844 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64621068 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137561.550171 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85557.935965 # average overall mshr miss latency -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5740030804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3570075994 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_blocks::1 0.207263 # Average occupied blocks per context -system.iocache.occ_percent::1 0.012954 # Average percentage of cache occupancy -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137561.550171 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85557.935965 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5740030804 # number of overall miss cycles -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3570075994 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41695 # number of replacements -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.207263 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1710304111000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 243081 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 47227 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 290308 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 61154.932642 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 368564.170526 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40302.705557 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 135076 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 29306 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 164382 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6605038500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.444317 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.379465 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 108005 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 17921 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125926 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5075158500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.518041 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 2.666398 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 125926 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1634357 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 503467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2137824 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 53314.961165 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2119707.492415 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40003.636264 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1332950 # number of ReadReq hits -system.l2c.ReadReq_hits::1 495886 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1828836 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16069502500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.184419 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.015058 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 301407 # number of ReadReq misses -system.l2c.ReadReq_misses::1 7581 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308988 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12359963500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.189047 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.613687 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 308971 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 838535000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 620 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 656 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1276 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 18379.965458 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 17109.324759 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40002.081599 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 41 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 34 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_latency 10642000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 0.933871 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.948171 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 579 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 622 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1201 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 48042500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.937097 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.830793 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 1201 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 3788 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 897 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4685 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 1321.100917 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 5809.290954 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.698754 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 191 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 79 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 270 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 4752000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.949578 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.911929 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 3597 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 818 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4415 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 176607500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.165523 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 4.921962 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 4415 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1545168498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 791892 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 791892 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 791892 # number of Writeback hits -system.l2c.Writeback_hits::total 791892 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.551399 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 1877438 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 550694 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2428132 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 55383.186130 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 889127.950749 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40090.232860 # average overall mshr miss latency -system.l2c.demand_hits::0 1468026 # number of demand (read+write) hits -system.l2c.demand_hits::1 525192 # number of demand (read+write) hits -system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1993218 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22674541000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.218070 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.046309 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 409412 # number of demand (read+write) misses -system.l2c.demand_misses::1 25502 # number of demand (read+write) misses -system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 434914 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17435122000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.231644 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.789725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 434897 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 10408.866153 # Average occupied blocks per context -system.l2c.occ_blocks::1 2398.359333 # Average occupied blocks per context -system.l2c.occ_blocks::2 23061.577659 # Average occupied blocks per context -system.l2c.occ_percent::0 0.158827 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.036596 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.351892 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 1877438 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 550694 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2428132 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 55383.186130 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 889127.950749 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40090.232860 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1468026 # number of overall hits -system.l2c.overall_hits::1 525192 # number of overall hits -system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1993218 # number of overall hits -system.l2c.overall_miss_latency 22674541000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.218070 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.046309 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 409412 # number of overall misses -system.l2c.overall_misses::1 25502 # number of overall misses -system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 434914 # number of overall misses -system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17435122000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.231644 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.789725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 434897 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2383703498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 397174 # number of replacements -system.l2c.sampled_refs 433601 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 35868.803144 # Cycle average of tags in use -system.l2c.total_refs 2407092 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9258990000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 122449 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.cpu1.kern.mode_switch_good::idle 0.032211 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.298525 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 43748791000 2.30% 2.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 905692500 0.05% 2.35% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1853996893000 97.65% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2024 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 2121232b8..be4d1c60b 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -10,12 +10,13 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +memories=system.physmem +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -495,7 +496,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -515,7 +516,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -611,6 +612,7 @@ port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system. [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -643,7 +645,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -762,6 +764,7 @@ pio=system.iobus.port[27] [system.tsunami.fake_OROM] type=IsaFake +fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 @@ -778,6 +781,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake +fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 @@ -794,6 +798,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake +fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 @@ -810,6 +815,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake +fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 @@ -826,6 +832,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake +fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 @@ -842,6 +849,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake +fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 @@ -858,6 +866,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake +fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 @@ -874,6 +883,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake +fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 @@ -890,6 +900,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake +fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 @@ -906,6 +917,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake +fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 @@ -922,6 +934,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake +fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 @@ -938,6 +951,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake +fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 @@ -954,6 +968,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake +fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 @@ -970,6 +985,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake +fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 @@ -986,6 +1002,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake +fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 @@ -1002,6 +1019,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake +fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 @@ -1018,6 +1036,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake +fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 @@ -1034,6 +1053,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake +fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 @@ -1050,6 +1070,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake +fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr index 0372a3b05..0bcb6e870 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr @@ -1,9 +1,5 @@ warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 6e8d29977..9aa3b6fd7 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,16 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:02:59 -M5 started Apr 21 2011 13:21:52 -M5 executing on maize -command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Jul 8 2011 15:02:59 +gem5 started Jul 8 2011 18:21:28 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1863702170500 because m5_exit instruction encountered +Exiting @ tick 1860642398500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 3d92c2fae..3bf0e1e63 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,563 +1,843 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 146689 # Simulator instruction rate (inst/s) -host_mem_usage 295516 # Number of bytes of host memory used -host_seconds 361.92 # Real time elapsed on the host -host_tick_rate 5149474067 # Simulator tick rate (ticks/s) +sim_seconds 1.860642 # Number of seconds simulated +sim_ticks 1860642398500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53089625 # Number of instructions simulated -sim_seconds 1.863702 # Number of seconds simulated -sim_ticks 1863702170500 # Number of ticks simulated +host_inst_rate 59629 # Simulator instruction rate (inst/s) +host_tick_rate 2089604255 # Simulator tick rate (ticks/s) +host_mem_usage 333232 # Number of bytes of host memory used +host_seconds 890.43 # Real time elapsed on the host +sim_insts 53094994 # Number of instructions simulated +system.l2c.replacements 391412 # number of replacements +system.l2c.tagsinuse 34941.270648 # Cycle average of tags in use +system.l2c.total_refs 2407591 # Total number of references to valid blocks. +system.l2c.sampled_refs 424295 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.674333 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5621019000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 12366.621064 # Average occupied blocks per context +system.l2c.occ_blocks::1 22574.649583 # Average occupied blocks per context +system.l2c.occ_percent::0 0.188700 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.344462 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1801894 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1801894 # number of ReadReq hits +system.l2c.Writeback_hits::0 835599 # number of Writeback hits +system.l2c.Writeback_hits::total 835599 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 183225 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183225 # number of ReadExReq hits +system.l2c.demand_hits::0 1985119 # number of demand (read+write) hits +system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1985119 # number of demand (read+write) hits +system.l2c.overall_hits::0 1985119 # number of overall hits +system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::total 1985119 # number of overall hits +system.l2c.ReadReq_misses::0 308127 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308127 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 31 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 31 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 116938 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116938 # number of ReadExReq misses +system.l2c.demand_misses::0 425065 # number of demand (read+write) misses +system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 425065 # number of demand (read+write) misses +system.l2c.overall_misses::0 425065 # number of overall misses +system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::total 425065 # number of overall misses +system.l2c.ReadReq_miss_latency 16037568500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 372000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6135692000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 22173260500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 22173260500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2110021 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2110021 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 835599 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835599 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 48 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 48 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 300163 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300163 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2410184 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2410184 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2410184 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2410184 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.146030 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.645833 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.389582 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.176362 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.176362 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52048.566013 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 12000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52469.616378 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::0 52164.399562 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency +system.l2c.demand_avg_miss_latency::total inf # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52164.399562 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency +system.l2c.overall_avg_miss_latency::total inf # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 117788 # number of writebacks +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 308127 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 116938 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 425065 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 425065 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency 12333883500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 1300000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4713361500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 17047245000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 17047245000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 810033500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1115471498 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 1925504998 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146030 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.645833 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.389582 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::0 0.176362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.176362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40028.571011 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 41935.483871 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40306.500026 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40105.030995 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40105.030995 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 41685 # number of replacements +system.iocache.tagsinuse 1.282104 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.warmup_cycle 1708339230000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 1.282104 # Average occupied blocks per context +system.iocache.occ_percent::1 0.080132 # Average percentage of cache occupancy +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.ReadReq_misses::1 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses +system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 5723029806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 5742967804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 5742967804 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137731.753129 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137638.533349 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137638.533349 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64649956 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6171.244368 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 41512 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3562178882 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3573120880 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3573120880 # number of overall MSHR miss cycles +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 85728.217222 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85635.012103 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85635.012103 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 10181490 # DTB read hits +system.cpu.dtb.read_misses 43507 # DTB read misses +system.cpu.dtb.read_acv 584 # DTB read access violations +system.cpu.dtb.read_accesses 956517 # DTB read accesses +system.cpu.dtb.write_hits 6638592 # DTB write hits +system.cpu.dtb.write_misses 9235 # DTB write misses +system.cpu.dtb.write_acv 315 # DTB write access violations +system.cpu.dtb.write_accesses 335365 # DTB write accesses +system.cpu.dtb.data_hits 16820082 # DTB hits +system.cpu.dtb.data_misses 52742 # DTB misses +system.cpu.dtb.data_acv 899 # DTB access violations +system.cpu.dtb.data_accesses 1291882 # DTB accesses +system.cpu.itb.fetch_hits 1343321 # ITB hits +system.cpu.itb.fetch_misses 39871 # ITB misses +system.cpu.itb.fetch_acv 1097 # ITB acv +system.cpu.itb.fetch_accesses 1383192 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.numCycles 117574512 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 14520870 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12129881 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 536127 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13102888 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 6784816 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6622434 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12800990 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 39895 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 599479 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11925971 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14248722 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 975192 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 769874 # The number of times a branch was mispredicted -system.cpu.commit.branches 8461745 # Number of branches committed -system.cpu.commit.bw_lim_events 1125976 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 56284256 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667734 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8032073 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 87254730 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.645057 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459520 # Number of insts commited each cycle +system.cpu.BPredUnit.usedRAS 988023 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45439 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29297731 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74578036 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14520870 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7772839 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 14464966 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2480365 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37381696 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 11813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 262360 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 335674 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9188867 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 332159 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 83395171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.894273 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.211331 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68930205 82.65% 82.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1027253 1.23% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2037570 2.44% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 996261 1.19% 87.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2986489 3.58% 91.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 701042 0.84% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 810374 0.97% 92.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1074366 1.29% 94.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4831611 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 83395171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123504 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.634304 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 30605129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36986989 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 13179583 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1024525 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1598944 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 618757 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42149 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 72864512 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 127083 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1598944 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 31853597 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12955306 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19880213 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 12336598 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4770511 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 68839007 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4216 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 997134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1470879 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 46134135 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 83694616 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 83214897 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479719 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38263079 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7871048 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1701317 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 251479 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12958659 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10852157 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7063465 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2081084 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2219281 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 60395993 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119342 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 58286883 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 83117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9015512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4849087 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1451479 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 83395171 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.698924 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.313462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56889866 68.22% 68.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11980340 14.37% 82.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5968113 7.16% 89.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3572850 4.28% 94.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2610876 3.13% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1337370 1.60% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 787156 0.94% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 190323 0.23% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 58277 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 83395171 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 67430 12.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 313148 55.72% 67.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 181376 32.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39850306 68.37% 68.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 63779 0.11% 68.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25609 0.04% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10660229 18.29% 86.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6723519 11.54% 98.37% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 952524 1.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 58286883 # Type of FU issued +system.cpu.iq.rate 0.495744 # Inst issue rate +system.cpu.iq.fu_busy_cnt 561954 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009641 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 199927311 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 71222511 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 56715823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 686696 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 334075 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327925 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58483404 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 358152 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 548522 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1737768 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13937 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28744 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 670362 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 19001 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 170467 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1598944 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9012018 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 624424 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 66178582 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 871819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10852157 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7063465 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1871966 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 491038 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13897 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28744 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 390552 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 383693 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 774245 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57578164 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10255391 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 708718 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 3663247 # number of nop insts executed +system.cpu.iew.exec_refs 16918441 # number of memory reference insts executed +system.cpu.iew.exec_branches 9135643 # Number of branches executed +system.cpu.iew.exec_stores 6663050 # Number of stores executed +system.cpu.iew.exec_rate 0.489716 # Inst execution rate +system.cpu.iew.wb_sent 57177610 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 57043748 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28229071 # num instructions producing a value +system.cpu.iew.wb_consumers 38069273 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.485171 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.741519 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 56289833 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9752851 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 667863 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 705919 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 81796227 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.688172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.561050 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 64129239 73.50% 73.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10001511 11.46% 84.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 5794569 6.64% 91.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2584226 2.96% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1856466 2.13% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 706744 0.81% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 418456 0.48% 97.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 637543 0.73% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1125976 1.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59880576 73.21% 73.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9259582 11.32% 84.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5272761 6.45% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2451209 3.00% 93.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1681883 2.06% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 629564 0.77% 96.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 461991 0.56% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 785484 0.96% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1373177 1.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 87254730 # Number of insts commited each cycle -system.cpu.commit.count 56284256 # Number of instructions committed -system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.function_calls 744594 # Number of function calls committed. -system.cpu.commit.int_insts 52122555 # Number of committed integer instructions. -system.cpu.commit.loads 9113387 # Number of loads committed -system.cpu.commit.membars 227959 # Number of memory barriers committed -system.cpu.commit.refs 15505823 # Number of memory references committed +system.cpu.commit.committed_per_cycle::total 81796227 # Number of insts commited each cycle +system.cpu.commit.count 56289833 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 53089625 # Number of Instructions Simulated -system.cpu.committedInsts_total 53089625 # Number of Instructions Simulated -system.cpu.cpi 2.304358 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.304358 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 213395 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 213395 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14731.007611 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.670030 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 191452 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 191452 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 323242500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.102828 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 21943 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 21943 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4499 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205816000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081745 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17444 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9261736 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9261736 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 21557.160878 # average ReadReq miss latency +system.cpu.commit.refs 15507492 # Number of memory references committed +system.cpu.commit.loads 9114389 # Number of loads committed +system.cpu.commit.membars 227923 # Number of memory barriers committed +system.cpu.commit.branches 8462531 # Number of branches committed +system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. +system.cpu.commit.int_insts 52127847 # Number of committed integer instructions. +system.cpu.commit.function_calls 744622 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1373177 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 146214633 # The number of ROB reads +system.cpu.rob.rob_writes 133687068 # The number of ROB writes +system.cpu.timesIdled 1253330 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34179341 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 53094994 # Number of Instructions Simulated +system.cpu.committedInsts_total 53094994 # Number of Instructions Simulated +system.cpu.cpi 2.214418 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.214418 # CPI: Total CPI of All Threads +system.cpu.ipc 0.451586 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.451586 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 75460784 # number of integer regfile reads +system.cpu.int_regfile_writes 41231418 # number of integer regfile writes +system.cpu.fp_regfile_reads 165968 # number of floating regfile reads +system.cpu.fp_regfile_writes 167480 # number of floating regfile writes +system.cpu.misc_regfile_reads 1996655 # number of misc regfile reads +system.cpu.misc_regfile_writes 950059 # number of misc regfile writes +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.cpu.icache.replacements 1005236 # number of replacements +system.cpu.icache.tagsinuse 509.950687 # Cycle average of tags in use +system.cpu.icache.total_refs 8124069 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1005745 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.077663 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 23367185000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 509.950687 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.995997 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8124070 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8124070 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8124070 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8124070 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8124070 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 8124070 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1064797 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064797 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1064797 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064797 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1064797 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 1064797 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15924471495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15924471495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15924471495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9188867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9188867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9188867 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9188867 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9188867 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9188867 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.115879 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.115879 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::0 0.115879 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::0 14955.406049 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::0 14955.406049 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14955.406049 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1315997 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 122 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10786.860656 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 236 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 58840 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 58840 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 58840 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1005957 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1005957 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1005957 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 12050949497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12050949497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12050949497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.109476 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.109476 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.109476 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11979.587097 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11979.587097 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11979.587097 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1403927 # number of replacements +system.cpu.dcache.tagsinuse 511.995946 # Cycle average of tags in use +system.cpu.dcache.total_refs 12182577 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1404439 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.674337 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 19464000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.995946 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 7545727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7545727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4224455 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4224455 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 192092 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192092 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 220106 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 220106 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 11770182 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11770182 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 11770182 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 11770182 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1787142 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1787142 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1933396 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1933396 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 23327 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23327 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 3720538 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3720538 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3720538 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 3720538 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 38546414500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 57324684255 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 362132500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 95871098755 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 95871098755 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9332869 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9332869 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6157851 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157851 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 215419 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 215419 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 220108 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 220108 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 15490720 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15490720 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 15490720 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15490720 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.191489 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.313973 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.108287 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.240179 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::0 0.240179 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::0 21568.747475 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22806.773244 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7478882 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7478882 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 38433270500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.192497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1782854 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1782854 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 698012 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24741745500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117132 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084842 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904671500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219886 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219886 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 24500 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 21375 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 219882 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219882 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 98000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000018 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 85500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6157400 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157400 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 29663.792257 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 29649.737692 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28277.245454 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4231311 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4231311 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 57135103964 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.312809 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 1926089 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1926089 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1626424 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 8473700759 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048667 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 299665 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235406998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8946.248648 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.647226 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 99695 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 891896259 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 24000 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15419136 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15419136 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 25767.010834 # average overall miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15524.177991 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 25768.074068 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23990.811357 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 11710193 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11710193 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 95568374464 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.240542 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3708943 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3708943 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2324436 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33215446259 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.089791 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1384507 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 511.995879 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 15419136 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15419136 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 25767.010834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 25768.074068 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23990.811357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 11710193 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11710193 # number of overall hits -system.cpu.dcache.overall_miss_latency 95568374464 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.240542 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3708943 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3708943 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2324436 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33215446259 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.089791 # mshr miss rate for overall accesses +system.cpu.dcache.blocked_cycles::no_mshrs 901455332 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 264000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 100284 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8989.024490 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 835363 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 699045 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1634457 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 5750 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2333502 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2333502 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1088097 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 298939 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 17577 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1387036 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1387036 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 24799761000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8488468332 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207628000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 33288229332 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33288229332 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904499500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234765498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 2139264998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116588 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048546 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081594 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.089540 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.089540 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1384507 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140078498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1401285 # number of replacements -system.cpu.dcache.sampled_refs 1401797 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22791.865983 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28395.319219 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11812.482221 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23999.542429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23999.542429 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995879 # Cycle average of tags in use -system.cpu.dcache.total_refs 12121656 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 19670000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 833416 # number of writebacks -system.cpu.decode.BlockedCycles 36259760 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 44553 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 598925 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 70789187 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 37160222 # Number of cycles decode is idle -system.cpu.decode.RunCycles 12840041 # Number of cycles decode is running -system.cpu.decode.SquashCycles 1435065 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 134914 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 994706 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1263492 # DTB accesses -system.cpu.dtb.data_acv 894 # DTB access violations -system.cpu.dtb.data_hits 16635681 # DTB hits -system.cpu.dtb.data_misses 51508 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 928978 # DTB read accesses -system.cpu.dtb.read_acv 572 # DTB read access violations -system.cpu.dtb.read_hits 10041253 # DTB read hits -system.cpu.dtb.read_misses 41018 # DTB read misses -system.cpu.dtb.write_accesses 334514 # DTB write accesses -system.cpu.dtb.write_acv 322 # DTB write access violations -system.cpu.dtb.write_hits 6594428 # DTB write hits -system.cpu.dtb.write_misses 10490 # DTB write misses -system.cpu.fetch.Branches 14248722 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8770990 # Number of cache lines fetched -system.cpu.fetch.Cycles 14042166 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 446901 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 72221007 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 40836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 893682 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.116471 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8770984 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7597626 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.590342 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 88689795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.814310 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.123238 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 74647629 84.17% 84.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1010703 1.14% 85.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1983506 2.24% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 916230 1.03% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2985219 3.37% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 672792 0.76% 92.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 771901 0.87% 93.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1056160 1.19% 94.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4645655 5.24% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 88689795 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 166013 # number of floating regfile reads -system.cpu.fp_regfile_writes 166759 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses::0 8770990 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8770990 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 15000.124864 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11953.663532 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7733870 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7733870 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15556929499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.118244 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1037120 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1037120 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 43680 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11875247499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.113264 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 993440 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 12654.527273 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.786451 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 695999 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8770990 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8770990 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 15000.124864 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11953.663532 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7733870 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7733870 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15556929499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.118244 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1037120 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1037120 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 43680 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11875247499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.113264 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 993440 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 509.827441 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.995757 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses::0 8770990 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8770990 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 15000.124864 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11953.663532 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7733870 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7733870 # number of overall hits -system.cpu.icache.overall_miss_latency 15556929499 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.118244 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1037120 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1037120 # number of overall misses -system.cpu.icache.overall_mshr_hits 43680 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11875247499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.113264 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 993440 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 992736 # number of replacements -system.cpu.icache.sampled_refs 993247 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.827441 # Cycle average of tags in use -system.cpu.icache.total_refs 7733869 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 23815676000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 201 # number of writebacks -system.cpu.idleCycles 33647698 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 834392 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 9077931 # Number of branches executed -system.cpu.iew.exec_nop 3561617 # number of nop insts executed -system.cpu.iew.exec_rate 0.466022 # Inst execution rate -system.cpu.iew.exec_refs 16730349 # number of memory reference insts executed -system.cpu.iew.exec_stores 6619936 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 9479709 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 10494692 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1785178 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 890339 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6849187 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 64447431 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10110413 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 516805 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57012019 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 106234 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 12252 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1435065 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 608300 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 167273 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 486953 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 6665 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 18985 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 17936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 1381305 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 456751 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 18985 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 404859 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 429533 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 36206464 # num instructions consuming a value -system.cpu.iew.wb_count 56518708 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.749991 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 27154531 # num instructions producing a value -system.cpu.iew.wb_rate 0.461990 # insts written-back per cycle -system.cpu.iew.wb_sent 56632372 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 74751539 # number of integer regfile reads -system.cpu.int_regfile_writes 40782350 # number of integer regfile writes -system.cpu.ipc 0.433960 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433960 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39349401 68.40% 68.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62002 0.11% 68.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25611 0.04% 68.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10457735 18.18% 86.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6670425 11.59% 98.34% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 952735 1.66% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57528826 # Type of FU issued -system.cpu.iq.fp_alu_accesses 358048 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 686320 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 327228 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 333627 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 549270 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009548 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45293 8.25% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 291133 53.00% 61.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 212842 38.75% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 57712767 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 203646640 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 56191480 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 67929762 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 58856413 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 57528826 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2029401 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7361535 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 36245 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1361667 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3591759 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 88689795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.648652 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.255048 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 61727681 69.60% 69.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 12782826 14.41% 84.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5739308 6.47% 90.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3779668 4.26% 94.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2566031 2.89% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1197199 1.35% 98.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 667320 0.75% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 163755 0.18% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 66007 0.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 88689795 # Number of insts issued each cycle -system.cpu.iq.rate 0.470247 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1283361 # ITB accesses -system.cpu.itb.fetch_acv 948 # ITB acv -system.cpu.itb.fetch_hits 1244403 # ITB hits -system.cpu.itb.fetch_misses 38958 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175553 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6791 3.53% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192522 # number of callpals executed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211679 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6434 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74901 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1887 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105871 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182902 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73534 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211631 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74888 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% 41.09% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1884 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105841 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182856 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73521 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1887 1.26% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73537 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149201 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1824267875500 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 98431000 0.01% 97.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 391220000 0.02% 97.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 38943770500 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1863701297000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1884 1.26% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73524 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149172 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1821901267000 97.92% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94071500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 385060500 0.02% 97.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 38261139000 2.06% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860641538000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981746 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694591 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1737 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5958 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.320074 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400796 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29982299000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2910857500 0.16% 1.76% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1830808132500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.ipl_used::31 0.694665 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -589,322 +869,36 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 1611665 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1565492 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 10494692 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6849187 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1995286 # number of misc regfile reads -system.cpu.misc_regfile_writes 949727 # number of misc regfile writes -system.cpu.numCycles 122337493 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 12932543 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 38258765 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 1039474 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 38708983 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 1241691 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 1519 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 81518808 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 66985432 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 44869849 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 12449033 # Number of cycles rename is running -system.cpu.rename.SquashCycles 1435065 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 4145083 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 6611082 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 474213 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 81044595 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 19019086 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 1691185 # count of serializing insts renamed -system.cpu.rename.skidInsts 11218533 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 244825 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 150193940 # The number of ROB reads -system.cpu.rob.rob_writes 130068170 # The number of ROB writes -system.cpu.timesIdled 1318957 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137723.402147 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85719.890306 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5722682806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3561832882 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6163.814415 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64565956 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137630.264925 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85626.767645 # average overall mshr miss latency -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5742622804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3572776880 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_blocks::1 1.289021 # Average occupied blocks per context -system.iocache.occ_percent::1 0.080564 # Average percentage of cache occupancy -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137630.264925 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85626.767645 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5742622804 # number of overall miss cycles -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3572776880 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41685 # number of replacements -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.289021 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1710301197000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300895 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300895 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52473.313718 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40319.645209 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 183981 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183981 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6134865000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.388554 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 116914 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116914 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4713931000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.388554 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 116914 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2094150 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2094150 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52039.282964 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40022.101207 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1786383 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1786383 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16015974000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.146965 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307767 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307767 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12317442000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146965 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307766 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 809986500 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_rate::0 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 40000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 1 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 38 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 38 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 14960 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 42440 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 374000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.657895 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 25 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 25 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 1061000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.657895 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116065498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 833617 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 833617 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 833617 # number of Writeback hits -system.l2c.Writeback_hits::total 833617 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.655777 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2395045 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2395045 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52158.770936 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40104.014788 # average overall mshr miss latency -system.l2c.demand_hits::0 1970364 # number of demand (read+write) hits -system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1970364 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22150839000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.177317 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 424681 # number of demand (read+write) misses -system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424681 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17031373000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.177316 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 424680 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 12180.929780 # Average occupied blocks per context -system.l2c.occ_blocks::1 22532.084945 # Average occupied blocks per context -system.l2c.occ_percent::0 0.185866 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.343812 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 2395045 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2395045 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52158.770936 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40104.014788 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1970364 # number of overall hits -system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1970364 # number of overall hits -system.l2c.overall_miss_latency 22150839000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.177317 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 424681 # number of overall misses -system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424681 # number of overall misses -system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17031373000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.177316 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 424680 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926051998 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 390703 # number of replacements -system.l2c.sampled_refs 423923 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 34713.014726 # Cycle average of tags in use -system.l2c.total_refs 2397614 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5626579000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 117022 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpipl 175513 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6789 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal::rti 5218 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.callpal::total 192477 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5955 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.320235 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.400957 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29480216500 1.58% 1.58% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2869428500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1828291885000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini index ef23b2e63..ee377ad76 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -19,6 +19,7 @@ kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing +memories=system.physmem system.diskmem midr_regval=890236928 physmem=system.physmem readfile=tests/halt.sh @@ -600,6 +601,7 @@ port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.r [system.membus.badaddr_responder] type=IsaFake +fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 @@ -732,6 +734,7 @@ pio=system.iobus.port[9] [system.realview.flash_fake] type=IsaFake +fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 @@ -818,6 +821,7 @@ pio=system.iobus.port[7] [system.realview.l2x0_fake] type=IsaFake +fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr index a758a5804..2cd67c8dd 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -1,35 +1,19 @@ warn: Sockets disabled, not accepting vnc client connections -For more information see: http://www.m5sim.org/warn/af6a84f6 warn: Sockets disabled, not accepting terminal connections -For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: The clidr register always reports 0 caches. -For more information see: http://www.m5sim.org/warn/23a3c326 warn: The csselr register isn't implemented. -For more information see: http://www.m5sim.org/warn/c0c486b8 warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: The ccsidr register isn't implemented and always reads as 0. -For more information see: http://www.m5sim.org/warn/2c4acb9c warn: instruction 'mcr dccimvac' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr dccmvau' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr icimvau' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -For more information see: http://www.m5sim.org/warn/7998f2ea warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb warn: instruction 'mcr bpiall' unimplemented -For more information see: http://www.m5sim.org/warn/21b09adb hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout index 8fc1c35c1..f8e4d4f40 100755 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,17 +1,11 @@ -Redirecting stdout to build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3/simout -Redirecting stderr to build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 21:41:16 -M5 started May 16 2011 21:43:01 -M5 executing on nadc-0271 -command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Jul 8 2011 15:21:58 +gem5 started Jul 9 2011 04:29:24 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/alisai01/dist/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 81956970500 because m5_exit instruction encountered +Exiting @ tick 80755049500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 147873eb2..3395088f8 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,97 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.081957 # Number of seconds simulated -sim_ticks 81956970500 # Number of ticks simulated +sim_seconds 0.080755 # Number of seconds simulated +sim_ticks 80755049500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32873 # Simulator instruction rate (inst/s) -host_tick_rate 51935468 # Simulator tick rate (ticks/s) -host_mem_usage 384040 # Number of bytes of host memory used -host_seconds 1578.05 # Real time elapsed on the host -sim_insts 51876153 # Number of instructions simulated -system.l2c.replacements 94702 # number of replacements -system.l2c.tagsinuse 38059.464310 # Cycle average of tags in use -system.l2c.total_refs 1031447 # Total number of references to valid blocks. -system.l2c.sampled_refs 126964 # Sample count of references to valid blocks. -system.l2c.avg_refs 8.123933 # Average number of references to valid blocks. +host_inst_rate 48628 # Simulator instruction rate (inst/s) +host_tick_rate 75697423 # Simulator tick rate (ticks/s) +host_mem_usage 388920 # Number of bytes of host memory used +host_seconds 1066.81 # Real time elapsed on the host +sim_insts 51876527 # Number of instructions simulated +system.l2c.replacements 94951 # number of replacements +system.l2c.tagsinuse 38190.664860 # Cycle average of tags in use +system.l2c.total_refs 1060547 # Total number of references to valid blocks. +system.l2c.sampled_refs 127388 # Sample count of references to valid blocks. +system.l2c.avg_refs 8.325329 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 6535.540690 # Average occupied blocks per context -system.l2c.occ_blocks::1 31523.923619 # Average occupied blocks per context -system.l2c.occ_percent::0 0.099724 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.481017 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 732124 # number of ReadReq hits -system.l2c.ReadReq_hits::1 105939 # number of ReadReq hits -system.l2c.ReadReq_hits::total 838063 # number of ReadReq hits -system.l2c.Writeback_hits::0 432446 # number of Writeback hits -system.l2c.Writeback_hits::total 432446 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 20 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 20 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 60973 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60973 # number of ReadExReq hits -system.l2c.demand_hits::0 793097 # number of demand (read+write) hits -system.l2c.demand_hits::1 105939 # number of demand (read+write) hits -system.l2c.demand_hits::total 899036 # number of demand (read+write) hits -system.l2c.overall_hits::0 793097 # number of overall hits -system.l2c.overall_hits::1 105939 # number of overall hits -system.l2c.overall_hits::total 899036 # number of overall hits -system.l2c.ReadReq_misses::0 20401 # number of ReadReq misses -system.l2c.ReadReq_misses::1 101 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20502 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1673 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1673 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 107993 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107993 # number of ReadExReq misses -system.l2c.demand_misses::0 128394 # number of demand (read+write) misses -system.l2c.demand_misses::1 101 # number of demand (read+write) misses -system.l2c.demand_misses::total 128495 # number of demand (read+write) misses -system.l2c.overall_misses::0 128394 # number of overall misses -system.l2c.overall_misses::1 101 # number of overall misses -system.l2c.overall_misses::total 128495 # number of overall misses -system.l2c.ReadReq_miss_latency 1071402500 # number of ReadReq miss cycles +system.l2c.occ_blocks::0 6775.267374 # Average occupied blocks per context +system.l2c.occ_blocks::1 31415.397486 # Average occupied blocks per context +system.l2c.occ_percent::0 0.103382 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.479361 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 745613 # number of ReadReq hits +system.l2c.ReadReq_hits::1 120260 # number of ReadReq hits +system.l2c.ReadReq_hits::total 865873 # number of ReadReq hits +system.l2c.Writeback_hits::0 435187 # number of Writeback hits +system.l2c.Writeback_hits::total 435187 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 60895 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60895 # number of ReadExReq hits +system.l2c.demand_hits::0 806508 # number of demand (read+write) hits +system.l2c.demand_hits::1 120260 # number of demand (read+write) hits +system.l2c.demand_hits::total 926768 # number of demand (read+write) hits +system.l2c.overall_hits::0 806508 # number of overall hits +system.l2c.overall_hits::1 120260 # number of overall hits +system.l2c.overall_hits::total 926768 # number of overall hits +system.l2c.ReadReq_misses::0 21201 # number of ReadReq misses +system.l2c.ReadReq_misses::1 103 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21304 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1679 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1679 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 107626 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107626 # number of ReadExReq misses +system.l2c.demand_misses::0 128827 # number of demand (read+write) misses +system.l2c.demand_misses::1 103 # number of demand (read+write) misses +system.l2c.demand_misses::total 128930 # number of demand (read+write) misses +system.l2c.overall_misses::0 128827 # number of overall misses +system.l2c.overall_misses::1 103 # number of overall misses +system.l2c.overall_misses::total 128930 # number of overall misses +system.l2c.ReadReq_miss_latency 1113607000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 5664440500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 6735843000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 6735843000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 752525 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 106040 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 858565 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 432446 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 432446 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 1693 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1693 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 168966 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 168966 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 921491 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 106040 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1027531 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 921491 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 106040 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1027531 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027110 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000952 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028063 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.988187 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.639140 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.139333 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000952 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.140285 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.139333 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000952 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.140285 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52517.156022 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 10607945.544554 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 10660462.700576 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 435.445308 # average UpgradeReq miss latency +system.l2c.ReadExReq_miss_latency 5645255000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 6758862000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 6758862000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 766814 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 120363 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 887177 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 435187 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 435187 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 1705 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1705 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 168521 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 168521 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 935335 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 120363 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1055698 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 935335 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 120363 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1055698 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.027648 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000856 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028504 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.984751 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.638650 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.137734 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000856 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.138589 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.137734 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000856 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.138589 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52526.154427 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 10811718.446602 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 10864244.601029 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 433.889220 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52451.922810 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52452.520766 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52462.287957 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 66691514.851485 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 66743977.139443 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52462.287957 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 66691514.851485 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 66743977.139443 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52464.638624 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 65620019.417476 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 65672484.056100 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52464.638624 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 65620019.417476 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 65672484.056100 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,44 +104,44 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 87773 # number of writebacks -system.l2c.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 47 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 47 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 20455 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 1673 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 107993 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 128448 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 128448 # number of overall MSHR misses +system.l2c.writebacks 87785 # number of writebacks +system.l2c.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 53 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 53 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 21251 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1679 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 107626 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 128877 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 128877 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 819077500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 66920000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4321060500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 5140138000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 5140138000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 28946041000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 748279439 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 29694320439 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.027182 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.192899 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.220081 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.988187 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 851149000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 67161500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4306288000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 5157437000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 5157437000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 28946617000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 748511947 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 29695128947 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.027713 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.176558 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.204271 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.984751 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.639140 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.638650 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.139391 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.211316 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.350708 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.139391 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.211316 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.350708 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40042.899047 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40012.412842 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40017.267688 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40017.267688 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.137787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.070736 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.208523 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.137787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.070736 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.208523 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40052.185779 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.893389 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40011.595711 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40018.288756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40018.288756 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -146,27 +150,27 @@ system.l2c.soft_prefetch_mshr_full 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 27773403 # DTB read hits -system.cpu.dtb.read_misses 62999 # DTB read misses -system.cpu.dtb.write_hits 7478070 # DTB write hits -system.cpu.dtb.write_misses 11819 # DTB write misses +system.cpu.dtb.read_hits 28171950 # DTB read hits +system.cpu.dtb.read_misses 70965 # DTB read misses +system.cpu.dtb.write_hits 7689357 # DTB write hits +system.cpu.dtb.write_misses 13471 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 2909 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3199 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1081 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 2907 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3957 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1100 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1182 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 27836402 # DTB read accesses -system.cpu.dtb.write_accesses 7489889 # DTB write accesses +system.cpu.dtb.perms_faults 937 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 28242915 # DTB read accesses +system.cpu.dtb.write_accesses 7702828 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 35251473 # DTB hits -system.cpu.dtb.misses 74818 # DTB misses -system.cpu.dtb.accesses 35326291 # DTB accesses -system.cpu.itb.inst_hits 6378307 # ITB inst hits -system.cpu.itb.inst_misses 7071 # ITB inst misses +system.cpu.dtb.hits 35861307 # DTB hits +system.cpu.dtb.misses 84436 # DTB misses +system.cpu.dtb.accesses 35945743 # DTB accesses +system.cpu.itb.inst_hits 7359425 # ITB inst hits +system.cpu.itb.inst_misses 7724 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -175,117 +179,120 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 1627 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 1636 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 5145 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4501 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 6385378 # ITB inst accesses -system.cpu.itb.hits 6378307 # DTB hits -system.cpu.itb.misses 7071 # DTB misses -system.cpu.itb.accesses 6385378 # DTB accesses -system.cpu.numCycles 163913942 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 7367149 # ITB inst accesses +system.cpu.itb.hits 7359425 # DTB hits +system.cpu.itb.misses 7724 # DTB misses +system.cpu.itb.accesses 7367149 # DTB accesses +system.cpu.numCycles 161510100 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 12907993 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10988942 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 671137 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11440578 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8975415 # Number of BTB hits +system.cpu.BPredUnit.lookups 13592134 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11458436 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 647586 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12137714 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9358977 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 783446 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 155600 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6371114 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 62781923 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12907993 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9758861 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 15757873 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1054135 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 7071 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 17008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 6372584 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264714 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3927 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 94752246 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.818183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.071967 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 895744 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 148599 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 17070311 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 67524465 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13592134 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10254721 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 17041944 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4127061 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 97740 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 55394199 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 13347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87578 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 326 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 7354402 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 335871 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4520 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 92740913 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.898020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.156020 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 79011674 83.39% 83.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1184236 1.25% 84.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1729223 1.82% 86.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1152880 1.22% 87.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4802064 5.07% 92.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 820808 0.87% 93.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 792852 0.84% 94.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 714149 0.75% 95.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4544360 4.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75718007 81.64% 81.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1434363 1.55% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1859616 2.01% 85.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1401287 1.51% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4885783 5.27% 91.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 931795 1.00% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 822935 0.89% 93.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 710992 0.77% 94.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4976135 5.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 94752246 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078749 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.383018 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23351217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 53571370 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 14396920 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1001314 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2431425 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1204609 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 71112 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 75302047 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 237029 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2431425 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24915043 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33439496 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16240153 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 12813964 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4912165 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 72500713 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 458049 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 112730 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2517697 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 125 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 74405789 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 315201303 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 315135556 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 65747 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 51886765 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22519023 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 806998 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 658881 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13649364 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 12530731 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8670127 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2363 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8454 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 64971047 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4028155 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 80215912 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 157537 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16406339 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29306942 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1065284 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 94752246 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.846586 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.419375 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 92740913 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.084157 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.418082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 19170041 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 54062693 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 15371067 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1173897 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2963215 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1326018 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 73901 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80423771 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 240700 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2963215 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20809926 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33458987 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16554506 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 13888577 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5065702 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 77066395 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 458305 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 144597 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2655814 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 87 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 79138164 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 336039003 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335972574 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 66429 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 51886671 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27251492 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 849161 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 666808 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 14017436 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 13569563 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9186562 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 338 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 772 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 69168297 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4042083 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 82065002 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 260128 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20656291 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 42322701 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1079276 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 92740913 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.884885 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.468016 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 59642752 62.95% 62.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15646635 16.51% 79.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6436241 6.79% 86.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4342320 4.58% 90.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6236918 6.58% 97.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1389324 1.47% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 710831 0.75% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 267243 0.28% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 79982 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58298864 62.86% 62.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14093921 15.20% 78.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6658255 7.18% 85.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4544945 4.90% 90.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6367225 6.87% 97.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1625042 1.75% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 756452 0.82% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 282758 0.30% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 113451 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 94752246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 92740913 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 27052 0.56% 0.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 27418 0.56% 0.56% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 1 0.00% 0.56% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available @@ -314,360 +321,373 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 4512476 93.02% 93.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 311301 6.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4528688 92.69% 93.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 329972 6.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2393223 2.98% 2.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 41066468 51.19% 54.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 70508 0.09% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 1 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 7 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 885 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28697043 35.77% 90.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7987756 9.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2393223 2.92% 2.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 42145979 51.36% 54.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 71705 0.09% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 1 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 15 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 889 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29241712 35.63% 89.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 8211450 10.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 80215912 # Type of FU issued -system.cpu.iq.rate 0.489378 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4850830 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.060472 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 260250560 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 85669706 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 61171405 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 16469 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9406 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6426 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 82664896 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8623 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 366873 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 82065002 # Type of FU issued +system.cpu.iq.rate 0.508111 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4886079 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.059539 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262084445 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 94207895 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 62666625 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 16580 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9518 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6446 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 84549185 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8673 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 425184 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3351745 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17637 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 321029 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1592843 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4390114 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12978 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 404267 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2109214 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17031974 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 9614 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17025483 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 9484 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2431425 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 21357875 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 254886 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 69165110 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 377919 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 12530731 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8670127 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3998128 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20657 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 45624 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 321029 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 537696 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 192380 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 730076 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 79002177 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28266423 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1213735 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2963215 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 21359658 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 253804 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 73379873 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 352437 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 13569563 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9186562 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4009981 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13852 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40391 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 404267 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 533633 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 173680 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 707313 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 80695154 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28677244 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1369848 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 165908 # number of nop insts executed -system.cpu.iew.exec_refs 36059018 # number of memory reference insts executed -system.cpu.iew.exec_branches 10339734 # Number of branches executed -system.cpu.iew.exec_stores 7792595 # Number of stores executed -system.cpu.iew.exec_rate 0.481974 # Inst execution rate -system.cpu.iew.wb_sent 78480189 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 61177831 # cumulative count of insts written-back -system.cpu.iew.wb_producers 31697588 # num instructions producing a value -system.cpu.iew.wb_consumers 56147470 # num instructions consuming a value +system.cpu.iew.exec_nop 169493 # number of nop insts executed +system.cpu.iew.exec_refs 36680386 # number of memory reference insts executed +system.cpu.iew.exec_branches 10545987 # Number of branches executed +system.cpu.iew.exec_stores 8003142 # Number of stores executed +system.cpu.iew.exec_rate 0.499629 # Inst execution rate +system.cpu.iew.wb_sent 80067231 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 62673071 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33197180 # num instructions producing a value +system.cpu.iew.wb_consumers 59582018 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.373231 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.564542 # average fanout of values written-back +system.cpu.iew.wb_rate 0.388044 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557168 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 51999383 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 14908448 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2962871 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 647540 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 92320849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.563246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.403184 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 51999757 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 19143621 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2962807 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 621959 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 89777726 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.579206 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.461343 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 71715015 77.68% 77.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9932500 10.76% 88.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3015414 3.27% 91.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1450347 1.57% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3545032 3.84% 97.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 778946 0.84% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 574470 0.62% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 309664 0.34% 98.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 999461 1.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 70089240 78.07% 78.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9267844 10.32% 88.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2668316 2.97% 91.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1388119 1.55% 92.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3443383 3.84% 96.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 819971 0.91% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 549038 0.61% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 351211 0.39% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1200604 1.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 92320849 # Number of insts commited each cycle -system.cpu.commit.count 51999383 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 89777726 # Number of insts commited each cycle +system.cpu.commit.count 51999757 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 16256270 # Number of memory references committed -system.cpu.commit.loads 9178986 # Number of loads committed +system.cpu.commit.refs 16256797 # Number of memory references committed +system.cpu.commit.loads 9179449 # Number of loads committed system.cpu.commit.membars 3 # Number of memory barriers committed -system.cpu.commit.branches 8429045 # Number of branches committed +system.cpu.commit.branches 8428992 # Number of branches committed system.cpu.commit.fp_insts 6017 # Number of committed floating point instructions. -system.cpu.commit.int_insts 42422970 # Number of committed integer instructions. -system.cpu.commit.function_calls 530172 # Number of function calls committed. -system.cpu.commit.bw_lim_events 999461 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 42423491 # Number of committed integer instructions. +system.cpu.commit.function_calls 530190 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1200604 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 157288126 # The number of ROB reads -system.cpu.rob.rob_writes 136297259 # The number of ROB writes -system.cpu.timesIdled 1087126 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 69161696 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 51876153 # Number of Instructions Simulated -system.cpu.committedInsts_total 51876153 # Number of Instructions Simulated -system.cpu.cpi 3.159717 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.159717 # CPI: Total CPI of All Threads -system.cpu.ipc 0.316484 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.316484 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 348377421 # number of integer regfile reads -system.cpu.int_regfile_writes 63134850 # number of integer regfile writes -system.cpu.fp_regfile_reads 5557 # number of floating regfile reads -system.cpu.fp_regfile_writes 1914 # number of floating regfile writes -system.cpu.misc_regfile_reads 83038352 # number of misc regfile reads -system.cpu.misc_regfile_writes 512623 # number of misc regfile writes -system.cpu.icache.replacements 500212 # number of replacements -system.cpu.icache.tagsinuse 496.830420 # Cycle average of tags in use -system.cpu.icache.total_refs 5827483 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 500724 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.638114 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6079257000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 496.830420 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.970372 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 5827483 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5827483 # number of ReadReq hits -system.cpu.icache.demand_hits::0 5827483 # number of demand (read+write) hits +system.cpu.rob.rob_reads 158779407 # The number of ROB reads +system.cpu.rob.rob_writes 145294275 # The number of ROB writes +system.cpu.timesIdled 1055860 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 68769187 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 51876527 # Number of Instructions Simulated +system.cpu.committedInsts_total 51876527 # Number of Instructions Simulated +system.cpu.cpi 3.113356 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.113356 # CPI: Total CPI of All Threads +system.cpu.ipc 0.321197 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.321197 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 356027200 # number of integer regfile reads +system.cpu.int_regfile_writes 64685711 # number of integer regfile writes +system.cpu.fp_regfile_reads 5606 # number of floating regfile reads +system.cpu.fp_regfile_writes 1941 # number of floating regfile writes +system.cpu.misc_regfile_reads 88439585 # number of misc regfile reads +system.cpu.misc_regfile_writes 512449 # number of misc regfile writes +system.cpu.icache.replacements 512265 # number of replacements +system.cpu.icache.tagsinuse 496.983905 # Cycle average of tags in use +system.cpu.icache.total_refs 6786376 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 512777 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13.234556 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 5988099000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 496.983905 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.970672 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 6786376 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6786376 # number of ReadReq hits +system.cpu.icache.demand_hits::0 6786376 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5827483 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 5827483 # number of overall hits +system.cpu.icache.demand_hits::total 6786376 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 6786376 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 5827483 # number of overall hits -system.cpu.icache.ReadReq_misses::0 545006 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 545006 # number of ReadReq misses -system.cpu.icache.demand_misses::0 545006 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 6786376 # number of overall hits +system.cpu.icache.ReadReq_misses::0 567912 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 567912 # number of ReadReq misses +system.cpu.icache.demand_misses::0 567912 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 545006 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 545006 # number of overall misses +system.cpu.icache.demand_misses::total 567912 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 567912 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 545006 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8053875993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8053875993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8053875993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 6372489 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6372489 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 6372489 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 567912 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 8362680490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8362680490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8362680490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 7354288 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 7354288 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 7354288 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6372489 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 6372489 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 7354288 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 7354288 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6372489 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.085525 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.085525 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 7354288 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.077222 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.077222 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.085525 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.077222 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14777.591427 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14725.310418 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14777.591427 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14725.310418 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14777.591427 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14725.310418 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 923494 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 1857992 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 110 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 226 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8395.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8221.203540 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 41542 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 44276 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 44276 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 44276 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 500730 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 500730 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 500730 # number of overall MSHR misses +system.cpu.icache.writebacks 42978 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 55127 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 55127 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 55127 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 512785 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 512785 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 512785 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6024482994 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6024482994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6024482994 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency 5116500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency 5116500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.078577 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 6200973492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6200973492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6200973492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency 5831500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency 5831500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.069726 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.078577 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.069726 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.078577 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.069726 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12031.400144 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12031.400144 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12031.400144 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12092.735731 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12092.735731 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12092.735731 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 422669 # number of replacements -system.cpu.dcache.tagsinuse 511.748488 # Cycle average of tags in use -system.cpu.dcache.total_refs 13739336 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 423181 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 32.466807 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48245000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.748488 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999509 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 8909058 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8909058 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4618812 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4618812 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 104652 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 104652 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 105045 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 105045 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 13527870 # number of demand (read+write) hits +system.cpu.dcache.replacements 424546 # number of replacements +system.cpu.dcache.tagsinuse 511.742424 # Cycle average of tags in use +system.cpu.dcache.total_refs 14088944 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 425058 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.145933 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 48611000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.742424 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999497 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 9259661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 9259661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 4618854 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4618854 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 103684 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 103684 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 104934 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 104934 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 13878515 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13527870 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 13527870 # number of overall hits +system.cpu.dcache.demand_hits::total 13878515 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 13878515 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13527870 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 535094 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 535094 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2043981 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2043981 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 6519 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6519 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 2579075 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 13878515 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 532064 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 532064 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2044074 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2044074 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 6626 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 6626 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 2576138 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2579075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 2579075 # number of overall misses +system.cpu.dcache.demand_misses::total 2576138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 2576138 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2579075 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 7852770500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 81637630250 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 97499500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 89490400750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 89490400750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9444152 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9444152 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6662793 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6662793 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 111171 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 111171 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 105045 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 105045 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 16106945 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 2576138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 7831574000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 81582591763 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 99296500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 14500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 89414165763 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 89414165763 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 9791725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9791725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 6662928 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6662928 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 110310 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 110310 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 104935 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 104935 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 16454653 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 16106945 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 16106945 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 16454653 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 16454653 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 16106945 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.056659 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.306775 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.058639 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.160122 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 16454653 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.054338 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.306783 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.060067 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000010 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.156560 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.160122 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.156560 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 14675.497202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 14719.233025 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 39940.503483 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 39911.760417 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14956.204939 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14985.888922 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 34698.642246 # average overall miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14500 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 34708.608686 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 34698.642246 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 34708.608686 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8797482 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 743000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1156 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7610.278547 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26535.714286 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 9862991 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 855500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1356 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 31 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7273.592183 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27596.774194 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 390904 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 286385 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1873352 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 983 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2159737 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2159737 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 248709 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 170629 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 5536 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 419338 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 419338 # number of overall MSHR misses +system.cpu.dcache.writebacks 392209 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 281075 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1873891 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1035 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2154966 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2154966 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 250989 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 170183 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 5591 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 421172 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 421172 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3317944000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 6570142982 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 65837500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9888086982 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9888086982 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38198704500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 944337693 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 39143042193 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.026335 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 3359805000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 6551180491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66352500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9910985491 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9910985491 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199653000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 946485168 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 39146138168 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025633 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025609 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025542 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.049797 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050684 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.026035 # mshr miss rate for demand accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000010 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.025596 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.026035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.025596 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13340.667205 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38505.429804 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11892.611994 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23580.231179 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23580.231179 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13386.263940 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38494.917183 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11867.733858 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23531.919242 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23531.919242 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status index f27ebe211..cac5c02c5 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status @@ -1 +1 @@ -build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED! +build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 passed. diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal Binary files differindex 6d04c79ea..fcb8d1a24 100644 --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini index 049d7897c..2374c04cc 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,14 +494,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/10.mcf/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout index 33d2d38b3..4a81b3d8f 100755 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 18:02:55 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 01:04:44 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 38330782000 because target called exit() +Exiting @ tick 33955329500 because target called exit() diff --git a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt index e7c27e9ae..cba4db906 100644 --- a/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.038331 # Number of seconds simulated -sim_ticks 38330782000 # Number of ticks simulated +sim_seconds 0.033955 # Number of seconds simulated +sim_ticks 33955329500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50765 # Simulator instruction rate (inst/s) -host_tick_rate 21324746 # Simulator tick rate (ticks/s) -host_mem_usage 388132 # Number of bytes of host memory used -host_seconds 1797.48 # Real time elapsed on the host -sim_insts 91249905 # Number of instructions simulated +host_inst_rate 64380 # Simulator instruction rate (inst/s) +host_tick_rate 23956859 # Simulator tick rate (ticks/s) +host_mem_usage 390580 # Number of bytes of host memory used +host_seconds 1417.35 # Real time elapsed on the host +sim_insts 91249680 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,298 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 76661565 # number of cpu cycles simulated +system.cpu.numCycles 67910660 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27657644 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22240511 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1744604 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 24744282 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 23393916 # Number of BTB hits +system.cpu.BPredUnit.lookups 28244508 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22629080 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1414299 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 25112752 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 24086234 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 124718 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 12906 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14552899 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 133105183 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27657644 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23518634 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 32520380 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1878354 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 14552899 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 370142 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 76631921 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.753228 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.654795 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 121674 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 12927 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 16032012 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 135606393 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28244508 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24207908 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 33529641 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6010411 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 13862842 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 15326942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 412294 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 67880028 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.019137 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.751435 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 44169594 57.64% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6017071 7.85% 65.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6194245 8.08% 73.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4415007 5.76% 79.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3274566 4.27% 83.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1452193 1.90% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1693941 2.21% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3142647 4.10% 91.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6272657 8.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 34404593 50.68% 50.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6761573 9.96% 60.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5940167 8.75% 69.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4952932 7.30% 76.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2875416 4.24% 80.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1738729 2.56% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1585314 2.34% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3119241 4.60% 90.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6502063 9.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 76631921 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.360776 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.736270 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30588008 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10266300 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31174404 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 260454 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4342755 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4341355 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 41083 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 130094148 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 33304 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4342755 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31960440 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 537193 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8162537 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30023248 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1605748 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 125609145 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 67880028 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.415907 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.996835 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 18687820 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12370381 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31414917 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 983964 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4422946 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4499724 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 32863 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133147735 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31368 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4422946 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20483676 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 968140 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8316666 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30556439 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3132161 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128513000 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 50871 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 833181 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 20 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 146281053 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 547382815 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 547382254 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 561 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 107429471 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 38851577 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 673626 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 677053 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5163872 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29426504 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6065519 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 977286 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 410445 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 117966564 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 652219 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107299468 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 25775 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24675448 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 62409285 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 97813 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 76631921 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.400193 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.609861 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 288426 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1795950 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 14 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 149798068 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 559931036 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 559926436 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4600 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 107429111 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 42368952 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 668763 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 669407 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7564309 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30008124 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6129267 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1456420 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 516652 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 120184129 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 637684 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107766890 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 87998 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 29120799 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 70180475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 83323 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 67880028 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.587608 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.759573 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 31086016 40.57% 40.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 16895448 22.05% 62.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 11625629 15.17% 77.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7628942 9.96% 87.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5191089 6.77% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2275199 2.97% 97.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1510567 1.97% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 290065 0.38% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128966 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25488891 37.55% 37.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14322408 21.10% 58.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10131350 14.93% 73.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 8118242 11.96% 85.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4318324 6.36% 91.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2337223 3.44% 95.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2482658 3.66% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 475759 0.70% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 205173 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 76631921 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 67880028 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 155894 31.11% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.01% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 83070 16.58% 47.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 262134 52.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57394 10.75% 10.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.01% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 196663 36.84% 47.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 279761 52.40% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 75289326 70.17% 70.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10516 0.01% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 12 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 24 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26536591 24.73% 94.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5462996 5.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 75833735 70.37% 70.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10982 0.01% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 110 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 182 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26490777 24.58% 94.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5431101 5.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107299468 # Type of FU issued -system.cpu.iq.rate 1.399651 # Inst issue rate -system.cpu.iq.fu_busy_cnt 501125 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.004670 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 291757623 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 143406422 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102963471 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 134 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 92 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 61 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 107800524 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 69 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 260883 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107766890 # Type of FU issued +system.cpu.iq.rate 1.586892 # Inst issue rate +system.cpu.iq.fu_busy_cnt 533845 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.004954 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 284035005 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 150060826 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 103585232 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 646 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 916 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 298 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 108300410 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 325 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 363305 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6850627 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7190 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 117769 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1318766 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7432292 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 39631 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 124361 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1382559 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 30723 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4342755 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 92075 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 26289 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118657452 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 642589 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29426504 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6065519 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 647367 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20754 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 246 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 117769 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1576147 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 244055 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1820202 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104961161 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25966774 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2338307 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4422946 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 101110 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18559 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 120860696 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 802315 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30008124 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6129267 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 632825 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 10731 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 224 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 124361 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1290705 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 209600 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1500305 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 105816782 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26069680 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1950108 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 38669 # number of nop insts executed -system.cpu.iew.exec_refs 31256963 # number of memory reference insts executed -system.cpu.iew.exec_branches 21029204 # Number of branches executed -system.cpu.iew.exec_stores 5290189 # Number of stores executed -system.cpu.iew.exec_rate 1.369150 # Inst execution rate -system.cpu.iew.wb_sent 103386173 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102963532 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59509513 # num instructions producing a value -system.cpu.iew.wb_consumers 95068105 # num instructions consuming a value +system.cpu.iew.exec_nop 38883 # number of nop insts executed +system.cpu.iew.exec_refs 31358457 # number of memory reference insts executed +system.cpu.iew.exec_branches 21276544 # Number of branches executed +system.cpu.iew.exec_stores 5288777 # Number of stores executed +system.cpu.iew.exec_rate 1.558176 # Inst execution rate +system.cpu.iew.wb_sent 104017986 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 103585530 # cumulative count of insts written-back +system.cpu.iew.wb_producers 60888984 # num instructions producing a value +system.cpu.iew.wb_consumers 97986900 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.343092 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.625967 # average fanout of values written-back +system.cpu.iew.wb_rate 1.525321 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.621399 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 91262514 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27394736 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 554406 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1716455 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 72289167 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.262465 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.025163 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 91262289 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 29597995 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 554361 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1394652 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 63457083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.438173 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.204542 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 36212335 50.09% 50.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18072720 25.00% 75.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6165923 8.53% 83.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4479757 6.20% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2050310 2.84% 92.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 555022 0.77% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 748999 1.04% 94.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 84475 0.12% 94.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3919626 5.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 29495808 46.48% 46.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16759375 26.41% 72.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5313552 8.37% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4030004 6.35% 87.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1955590 3.08% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 709900 1.12% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 461456 0.73% 92.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 205982 0.32% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4525416 7.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 72289167 # Number of insts commited each cycle -system.cpu.commit.count 91262514 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 63457083 # Number of insts commited each cycle +system.cpu.commit.count 91262289 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27322629 # Number of memory references committed -system.cpu.commit.loads 22575876 # Number of loads committed +system.cpu.commit.refs 27322539 # Number of memory references committed +system.cpu.commit.loads 22575831 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722470 # Number of branches committed +system.cpu.commit.branches 18722425 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 72533318 # Number of committed integer instructions. +system.cpu.commit.int_insts 72533138 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3919626 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4525416 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 187021057 # The number of ROB reads -system.cpu.rob.rob_writes 241665246 # The number of ROB writes -system.cpu.timesIdled 1537 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29644 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 91249905 # Number of Instructions Simulated -system.cpu.committedInsts_total 91249905 # Number of Instructions Simulated -system.cpu.cpi 0.840128 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.840128 # CPI: Total CPI of All Threads -system.cpu.ipc 1.190295 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.190295 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 499502252 # number of integer regfile reads -system.cpu.int_regfile_writes 121448309 # number of integer regfile writes -system.cpu.fp_regfile_reads 60 # number of floating regfile reads -system.cpu.fp_regfile_writes 46 # number of floating regfile writes -system.cpu.misc_regfile_reads 187007485 # number of misc regfile reads -system.cpu.misc_regfile_writes 11602 # number of misc regfile writes +system.cpu.rob.rob_reads 179786217 # The number of ROB reads +system.cpu.rob.rob_writes 246157217 # The number of ROB writes +system.cpu.timesIdled 1527 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30632 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 91249680 # Number of Instructions Simulated +system.cpu.committedInsts_total 91249680 # Number of Instructions Simulated +system.cpu.cpi 0.744229 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.744229 # CPI: Total CPI of All Threads +system.cpu.ipc 1.343672 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.343672 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502577811 # number of integer regfile reads +system.cpu.int_regfile_writes 122258624 # number of integer regfile writes +system.cpu.fp_regfile_reads 150 # number of floating regfile reads +system.cpu.fp_regfile_writes 373 # number of floating regfile writes +system.cpu.misc_regfile_reads 189862426 # number of misc regfile reads +system.cpu.misc_regfile_writes 11512 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 569.362196 # Cycle average of tags in use -system.cpu.icache.total_refs 14552080 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 678 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 21463.244838 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 615.328313 # Cycle average of tags in use +system.cpu.icache.total_refs 15326008 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 726 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 21110.203857 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 569.362196 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.278009 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 14552080 # number of ReadReq hits -system.cpu.icache.demand_hits 14552080 # number of demand (read+write) hits -system.cpu.icache.overall_hits 14552080 # number of overall hits -system.cpu.icache.ReadReq_misses 819 # number of ReadReq misses -system.cpu.icache.demand_misses 819 # number of demand (read+write) misses -system.cpu.icache.overall_misses 819 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 29501500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 29501500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 29501500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 14552899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 14552899 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 14552899 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000056 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000056 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000056 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36021.367521 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36021.367521 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36021.367521 # average overall miss latency +system.cpu.icache.occ_blocks::0 615.328313 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.300453 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 15326008 # number of ReadReq hits +system.cpu.icache.demand_hits 15326008 # number of demand (read+write) hits +system.cpu.icache.overall_hits 15326008 # number of overall hits +system.cpu.icache.ReadReq_misses 934 # number of ReadReq misses +system.cpu.icache.demand_misses 934 # number of demand (read+write) misses +system.cpu.icache.overall_misses 934 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 32832500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 32832500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 32832500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 15326942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 15326942 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 15326942 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35152.569593 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35152.569593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35152.569593 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,142 +354,142 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 140 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 140 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 140 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 679 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 679 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 679 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 207 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 207 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 207 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 727 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 727 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 727 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 23405500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 23405500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 23405500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25012500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25012500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25012500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000047 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000047 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000047 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34470.544919 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34470.544919 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34470.544919 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34405.089409 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34405.089409 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34405.089409 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943332 # number of replacements -system.cpu.dcache.tagsinuse 3485.983944 # Cycle average of tags in use -system.cpu.dcache.total_refs 29091101 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947428 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 30.705342 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 16303802000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3485.983944 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.851070 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 24496946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 4581580 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 6778 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 5796 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 29078526 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 29078526 # number of overall hits -system.cpu.dcache.ReadReq_misses 1032002 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 153401 # number of WriteReq misses +system.cpu.dcache.replacements 943475 # number of replacements +system.cpu.dcache.tagsinuse 3548.617037 # Cycle average of tags in use +system.cpu.dcache.total_refs 29160006 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947571 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 30.773426 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12936791000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 3548.617037 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.866362 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24566182 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 4581344 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 6728 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 5751 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 29147526 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 29147526 # number of overall hits +system.cpu.dcache.ReadReq_misses 998551 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 153637 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1185403 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1185403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5774861500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4244831902 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 124000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 10019693402 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 10019693402 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 25528948 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 1152188 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1152188 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5569139000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4384723397 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 126500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 9953862397 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 9953862397 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 25564733 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 6785 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 5796 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30263929 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30263929 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.040425 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.032397 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001032 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.039169 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.039169 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 5595.785183 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27671.474775 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 17714.285714 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 8452.562885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 8452.562885 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23297488 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 6735 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 5751 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30299714 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30299714 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.039060 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.032447 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001039 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.038026 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.038026 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 5577.220392 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 28539.501533 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 18071.428571 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 8639.095701 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 8639.095701 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23292477 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8138 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8136 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2862.802654 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2862.890487 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 942849 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 119201 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 118773 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 942916 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 85616 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 119000 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 237974 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 237974 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 912801 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 34628 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 947429 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 947429 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 204616 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 204616 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 912935 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 34637 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 947572 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 947572 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2307886000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1057417534 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3365303534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3365303534 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2294888500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1057301024 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3352189524 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3352189524 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035756 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.007313 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.031306 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.031306 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2528.356126 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30536.488795 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3552.037708 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3552.037708 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035711 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.007315 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.031273 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.031273 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2513.747967 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30525.190519 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3537.662071 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3537.662071 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 702 # number of replacements -system.cpu.l2cache.tagsinuse 8532.679465 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1625371 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15516 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 104.754511 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 747 # number of replacements +system.cpu.l2cache.tagsinuse 9154.979721 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1625557 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15570 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 104.403147 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 402.391901 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 8130.287564 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.012280 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.248117 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 912439 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 942849 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 20125 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 932564 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 932564 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1003 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 397.893639 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 8757.086082 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.012143 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.267245 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 912568 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 942916 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 20133 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 932701 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 932701 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1056 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 14539 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 15542 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 15542 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 34422500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 499217500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 533640000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 533640000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 913442 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 942849 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses 14540 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 15596 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 15596 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 36204000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 498983500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 535187500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 535187500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 913624 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 942916 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 34664 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 948106 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 948106 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.001098 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses 34673 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 948297 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 948297 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.001156 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.419426 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.016393 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.016393 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34319.541376 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34336.439920 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34335.349376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34335.349376 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.419346 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.016446 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.016446 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34284.090909 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34317.984869 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34315.689920 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34315.689920 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,28 +502,28 @@ system.cpu.l2cache.writebacks 32 # nu system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 993 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1046 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 14539 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 15532 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 15532 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 14540 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 15586 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 15586 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 30896000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 451520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 482416000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 482416000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 32557500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 451767000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 484324500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 484324500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001087 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001145 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.419426 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.016382 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.016382 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31113.796576 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31055.781003 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31059.490085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31059.490085 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.419346 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.016436 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.016436 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31125.717017 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31070.632737 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31074.329526 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31074.329526 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index de48f92fd..e75669d96 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,14 +494,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/chips/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index 730df25c3..43f4aeb73 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 8 2011 19:53:01 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -19,8 +19,9 @@ simplex iterations : 1502 flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 +info: Increasing stack size by one page. simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 81353358500 because target called exit() +Exiting @ tick 72726971500 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index a8865befa..8534b7b7b 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,249 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.081353 # Number of seconds simulated -sim_ticks 81353358500 # Number of ticks simulated +sim_seconds 0.072727 # Number of seconds simulated +sim_ticks 72726971500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205113 # Simulator instruction rate (inst/s) -host_tick_rate 59982451 # Simulator tick rate (ticks/s) -host_mem_usage 365084 # Number of bytes of host memory used -host_seconds 1356.29 # Real time elapsed on the host +host_inst_rate 68290 # Simulator instruction rate (inst/s) +host_tick_rate 17852786 # Simulator tick rate (ticks/s) +host_mem_usage 388028 # Number of bytes of host memory used +host_seconds 4073.70 # Real time elapsed on the host sim_insts 278192519 # Number of instructions simulated system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 162706718 # number of cpu cycles simulated +system.cpu.numCycles 145453944 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 43478033 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 43478033 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2457578 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 38773202 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 38222212 # Number of BTB hits +system.cpu.BPredUnit.lookups 39128056 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 39128056 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1285795 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 34407152 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 33889591 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30836194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 225319864 # Number of instructions fetch has processed -system.cpu.fetch.Branches 43478033 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 38222212 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 71185003 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2631314 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 30836194 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 310702 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 161537602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.462501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.241161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29588069 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 209386921 # Number of instructions fetch has processed +system.cpu.fetch.Branches 39128056 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33889591 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 65111619 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11621082 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 39294448 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 127 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28796477 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 238037 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 144111677 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.561755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.288092 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 92871455 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4826864 2.99% 60.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3003358 1.86% 62.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6248204 3.87% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7317456 4.53% 70.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5554189 3.44% 74.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 8050336 4.98% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 6460332 4.00% 83.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27205408 16.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 81461032 56.53% 56.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3926007 2.72% 59.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2843085 1.97% 61.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4618863 3.21% 64.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6929331 4.81% 69.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5578828 3.87% 73.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7691595 5.34% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4554481 3.16% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 26508455 18.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 161537602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.267217 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.384822 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 68100520 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13645788 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66107585 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1213655 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12470054 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 390299102 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 12470054 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 72027632 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3012062 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6445 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63003531 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11017878 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 382954672 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 129805 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 9724942 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 343637650 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 940851472 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 940850893 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 579 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 144111677 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.269006 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.439541 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 42334644 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 29762063 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 54385999 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7511580 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10117391 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 364671921 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10117391 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 49398641 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4827860 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6920 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 54606982 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25153883 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 359809940 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 28 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 255433 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20983622 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 323256675 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 885580834 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 885576522 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4312 # Number of floating rename lookups system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 95293458 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 462 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 25876087 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 121481389 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 39633547 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49140895 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10609784 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 366915906 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 331721300 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 173691 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 88480232 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 124860059 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 161537602 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.792236 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 74912483 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 481 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 474 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 57974009 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 116578971 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38504515 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58165962 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12487625 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 352625128 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 468 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 320274168 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 148663 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 74313113 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 111731092 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 144111677 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.222403 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.776502 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 44404154 27.49% 27.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 26523670 16.42% 43.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 27554042 17.06% 60.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26722697 16.54% 77.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19519009 12.08% 89.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 11121773 6.88% 96.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3849891 2.38% 98.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1601720 0.99% 99.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 240646 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 34558203 23.98% 23.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19108427 13.26% 37.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 27976000 19.41% 56.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 28361257 19.68% 76.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18381125 12.75% 89.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10394236 7.21% 96.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2736273 1.90% 98.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2552596 1.77% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 43560 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 161537602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 144111677 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 20533 1.17% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1580184 90.40% 91.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 147351 8.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 26349 1.28% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1847389 89.85% 91.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 182278 8.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 16703 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 188283743 56.76% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 16 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 108606815 32.74% 89.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34814023 10.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 182479275 56.98% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 71 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103720585 32.38% 89.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34057526 10.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 331721300 # Type of FU issued -system.cpu.iq.rate 2.038768 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1748068 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005270 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 826901753 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 455618803 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 324135014 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 208 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 333452564 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 43811715 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 320274168 # Type of FU issued +system.cpu.iq.rate 2.201894 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2056016 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006420 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 786864122 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 427256918 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 315787747 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 570 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2776 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 224 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 322313191 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 282 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 45099386 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30702001 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 37170 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 238201 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8193796 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 25799583 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7450 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 343486 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7064764 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3292 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 14215 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3530 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 14483 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12470054 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 739464 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 101352 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 366916371 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 440258 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 121481389 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 39633547 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4279 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 66728 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 238201 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2276962 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 580211 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2857173 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 327057192 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 107334804 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4664108 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10117391 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 811347 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 102359 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 352625596 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16735 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 116578971 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38504515 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 471 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 58728 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 343486 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1207902 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 198656 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1406558 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 317936612 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103056411 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2337556 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 141680841 # number of memory reference insts executed -system.cpu.iew.exec_branches 32801587 # Number of branches executed -system.cpu.iew.exec_stores 34346037 # Number of stores executed -system.cpu.iew.exec_rate 2.010103 # Inst execution rate -system.cpu.iew.wb_sent 325338225 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 324135094 # cumulative count of insts written-back -system.cpu.iew.wb_producers 242967410 # num instructions producing a value -system.cpu.iew.wb_consumers 330454956 # num instructions consuming a value +system.cpu.iew.exec_refs 136663121 # number of memory reference insts executed +system.cpu.iew.exec_branches 31969004 # Number of branches executed +system.cpu.iew.exec_stores 33606710 # Number of stores executed +system.cpu.iew.exec_rate 2.185823 # Inst execution rate +system.cpu.iew.wb_sent 316589546 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 315787971 # cumulative count of insts written-back +system.cpu.iew.wb_producers 236874431 # num instructions producing a value +system.cpu.iew.wb_consumers 330545022 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.992143 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735251 # average fanout of values written-back +system.cpu.iew.wb_rate 2.171051 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.716618 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 88730028 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 74441748 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2457587 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149067548 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.866218 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.482505 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1285812 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 133994286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.076152 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.625929 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 63468061 42.58% 42.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 26994600 18.11% 60.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19490262 13.07% 73.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13117480 8.80% 82.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4245570 2.85% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3438248 2.31% 87.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3061065 2.05% 89.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1693051 1.14% 90.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13559211 9.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52509499 39.19% 39.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24995000 18.65% 57.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 17512781 13.07% 70.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12345203 9.21% 80.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3532539 2.64% 82.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3553321 2.65% 85.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3000350 2.24% 87.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1127257 0.84% 88.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15418336 11.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149067548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133994286 # Number of insts commited each cycle system.cpu.commit.count 278192519 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219139 # Number of memory references committed @@ -253,49 +255,49 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 13559211 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15418336 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 502430884 # The number of ROB reads -system.cpu.rob.rob_writes 746329282 # The number of ROB writes -system.cpu.timesIdled 40054 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1169116 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 471210217 # The number of ROB reads +system.cpu.rob.rob_writes 715407828 # The number of ROB writes +system.cpu.timesIdled 40427 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1342267 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.584871 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.584871 # CPI: Total CPI of All Threads -system.cpu.ipc 1.709779 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.709779 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 572576247 # number of integer regfile reads -system.cpu.int_regfile_writes 291474006 # number of integer regfile writes -system.cpu.fp_regfile_reads 75 # number of floating regfile reads -system.cpu.fp_regfile_writes 41 # number of floating regfile writes -system.cpu.misc_regfile_reads 211119046 # number of misc regfile reads -system.cpu.icache.replacements 60 # number of replacements -system.cpu.icache.tagsinuse 811.599985 # Cycle average of tags in use -system.cpu.icache.total_refs 30834919 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1009 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 30559.880079 # Average number of references to valid blocks. +system.cpu.cpi 0.522854 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.522854 # CPI: Total CPI of All Threads +system.cpu.ipc 1.912581 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.912581 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557964995 # number of integer regfile reads +system.cpu.int_regfile_writes 283520691 # number of integer regfile writes +system.cpu.fp_regfile_reads 186 # number of floating regfile reads +system.cpu.fp_regfile_writes 177 # number of floating regfile writes +system.cpu.misc_regfile_reads 204022079 # number of misc regfile reads +system.cpu.icache.replacements 65 # number of replacements +system.cpu.icache.tagsinuse 828.162739 # Cycle average of tags in use +system.cpu.icache.total_refs 28795146 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1029 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 27983.620991 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 811.599985 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.396289 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 30834919 # number of ReadReq hits -system.cpu.icache.demand_hits 30834919 # number of demand (read+write) hits -system.cpu.icache.overall_hits 30834919 # number of overall hits -system.cpu.icache.ReadReq_misses 1275 # number of ReadReq misses -system.cpu.icache.demand_misses 1275 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1275 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 46105500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 46105500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 46105500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 30836194 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 30836194 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 30836194 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36161.176471 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36161.176471 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36161.176471 # average overall miss latency +system.cpu.icache.occ_blocks::0 828.162739 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.404376 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28795146 # number of ReadReq hits +system.cpu.icache.demand_hits 28795146 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28795146 # number of overall hits +system.cpu.icache.ReadReq_misses 1331 # number of ReadReq misses +system.cpu.icache.demand_misses 1331 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1331 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 47629500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 47629500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 47629500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28796477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28796477 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28796477 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35784.748310 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35784.748310 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35784.748310 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 265 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 265 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 265 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1010 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1010 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1010 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 301 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1030 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1030 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1030 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 35558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 35558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 35558500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 36247000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 36247000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 36247000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35206.435644 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35206.435644 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35206.435644 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35191.262136 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35191.262136 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35191.262136 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2073960 # number of replacements -system.cpu.dcache.tagsinuse 4075.298640 # Cycle average of tags in use -system.cpu.dcache.total_refs 92302253 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2078056 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 44.417597 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 30307591000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4075.298640 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994946 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 61099794 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31202450 # number of WriteReq hits -system.cpu.dcache.demand_hits 92302244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 92302244 # number of overall hits -system.cpu.dcache.ReadReq_misses 2219212 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 237301 # number of WriteReq misses -system.cpu.dcache.demand_misses 2456513 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2456513 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14180205500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4209484208 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18389689708 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18389689708 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 63319006 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2072723 # number of replacements +system.cpu.dcache.tagsinuse 4076.250938 # Cycle average of tags in use +system.cpu.dcache.total_refs 86852791 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2076819 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 41.820106 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 24787226000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4076.250938 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995178 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 55654749 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 31198033 # number of WriteReq hits +system.cpu.dcache.demand_hits 86852782 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 86852782 # number of overall hits +system.cpu.dcache.ReadReq_misses 2230129 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 241718 # number of WriteReq misses +system.cpu.dcache.demand_misses 2471847 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2471847 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14270225000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4343136672 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 18613361672 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 18613361672 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 57884878 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 94758757 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 94758757 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.035048 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.007548 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.025924 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.025924 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 6389.748028 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17739.007455 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 7486.095009 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 7486.095009 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 290000 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 89324629 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 89324629 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.038527 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.007688 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.027673 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.027673 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 6398.833879 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17967.783417 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 7530.143116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 7530.143116 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 275500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 82 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3411.764706 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3359.756098 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1448049 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 247154 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 131299 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 378453 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 378453 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1972058 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106002 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2078060 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2078060 # number of overall MSHR misses +system.cpu.dcache.writebacks 1446764 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 259013 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 136012 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 395025 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 395025 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1971116 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 105706 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2076822 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2076822 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5532610500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1870145708 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7402756208 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7402756208 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5556895000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1872300172 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7429195172 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7429195172 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.031145 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003372 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.021930 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.021930 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2805.500903 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17642.551159 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3562.339975 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3562.339975 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.034052 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003362 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.023250 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.023250 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2819.161835 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17712.335837 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3577.193988 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3577.193988 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 49058 # number of replacements -system.cpu.l2cache.tagsinuse 18069.203236 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3319340 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 77063 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 43.073070 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 49102 # number of replacements +system.cpu.l2cache.tagsinuse 18807.221207 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3317038 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 77109 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 43.017521 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6443.195976 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11626.007260 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.196631 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.354798 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1938598 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1448049 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 63959 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2002557 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2002557 # number of overall hits -system.cpu.l2cache.ReadReq_misses 34456 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 6724.342247 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12082.878960 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.205211 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.368740 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1937588 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1446764 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 63709 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 2001297 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2001297 # number of overall hits +system.cpu.l2cache.ReadReq_misses 34500 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 42055 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 76511 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 76511 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1178964000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1437688500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 2616652500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 2616652500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1973054 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1448049 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses 42053 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 76553 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 76553 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1179515000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1442921000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 2622436000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 2622436000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1972088 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1446764 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106014 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2079068 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2079068 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.017463 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses 105762 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2077850 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2077850 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.017494 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.396693 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.036801 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.036801 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34216.508010 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34185.911307 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34199.690241 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34199.690241 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 0.397619 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.036842 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.036842 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34188.840580 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34311.963475 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34256.475906 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34256.475906 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2461.538462 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 29183 # number of writebacks +system.cpu.l2cache.writebacks 29195 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 34456 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 34500 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 42055 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 76511 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 76511 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 42053 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 76553 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 76553 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1068941000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1070219000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1308447000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2377388000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2377388000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1309892500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2380111500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2380111500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017463 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017494 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.396693 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.036801 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.036801 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31023.363130 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.397619 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.036842 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.036842 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.840580 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31112.757104 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31072.499379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31072.499379 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31148.610087 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31091.028438 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31091.028438 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini index 91e8c0469..da98ab03d 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,14 +494,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/20.parser/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/20.parser/ref/arm/linux/o3-timing/simout index 5a0807465..9edf46eb3 100755 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 15:29:17 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 01:33:51 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -73,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 320953109000 because target called exit() +Exiting @ tick 302517583000 because target called exit() diff --git a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt index b11250106..954793f3d 100644 --- a/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.320953 # Number of seconds simulated -sim_ticks 320953109000 # Number of ticks simulated +sim_seconds 0.302518 # Number of seconds simulated +sim_ticks 302517583000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40042 # Simulator instruction rate (inst/s) -host_tick_rate 22415184 # Simulator tick rate (ticks/s) -host_mem_usage 260460 # Number of bytes of host memory used -host_seconds 14318.56 # Real time elapsed on the host -sim_insts 573342262 # Number of instructions simulated +host_inst_rate 48998 # Simulator instruction rate (inst/s) +host_tick_rate 25853029 # Simulator tick rate (ticks/s) +host_mem_usage 270368 # Number of bytes of host memory used +host_seconds 11701.44 # Real time elapsed on the host +sim_insts 573342442 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,297 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 641906219 # number of cpu cycles simulated +system.cpu.numCycles 605035167 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 223949599 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 179054613 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19156129 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 184229626 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 147971030 # Number of BTB hits +system.cpu.BPredUnit.lookups 237948628 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 189643896 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18525471 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 200558633 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 165003293 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 11972868 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2532941 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 130565917 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973113322 # Number of instructions fetch has processed -system.cpu.fetch.Branches 223949599 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 159943898 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 241546376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 21862580 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2406 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 130565917 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3998860 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 637850640 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.791502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.743865 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12776963 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2655849 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 165318082 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1053599180 # Number of instructions fetch has processed +system.cpu.fetch.Branches 237948628 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 177780256 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 271034430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 85133152 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 100456864 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 121417 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 151931838 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4658920 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 600617430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.083903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.829133 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 396316059 62.13% 62.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20357816 3.19% 65.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 35705192 5.60% 70.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 35959525 5.64% 76.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 37219035 5.84% 82.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 17602838 2.76% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18536216 2.91% 88.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 14275483 2.24% 90.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61878476 9.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 329595233 54.88% 54.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24765043 4.12% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43080599 7.17% 66.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 41413060 6.90% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43530596 7.25% 80.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16033141 2.67% 82.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19523127 3.25% 86.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 16376620 2.73% 88.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 66300011 11.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 637850640 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348882 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.515974 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 274650627 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79437827 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 227463937 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2944119 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 53354130 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31952595 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76091 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1091620209 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 217331 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 53354130 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 289506174 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9893108 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49317817 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 215240896 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20538515 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1036732054 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 236 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6072390 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 9974912 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1156982067 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4582431546 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4582430193 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1353 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672201056 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 484781006 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2811540 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2811485 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 54423240 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 192516932 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 113728531 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52019514 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 56045106 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 898220409 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4649392 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 742085900 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4028217 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 325034737 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 902951971 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 771526 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 637850640 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.163416 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.451606 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 600617430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.393281 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.741385 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 185610198 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93209648 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 249465251 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8754516 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 63577817 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 34830541 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109065 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1190327461 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 219958 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 63577817 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 203483134 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12711979 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52382429 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 240021493 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 28440578 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1124560978 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 631 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9752153 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 15058133 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1694 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1243412483 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4977837521 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4977834393 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3128 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672201344 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 571211134 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2776537 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2776073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 72944066 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 210041655 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 130199534 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 69466757 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 73938650 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 989222584 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4552609 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 764881922 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1674381 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 418150078 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1236634953 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 674707 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 600617430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.273493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.529486 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 296239264 46.44% 46.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 133409185 20.92% 67.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 102098632 16.01% 83.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53722534 8.42% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 32322089 5.07% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 11168911 1.75% 98.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5441714 0.85% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2057834 0.32% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1390477 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 269133638 44.81% 44.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 116546536 19.40% 64.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 93441125 15.56% 79.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 61796479 10.29% 90.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 37339082 6.22% 96.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12656566 2.11% 98.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5425017 0.90% 99.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3357457 0.56% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 921530 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 637850640 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 600617430 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 95830 1.04% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5443662 59.10% 60.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3670689 39.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 286700 3.30% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5674602 65.33% 68.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2725077 31.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 503818075 67.89% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 366199 0.05% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 82 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 163695097 22.06% 90.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 74206444 10.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 522376749 68.30% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 381409 0.05% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 80 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 170546214 22.30% 90.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 71577467 9.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 742085900 # Type of FU issued -system.cpu.iq.rate 1.156066 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9210181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2135260638 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1228450518 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 694522935 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 200 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 764881922 # Type of FU issued +system.cpu.iq.rate 1.264194 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8686379 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011356 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2140741838 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1412472990 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 713443043 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 196 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 472 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 751295979 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 102 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5771553 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 773568201 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 100 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 6159543 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 65743781 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15629 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 596063 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 56124460 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 83268468 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32978 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 628275 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 72595427 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 24980 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 144 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 27007 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 156 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 53354130 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2618576 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 142825 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 912051296 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 21556193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 192516932 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 113728531 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2788498 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 84227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8711 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 596063 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 17931306 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6522754 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 24454060 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 711877956 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 154430876 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30207944 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 63577817 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2968769 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 160563 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1003649799 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12343350 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 210041655 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 130199534 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2755333 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 81778 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 10213 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 628275 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18784960 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6284429 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25069389 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 737887948 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 162551175 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 26993974 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9181495 # number of nop insts executed -system.cpu.iew.exec_refs 222561224 # number of memory reference insts executed -system.cpu.iew.exec_branches 143781551 # Number of branches executed -system.cpu.iew.exec_stores 68130348 # Number of stores executed -system.cpu.iew.exec_rate 1.109006 # Inst execution rate -system.cpu.iew.wb_sent 704134955 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 694522951 # cumulative count of insts written-back -system.cpu.iew.wb_producers 388125156 # num instructions producing a value -system.cpu.iew.wb_consumers 688020690 # num instructions consuming a value +system.cpu.iew.exec_nop 9874606 # number of nop insts executed +system.cpu.iew.exec_refs 230127290 # number of memory reference insts executed +system.cpu.iew.exec_branches 150192140 # Number of branches executed +system.cpu.iew.exec_stores 67576115 # Number of stores executed +system.cpu.iew.exec_rate 1.219579 # Inst execution rate +system.cpu.iew.wb_sent 726019609 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 713443059 # cumulative count of insts written-back +system.cpu.iew.wb_producers 405782893 # num instructions producing a value +system.cpu.iew.wb_consumers 732949927 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.081970 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.564118 # average fanout of values written-back +system.cpu.iew.wb_rate 1.179176 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553630 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 574686146 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 337368429 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3877866 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 21251956 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 584496511 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.983216 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.594536 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 574686326 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 428980158 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3877902 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 20816789 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 537039614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.070100 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.725106 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 311654164 53.32% 53.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 150316632 25.72% 79.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 55227209 9.45% 88.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 24753339 4.23% 92.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 15848741 2.71% 95.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6546524 1.12% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7691194 1.32% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2289333 0.39% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10169375 1.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 281877385 52.49% 52.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 136335503 25.39% 77.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 48132590 8.96% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 21242728 3.96% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19119215 3.56% 94.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6739612 1.25% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8597333 1.60% 97.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3363443 0.63% 97.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11631805 2.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 584496511 # Number of insts commited each cycle -system.cpu.commit.count 574686146 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 537039614 # Number of insts commited each cycle +system.cpu.commit.count 574686326 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377221 # Number of memory references committed -system.cpu.commit.loads 126773150 # Number of loads committed +system.cpu.commit.refs 184377293 # Number of memory references committed +system.cpu.commit.loads 126773186 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192335 # Number of branches committed +system.cpu.commit.branches 120192371 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473702077 # Number of committed integer instructions. +system.cpu.commit.int_insts 473702221 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 10169375 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11631805 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1486374573 # The number of ROB reads -system.cpu.rob.rob_writes 1877592139 # The number of ROB writes -system.cpu.timesIdled 93100 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4055579 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 573342262 # Number of Instructions Simulated -system.cpu.committedInsts_total 573342262 # Number of Instructions Simulated -system.cpu.cpi 1.119586 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.119586 # CPI: Total CPI of All Threads -system.cpu.ipc 0.893187 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.893187 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3288876394 # number of integer regfile reads -system.cpu.int_regfile_writes 807633235 # number of integer regfile writes +system.cpu.rob.rob_reads 1529067155 # The number of ROB reads +system.cpu.rob.rob_writes 2071246317 # The number of ROB writes +system.cpu.timesIdled 105999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4417737 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 573342442 # Number of Instructions Simulated +system.cpu.committedInsts_total 573342442 # Number of Instructions Simulated +system.cpu.cpi 1.055277 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.055277 # CPI: Total CPI of All Threads +system.cpu.ipc 0.947618 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.947618 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3393544591 # number of integer regfile reads +system.cpu.int_regfile_writes 828738212 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1209708694 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464272 # number of misc regfile writes -system.cpu.icache.replacements 11767 # number of replacements -system.cpu.icache.tagsinuse 1053.166926 # Cycle average of tags in use -system.cpu.icache.total_refs 130550979 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 13545 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9638.315172 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1294615924 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464344 # number of misc regfile writes +system.cpu.icache.replacements 14868 # number of replacements +system.cpu.icache.tagsinuse 1047.725210 # Cycle average of tags in use +system.cpu.icache.total_refs 151911457 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16514 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 9198.949800 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1053.166926 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.514242 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 130550990 # number of ReadReq hits -system.cpu.icache.demand_hits 130550990 # number of demand (read+write) hits -system.cpu.icache.overall_hits 130550990 # number of overall hits -system.cpu.icache.ReadReq_misses 14927 # number of ReadReq misses -system.cpu.icache.demand_misses 14927 # number of demand (read+write) misses -system.cpu.icache.overall_misses 14927 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 215353500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 215353500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 215353500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 130565917 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 130565917 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 130565917 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000114 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000114 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 14427.111945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 14427.111945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 14427.111945 # average overall miss latency +system.cpu.icache.occ_blocks::0 1047.725210 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.511585 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 151911844 # number of ReadReq hits +system.cpu.icache.demand_hits 151911844 # number of demand (read+write) hits +system.cpu.icache.overall_hits 151911844 # number of overall hits +system.cpu.icache.ReadReq_misses 19994 # number of ReadReq misses +system.cpu.icache.demand_misses 19994 # number of demand (read+write) misses +system.cpu.icache.overall_misses 19994 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 277167000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 277167000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 277167000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 151931838 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 151931838 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 151931838 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000132 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000132 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000132 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 13862.508753 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 13862.508753 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 13862.508753 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,146 +352,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1072 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1072 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1072 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 13855 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 13855 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 13855 # number of overall MSHR misses +system.cpu.icache.writebacks 29 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1670 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1670 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1670 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 18324 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 18324 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 18324 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 147833000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 147833000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 147833000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 184845500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 184845500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 184845500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000106 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000106 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000106 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10670.010826 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10670.010826 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000121 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000121 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000121 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 10087.617332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 10087.617332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 10087.617332 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1189612 # number of replacements -system.cpu.dcache.tagsinuse 4060.806862 # Cycle average of tags in use -system.cpu.dcache.total_refs 200134121 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1193708 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.657518 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6159317000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4060.806862 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.991408 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 142442366 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 52854608 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 2604415 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 2232135 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 195296974 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 195296974 # number of overall hits -system.cpu.dcache.ReadReq_misses 1102250 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1384698 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 36 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2486948 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2486948 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 11846428500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 20406027500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 313000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 32252456000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 32252456000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 143544616 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1208536 # number of replacements +system.cpu.dcache.tagsinuse 4059.803539 # Cycle average of tags in use +system.cpu.dcache.total_refs 207709608 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1212632 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 171.288246 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5997963000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4059.803539 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.991163 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 150052810 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 52876507 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 2544785 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 2232171 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 202929317 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 202929317 # number of overall hits +system.cpu.dcache.ReadReq_misses 1147618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1362799 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 51 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 2510417 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2510417 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 12147896500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 20751705500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 582000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 32899602000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 32899602000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 151200428 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 2604451 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 2232135 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 197783922 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 197783922 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.007679 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.025529 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000014 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.012574 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.012574 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10747.496938 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 14736.807232 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 8694.444444 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 12968.689333 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 12968.689333 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 2544836 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 2232171 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 205439734 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 205439734 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.007590 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.025126 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000020 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.012220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.012220 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10585.313667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 15227.267924 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 11411.764706 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 13105.233911 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 13105.233911 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 172500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 98500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 32 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 20 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5390.625000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4925 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1065401 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 244002 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1048961 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1292963 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1292963 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 858248 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 335737 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1193985 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1193985 # number of overall MSHR misses +system.cpu.dcache.writebacks 1079332 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 271534 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1024501 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 51 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1296035 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1296035 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 876084 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 338298 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1214382 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1214382 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 6157877500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4228090500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 10385968000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 10385968000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6267336500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4269582000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10536918500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10536918500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005979 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006190 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006037 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006037 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7174.939528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12593.460060 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8698.574940 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.005911 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.807740 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12620.772219 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8676.774277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8676.774277 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 214616 # number of replacements -system.cpu.l2cache.tagsinuse 21258.843371 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1538764 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 234845 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.552254 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 231195370000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7817.837138 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13441.006233 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.238581 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.410187 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 742273 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1065403 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 160 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 231247 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 973520 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 973520 # number of overall hits -system.cpu.l2cache.ReadReq_misses 129152 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 104568 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 233720 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 233720 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 4416243000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 547000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3581590000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 7997833000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 7997833000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 871425 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1065403 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 272 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 335815 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1207240 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1207240 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.148208 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.411765 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.311386 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.193599 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.193599 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34194.151078 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 4883.928571 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34251.300589 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34219.720178 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34219.720178 # average overall miss latency +system.cpu.l2cache.replacements 217502 # number of replacements +system.cpu.l2cache.tagsinuse 21268.774974 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1567233 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 237739 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.592242 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7619.579259 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13649.195715 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.232531 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.416540 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 761070 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1079361 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1189 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 231140 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 992210 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 992210 # number of overall hits +system.cpu.l2cache.ReadReq_misses 130897 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 521 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 105763 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 236660 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 236660 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 4476495000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 5061500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3624223500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 8100718500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 8100718500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 891967 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1079361 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 1710 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 336903 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1228870 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1228870 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.146751 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.304678 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.313927 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.192583 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.192583 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34198.606538 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 9714.971209 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.404480 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34229.352235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34229.352235 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,32 +500,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 169760 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 129137 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 104568 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 233705 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 233705 # number of overall MSHR misses +system.cpu.l2cache.writebacks 170191 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 130875 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 521 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 105763 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 236638 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 236638 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4006675000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3473000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3242222500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 7248897500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 7248897500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4061689500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 16157000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3279601500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7341291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7341291000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.148191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.411765 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.311386 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.193586 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.193586 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31026.545452 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31008.928571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.876559 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31017.297448 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146726 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.304678 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313927 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.192566 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.192566 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.876791 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31011.516315 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.968165 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31023.297188 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31023.297188 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 523530b80..5d31afbd4 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,14 +494,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/chips/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index c4825a4e7..d1c3d672a 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 8 2011 20:37:07 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,6 +21,7 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success +info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor info: Increasing stack size by one page. @@ -32,7 +33,6 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -77,4 +77,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 584042944000 because target called exit() +Exiting @ tick 589091030500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index a6db3838d..0a390d5cd 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,249 +1,252 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.584043 # Number of seconds simulated -sim_ticks 584042944000 # Number of ticks simulated +sim_seconds 0.589091 # Number of seconds simulated +sim_ticks 589091030500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221280 # Simulator instruction rate (inst/s) -host_tick_rate 84524523 # Simulator tick rate (ticks/s) -host_mem_usage 274300 # Number of bytes of host memory used -host_seconds 6909.75 # Real time elapsed on the host +host_inst_rate 58676 # Simulator instruction rate (inst/s) +host_tick_rate 22606879 # Simulator tick rate (ticks/s) +host_mem_usage 302632 # Number of bytes of host memory used +host_seconds 26058.04 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1168085889 # number of cpu cycles simulated +system.cpu.numCycles 1178182062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 253398223 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 253398223 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16660589 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 238496117 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219579135 # Number of BTB hits +system.cpu.BPredUnit.lookups 273761240 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 273761240 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16674451 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 263536261 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 242767527 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 188493207 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1362528555 # Number of instructions fetch has processed -system.cpu.fetch.Branches 253398223 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 219579135 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 442066407 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 19282041 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 77357 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 188493207 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3791136 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1143941897 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.224075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.207990 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 225401733 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1479491232 # Number of instructions fetch has processed +system.cpu.fetch.Branches 273761240 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 242767527 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 481293494 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 151906633 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 310358472 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 81567 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 542630 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 210837280 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3978525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1150020801 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.401549 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.263992 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 706029092 61.72% 61.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32745689 2.86% 64.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38225778 3.34% 67.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34592742 3.02% 70.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20873132 1.82% 72.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 39592075 3.46% 76.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44500061 3.89% 80.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36282476 3.17% 83.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 191100852 16.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 673309594 58.55% 58.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 35910144 3.12% 61.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 42110719 3.66% 65.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 37429485 3.25% 68.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23065552 2.01% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42484626 3.69% 74.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 50557962 4.40% 78.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 39843815 3.46% 82.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 205308904 17.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1143941897 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.216935 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.166463 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 421359771 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 186435003 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405946069 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21628019 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 108573035 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2494021022 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 108573035 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 460289272 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50662445 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15855 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 387005567 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 137395723 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2428811074 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8205 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 53921903 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 70830357 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2267152647 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5703018907 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5703000611 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18296 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1150020801 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.232359 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.255741 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 295424105 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258223017 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 403450338 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 60580436 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 132342905 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2687346589 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 53 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 132342905 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 338937810 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 65386701 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28780 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 418304086 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 195020519 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2631430094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 26828 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 78975062 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 100019003 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2450674662 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6174029113 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6173774259 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 254854 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 839853620 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2555 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2515 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 298765601 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 586920489 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 222789217 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 352764399 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 138805015 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2327145816 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 9782 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1903699652 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 745209 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 795395556 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1355118976 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9229 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1143941897 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.664158 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.649963 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1023375635 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3023 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3014 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 414859898 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 629524584 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 242192886 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 419436220 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 160455315 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2509631726 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14401 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1981481069 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1143998 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979086329 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1684803071 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13848 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1150020801 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.722996 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.682483 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 364171044 31.83% 31.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 265972258 23.25% 55.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 191418370 16.73% 71.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151056709 13.20% 85.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 94863070 8.29% 93.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 46725885 4.08% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 20369113 1.78% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8499440 0.74% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 866008 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 371533820 32.31% 32.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 234816386 20.42% 52.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 195375199 16.99% 69.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 160336940 13.94% 83.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104083103 9.05% 92.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 52438845 4.56% 97.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24322326 2.11% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6470584 0.56% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 643598 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1143941897 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1150020801 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1290505 11.43% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7282962 64.50% 75.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2717631 24.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2000225 14.58% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9217501 67.18% 81.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2502434 18.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2277009 0.12% 0.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1273302138 66.89% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 457949055 24.06% 91.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170171450 8.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2582215 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1339393426 67.60% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 465725544 23.50% 91.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173779884 8.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1903699652 # Type of FU issued -system.cpu.iq.rate 1.629760 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11291098 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005931 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4963377358 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3125135181 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1859937909 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 150 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 7364 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 35 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1912713667 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 121955986 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1981481069 # Type of FU issued +system.cpu.iq.rate 1.681812 # Inst issue rate +system.cpu.iq.fu_busy_cnt 13720160 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006924 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5127845391 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3491473273 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1932208550 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1706 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 91974 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 40 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1992618257 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 757 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 130432763 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 202818329 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 145118 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 2595412 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 73631154 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 245422424 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 85551 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 2844514 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 93035934 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1267 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 2121 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 108573035 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9607775 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1579187 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2327155598 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2263253 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 586920489 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 222791339 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 9782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1056355 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 44992 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 2595412 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15396927 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2702189 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18099116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1873386406 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 447925301 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30313246 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 132342905 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11594389 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3099842 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2509646127 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 554822 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 629524584 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 242196119 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14401 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2636094 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 28755 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 2844514 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15750968 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2390539 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18141507 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1946393180 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456989279 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 35087889 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 613922207 # number of memory reference insts executed -system.cpu.iew.exec_branches 173516320 # Number of branches executed -system.cpu.iew.exec_stores 165996906 # Number of stores executed -system.cpu.iew.exec_rate 1.603809 # Inst execution rate -system.cpu.iew.wb_sent 1866315288 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1859937944 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1434930162 # num instructions producing a value -system.cpu.iew.wb_consumers 2113232937 # num instructions consuming a value +system.cpu.iew.exec_refs 625199049 # number of memory reference insts executed +system.cpu.iew.exec_branches 178040376 # Number of branches executed +system.cpu.iew.exec_stores 168209770 # Number of stores executed +system.cpu.iew.exec_rate 1.652031 # Inst execution rate +system.cpu.iew.wb_sent 1940174748 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1932208590 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1494691214 # num instructions producing a value +system.cpu.iew.wb_consumers 2239401377 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.592296 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.679021 # average fanout of values written-back +system.cpu.iew.wb_rate 1.639992 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667451 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 798170363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 980665483 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16691926 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1035368862 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.476758 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.996244 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16734282 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1017677896 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.502429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.032638 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 433054636 41.83% 41.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 271974415 26.27% 68.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 102879563 9.94% 78.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 102354239 9.89% 87.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 37870792 3.66% 91.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24412946 2.36% 93.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10660961 1.03% 94.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10611646 1.02% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 41549664 4.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 426781992 41.94% 41.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 262838337 25.83% 67.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 100636861 9.89% 77.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 98086664 9.64% 87.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 37562129 3.69% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27349053 2.69% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 11151176 1.10% 94.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9457604 0.93% 95.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43814080 4.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1035368862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1017677896 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -253,48 +256,48 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 41549664 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 43814080 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3320978317 # The number of ROB reads -system.cpu.rob.rob_writes 4762953278 # The number of ROB writes -system.cpu.timesIdled 612203 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24143992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3483518055 # The number of ROB reads +system.cpu.rob.rob_writes 5151797430 # The number of ROB writes +system.cpu.timesIdled 664618 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28161261 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.763960 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.763960 # CPI: Total CPI of All Threads -system.cpu.ipc 1.308969 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.308969 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3113988878 # number of integer regfile reads -system.cpu.int_regfile_writes 1735338379 # number of integer regfile writes -system.cpu.fp_regfile_reads 35 # number of floating regfile reads -system.cpu.misc_regfile_reads 1026178630 # number of misc regfile reads -system.cpu.icache.replacements 9690 # number of replacements -system.cpu.icache.tagsinuse 963.166837 # Cycle average of tags in use -system.cpu.icache.total_refs 188230465 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11136 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16902.879400 # Average number of references to valid blocks. +system.cpu.cpi 0.770563 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.770563 # CPI: Total CPI of All Threads +system.cpu.ipc 1.297753 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.297753 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3171957706 # number of integer regfile reads +system.cpu.int_regfile_writes 1803005697 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.misc_regfile_reads 1059979955 # number of misc regfile reads +system.cpu.icache.replacements 11725 # number of replacements +system.cpu.icache.tagsinuse 992.230576 # Cycle average of tags in use +system.cpu.icache.total_refs 210562203 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 13217 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15931.164636 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 963.166837 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.470296 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 188237743 # number of ReadReq hits -system.cpu.icache.demand_hits 188237743 # number of demand (read+write) hits -system.cpu.icache.overall_hits 188237743 # number of overall hits -system.cpu.icache.ReadReq_misses 255464 # number of ReadReq misses -system.cpu.icache.demand_misses 255464 # number of demand (read+write) misses -system.cpu.icache.overall_misses 255464 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1671443500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1671443500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1671443500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 188493207 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 188493207 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 188493207 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001355 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001355 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001355 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 6542.775107 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 6542.775107 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 6542.775107 # average overall miss latency +system.cpu.icache.occ_blocks::0 992.230576 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.484488 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 210569051 # number of ReadReq hits +system.cpu.icache.demand_hits 210569051 # number of demand (read+write) hits +system.cpu.icache.overall_hits 210569051 # number of overall hits +system.cpu.icache.ReadReq_misses 268229 # number of ReadReq misses +system.cpu.icache.demand_misses 268229 # number of demand (read+write) misses +system.cpu.icache.overall_misses 268229 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1801320500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1801320500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1801320500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 210837280 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 210837280 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 210837280 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001272 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001272 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001272 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6715.606814 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6715.606814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6715.606814 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,60 +306,60 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1428 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1428 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1428 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 254036 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 254036 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 254036 # number of overall MSHR misses +system.cpu.icache.writebacks 8 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1476 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1476 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1476 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 266753 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 266753 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 266753 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 873542000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 873542000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 873542000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 963323500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 963323500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 963323500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001348 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.001348 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.001348 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3438.654364 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3438.654364 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3438.654364 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.001265 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.001265 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.001265 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3611.293969 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3611.293969 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3611.293969 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2526737 # number of replacements -system.cpu.dcache.tagsinuse 4088.695382 # Cycle average of tags in use -system.cpu.dcache.total_refs 470726270 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2530833 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 185.996575 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2167120000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4088.695382 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.998217 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 321866059 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 147543837 # number of WriteReq hits -system.cpu.dcache.demand_hits 469409896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 469409896 # number of overall hits -system.cpu.dcache.ReadReq_misses 3006715 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1616364 # number of WriteReq misses -system.cpu.dcache.demand_misses 4623079 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4623079 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 47957140000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 38289086000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 86246226000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 86246226000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 324872774 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529482 # number of replacements +system.cpu.dcache.tagsinuse 4088.837997 # Cycle average of tags in use +system.cpu.dcache.total_refs 471282230 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533578 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 186.014494 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2156497000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4088.837997 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998251 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 322424417 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147507556 # number of WriteReq hits +system.cpu.dcache.demand_hits 469931973 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 469931973 # number of overall hits +system.cpu.dcache.ReadReq_misses 3022528 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1652645 # number of WriteReq misses +system.cpu.dcache.demand_misses 4675173 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4675173 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 48854800500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 39692092500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 88546893000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 88546893000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 325446945 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 474032975 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 474032975 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.009255 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010836 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.009753 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.009753 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 15950.011890 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23688.405582 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18655.581270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18655.581270 # average overall miss latency +system.cpu.dcache.demand_accesses 474607146 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 474607146 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.009287 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.011080 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.009851 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.009851 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16163.555970 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 24017.313156 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18939.810997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18939.810997 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,75 +368,75 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229867 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1247117 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 605322 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1852439 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1852439 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1759598 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1011042 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2770640 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2770640 # number of overall MSHR misses +system.cpu.dcache.writebacks 2230911 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1260687 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 634109 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1894796 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1894796 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1761841 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1018536 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2780377 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2780377 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14841801000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 18214921000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 33056722000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 33056722000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14865117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 18574591000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 33439708000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 33439708000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006778 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005845 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005845 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8434.768055 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18015.988455 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11931.078018 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11931.078018 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006828 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.005858 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005858 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8437.263635 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18236.558158 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12027.040937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12027.040937 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 574893 # number of replacements -system.cpu.l2cache.tagsinuse 21475.591540 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3187531 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 594020 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.366033 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 306954721000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7759.826991 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13715.764549 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.236811 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.418572 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1427752 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229874 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1226 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 528421 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1956173 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1956173 # number of overall hits -system.cpu.l2cache.ReadReq_misses 338145 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 241551 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247520 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 585665 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 585665 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11551149000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 10207000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8480925000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20032074000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20032074000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1765897 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229874 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 242777 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 775941 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2541838 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2541838 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191486 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.994950 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.318993 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230410 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230410 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34160.342457 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 42.256087 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.594861 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34203.980091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34203.980091 # average overall miss latency +system.cpu.l2cache.replacements 576328 # number of replacements +system.cpu.l2cache.tagsinuse 21485.488039 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3192646 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 595469 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.361565 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 312361641000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7744.786330 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13740.701709 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.236352 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.419333 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1431746 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2230919 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1301 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 527734 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1959480 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1959480 # number of overall hits +system.cpu.l2cache.ReadReq_misses 339175 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 252088 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 248002 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 587177 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 587177 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11584401000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 11543000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8495722000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20080123000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20080123000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1770921 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2230919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 253389 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 775736 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2546657 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2546657 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191525 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994866 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.319699 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230568 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230568 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34154.642883 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 45.789566 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34256.667285 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34197.734244 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34197.734244 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,32 +445,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 412030 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 338144 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 241551 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247520 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 585664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 585664 # number of overall MSHR misses +system.cpu.l2cache.writebacks 412300 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 339175 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 252088 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 248002 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 587177 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 587177 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10484231000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7489077000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7673754000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18157985000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18157985000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10515780500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7815593500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7689085500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18204866000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18204866000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191486 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994950 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318993 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230410 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230410 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.225584 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31004.123353 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31002.561409 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.099620 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.099620 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191525 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994866 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.319699 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230568 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230568 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.996462 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.433325 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.126983 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31004.051589 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31004.051589 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini index b61906e1d..c7fe40f76 100644 --- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/y/ksewell/cpu2000/binaries/alpha/tru64/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout index ae0215b03..9794df862 100755 --- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 09:22:03 -gem5 started Jun 19 2011 12:35:06 -gem5 executing on zooks -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/inorder-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:26 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 140230347500 because target called exit() +Exiting @ tick 139995113500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 9448fafb4..8f2720cda 100644 --- a/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.140230 # Number of seconds simulated -sim_ticks 140230347500 # Number of ticks simulated +sim_seconds 0.139995 # Number of seconds simulated +sim_ticks 139995113500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92522 # Simulator instruction rate (inst/s) -host_tick_rate 32544608 # Simulator tick rate (ticks/s) -host_mem_usage 159896 # Number of bytes of host memory used -host_seconds 4308.87 # Real time elapsed on the host +host_inst_rate 56567 # Simulator instruction rate (inst/s) +host_tick_rate 19864025 # Simulator tick rate (ticks/s) +host_mem_usage 252292 # Number of bytes of host memory used +host_seconds 7047.67 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 168277058 # DT system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 168277114 # DTB accesses -system.cpu.itb.fetch_hits 48911022 # ITB hits -system.cpu.itb.fetch_misses 44512 # ITB misses +system.cpu.itb.fetch_hits 48859849 # ITB hits +system.cpu.itb.fetch_misses 44521 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48955534 # ITB accesses +system.cpu.itb.fetch_accesses 48904370 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 280460696 # number of cpu cycles simulated +system.cpu.numCycles 279990228 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 280031759 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279561038 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 6816 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13555694 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266905002 # Number of cycles cpu stages are processed. -system.cpu.activity 95.166633 # Percentage of cycles cpu is active +system.cpu.timesIdled 6809 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13513618 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266476610 # Number of cycles cpu stages are processed. +system.cpu.activity 95.173539 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -61,79 +61,79 @@ system.cpu.comFloats 50439198 # Nu system.cpu.committedInsts 398664595 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions Simulated (Total) -system.cpu.cpi 0.703500 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.703500 # CPI: Total CPI of All Threads -system.cpu.ipc 1.421463 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads +system.cpu.ipc 1.423852 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.421463 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 53559776 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 30675983 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 15431294 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 36114910 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 15774675 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 8007515 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 43.679120 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 29804615 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 23755161 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280315566 # Number of Reads from Int. Register File +system.cpu.ipc_total 1.423852 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 53456377 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 30648707 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 15206922 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 35068414 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 15659516 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 44.654189 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 29689183 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 23767194 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280275252 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439651425 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119618904 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439611111 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119572386 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219815385 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100663476 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 168393095 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 14667100 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 763535 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 15430635 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 29156916 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 34.607496 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 205476801 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 219768867 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100597400 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 168369236 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 14604498 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 601765 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 15206263 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 29381288 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 34.104279 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 205417549 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 2124324 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 78228073 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 202232623 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.107296 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107968598 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172492098 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.503127 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 103201194 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177259502 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.202974 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181732278 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98728418 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.202230 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90865904 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189594792 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.601199 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 1967 # number of replacements -system.cpu.icache.tagsinuse 1829.231960 # Cycle average of tags in use -system.cpu.icache.total_refs 48906646 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3894 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12559.487930 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 78021134 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201969094 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.134337 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107567321 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172422907 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.581759 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102759298 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177230930 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.298970 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181219893 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98770335 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.276351 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90498113 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189492115 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.678117 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 1970 # number of replacements +system.cpu.icache.tagsinuse 1829.847469 # Cycle average of tags in use +system.cpu.icache.total_refs 48855472 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1829.231960 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.893180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 48906646 # number of ReadReq hits -system.cpu.icache.demand_hits 48906646 # number of demand (read+write) hits -system.cpu.icache.overall_hits 48906646 # number of overall hits -system.cpu.icache.ReadReq_misses 4375 # number of ReadReq misses -system.cpu.icache.demand_misses 4375 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4375 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 214226000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 214226000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 214226000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 48911021 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 48911021 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 48911021 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 48965.942857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 48965.942857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 48965.942857 # average overall miss latency +system.cpu.icache.occ_blocks::0 1829.847469 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.893480 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 48855472 # number of ReadReq hits +system.cpu.icache.demand_hits 48855472 # number of demand (read+write) hits +system.cpu.icache.overall_hits 48855472 # number of overall hits +system.cpu.icache.ReadReq_misses 4376 # number of ReadReq misses +system.cpu.icache.demand_misses 4376 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4376 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 214318500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 214318500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 214318500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 48859848 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 48859848 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 48859848 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000090 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000090 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000090 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 48975.891225 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 48975.891225 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 48975.891225 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -143,35 +143,35 @@ system.cpu.icache.avg_blocked_cycles::no_targets 45000 system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 481 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 481 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 481 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3894 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3894 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3894 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 479 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 479 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 479 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3897 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3897 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3897 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 185204000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 185204000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 185204000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 185285000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 185285000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 185285000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 47561.376477 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 47561.376477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 47561.376477 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 47545.547857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 47545.547857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3284.909965 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 3284.892021 # Cycle average of tags in use system.cpu.dcache.total_refs 168261959 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 40525.519990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3284.909965 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.801980 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3284.892021 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.801976 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 94753265 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 73508694 # number of WriteReq hits system.cpu.dcache.demand_hits 168261959 # number of demand (read+write) hits @@ -180,10 +180,10 @@ system.cpu.dcache.ReadReq_misses 1224 # nu system.cpu.dcache.WriteReq_misses 12035 # number of WriteReq misses system.cpu.dcache.demand_misses 13259 # number of demand (read+write) misses system.cpu.dcache.overall_misses 13259 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 63822000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 626725500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 690547500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 690547500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency 63830500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 626731500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 690562000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 690562000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses @@ -192,16 +192,16 @@ system.cpu.dcache.ReadReq_miss_rate 0.000013 # mi system.cpu.dcache.WriteReq_miss_rate 0.000164 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.000079 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 52142.156863 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52075.238887 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 52081.416396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 52081.416396 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 52149.101307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 52075.737432 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 52082.509993 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 52082.509993 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 82468000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82468500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1848 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44625.541126 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 649 # number of writebacks @@ -214,59 +214,59 @@ system.cpu.dcache.WriteReq_mshr_misses 3202 # nu system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 46179500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 169543500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 215723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 215723000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 46185000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 169537500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 215722500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 215722500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48610 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52949.250468 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51956.406551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51956.406551 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48615.789474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52947.376640 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51956.286127 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.tagsinuse 3899.405791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 727 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 4719 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.154058 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3900.004949 # Cycle average of tags in use +system.cpu.l2cache.total_refs 729 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4720 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.154449 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3528.869361 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 370.536429 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.107693 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3529.472340 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 370.532609 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.107711 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 656 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 658 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 649 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 716 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 716 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4185 # number of ReadReq misses +system.cpu.l2cache.demand_hits 718 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 718 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4186 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 3145 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7330 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7330 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 219146000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 164975000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 384121000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 384121000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4841 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 7331 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7331 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 219209500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 164966000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 384175500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 384175500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4844 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 649 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 3205 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8046 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8046 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.864491 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 8049 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8049 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.864162 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.981279 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.911012 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.911012 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52364.635603 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52456.279809 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52403.956344 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52403.956344 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.910796 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.910796 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52367.295748 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52453.418124 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52404.242259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52404.242259 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,24 +278,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4185 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 4186 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 3145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7330 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7330 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 7331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7331 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 168185500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 126767000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 294952500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 294952500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 168226500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 126764000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 294990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 294990500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864491 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864162 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981279 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.911012 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.911012 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.694146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40307.472178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40239.085948 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40239.085948 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.910796 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.910796 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index b5728d762..eb7300ec9 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr index ea7dd73a3..860580eeb 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr @@ -1,11 +1,7 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera @@ -53,5 +49,4 @@ Writing to chair.cook.ppm 13 8 14 14 8 14 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 1209b95f2..49472bb38 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,18 +1,14 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:29:56 -M5 started Apr 21 2011 13:02:51 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:09:26 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. -OO-style eon Time= 0.100000 -Exiting @ tick 113012733500 because target called exit() +OO-style eon Time= 0.083333 +Exiting @ tick 90884909500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index d0a61b61f..1cdac8523 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,504 +1,506 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 199356 # Simulator instruction rate (inst/s) -host_mem_usage 214136 # Number of bytes of host memory used -host_seconds 1883.94 # Real time elapsed on the host -host_tick_rate 59987309 # Simulator tick rate (ticks/s) +sim_seconds 0.090885 # Number of seconds simulated +sim_ticks 90884909500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574812 # Number of instructions simulated -sim_seconds 0.113013 # Number of seconds simulated -sim_ticks 113012733500 # Number of ticks simulated +host_inst_rate 96810 # Simulator instruction rate (inst/s) +host_tick_rate 23426991 # Simulator tick rate (ticks/s) +host_mem_usage 252820 # Number of bytes of host memory used +host_seconds 3879.50 # Real time elapsed on the host +sim_insts 375574794 # Number of instructions simulated +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 105630800 # DTB read hits +system.cpu.dtb.read_misses 100510 # DTB read misses +system.cpu.dtb.read_acv 48612 # DTB read access violations +system.cpu.dtb.read_accesses 105731310 # DTB read accesses +system.cpu.dtb.write_hits 79936147 # DTB write hits +system.cpu.dtb.write_misses 1547 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 79937694 # DTB write accesses +system.cpu.dtb.data_hits 185566947 # DTB hits +system.cpu.dtb.data_misses 102057 # DTB misses +system.cpu.dtb.data_acv 48612 # DTB access violations +system.cpu.dtb.data_accesses 185669004 # DTB accesses +system.cpu.itb.fetch_hits 58326026 # ITB hits +system.cpu.itb.fetch_misses 337 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 58326363 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.numCycles 181769821 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 57225452 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 33446848 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3610875 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 40879451 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 32187006 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 30270394 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 39807126 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1409 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5223677 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 31927422 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 56786170 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 11422526 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 5219312 # The number of times a branch was mispredicted -system.cpu.commit.branches 44587533 # Number of branches committed -system.cpu.commit.bw_lim_events 16035403 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions +system.cpu.BPredUnit.usedRAS 10725194 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1200 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 60337386 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 506200677 # Number of instructions fetch has processed +system.cpu.fetch.Branches 57225452 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42912200 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 94142068 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13173843 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 17624322 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7572 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 58326026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1118192 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 181648006 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.786712 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.242035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 87505938 48.17% 48.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8084169 4.45% 52.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9812284 5.40% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6556715 3.61% 61.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 13799395 7.60% 69.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9400037 5.17% 74.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5907170 3.25% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3477374 1.91% 79.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 37104924 20.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 181648006 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.314824 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.784844 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 66587043 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13622871 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 88021771 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3884112 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9532209 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 10337474 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4322 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 494122650 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12073 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9532209 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 71008708 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4690007 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 394366 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 87374252 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8648464 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 480990212 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42769 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7153610 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 312500874 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 630714726 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 332574792 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 298139934 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 52968555 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 38325 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 292 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 23912108 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 111095455 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 85873017 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14526105 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8463039 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 435543273 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 257 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 420425800 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1773859 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 58536245 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 32877731 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 42 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 181648006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.314508 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.994579 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 45216412 24.89% 24.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 30232996 16.64% 41.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 28617209 15.75% 57.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25676408 14.14% 71.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23156698 12.75% 84.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15699012 8.64% 92.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7807681 4.30% 97.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3971496 2.19% 99.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1270094 0.70% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 181648006 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 135221 1.15% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.15% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 39442 0.34% 1.49% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 7017 0.06% 1.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 13904 0.12% 1.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 2001949 17.09% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 880826 7.52% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5776712 49.33% 75.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2855706 24.39% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 164795138 39.20% 39.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2124451 0.51% 39.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 34088388 8.11% 47.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8064196 1.92% 49.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3086941 0.73% 50.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16853454 4.01% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1579988 0.38% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 108302425 25.76% 80.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 81497238 19.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 420425800 # Type of FU issued +system.cpu.iq.rate 2.312957 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11710777 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027855 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 685991050 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 291244200 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 242469849 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 349993192 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 202862270 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 165589366 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253586541 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 178516455 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13913922 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 16340969 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 171857 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 26790 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12352289 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 176199 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 9532209 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2220194 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 306578 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 461167180 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2274758 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 111095455 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 85873017 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 257 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 130 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26790 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3503569 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 569738 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 4073307 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 411738121 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 105779948 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8687679 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 25623650 # number of nop insts executed +system.cpu.iew.exec_refs 185717662 # number of memory reference insts executed +system.cpu.iew.exec_branches 48391334 # Number of branches executed +system.cpu.iew.exec_stores 79937714 # Number of stores executed +system.cpu.iew.exec_rate 2.265162 # Inst execution rate +system.cpu.iew.wb_sent 409282340 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 408059215 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198971045 # num instructions producing a value +system.cpu.iew.wb_consumers 279819296 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 2.244923 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.711070 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 62502516 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 56265161 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 216073988 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.845037 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.480996 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3606605 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 172115797 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.316258 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.838436 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 99774969 46.18% 46.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 35667629 16.51% 62.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 19281907 8.92% 71.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 16238513 7.52% 79.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11569134 5.35% 84.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7732170 3.58% 88.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5922846 2.74% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3851417 1.78% 92.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16035403 7.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71294232 41.42% 41.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 26334848 15.30% 56.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15061233 8.75% 65.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13435550 7.81% 73.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8560921 4.97% 78.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6120977 3.56% 81.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5034670 2.93% 84.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3342912 1.94% 86.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22930454 13.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 216073988 # Number of insts commited each cycle -system.cpu.commit.count 398664587 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 172115797 # Number of insts commited each cycle +system.cpu.commit.count 398664569 # Number of instructions committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 168275214 # Number of memory references committed +system.cpu.commit.loads 94754486 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 44587530 # Number of branches committed system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. +system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.int_insts 316365844 # Number of committed integer instructions. -system.cpu.commit.loads 94754489 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 168275218 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.committedInsts 375574812 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated -system.cpu.cpi 0.601812 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.601812 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 93199835 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33131.956912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31878.172589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 93198164 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 55363500 # number of ReadReq miss cycles +system.cpu.commit.bw_lim_events 22930454 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 610349451 # The number of ROB reads +system.cpu.rob.rob_writes 931879411 # The number of ROB writes +system.cpu.timesIdled 2704 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 121815 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 375574794 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated +system.cpu.cpi 0.483978 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.483978 # CPI: Total CPI of All Threads +system.cpu.ipc 2.066211 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.066211 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 410939724 # number of integer regfile reads +system.cpu.int_regfile_writes 176360806 # number of integer regfile writes +system.cpu.fp_regfile_reads 160541736 # number of floating regfile reads +system.cpu.fp_regfile_writes 106688075 # number of floating regfile writes +system.cpu.misc_regfile_reads 350572 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.icache.replacements 2140 # number of replacements +system.cpu.icache.tagsinuse 1834.625402 # Cycle average of tags in use +system.cpu.icache.total_refs 58320710 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4067 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14339.982788 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1834.625402 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.895813 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 58320710 # number of ReadReq hits +system.cpu.icache.demand_hits 58320710 # number of demand (read+write) hits +system.cpu.icache.overall_hits 58320710 # number of overall hits +system.cpu.icache.ReadReq_misses 5316 # number of ReadReq misses +system.cpu.icache.demand_misses 5316 # number of demand (read+write) misses +system.cpu.icache.overall_misses 5316 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 168223000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 168223000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 168223000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 58326026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 58326026 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 58326026 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 31644.657637 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 31644.657637 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 31644.657637 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 1249 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1249 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1249 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 4067 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 4067 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 4067 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 123582000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 123582000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 123582000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000070 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000070 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30386.525695 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30386.525695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30386.525695 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 788 # number of replacements +system.cpu.dcache.tagsinuse 3295.374104 # Cycle average of tags in use +system.cpu.dcache.total_refs 165040256 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4187 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 39417.304992 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 3295.374104 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.804535 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 91538987 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 73501262 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 165040249 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 165040249 # number of overall hits +system.cpu.dcache.ReadReq_misses 1683 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19466 # number of WriteReq misses +system.cpu.dcache.demand_misses 21149 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 21149 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 56075000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 568706500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 624781500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 624781500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 91540670 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 73520728 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 165061398 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 165061398 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1671 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 686 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 31400000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30218.957186 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35474.663747 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73502931 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 537837000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000242 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 17798 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 14601 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 113412500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3197 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 39861.573171 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate 0.000265 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33318.478907 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 29215.375527 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 29541.893234 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 29541.893234 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 166720564 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30468.976321 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency -system.cpu.dcache.demand_hits 166701095 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 593200500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses -system.cpu.dcache.demand_misses 19469 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 15287 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 144812500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.writebacks 662 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 689 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16273 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 16962 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 16962 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 994 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4187 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4187 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 31676000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 113165000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 144841000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 144841000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 3293.121210 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.803985 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 166720564 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30468.976321 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34627.570540 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 166701095 # number of overall hits -system.cpu.dcache.overall_miss_latency 593200500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses -system.cpu.dcache.overall_misses 19469 # number of overall misses -system.cpu.dcache.overall_mshr_hits 15287 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 144812500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 786 # number of replacements -system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31867.203219 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35441.590980 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34593.026033 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34593.026033 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3293.121210 # Cycle average of tags in use -system.cpu.dcache.total_refs 166701099 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 664 # number of writebacks -system.cpu.decode.BlockedCycles 5613634 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 4438 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 10679460 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 490538381 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 118863884 # Number of cycles decode is idle -system.cpu.decode.RunCycles 90994213 # Number of cycles decode is running -system.cpu.decode.SquashCycles 9813191 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 13275 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 602257 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 183645342 # DTB accesses -system.cpu.dtb.data_acv 48603 # DTB access violations -system.cpu.dtb.data_hits 183566296 # DTB hits -system.cpu.dtb.data_misses 79046 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 103678274 # DTB read accesses -system.cpu.dtb.read_acv 48603 # DTB read access violations -system.cpu.dtb.read_hits 103600815 # DTB read hits -system.cpu.dtb.read_misses 77459 # DTB read misses -system.cpu.dtb.write_accesses 79967068 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 79965481 # DTB write hits -system.cpu.dtb.write_misses 1587 # DTB write misses -system.cpu.fetch.Branches 56786170 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 58423687 # Number of cache lines fetched -system.cpu.fetch.Cycles 93710532 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1318185 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 502037270 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 304 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 5229387 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.251238 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 58423687 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 41692920 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.221154 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 225887179 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.222513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.113255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132176647 58.51% 58.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9507177 4.21% 62.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 8947595 3.96% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6461834 2.86% 69.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 13588400 6.02% 75.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8169586 3.62% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6674990 2.96% 82.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2889669 1.28% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 37471281 16.59% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 225887179 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 159270832 # number of floating regfile reads -system.cpu.fp_regfile_writes 104392422 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 58423687 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 32309.424084 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30830.816483 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 58418912 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 154277500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4775 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 868 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120456000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000067 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3907 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 14952.370617 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 58423687 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 32309.424084 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency -system.cpu.icache.demand_hits 58418912 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 154277500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000082 # miss rate for demand accesses -system.cpu.icache.demand_misses 4775 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 868 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120456000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000067 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3907 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 1823.959859 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.890605 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 58423687 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 32309.424084 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30830.816483 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 58418912 # number of overall hits -system.cpu.icache.overall_miss_latency 154277500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000082 # miss rate for overall accesses -system.cpu.icache.overall_misses 4775 # number of overall misses -system.cpu.icache.overall_mshr_hits 868 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120456000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000067 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3907 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1986 # number of replacements -system.cpu.icache.sampled_refs 3907 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1823.959859 # Cycle average of tags in use -system.cpu.icache.total_refs 58418912 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 138291 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 5625617 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 48687009 # Number of branches executed -system.cpu.iew.exec_nop 26082950 # number of nop insts executed -system.cpu.iew.exec_rate 1.805331 # Inst execution rate -system.cpu.iew.exec_refs 183693980 # number of memory reference insts executed -system.cpu.iew.exec_stores 79967080 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 1911401 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 106982646 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6012421 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 86376940 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 454930236 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 103726900 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9802128 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 408050842 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 63 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 51 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9813191 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 192371 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 10208559 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 208520 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 5629 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 192417 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 12228157 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 12856211 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5629 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 886790 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4738827 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 258989364 # num instructions consuming a value -system.cpu.iew.wb_count 404042671 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.726642 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 188192474 # num instructions producing a value -system.cpu.iew.wb_rate 1.787598 # insts written-back per cycle -system.cpu.iew.wb_sent 405020447 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 406883956 # number of integer regfile reads -system.cpu.int_regfile_writes 173490032 # number of integer regfile writes -system.cpu.ipc 1.661648 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.661648 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 165161738 39.53% 39.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2124398 0.51% 40.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 40.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33524704 8.02% 48.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7711996 1.85% 49.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2967896 0.71% 50.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16674434 3.99% 54.61% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1571336 0.38% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105669831 25.29% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 82413056 19.72% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 417852970 # Type of FU issued -system.cpu.iq.fp_alu_accesses 175354000 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 344883249 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 164390765 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 192579711 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 10358398 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024790 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4298 0.04% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 768 0.01% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 7 0.00% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 10130 0.10% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1743113 16.83% 16.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 627758 6.06% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5427565 52.40% 75.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2544759 24.57% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 252823787 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 727796795 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 239651906 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 283872417 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 428847047 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 417852970 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 47599271 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 728527 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 28893091 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 225887179 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.849830 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.928832 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 80384230 35.59% 35.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 40475639 17.92% 53.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 30160734 13.35% 66.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 26305410 11.65% 78.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21278104 9.42% 87.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14868616 6.58% 94.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9130443 4.04% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2370545 1.05% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 913458 0.40% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 225887179 # Number of insts issued each cycle -system.cpu.iq.rate 1.848699 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 58423991 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 58423687 # ITB hits -system.cpu.itb.fetch_misses 304 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 3201 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.558495 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31458.559133 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 64 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 108554500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.980006 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3137 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 98685500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980006 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4888 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34349.065531 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31163.354625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 661 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 145193500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.864771 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4227 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 131727500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864771 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4227 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 664 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 664 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.153637 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 10 # number of replacements +system.cpu.l2cache.tagsinuse 4007.918811 # Cycle average of tags in use +system.cpu.l2cache.total_refs 828 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 4847 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.170827 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 3630.264414 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 377.654397 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.110787 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011525 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 755 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 817 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 817 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4306 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 3131 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 7437 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7437 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 148211500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 108422000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 256633500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 256633500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 5061 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 3193 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8254 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8254 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.850820 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.980583 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.901018 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.901018 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34419.763121 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34628.553178 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34507.664381 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34507.664381 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8089 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34457.903313 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 725 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 253748000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.910372 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7364 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 230413000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.910372 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7364 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 3557.826949 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 379.777727 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.108576 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011590 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 8089 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34457.903313 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31289.109180 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 725 # number of overall hits -system.cpu.l2cache.overall_miss_latency 253748000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.910372 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7364 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 230413000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.910372 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7364 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 4306 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 3131 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 7437 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 14 # number of replacements -system.cpu.l2cache.sampled_refs 4771 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 134349000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 98553500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 232902500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 232902500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.850820 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980583 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.901018 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.901018 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31200.418021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31476.684765 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31316.727175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31316.727175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3937.604676 # Cycle average of tags in use -system.cpu.l2cache.total_refs 733 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 7819910 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6085624 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 106982646 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 86376940 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 350572 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 226025470 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 3360184 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 259532333 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 311 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 122116498 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 1529212 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 625408393 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 477751875 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 306658733 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 88296359 # Number of cycles rename is running -system.cpu.rename.SquashCycles 9813191 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 1960754 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 47126400 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 292973848 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 332434545 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 340193 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 36156 # count of serializing insts renamed -system.cpu.rename.skidInsts 5383709 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 253 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 654965356 # The number of ROB reads -system.cpu.rob.rob_writes 919674888 # The number of ROB writes -system.cpu.timesIdled 3011 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini index b2f50f12f..00bbabd01 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/30.eon/ref/arm/linux/o3-timing/simerr index 0de362399..bf930ad43 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simerr +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simerr @@ -1,5 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/30.eon/ref/arm/linux/o3-timing/simout index 62ab94a46..fb668f921 100755 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 19:29:23 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 02:03:43 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -18,5 +12,5 @@ Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.110000 -Exiting @ tick 117852123500 because target called exit() +OO-style eon Time= 0.100000 +Exiting @ tick 108112565000 because target called exit() diff --git a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt index 48dd38840..467f5453a 100644 --- a/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.117852 # Number of seconds simulated -sim_ticks 117852123500 # Number of ticks simulated +sim_seconds 0.108113 # Number of seconds simulated +sim_ticks 108112565000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49475 # Simulator instruction rate (inst/s) -host_tick_rate 16703679 # Simulator tick rate (ticks/s) -host_mem_usage 264264 # Number of bytes of host memory used -host_seconds 7055.46 # Real time elapsed on the host -sim_insts 349066258 # Number of instructions simulated +host_inst_rate 68175 # Simulator instruction rate (inst/s) +host_tick_rate 21114970 # Simulator tick rate (ticks/s) +host_mem_usage 266872 # Number of bytes of host memory used +host_seconds 5120.19 # Real time elapsed on the host +sim_insts 349066124 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,103 +51,106 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 235704248 # number of cpu cycles simulated +system.cpu.numCycles 216225131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 37732885 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 20795463 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3471100 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 27302215 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 21001151 # Number of BTB hits +system.cpu.BPredUnit.lookups 38871530 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21265030 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3261176 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 27909151 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 21653043 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7420100 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72463 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 39991725 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 328152707 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37732885 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 28421251 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 76800425 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3608252 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 39991725 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 624732 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 235576888 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.817631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.040837 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 7689864 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 61658 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 44557213 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 344579360 # Number of instructions fetch has processed +system.cpu.fetch.Branches 38871530 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 29342907 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80636459 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11681756 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 82619379 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 42088076 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 916191 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 216112788 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.095569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.185948 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 159366483 67.65% 67.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9270231 3.94% 71.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5914286 2.51% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6643493 2.82% 76.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5462624 2.32% 79.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4799627 2.04% 81.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3754754 1.59% 82.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4137731 1.76% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36227659 15.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136175266 63.01% 63.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 9565429 4.43% 67.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6238703 2.89% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6748883 3.12% 73.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5364932 2.48% 75.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4989535 2.31% 78.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3875216 1.79% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4307528 1.99% 82.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 38847296 17.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 235576888 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160086 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.392222 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84492760 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69387883 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 73181829 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1548924 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6965492 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7488186 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 73175 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 420043685 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 215754 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6965492 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 90152933 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 976284 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57875196 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 69216447 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10390536 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 409431138 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 10006 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5114847 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 42 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 449313195 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2409887049 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1322854173 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1087032876 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384568949 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 64744241 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3898927 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3897858 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35694607 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106772052 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 90018438 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11281294 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21363407 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384862513 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3813526 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 372770888 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1408906 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 37984896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 125485450 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 258042 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 235576888 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.582375 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.822791 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 216112788 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.179773 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.593614 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 53033788 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 77116773 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 73749422 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3985890 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8226915 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7647714 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 72935 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 439814331 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 207402 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8226915 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 61196526 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1203573 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 59638529 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 69748798 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 16098447 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 424223689 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 22825 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 9278494 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 99 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 462213475 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2492907388 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1378161419 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1114745969 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384568743 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 77644727 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3986897 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4043470 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 51924156 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 109846529 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 95332472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14399866 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29809960 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 399729408 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3865767 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 378419662 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1473555 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 54144389 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 177169340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 310299 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 216112788 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.751029 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.895618 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 95699423 40.62% 40.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 48065676 20.40% 61.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 27569248 11.70% 72.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20762200 8.81% 81.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21955543 9.32% 90.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12942689 5.49% 96.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5977724 2.54% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1956925 0.83% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 647460 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82036681 37.96% 37.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 39071702 18.08% 56.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 28236809 13.07% 69.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20423013 9.45% 78.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 23529038 10.89% 89.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13145418 6.08% 95.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6683366 3.09% 98.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2232223 1.03% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 754538 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 235576888 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 216112788 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2414 0.02% 0.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2198 0.02% 0.02% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 5043 0.04% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available @@ -167,181 +170,181 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 11301 0.09% 0.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 9996 0.08% 0.14% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 197 0.00% 0.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 1510 0.01% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.15% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 142649 1.07% 1.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 1224 0.01% 1.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 303363 2.28% 3.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7115466 53.58% 57.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5697057 42.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 2604 0.02% 0.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 194 0.00% 0.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 114242 0.95% 1.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 418 0.00% 1.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 276715 2.30% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7458735 61.87% 65.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4186007 34.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126467737 33.93% 33.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2147032 0.58% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6836061 1.83% 36.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8620472 2.31% 38.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3526603 0.95% 39.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1580695 0.42% 40.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21030277 5.64% 45.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7283358 1.95% 47.61% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7262499 1.95% 49.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102234129 27.43% 77.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85606734 22.96% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 130620873 34.52% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2147251 0.57% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 20 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 35.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6800768 1.80% 36.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8475274 2.24% 39.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3501119 0.93% 40.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1584837 0.42% 40.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21128819 5.58% 46.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7289356 1.93% 47.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7313976 1.93% 49.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175288 0.05% 49.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102741469 27.15% 77.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 86640612 22.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 372770888 # Type of FU issued -system.cpu.iq.rate 1.581520 # Inst issue rate -system.cpu.iq.fu_busy_cnt 13280227 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035626 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 746488455 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 293551634 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 247041034 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249319342 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 133204458 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118172579 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258240891 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 127810224 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4605348 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 378419662 # Type of FU issued +system.cpu.iq.rate 1.750119 # Inst issue rate +system.cpu.iq.fu_busy_cnt 12056154 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.031859 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 736575285 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 322046718 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 251010826 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249906536 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 135772025 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118653498 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262435143 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128040673 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5198793 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12123008 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25231 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 199737 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7642570 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15197510 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2287 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 168315 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12956623 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 301 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 168 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 309 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6965492 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10869 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 480 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 388723243 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6854795 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106772052 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 90018438 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3802280 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 341 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 199737 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3305937 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 361135 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3667072 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 368528754 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101011008 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4242134 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8226915 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 19822 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 465 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 403642432 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2591477 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 109846529 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 95332472 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3854525 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 191 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 168315 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3199953 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 312751 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3512704 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 372398400 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101298405 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6021262 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 47204 # number of nop insts executed -system.cpu.iew.exec_refs 185554303 # number of memory reference insts executed -system.cpu.iew.exec_branches 31933479 # Number of branches executed -system.cpu.iew.exec_stores 84543295 # Number of stores executed -system.cpu.iew.exec_rate 1.563522 # Inst execution rate -system.cpu.iew.wb_sent 365991200 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 365213613 # cumulative count of insts written-back -system.cpu.iew.wb_producers 165367337 # num instructions producing a value -system.cpu.iew.wb_consumers 317313225 # num instructions consuming a value +system.cpu.iew.exec_nop 47257 # number of nop insts executed +system.cpu.iew.exec_refs 186410418 # number of memory reference insts executed +system.cpu.iew.exec_branches 32413413 # Number of branches executed +system.cpu.iew.exec_stores 85112013 # Number of stores executed +system.cpu.iew.exec_rate 1.722272 # Inst execution rate +system.cpu.iew.wb_sent 370241650 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 369664324 # cumulative count of insts written-back +system.cpu.iew.wb_producers 175377527 # num instructions producing a value +system.cpu.iew.wb_consumers 344318453 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.549457 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.521149 # average fanout of values written-back +system.cpu.iew.wb_rate 1.709627 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.509347 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 349066870 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 39653224 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3555484 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3440231 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 228611397 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.526901 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.127678 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 349066736 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 54571176 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3555468 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 3230397 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 207885874 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.679127 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.249386 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102653839 44.90% 44.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 52967573 23.17% 68.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 21494828 9.40% 77.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 16426131 7.19% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11610822 5.08% 89.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6946497 3.04% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3261718 1.43% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2914745 1.27% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10335244 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88802662 42.72% 42.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 47260336 22.73% 65.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 19727320 9.49% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 15331284 7.37% 82.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11254360 5.41% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7570851 3.64% 91.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3388756 1.63% 93.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3248763 1.56% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11301542 5.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 228611397 # Number of insts commited each cycle -system.cpu.commit.count 349066870 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 207885874 # Number of insts commited each cycle +system.cpu.commit.count 349066736 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177024911 # Number of memory references committed -system.cpu.commit.loads 94649043 # Number of loads committed +system.cpu.commit.refs 177024867 # Number of memory references committed +system.cpu.commit.loads 94649018 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30521922 # Number of branches committed +system.cpu.commit.branches 30521897 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279586109 # Number of committed integer instructions. +system.cpu.commit.int_insts 279586001 # Number of committed integer instructions. system.cpu.commit.function_calls 6225114 # Number of function calls committed. -system.cpu.commit.bw_lim_events 10335244 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 11301542 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 606993724 # The number of ROB reads -system.cpu.rob.rob_writes 784416922 # The number of ROB writes -system.cpu.timesIdled 2785 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 127360 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 349066258 # Number of Instructions Simulated -system.cpu.committedInsts_total 349066258 # Number of Instructions Simulated -system.cpu.cpi 0.675242 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.675242 # CPI: Total CPI of All Threads -system.cpu.ipc 1.480950 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.480950 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1759160975 # number of integer regfile reads -system.cpu.int_regfile_writes 232094825 # number of integer regfile writes -system.cpu.fp_regfile_reads 189729002 # number of floating regfile reads -system.cpu.fp_regfile_writes 134274190 # number of floating regfile writes -system.cpu.misc_regfile_reads 986066945 # number of misc regfile reads -system.cpu.misc_regfile_writes 34422257 # number of misc regfile writes -system.cpu.icache.replacements 13781 # number of replacements -system.cpu.icache.tagsinuse 1824.800983 # Cycle average of tags in use -system.cpu.icache.total_refs 39975644 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15643 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2555.497283 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 600219721 # The number of ROB reads +system.cpu.rob.rob_writes 815506085 # The number of ROB writes +system.cpu.timesIdled 2585 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 112343 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 349066124 # Number of Instructions Simulated +system.cpu.committedInsts_total 349066124 # Number of Instructions Simulated +system.cpu.cpi 0.619439 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.619439 # CPI: Total CPI of All Threads +system.cpu.ipc 1.614364 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.614364 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1775936880 # number of integer regfile reads +system.cpu.int_regfile_writes 235580324 # number of integer regfile writes +system.cpu.fp_regfile_reads 189945628 # number of floating regfile reads +system.cpu.fp_regfile_writes 134544688 # number of floating regfile writes +system.cpu.misc_regfile_reads 1009447373 # number of misc regfile reads +system.cpu.misc_regfile_writes 34422229 # number of misc regfile writes +system.cpu.icache.replacements 14157 # number of replacements +system.cpu.icache.tagsinuse 1842.318723 # Cycle average of tags in use +system.cpu.icache.total_refs 42071371 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16032 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2624.212263 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1824.800983 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.891016 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 39975644 # number of ReadReq hits -system.cpu.icache.demand_hits 39975644 # number of demand (read+write) hits -system.cpu.icache.overall_hits 39975644 # number of overall hits -system.cpu.icache.ReadReq_misses 16081 # number of ReadReq misses -system.cpu.icache.demand_misses 16081 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16081 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 189840000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 189840000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 189840000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 39991725 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 39991725 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 39991725 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000402 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000402 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000402 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 11805.235993 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 11805.235993 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 11805.235993 # average overall miss latency +system.cpu.icache.occ_blocks::0 1842.318723 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.899570 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 42071371 # number of ReadReq hits +system.cpu.icache.demand_hits 42071371 # number of demand (read+write) hits +system.cpu.icache.overall_hits 42071371 # number of overall hits +system.cpu.icache.ReadReq_misses 16705 # number of ReadReq misses +system.cpu.icache.demand_misses 16705 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16705 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 202344500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 202344500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 202344500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 42088076 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 42088076 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 42088076 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000397 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000397 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000397 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 12112.810536 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 12112.810536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 12112.810536 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,142 +354,142 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 435 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 435 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 15646 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 15646 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 15646 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 669 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 669 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 669 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 16036 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 16036 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 16036 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 131146500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 131146500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 131146500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 136366000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 136366000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 136366000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000391 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000391 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000391 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 8382.110444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 8382.110444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 8382.110444 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000381 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000381 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000381 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8503.741581 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8503.741581 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8503.741581 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1396 # number of replacements -system.cpu.dcache.tagsinuse 3097.520126 # Cycle average of tags in use -system.cpu.dcache.total_refs 178371323 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4582 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 38928.704278 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1406 # number of replacements +system.cpu.dcache.tagsinuse 3100.332801 # Cycle average of tags in use +system.cpu.dcache.total_refs 178043182 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4595 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 38747.156039 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 3097.520126 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.756230 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 96315033 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 82033723 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 11410 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11146 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 178348756 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 178348756 # number of overall hits -system.cpu.dcache.ReadReq_misses 3256 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 18976 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 3100.332801 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.756917 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 95986293 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 82033252 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 12491 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 11132 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 178019545 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 178019545 # number of overall hits +system.cpu.dcache.ReadReq_misses 3385 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 19442 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 22232 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 22232 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 108888000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 618616000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 22827 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 22827 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 112128500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 646930500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 727504000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 727504000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 96318289 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11412 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11146 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 178370988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 178370988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000034 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000231 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000175 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33442.260442 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32599.915683 # average WriteReq miss latency +system.cpu.dcache.demand_miss_latency 759059000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 759059000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 95989678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 82052694 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses 12493 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 11132 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 178042372 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 178042372 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000035 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000237 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000160 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33125.110783 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33274.894558 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32723.281756 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32723.281756 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33252.683226 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33252.683226 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 288500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 308500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26227.272727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28045.454545 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1019 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1507 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 16140 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 1025 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1630 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 16598 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 17647 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 17647 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1749 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 2836 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 4585 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 4585 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 18228 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 18228 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1755 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 2844 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 4599 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 4599 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 54106000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 100544000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 154650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 154650000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 53650500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 101058500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 154709000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 154709000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30935.391652 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35452.750353 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33729.552890 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33729.552890 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30570.085470 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35533.931083 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33639.704284 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33639.704284 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 54 # number of replacements -system.cpu.l2cache.tagsinuse 3793.062863 # Cycle average of tags in use -system.cpu.l2cache.total_refs 13102 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 5236 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.502292 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 59 # number of replacements +system.cpu.l2cache.tagsinuse 3910.187993 # Cycle average of tags in use +system.cpu.l2cache.total_refs 13367 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 5367 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.490591 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3424.878969 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 368.183894 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.104519 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.011236 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 13017 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1019 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 3537.549748 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 372.638245 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.107957 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.011372 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 13284 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1025 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 13034 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 13034 # number of overall hits -system.cpu.l2cache.ReadReq_misses 4374 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 3 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 2816 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 7190 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 7190 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 150210000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 96886500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 247096500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 247096500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 17391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1019 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 3 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 2833 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 20224 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 20224 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.251509 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_hits 13301 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 13301 # number of overall hits +system.cpu.l2cache.ReadReq_misses 4501 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 2824 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 7325 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 7325 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 154458500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 97367500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 251826000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 251826000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 17785 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1025 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 4 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 2841 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 20626 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 20626 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.253078 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.993999 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.355518 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.355518 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34341.563786 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34405.717330 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34366.689847 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34366.689847 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.994016 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.355134 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.355134 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34316.485226 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34478.576487 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34378.976109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34378.976109 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,31 +499,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 51 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 4323 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 2816 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 7139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 7139 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 4447 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 2824 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 7271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 7271 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 134686000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 93000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 88056000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 222742000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 222742000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 138555000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 88338500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 226893500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 226893500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.248577 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250042 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993999 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.352996 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.352996 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31155.678927 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994016 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.352516 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.352516 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.959748 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31269.886364 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31200.728393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31200.728393 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31281.338527 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.267501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.267501 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index f5ffa5534..19cfbefe1 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 07cbaf4f4..973e6058b 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 10:33:23 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:14:22 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 689104583500 because target called exit() +Exiting @ tick 643278327500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 04c2afe0b..9f87a64ab 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.689105 # Number of seconds simulated -sim_ticks 689104583500 # Number of ticks simulated +sim_seconds 0.643278 # Number of seconds simulated +sim_ticks 643278327500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190198 # Simulator instruction rate (inst/s) -host_tick_rate 71894197 # Simulator tick rate (ticks/s) -host_mem_usage 200384 # Number of bytes of host memory used -host_seconds 9584.98 # Real time elapsed on the host +host_inst_rate 72554 # Simulator instruction rate (inst/s) +host_tick_rate 25601460 # Simulator tick rate (ticks/s) +host_mem_usage 253232 # Number of bytes of host memory used +host_seconds 25126.63 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 514070459 # DTB read hits -system.cpu.dtb.read_misses 615925 # DTB read misses +system.cpu.dtb.read_hits 519966765 # DTB read hits +system.cpu.dtb.read_misses 661962 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 514686384 # DTB read accesses -system.cpu.dtb.write_hits 251680293 # DTB write hits -system.cpu.dtb.write_misses 42864 # DTB write misses +system.cpu.dtb.read_accesses 520628727 # DTB read accesses +system.cpu.dtb.write_hits 283803273 # DTB write hits +system.cpu.dtb.write_misses 53019 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 251723157 # DTB write accesses -system.cpu.dtb.data_hits 765750752 # DTB hits -system.cpu.dtb.data_misses 658789 # DTB misses +system.cpu.dtb.write_accesses 283856292 # DTB write accesses +system.cpu.dtb.data_hits 803770038 # DTB hits +system.cpu.dtb.data_misses 714981 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 766409541 # DTB accesses -system.cpu.itb.fetch_hits 343698672 # ITB hits -system.cpu.itb.fetch_misses 197 # ITB misses +system.cpu.dtb.data_accesses 804485019 # DTB accesses +system.cpu.itb.fetch_hits 398172437 # ITB hits +system.cpu.itb.fetch_misses 227 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 343698869 # ITB accesses +system.cpu.itb.fetch_accesses 398172664 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1378209168 # number of cpu cycles simulated +system.cpu.numCycles 1286556656 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 342127414 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 229155282 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 28355376 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 286093994 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 234435463 # Number of BTB hits +system.cpu.BPredUnit.lookups 402336394 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 266883320 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 28923526 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 333487818 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 271623617 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 49327534 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 847 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 343698672 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2972544545 # Number of instructions fetch has processed -system.cpu.fetch.Branches 342127414 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 283762997 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 569144710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28790520 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 197 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 343698672 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4322809 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1378074830 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.157027 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.030206 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 61006515 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1123 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 414972341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3352664907 # Number of instructions fetch has processed +system.cpu.fetch.Branches 402336394 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 332630132 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 645381442 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 165705235 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 89720860 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 148 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 4171 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 398172437 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11167265 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1286425438 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.606187 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.132190 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 808930120 58.70% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53203120 3.86% 62.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38710034 2.81% 65.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 60833254 4.41% 69.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 120527197 8.75% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36009747 2.61% 81.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37301448 2.71% 83.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7023896 0.51% 84.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 215536014 15.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 641043996 49.83% 49.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57060222 4.44% 54.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45200815 3.51% 57.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 74446189 5.79% 63.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 134854552 10.48% 74.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 43347618 3.37% 77.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 44933428 3.49% 80.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8201322 0.64% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 237337296 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1378074830 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248241 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.156817 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 703418574 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 27367471 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 551446436 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1252504 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 94589845 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 29084935 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11874 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2889732822 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 45736 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 94589845 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 717318588 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17364773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538784806 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9995832 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2789102688 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 667601 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 9756545 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 1858404761 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3251110860 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3141674529 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 109436331 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1286425438 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.312723 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.605921 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 450744873 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 71473924 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 619092915 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8779214 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 136334512 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 30672233 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12086 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3254497888 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 45897 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 136334512 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 481076883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 28014325 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 24661 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 596193290 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 44781767 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3152490171 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 251 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 750331 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 37577847 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2105819344 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3700266531 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3588526705 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 111739826 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 473435691 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2820 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 67 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 26060288 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 641174032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 294900052 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 45514192 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5837090 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2345716556 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2067604433 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 20671442 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 522645709 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 487946872 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1378074830 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.500357 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.637561 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 720850274 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2943 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 124041279 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 733340932 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 346031420 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 95137569 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 27633179 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2644257175 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2155824179 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 16126742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 820828364 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 783816601 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1286425438 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.675825 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.770169 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 509079016 36.94% 36.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 296362701 21.51% 58.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 259221008 18.81% 77.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 152505049 11.07% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 67550622 4.90% 93.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 50043003 3.63% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 31234899 2.27% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9170584 0.67% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2907948 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 467246309 36.32% 36.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 226022267 17.57% 53.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 245197843 19.06% 72.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131574377 10.23% 83.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 102243605 7.95% 91.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 70385882 5.47% 96.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 25434522 1.98% 98.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15392931 1.20% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2927702 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1378074830 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1286425438 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5127 0.01% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27845547 76.88% 76.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 8367330 23.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 16153 0.06% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 21369886 75.29% 75.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 6999064 24.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1197059589 57.90% 57.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 18404 0.00% 57.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27850873 1.35% 59.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254690 0.40% 59.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204648 0.35% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 550666151 26.63% 86.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 276547322 13.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1238199555 57.44% 57.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16604 0.00% 57.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27850923 1.29% 58.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254691 0.38% 59.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 584881936 27.13% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 289413066 13.42% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2067604433 # Type of FU issued -system.cpu.iq.rate 1.500211 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36218004 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017517 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5422106783 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2793381779 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1916512220 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 148066359 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 74982161 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72617602 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2028403798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 75415887 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 51921347 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2155824179 # Type of FU issued +system.cpu.iq.rate 1.675654 # Inst issue rate +system.cpu.iq.fu_busy_cnt 28385103 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013167 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5494149121 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3387002536 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1990375209 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 148436520 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 78085554 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 72618270 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2108584760 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 75621770 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67562501 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 130104006 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 444 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1647 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 84105156 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 222270906 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2427 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 2537 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 135236524 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4160 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5770 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 94589845 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3355843 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 136604 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2668815228 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3006027 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 641174032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 294900052 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 62 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 131680 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3376 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1647 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 30089490 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 787925 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 30877415 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1990177336 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 514686474 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 77427097 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 136334512 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3822943 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 203706 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3007852435 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2742591 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 733340932 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 346031420 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 131030 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4921 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 2537 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 30744167 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 897447 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 31641614 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2065462954 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 520628814 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 90361225 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 323098610 # number of nop insts executed -system.cpu.iew.exec_refs 766410290 # number of memory reference insts executed -system.cpu.iew.exec_branches 273848647 # Number of branches executed -system.cpu.iew.exec_stores 251723816 # Number of stores executed -system.cpu.iew.exec_rate 1.444031 # Inst execution rate -system.cpu.iew.wb_sent 1990119861 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1989129822 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1118735591 # num instructions producing a value -system.cpu.iew.wb_consumers 1598918223 # num instructions consuming a value +system.cpu.iew.exec_nop 363595182 # number of nop insts executed +system.cpu.iew.exec_refs 804485830 # number of memory reference insts executed +system.cpu.iew.exec_branches 279503743 # Number of branches executed +system.cpu.iew.exec_stores 283857016 # Number of stores executed +system.cpu.iew.exec_rate 1.605419 # Inst execution rate +system.cpu.iew.wb_sent 2064970542 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2062993479 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1176781433 # num instructions producing a value +system.cpu.iew.wb_consumers 1743261069 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.443271 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.699683 # average fanout of values written-back +system.cpu.iew.wb_rate 1.603500 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675046 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 649535600 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 982155641 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 28343556 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1283484985 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.565260 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.221446 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 28911563 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1150090926 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.746808 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513435 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 584328523 45.53% 45.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 266282466 20.75% 66.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 167965913 13.09% 79.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 72752284 5.67% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 49726595 3.87% 88.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 31709768 2.47% 91.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15719812 1.22% 92.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23254624 1.81% 94.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 71745000 5.59% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 542926028 47.21% 47.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 216885753 18.86% 66.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119710361 10.41% 76.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 61150951 5.32% 81.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 44124600 3.84% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24943285 2.17% 87.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19289585 1.68% 89.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16206963 1.41% 90.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 104853400 9.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1283484985 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1150090926 # Number of insts commited each cycle system.cpu.commit.count 2008987604 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 721864922 # Number of memory references committed @@ -288,50 +290,50 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 71745000 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 104853400 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3864626779 # The number of ROB reads -system.cpu.rob.rob_writes 5411636382 # The number of ROB writes -system.cpu.timesIdled 3611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 134338 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4030744361 # The number of ROB reads +system.cpu.rob.rob_writes 6118806810 # The number of ROB writes +system.cpu.timesIdled 3658 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 131218 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.755994 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755994 # CPI: Total CPI of All Threads -system.cpu.ipc 1.322762 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.322762 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2524191182 # number of integer regfile reads -system.cpu.int_regfile_writes 1452780579 # number of integer regfile writes -system.cpu.fp_regfile_reads 77822211 # number of floating regfile reads -system.cpu.fp_regfile_writes 52656376 # number of floating regfile writes +system.cpu.cpi 0.705719 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.705719 # CPI: Total CPI of All Threads +system.cpu.ipc 1.416994 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.416994 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2630024814 # number of integer regfile reads +system.cpu.int_regfile_writes 1492719850 # number of integer regfile writes +system.cpu.fp_regfile_reads 77822488 # number of floating regfile reads +system.cpu.fp_regfile_writes 52815654 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8102 # number of replacements -system.cpu.icache.tagsinuse 1613.087790 # Cycle average of tags in use -system.cpu.icache.total_refs 343688083 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9773 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 35167.101504 # Average number of references to valid blocks. +system.cpu.icache.replacements 8249 # number of replacements +system.cpu.icache.tagsinuse 1648.525353 # Cycle average of tags in use +system.cpu.icache.total_refs 398161333 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9955 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39996.115821 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1613.087790 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.787641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 343688083 # number of ReadReq hits -system.cpu.icache.demand_hits 343688083 # number of demand (read+write) hits -system.cpu.icache.overall_hits 343688083 # number of overall hits -system.cpu.icache.ReadReq_misses 10589 # number of ReadReq misses -system.cpu.icache.demand_misses 10589 # number of demand (read+write) misses -system.cpu.icache.overall_misses 10589 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 166169000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 166169000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 166169000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 343698672 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 343698672 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 343698672 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15692.605534 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15692.605534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15692.605534 # average overall miss latency +system.cpu.icache.occ_blocks::0 1648.525353 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.804944 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 398161333 # number of ReadReq hits +system.cpu.icache.demand_hits 398161333 # number of demand (read+write) hits +system.cpu.icache.overall_hits 398161333 # number of overall hits +system.cpu.icache.ReadReq_misses 11104 # number of ReadReq misses +system.cpu.icache.demand_misses 11104 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11104 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 182797500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 182797500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 182797500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 398172437 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 398172437 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 398172437 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000028 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000028 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 16462.310879 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 16462.310879 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 16462.310879 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,161 +343,170 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 815 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 815 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 815 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9774 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9774 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9774 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1148 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1148 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1148 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 9956 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 9956 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 9956 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 113082000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 113082000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 113082000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 119908500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 119908500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 119908500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11569.674647 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11569.674647 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12043.842909 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12043.842909 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12043.842909 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1526504 # number of replacements -system.cpu.dcache.tagsinuse 4095.093805 # Cycle average of tags in use -system.cpu.dcache.total_refs 670466697 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1530600 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 438.041746 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 272263000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4095.093805 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999779 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 460219169 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 210247520 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 670466689 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 670466689 # number of overall hits -system.cpu.dcache.ReadReq_misses 1925769 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 547376 # number of WriteReq misses -system.cpu.dcache.demand_misses 2473145 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2473145 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 71430113000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 20787135492 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 92217248492 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 92217248492 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 462144938 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1526943 # number of replacements +system.cpu.dcache.tagsinuse 4095.108553 # Cycle average of tags in use +system.cpu.dcache.total_refs 660714952 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531039 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 431.546781 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 256550000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.108553 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999782 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 450471495 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 210243448 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 660714943 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 660714943 # number of overall hits +system.cpu.dcache.ReadReq_misses 1926978 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 551448 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 2478426 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2478426 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 71403545500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 20877102491 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 92500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 92280647991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 92280647991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 452398473 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 8 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 672939834 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 672939834 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.004167 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002597 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.003675 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003675 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 37091.734782 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37975.971712 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 37287.441089 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 37287.441089 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 67000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 663193369 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 663193369 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.004259 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.002616 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.003737 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.003737 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 37054.676026 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37858.696543 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 30833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 37233.570012 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 37233.570012 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 73500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5583.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5653.846154 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107391 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 466816 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 475729 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 942545 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 942545 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1458953 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 71647 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1530600 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1530600 # number of overall MSHR misses +system.cpu.dcache.writebacks 107355 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 467583 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 479805 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 947388 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 947388 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1459395 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 71643 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1531038 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1531038 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 49864130500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2492449500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52356580000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52356580000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 49913534500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2493312500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 52406847000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 52406847000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003226 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.002274 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.002274 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34178.023898 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34787.911566 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34206.572586 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.083333 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.002309 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.002309 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34201.524947 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34801.899697 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34229.618729 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34229.618729 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480376 # number of replacements -system.cpu.l2cache.tagsinuse 31940.931964 # Cycle average of tags in use -system.cpu.l2cache.total_refs 62599 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513063 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.041372 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480567 # number of replacements +system.cpu.l2cache.tagsinuse 31934.538641 # Cycle average of tags in use +system.cpu.l2cache.total_refs 62997 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513254 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.041630 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 28887.056134 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3053.875830 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.881563 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.093197 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 54988 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107391 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 4793 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 59781 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 59781 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1413739 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 66854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1480593 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1480593 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48438065500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2348993500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50787059000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50787059000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1468727 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107391 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 71647 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1540374 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1540374 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.962561 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.933103 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.961191 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.961191 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34262.381882 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.169863 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34301.836494 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34301.836494 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 34500 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::0 28868.809118 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3065.729523 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.881006 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.093559 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 55380 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 107355 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 4788 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 60168 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 60168 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1413972 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 66855 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 1480827 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 1480827 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 48486615500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2348963000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 50835578500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 50835578500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1469352 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 107355 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 71643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1540995 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1540995 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.962310 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.933169 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.960955 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.960955 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34291.071888 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 35135.188094 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34329.181262 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34329.181262 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8625 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5500 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 66898 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1413739 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1480593 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1480593 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1413972 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 66855 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 1480827 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 1480827 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43826861000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148213000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 45975074000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 45975074000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 43834352500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147649000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 45982001500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 45982001500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962561 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933103 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.961191 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.961191 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.673392 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32132.901547 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.797489 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962310 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933169 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.960955 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.960955 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.863171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32123.984743 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568819 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 410b12d67..263380878 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr index 805a6606f..cba73e085 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr @@ -1,5 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 warn: fcntl64(3, 2) passed through to host -For more information see: http://www.m5sim.org/warn/a55e2c46 hack: be nice to actually delete the event here diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout index bf375000b..48d5b0b7a 100755 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 15:11:57 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 02:34:35 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1391,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 795626752000 because target called exit() +Exiting @ tick 744105966500 because target called exit() diff --git a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index ce16cf8d2..bce6cbb05 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.795627 # Number of seconds simulated -sim_ticks 795626752000 # Number of ticks simulated +sim_seconds 0.744106 # Number of seconds simulated +sim_ticks 744105966500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 37469 # Simulator instruction rate (inst/s) -host_tick_rate 15812352 # Simulator tick rate (ticks/s) -host_mem_usage 261444 # Number of bytes of host memory used -host_seconds 50316.79 # Real time elapsed on the host -sim_insts 1885343131 # Number of instructions simulated +host_inst_rate 75556 # Simulator instruction rate (inst/s) +host_tick_rate 29820362 # Simulator tick rate (ticks/s) +host_mem_usage 264164 # Number of bytes of host memory used +host_seconds 24952.95 # Real time elapsed on the host +sim_insts 1885342016 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,297 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1591253505 # number of cpu cycles simulated +system.cpu.numCycles 1488211934 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 519677239 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 398144928 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 40174420 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 410482703 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 293585496 # Number of BTB hits +system.cpu.BPredUnit.lookups 518896793 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 400040732 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 32908651 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 412694566 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 290043770 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 53540823 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2841317 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 361951635 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2537428028 # Number of instructions fetch has processed -system.cpu.fetch.Branches 519677239 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 347126319 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 659124412 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 47088491 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 166 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 361951635 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 20842559 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1554259692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.199934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.044955 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 65454853 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2848873 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 431006584 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2627710278 # Number of instructions fetch has processed +system.cpu.fetch.Branches 518896793 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 355498623 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 704801435 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 227434994 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 113516280 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5111 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 399257672 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8382302 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1436630001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.536830 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.149737 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 895170810 57.59% 57.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 41935957 2.70% 60.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 103275417 6.64% 66.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 61539532 3.96% 70.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 89553793 5.76% 76.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 52982183 3.41% 80.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 34961510 2.25% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 45455804 2.92% 85.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 229384686 14.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 731865766 50.94% 50.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 52278672 3.64% 54.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 109951004 7.65% 62.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 64331025 4.48% 66.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 92104513 6.41% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 55434190 3.86% 76.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39408243 2.74% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 32778762 2.28% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 258477826 17.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1554259692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.326584 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.594610 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 723197107 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 41283634 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 642007597 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1402750 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 146368604 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 76799900 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11033 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3347346347 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 20349 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 146368604 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 756568519 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 25444222 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3271742 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 608636712 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13969893 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3194137589 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3931047 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7404635 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3358259430 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 15045243779 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14391074287 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 654169492 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993168551 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1365090874 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 254462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 254764 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 34849726 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 925173948 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 465395627 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 97302082 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144361448 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889677990 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 244825 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2448298992 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 12457526 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 987757973 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2669097969 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 33037 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1554259692 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.575219 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.653577 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1436630001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.348671 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.765683 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 474703889 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92089695 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 671736516 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10812998 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 187286903 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 70416009 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13639 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3539876246 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 23440 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 187286903 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 514963010 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 29220198 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3511276 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 640788708 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 60859906 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3412725631 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 46 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4123400 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 48521988 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 3397910620 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16198267301 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15450730698 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 747536603 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993166767 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1404743848 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 278280 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 278424 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 178635722 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1114561414 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 545702989 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 154567236 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 147667095 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3238356442 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 281581 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2642482384 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5796308 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1352960304 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3645177300 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 70016 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1436630001 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.839362 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.852230 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 571543598 36.77% 36.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 302403348 19.46% 56.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 272921305 17.56% 73.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 170079995 10.94% 84.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 141872535 9.13% 93.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 62133878 4.00% 97.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24302902 1.56% 99.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6180941 0.40% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2821190 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 506457907 35.25% 35.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 223599177 15.56% 50.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 229642094 15.98% 66.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 172448421 12.00% 78.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 157180454 10.94% 89.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 90857048 6.32% 96.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 40453427 2.82% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11405646 0.79% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4585827 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1554259692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1436630001 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5100 0.01% 0.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23970 0.03% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 52395536 69.00% 69.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23506568 30.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1185558 1.85% 1.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23950 0.04% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 40505203 63.35% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22224408 34.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1194651657 48.80% 48.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11220052 0.46% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 8628 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 49.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 49.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 49.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 6176938 0.25% 49.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 25435651 1.04% 50.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 792339955 32.36% 83.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 410214348 16.76% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1237165385 46.82% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11226668 0.42% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 8630 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 47.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.26% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 6142371 0.23% 47.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 24460385 0.93% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 896605446 33.93% 82.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 458621735 17.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2448298992 # Type of FU issued -system.cpu.iq.rate 1.538598 # Inst issue rate -system.cpu.iq.fu_busy_cnt 75931174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.031014 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6412694569 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3775928903 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2259827011 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 126551807 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 103128995 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57766877 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2458203699 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 66026467 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 38019387 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2642482384 # Type of FU issued +system.cpu.iq.rate 1.775609 # Inst issue rate +system.cpu.iq.fu_busy_cnt 63939119 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024197 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6661297580 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4469277070 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2420670942 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 130032616 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 124010144 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59075392 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2641405327 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 65016176 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 73114963 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 293783209 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1377644 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 2672008 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 188396774 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 483170898 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 99011 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3650929 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 268704359 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 94 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 146368604 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17402025 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3966817 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2889988302 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 9053008 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 925173948 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 465395627 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 232022 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2656731 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 304 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 2672008 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 37424548 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 12425696 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 49850244 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2354181989 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 757207603 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94117003 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 187286903 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16548451 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1477546 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3238703739 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 11872283 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1114561414 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 545702989 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 268887 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1475433 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 305 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3650929 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36090139 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8517669 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 44607808 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2538548253 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 842723322 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 103934131 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 65487 # number of nop insts executed -system.cpu.iew.exec_refs 1128829223 # number of memory reference insts executed -system.cpu.iew.exec_branches 348669519 # Number of branches executed -system.cpu.iew.exec_stores 371621620 # Number of stores executed -system.cpu.iew.exec_rate 1.479451 # Inst execution rate -system.cpu.iew.wb_sent 2328619665 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2317593888 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1309821619 # num instructions producing a value -system.cpu.iew.wb_consumers 2336262105 # num instructions consuming a value +system.cpu.iew.exec_nop 65716 # number of nop insts executed +system.cpu.iew.exec_refs 1272992998 # number of memory reference insts executed +system.cpu.iew.exec_branches 351489842 # Number of branches executed +system.cpu.iew.exec_stores 430269676 # Number of stores executed +system.cpu.iew.exec_rate 1.705771 # Inst execution rate +system.cpu.iew.wb_sent 2508384244 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2479746334 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1467036313 # num instructions producing a value +system.cpu.iew.wb_consumers 2710651250 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.456458 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.560648 # average fanout of values written-back +system.cpu.iew.wb_rate 1.666259 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.541212 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1885354147 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1004600706 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 211788 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 45699022 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1407891090 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.339134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.034210 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1885353032 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1353312364 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 211565 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 38431023 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1249343100 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.509075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.191779 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 652274208 46.33% 46.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 388083214 27.56% 73.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 132034153 9.38% 83.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 69283607 4.92% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 48326626 3.43% 91.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18528976 1.32% 92.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 23779079 1.69% 94.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 7923868 0.56% 95.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 67657359 4.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 548617532 43.91% 43.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 340979538 27.29% 71.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 105479188 8.44% 79.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 77201400 6.18% 85.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 51871134 4.15% 89.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 18884009 1.51% 91.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20943022 1.68% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8690011 0.70% 93.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76677266 6.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1407891090 # Number of insts commited each cycle -system.cpu.commit.count 1885354147 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 1249343100 # Number of insts commited each cycle +system.cpu.commit.count 1885353032 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908389591 # Number of memory references committed -system.cpu.commit.loads 631390738 # Number of loads committed +system.cpu.commit.refs 908389145 # Number of memory references committed +system.cpu.commit.loads 631390515 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291352101 # Number of branches committed +system.cpu.commit.branches 291351878 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653713099 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653712207 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 67657359 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76677266 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4230170239 # The number of ROB reads -system.cpu.rob.rob_writes 5926292122 # The number of ROB writes -system.cpu.timesIdled 1344848 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 36993813 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1885343131 # Number of Instructions Simulated -system.cpu.committedInsts_total 1885343131 # Number of Instructions Simulated -system.cpu.cpi 0.844013 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.844013 # CPI: Total CPI of All Threads -system.cpu.ipc 1.184816 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.184816 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11587728749 # number of integer regfile reads -system.cpu.int_regfile_writes 2306495167 # number of integer regfile writes -system.cpu.fp_regfile_reads 69468418 # number of floating regfile reads -system.cpu.fp_regfile_writes 51554923 # number of floating regfile writes -system.cpu.misc_regfile_reads 3827336094 # number of misc regfile reads -system.cpu.misc_regfile_writes 13780014 # number of misc regfile writes -system.cpu.icache.replacements 25559 # number of replacements -system.cpu.icache.tagsinuse 1546.566470 # Cycle average of tags in use -system.cpu.icache.total_refs 361924025 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 27145 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13332.990422 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4411312885 # The number of ROB reads +system.cpu.rob.rob_writes 6664635759 # The number of ROB writes +system.cpu.timesIdled 1344981 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51581933 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1885342016 # Number of Instructions Simulated +system.cpu.committedInsts_total 1885342016 # Number of Instructions Simulated +system.cpu.cpi 0.789359 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.789359 # CPI: Total CPI of All Threads +system.cpu.ipc 1.266850 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.266850 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12578509945 # number of integer regfile reads +system.cpu.int_regfile_writes 2395231974 # number of integer regfile writes +system.cpu.fp_regfile_reads 70809202 # number of floating regfile reads +system.cpu.fp_regfile_writes 51453484 # number of floating regfile writes +system.cpu.misc_regfile_reads 4059454744 # number of misc regfile reads +system.cpu.misc_regfile_writes 13779568 # number of misc regfile writes +system.cpu.icache.replacements 25817 # number of replacements +system.cpu.icache.tagsinuse 1640.813432 # Cycle average of tags in use +system.cpu.icache.total_refs 399229379 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 27501 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14516.904076 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1546.566470 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.755159 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 361924028 # number of ReadReq hits -system.cpu.icache.demand_hits 361924028 # number of demand (read+write) hits -system.cpu.icache.overall_hits 361924028 # number of overall hits -system.cpu.icache.ReadReq_misses 27607 # number of ReadReq misses -system.cpu.icache.demand_misses 27607 # number of demand (read+write) misses -system.cpu.icache.overall_misses 27607 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 250013500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 250013500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 250013500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 361951635 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 361951635 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 361951635 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 9056.163292 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 9056.163292 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 9056.163292 # average overall miss latency +system.cpu.icache.occ_blocks::0 1640.813432 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.801178 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 399229380 # number of ReadReq hits +system.cpu.icache.demand_hits 399229380 # number of demand (read+write) hits +system.cpu.icache.overall_hits 399229380 # number of overall hits +system.cpu.icache.ReadReq_misses 28292 # number of ReadReq misses +system.cpu.icache.demand_misses 28292 # number of demand (read+write) misses +system.cpu.icache.overall_misses 28292 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 269405500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 269405500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 269405500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 399257672 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 399257672 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 399257672 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000071 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000071 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 9522.320797 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 9522.320797 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 9522.320797 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,143 +353,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 455 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 455 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 455 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 27152 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 27152 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 27152 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 785 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 785 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 785 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 27507 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 27507 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 27507 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 155884000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 155884000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 155884000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 166096000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 166096000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 166096000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000075 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 5741.160872 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 5741.160872 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 5741.160872 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000069 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000069 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000069 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6038.317519 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6038.317519 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6038.317519 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1531405 # number of replacements -system.cpu.dcache.tagsinuse 4094.850466 # Cycle average of tags in use -system.cpu.dcache.total_refs 980041629 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1535501 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 638.255285 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 325046000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.850466 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999719 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 703882480 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 276128743 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 16835 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 13541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 980011223 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 980011223 # number of overall hits -system.cpu.dcache.ReadReq_misses 1932681 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 806935 # number of WriteReq misses +system.cpu.dcache.replacements 1531025 # number of replacements +system.cpu.dcache.tagsinuse 4094.846671 # Cycle average of tags in use +system.cpu.dcache.total_refs 1028461825 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1535121 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 669.954893 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 306448000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.846671 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999718 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 752304344 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 276127089 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 17060 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 13318 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 1028431433 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 1028431433 # number of overall hits +system.cpu.dcache.ReadReq_misses 1932486 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 808589 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2739616 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2739616 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 66544329000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 28306423000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 2741075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2741075 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 69636872500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 28315241500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 108500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 94850752000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 94850752000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 705815161 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 97952114000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 97952114000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 754236830 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 16838 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 13541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 982750839 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 982750839 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.002738 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.002914 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000178 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.002788 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.002788 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 34431.098045 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35078.938204 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 17063 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 13318 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 1031172508 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 1031172508 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.002562 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.002920 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000176 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.002658 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.002658 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 36034.865194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35018.088918 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34621.914896 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34621.914896 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 35734.926626 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35734.926626 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 59500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 59000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14875 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14750 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 107019 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 469901 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 734207 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 106614 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 470081 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 735866 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1204108 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1204108 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1462780 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 72728 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1535508 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1535508 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 1205947 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1205947 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1462405 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 72723 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1535128 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1535128 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 49902321500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2361229000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 52263550500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 52263550500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 50067282500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2361289000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 52428571500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 52428571500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002072 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001939 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001562 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001562 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34114.714106 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32466.574084 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34036.651388 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34036.651388 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001489 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001489 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34236.263210 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32469.631341 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34152.573271 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34152.573271 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1479610 # number of replacements -system.cpu.l2cache.tagsinuse 31966.303160 # Cycle average of tags in use -system.cpu.l2cache.total_refs 83557 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512330 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.055251 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1479866 # number of replacements +system.cpu.l2cache.tagsinuse 31973.633477 # Cycle average of tags in use +system.cpu.l2cache.total_refs 82869 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512586 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.054786 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 28970.488218 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 2995.814942 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.884109 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.091425 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 75230 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 107019 # number of Writeback hits +system.cpu.l2cache.occ_blocks::0 29008.320334 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 2965.313143 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.885264 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.090494 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 74752 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 106614 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 6637 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 81867 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 81867 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1414695 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 66084 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 1480779 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 1480779 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 48470185000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2279814000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 50749999000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 50749999000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1489925 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 107019 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 7 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 72721 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1562646 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1562646 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.949508 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.714286 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.908733 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.947610 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.947610 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34261.932784 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.728891 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34272.500488 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34272.500488 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits 6636 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 81388 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 81388 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1415154 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 66081 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 1481235 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 1481235 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 48603615500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2279719000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 50883334500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 50883334500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1489906 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 106614 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 6 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 72717 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1562623 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1562623 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.949828 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.908742 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.947916 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.947916 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34345.106964 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34498.857463 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34351.966096 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34351.966096 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,31 +499,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 66099 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 23 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1414672 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 66084 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 1480756 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 1480756 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 27 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 1415127 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 66081 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 1481208 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 1481208 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43855333500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 155000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048687000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 45904020500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 45904020500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 44021028500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048574500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 46069603000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 46069603000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949492 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.714286 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908733 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.947595 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.947595 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.354499 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.949810 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908742 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.947899 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.947899 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31107.475513 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.255977 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.394731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.394731 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.960942 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.723588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.723588 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 2452e8b3b..e20a60e8c 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 78f49b74e..a3cf9c876 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 13:35:14 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 16:45:59 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 46960422500 because target called exit() +Exiting @ tick 46914279500 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 33754d9f7..a84fb4906 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.046960 # Number of seconds simulated -sim_ticks 46960422500 # Number of ticks simulated +sim_seconds 0.046914 # Number of seconds simulated +sim_ticks 46914279500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121209 # Simulator instruction rate (inst/s) -host_tick_rate 64432457 # Simulator tick rate (ticks/s) -host_mem_usage 201704 # Number of bytes of host memory used -host_seconds 728.83 # Real time elapsed on the host +host_inst_rate 53929 # Simulator instruction rate (inst/s) +host_tick_rate 28639497 # Simulator tick rate (ticks/s) +host_mem_usage 254456 # Number of bytes of host memory used +host_seconds 1638.10 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277221 # DTB read hits +system.cpu.dtb.read_hits 20277222 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367369 # DTB read accesses +system.cpu.dtb.read_accesses 20367370 # DTB read accesses system.cpu.dtb.write_hits 14736811 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 14744063 # DTB write accesses -system.cpu.dtb.data_hits 35014032 # DTB hits +system.cpu.dtb.data_hits 35014033 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111432 # DTB accesses -system.cpu.itb.fetch_hits 12387546 # ITB hits -system.cpu.itb.fetch_misses 10588 # ITB misses +system.cpu.dtb.data_accesses 35111433 # DTB accesses +system.cpu.itb.fetch_hits 12380499 # ITB hits +system.cpu.itb.fetch_misses 10576 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12398134 # ITB accesses +system.cpu.itb.fetch_accesses 12391075 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 93920846 # number of cpu cycles simulated +system.cpu.numCycles 93828560 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77525843 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77431415 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305872 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24229643 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69691203 # Number of cycles cpu stages are processed. -system.cpu.activity 74.202061 # Percentage of cycles cpu is active +system.cpu.timesIdled 305691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24228941 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69599619 # Number of cycles cpu stages are processed. +system.cpu.activity 74.177435 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -61,212 +61,212 @@ system.cpu.comFloats 151453 # Nu system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) -system.cpu.cpi 1.063167 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.063167 # CPI: Total CPI of All Threads -system.cpu.ipc 0.940586 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads +system.cpu.ipc 0.941512 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.940586 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 18775711 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12354362 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4821711 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 15677307 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4750423 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 30.301269 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8154380 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10621331 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74177297 # Number of Reads from Int. Register File +system.cpu.ipc_total 0.941512 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 18761151 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12342012 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4785453 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 15763185 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 4708455 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660959 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 29.869947 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8112975 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10648176 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74148043 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126496547 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65349 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126467293 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65874 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292979 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14162850 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35055536 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4522867 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 188344 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4711211 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9061038 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 34.208000 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44765481 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293504 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14179622 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35053135 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4496417 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 178536 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4674953 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9097544 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.944121 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44764178 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 41151668 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52769178 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 56.184735 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 51441694 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42479152 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.228673 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 50863748 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43057098 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.844027 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 71800106 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120740 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.552535 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47858752 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46062094 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.043525 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 83802 # number of replacements -system.cpu.icache.tagsinuse 1886.866724 # Cycle average of tags in use -system.cpu.icache.total_refs 12270472 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 85848 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 142.932532 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 41142190 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52686370 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 56.151741 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 51376338 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42452222 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.244456 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 50789796 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43038764 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.869577 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 71702339 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22126221 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.581542 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 47784207 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46044353 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 49.072855 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 83610 # number of replacements +system.cpu.icache.tagsinuse 1886.858130 # Cycle average of tags in use +system.cpu.icache.total_refs 12263478 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1886.866724 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.921322 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 12270472 # number of ReadReq hits -system.cpu.icache.demand_hits 12270472 # number of demand (read+write) hits -system.cpu.icache.overall_hits 12270472 # number of overall hits -system.cpu.icache.ReadReq_misses 117039 # number of ReadReq misses -system.cpu.icache.demand_misses 117039 # number of demand (read+write) misses -system.cpu.icache.overall_misses 117039 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 2068714000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 2068714000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 2068714000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 12387511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 12387511 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 12387511 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.009448 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.009448 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.009448 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 17675.424431 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 17675.424431 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 17675.424431 # average overall miss latency +system.cpu.icache.occ_blocks::0 1886.858130 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.921317 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12263478 # number of ReadReq hits +system.cpu.icache.demand_hits 12263478 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12263478 # number of overall hits +system.cpu.icache.ReadReq_misses 116984 # number of ReadReq misses +system.cpu.icache.demand_misses 116984 # number of demand (read+write) misses +system.cpu.icache.overall_misses 116984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 2068004000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 2068004000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 2068004000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12380462 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12380462 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12380462 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.009449 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.009449 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.009449 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 17677.665322 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 17677.665322 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 17677.665322 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1666000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1596000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 174 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 172 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 9574.712644 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 9279.069767 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 31191 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 31191 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 31191 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 85848 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 85848 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 85848 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 31328 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 31328 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 31328 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 85656 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 85656 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 85656 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 1347366500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 1347366500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 1347366500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 1345401500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 1345401500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 1345401500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006930 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.006930 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.006930 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15694.791958 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15694.791958 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15694.791958 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.006919 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.006919 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.006919 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15707.031615 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15707.031615 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.088977 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126006 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4073.105766 # Cycle average of tags in use +system.cpu.dcache.total_refs 34126014 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000279 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 486750000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4073.088977 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994406 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20180454 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13945552 # number of WriteReq hits -system.cpu.dcache.demand_hits 34126006 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 34126006 # number of overall hits -system.cpu.dcache.ReadReq_misses 96184 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 667825 # number of WriteReq misses -system.cpu.dcache.demand_misses 764009 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 764009 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4158459500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 35331617000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 39490076500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39490076500 # number of overall miss cycles +system.cpu.dcache.avg_refs 167.000318 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 486265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4073.105766 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.994411 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 20180445 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 13945569 # number of WriteReq hits +system.cpu.dcache.demand_hits 34126014 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 34126014 # number of overall hits +system.cpu.dcache.ReadReq_misses 96193 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 667808 # number of WriteReq misses +system.cpu.dcache.demand_misses 764001 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 764001 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4158649000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 35332073000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 39490722000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 39490722000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.004744 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.021898 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021898 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 43234.420486 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 52905.502190 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 51687.972917 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 51687.972917 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate 0.045698 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 43232.345389 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 52907.531806 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 51689.359045 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 51689.359045 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6330419000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6330522500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124111 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124112 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51006.107436 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 161216 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 35417 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 524245 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 559662 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 559662 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 35426 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 524228 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 559654 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 559654 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 143580 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2088747000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 7254442500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9343189500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9343189500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2088724500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 7254420000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9343144500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9343144500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34373.047871 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.438780 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 45722.176005 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 45722.176005 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34372.677605 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.282073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 45721.955791 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 148058 # number of replacements -system.cpu.l2cache.tagsinuse 18662.722702 # Cycle average of tags in use -system.cpu.l2cache.total_refs 131525 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 173403 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.758493 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 148060 # number of replacements +system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use +system.cpu.l2cache.total_refs 131331 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 3004.603682 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15658.119020 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.091693 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.477848 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 103488 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::0 3005.792321 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15657.764606 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.091730 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.477837 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 103294 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 161216 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 12270 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 115758 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 115758 # number of overall hits -system.cpu.l2cache.ReadReq_misses 42937 # number of ReadReq misses +system.cpu.l2cache.demand_hits 115564 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 115564 # number of overall hits +system.cpu.l2cache.ReadReq_misses 42939 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 131500 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 174437 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 174437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 2242217000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses 174439 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 174439 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 2242306500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 6854385000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9096602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9096602000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 146425 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency 9096691500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 9096691500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 146233 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 161216 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 290195 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 290195 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.293235 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 290003 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 290003 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.293634 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.914655 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.601103 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.601103 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52221.091366 # average ReadReq miss latency +system.cpu.l2cache.demand_miss_rate 0.601508 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.601508 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52220.743380 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52148.351554 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52148.351554 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52148.266729 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52148.266729 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,24 +278,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 120515 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 42937 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 42939 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 131500 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 174437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 174437 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 174439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 174439 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1718546000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262803000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 6981349000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 6981349000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1718628500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262711000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 6981339500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 6981339500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293235 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293634 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.914655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.601103 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.601103 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.827072 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40021.315589 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40022.179927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40022.179927 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.601508 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.601508 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.884138 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40020.615970 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index c10dc5f2b..7b47004d6 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 3a856c6f6..524033226 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:05:16 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 17:12:27 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 25567234000 because target called exit() +Exiting @ tick 24044597000 because target called exit() diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 0ff0f8618..1270e8887 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025567 # Number of seconds simulated -sim_ticks 25567234000 # Number of ticks simulated +sim_seconds 0.024045 # Number of seconds simulated +sim_ticks 24044597000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 215433 # Simulator instruction rate (inst/s) -host_tick_rate 69203497 # Simulator tick rate (ticks/s) -host_mem_usage 202972 # Number of bytes of host memory used -host_seconds 369.45 # Real time elapsed on the host +host_inst_rate 91114 # Simulator instruction rate (inst/s) +host_tick_rate 27525458 # Simulator tick rate (ticks/s) +host_mem_usage 256064 # Number of bytes of host memory used +host_seconds 873.54 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 21577330 # DTB read hits -system.cpu.dtb.read_misses 171148 # DTB read misses -system.cpu.dtb.read_acv 19 # DTB read access violations -system.cpu.dtb.read_accesses 21748478 # DTB read accesses -system.cpu.dtb.write_hits 15194902 # DTB write hits -system.cpu.dtb.write_misses 30538 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15225440 # DTB write accesses -system.cpu.dtb.data_hits 36772232 # DTB hits -system.cpu.dtb.data_misses 201686 # DTB misses -system.cpu.dtb.data_acv 20 # DTB access violations -system.cpu.dtb.data_accesses 36973918 # DTB accesses -system.cpu.itb.fetch_hits 13158718 # ITB hits -system.cpu.itb.fetch_misses 26109 # ITB misses +system.cpu.dtb.read_hits 23266854 # DTB read hits +system.cpu.dtb.read_misses 225542 # DTB read misses +system.cpu.dtb.read_acv 45 # DTB read access violations +system.cpu.dtb.read_accesses 23492396 # DTB read accesses +system.cpu.dtb.write_hits 16036454 # DTB write hits +system.cpu.dtb.write_misses 32845 # DTB write misses +system.cpu.dtb.write_acv 10 # DTB write access violations +system.cpu.dtb.write_accesses 16069299 # DTB write accesses +system.cpu.dtb.data_hits 39303308 # DTB hits +system.cpu.dtb.data_misses 258387 # DTB misses +system.cpu.dtb.data_acv 55 # DTB access violations +system.cpu.dtb.data_accesses 39561695 # DTB accesses +system.cpu.itb.fetch_hits 15336941 # ITB hits +system.cpu.itb.fetch_misses 33582 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13184827 # ITB accesses +system.cpu.itb.fetch_accesses 15370523 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 51134470 # number of cpu cycles simulated +system.cpu.numCycles 48089197 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16008370 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10401089 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 450273 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13917590 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7985382 # Number of BTB hits +system.cpu.BPredUnit.lookups 18361326 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11820514 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 546274 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 16009789 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9688195 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1909965 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 35809 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 13158718 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101571141 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16008370 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9895347 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19591284 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 555760 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 26109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 13158718 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 152584 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 50718006 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.002664 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.959146 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 2216159 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 37765 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 16493376 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 115096464 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18361326 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11904354 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22748230 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3321567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5575284 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 339871 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 15336941 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 325972 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47646209 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.415648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.066102 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 31126722 61.37% 61.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1893724 3.73% 65.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1511025 2.98% 68.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1863843 3.67% 71.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3852588 7.60% 79.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1892655 3.73% 83.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 670633 1.32% 84.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1088115 2.15% 86.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6818701 13.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24897979 52.26% 52.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2453036 5.15% 57.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1946901 4.09% 61.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2330257 4.89% 66.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4220177 8.86% 75.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2180283 4.58% 79.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 821973 1.73% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1319930 2.77% 84.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7475673 15.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 50718006 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.313064 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.986354 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27762644 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2460997 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19396266 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34450 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1063649 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3594435 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 97681 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100084760 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 276834 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1063649 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 28153155 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1389160 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 69579 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19024050 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1018413 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99297358 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 39 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11049 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 921609 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 59691366 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 119490611 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119061718 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 428893 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 47646209 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.381818 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.393395 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17905619 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5001845 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21498707 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 855219 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2384819 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4163553 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 99872 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112485204 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 269698 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2384819 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18579816 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2454161 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 95593 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21627471 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2504349 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110486741 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 205 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26203 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2324239 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 66683343 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 133326137 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 132820452 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 505685 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7144485 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5023 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5020 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2212492 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 22491432 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 15781594 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5725093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4370544 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 88005519 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4739 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 85477986 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 24789 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8137764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4541669 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 156 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 50718006 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.685358 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.886898 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 14136462 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5422 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5420 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5146770 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24822811 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 17209754 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6587978 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5178123 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97041243 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5374 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 92467963 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 130783 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 16243425 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8385088 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 791 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47646209 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.940720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.968352 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18797586 37.06% 37.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10551252 20.80% 57.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7740515 15.26% 73.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3878311 7.65% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5219123 10.29% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1973435 3.89% 94.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1302970 2.57% 97.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 789228 1.56% 99.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 465586 0.92% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15463365 32.45% 32.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9039378 18.97% 51.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7091354 14.88% 66.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5453112 11.45% 77.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4876639 10.24% 87.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2621564 5.50% 93.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1784714 3.75% 97.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 964783 2.02% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 351300 0.74% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 50718006 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47646209 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 99607 9.46% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 509872 48.45% 57.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 442934 42.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 124763 7.84% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 734633 46.19% 54.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 731207 45.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 47939957 56.08% 56.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43473 0.05% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122672 0.14% 56.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 123541 0.14% 56.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 52 0.00% 56.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38558 0.05% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 21877865 25.59% 82.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15331781 17.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 52052276 56.29% 56.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44017 0.05% 56.34% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 56.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 126208 0.14% 56.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 127891 0.14% 56.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38663 0.04% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23785526 25.72% 82.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16293239 17.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 85477986 # Type of FU issued -system.cpu.iq.rate 1.671631 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1052413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012312 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222155982 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 95743057 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 84083834 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 595198 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 410179 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 282834 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 86232746 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 297653 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1016178 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 92467963 # Type of FU issued +system.cpu.iq.rate 1.922843 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1590603 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017202 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 233677952 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 112998578 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89931166 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 625569 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 496845 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 303653 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93745634 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 312932 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1274888 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2214794 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1322 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6217 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1168217 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4546173 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15179 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 214045 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2596377 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1472 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1708 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1063649 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 429488 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 29880 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97321762 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 365032 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 22491432 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 15781594 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4739 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 23208 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1058 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6217 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 262730 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 133065 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 395795 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 84908070 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 21750177 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 569916 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2384819 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1408212 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 65481 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 106909939 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 348634 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 24822811 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 17209754 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5373 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 47651 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1257 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 214045 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 396366 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 133925 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 530291 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 91241048 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23498667 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1226915 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9311504 # number of nop insts executed -system.cpu.iew.exec_refs 36975872 # number of memory reference insts executed -system.cpu.iew.exec_branches 14700654 # Number of branches executed -system.cpu.iew.exec_stores 15225695 # Number of stores executed -system.cpu.iew.exec_rate 1.660486 # Inst execution rate -system.cpu.iew.wb_sent 84634554 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 84366668 # cumulative count of insts written-back -system.cpu.iew.wb_producers 31039892 # num instructions producing a value -system.cpu.iew.wb_consumers 40429267 # num instructions consuming a value +system.cpu.iew.exec_nop 9863322 # number of nop insts executed +system.cpu.iew.exec_refs 39568381 # number of memory reference insts executed +system.cpu.iew.exec_branches 15970661 # Number of branches executed +system.cpu.iew.exec_stores 16069714 # Number of stores executed +system.cpu.iew.exec_rate 1.897329 # Inst execution rate +system.cpu.iew.wb_sent 90664382 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 90234819 # cumulative count of insts written-back +system.cpu.iew.wb_producers 34760730 # num instructions producing a value +system.cpu.iew.wb_consumers 45726026 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.649898 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767758 # average fanout of values written-back +system.cpu.iew.wb_rate 1.876405 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.760196 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6568373 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 15596601 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 354109 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49654357 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.779112 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.457508 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 449200 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45261390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.951789 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.640164 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22596462 45.51% 45.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9701520 19.54% 65.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4636863 9.34% 74.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2945074 5.93% 80.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2498358 5.03% 85.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1627223 3.28% 88.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 982509 1.98% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 825181 1.66% 92.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3841167 7.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20510945 45.32% 45.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8049130 17.78% 63.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4022759 8.89% 71.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2704759 5.98% 77.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2151725 4.75% 82.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1309190 2.89% 85.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1156461 2.56% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 811237 1.79% 89.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4545184 10.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49654357 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 45261390 # Number of insts commited each cycle system.cpu.commit.count 88340672 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 34890015 # Number of memory references committed @@ -288,50 +290,50 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3841167 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4545184 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 139404893 # The number of ROB reads -system.cpu.rob.rob_writes 190882895 # The number of ROB writes -system.cpu.timesIdled 12185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 416464 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 143336137 # The number of ROB reads +system.cpu.rob.rob_writes 210280269 # The number of ROB writes +system.cpu.timesIdled 17593 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 442988 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.642459 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.642459 # CPI: Total CPI of All Threads -system.cpu.ipc 1.556519 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.556519 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 112360564 # number of integer regfile reads -system.cpu.int_regfile_writes 55786710 # number of integer regfile writes -system.cpu.fp_regfile_reads 235864 # number of floating regfile reads -system.cpu.fp_regfile_writes 240719 # number of floating regfile writes -system.cpu.misc_regfile_reads 37825 # number of misc regfile reads +system.cpu.cpi 0.604198 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.604198 # CPI: Total CPI of All Threads +system.cpu.ipc 1.655086 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.655086 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 120263319 # number of integer regfile reads +system.cpu.int_regfile_writes 59810170 # number of integer regfile writes +system.cpu.fp_regfile_reads 254298 # number of floating regfile reads +system.cpu.fp_regfile_writes 248799 # number of floating regfile writes +system.cpu.misc_regfile_reads 38083 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 83010 # number of replacements -system.cpu.icache.tagsinuse 1916.040169 # Cycle average of tags in use -system.cpu.icache.total_refs 13070837 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 85057 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 153.671503 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1916.040169 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.935566 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 13070837 # number of ReadReq hits -system.cpu.icache.demand_hits 13070837 # number of demand (read+write) hits -system.cpu.icache.overall_hits 13070837 # number of overall hits -system.cpu.icache.ReadReq_misses 87881 # number of ReadReq misses -system.cpu.icache.demand_misses 87881 # number of demand (read+write) misses -system.cpu.icache.overall_misses 87881 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 842081500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 842081500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 842081500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 13158718 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 13158718 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 13158718 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.006679 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.006679 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.006679 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 9582.065520 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 9582.065520 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 9582.065520 # average overall miss latency +system.cpu.icache.replacements 89120 # number of replacements +system.cpu.icache.tagsinuse 1938.678415 # Cycle average of tags in use +system.cpu.icache.total_refs 15241390 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 91168 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 167.179164 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19910148000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 1938.678415 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.946620 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 15241390 # number of ReadReq hits +system.cpu.icache.demand_hits 15241390 # number of demand (read+write) hits +system.cpu.icache.overall_hits 15241390 # number of overall hits +system.cpu.icache.ReadReq_misses 95551 # number of ReadReq misses +system.cpu.icache.demand_misses 95551 # number of demand (read+write) misses +system.cpu.icache.overall_misses 95551 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 914249000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 914249000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 914249000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 15336941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 15336941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 15336941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.006230 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.006230 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.006230 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 9568.178250 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 9568.178250 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 9568.178250 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,132 +343,132 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2823 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2823 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2823 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 85058 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 85058 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 85058 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 4382 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 4382 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 4382 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 91169 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 91169 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 91169 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 517072500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 517072500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 517072500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 543344000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 543344000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 543344000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006464 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.006464 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.006464 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6079.057819 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6079.057819 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.005944 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.005944 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.005944 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 5959.745089 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 5959.745089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 5959.745089 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201055 # number of replacements -system.cpu.dcache.tagsinuse 4076.644885 # Cycle average of tags in use -system.cpu.dcache.total_refs 33980616 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205151 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.637097 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 177876000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.644885 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995275 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 20399248 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 13581325 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 33980573 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 33980573 # number of overall hits -system.cpu.dcache.ReadReq_misses 160360 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1032052 # number of WriteReq misses -system.cpu.dcache.demand_misses 1192412 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1192412 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4313092000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 33595323500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 37908415500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 37908415500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 20559608 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201407 # number of replacements +system.cpu.dcache.tagsinuse 4078.388125 # Cycle average of tags in use +system.cpu.dcache.total_refs 35317915 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205503 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 171.860824 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 157900000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4078.388125 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995700 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 21738841 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 13579023 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 51 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 35317864 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 35317864 # number of overall hits +system.cpu.dcache.ReadReq_misses 251339 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1034354 # number of WriteReq misses +system.cpu.dcache.demand_misses 1285693 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1285693 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 8138657000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 33935878000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 42074535000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 42074535000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 21990180 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 35172985 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 35172985 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.007800 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.070624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.033901 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.033901 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 26896.308306 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32551.967827 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31791.373703 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31791.373703 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses 51 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 36603557 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 36603557 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.011430 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.070781 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.035125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 32381.194323 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 32808.765664 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 32725.180117 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 32725.180117 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 35000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2916.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 161514 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 98657 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 888604 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 987261 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 987261 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 61703 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 143448 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 205151 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 205151 # number of overall MSHR misses +system.cpu.dcache.writebacks 161690 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 189291 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 890899 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1080190 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1080190 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 62048 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 205503 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 205503 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1273620000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4749061000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6022681000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6022681000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1276790500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4734659000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6011449500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6011449500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009816 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.005833 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.005833 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20641.135763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33106.498522 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29357.307544 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002822 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.005614 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.005614 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20577.464221 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33004.489213 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29252.368579 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29252.368579 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 148713 # number of replacements -system.cpu.l2cache.tagsinuse 18791.098718 # Cycle average of tags in use -system.cpu.l2cache.total_refs 131477 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 174075 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.755289 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 149093 # number of replacements +system.cpu.l2cache.tagsinuse 19055.908605 # Cycle average of tags in use +system.cpu.l2cache.total_refs 137732 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 174459 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.789481 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2983.162459 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15807.936259 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.091039 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.482420 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 103089 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 161514 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 12057 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 115146 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 115146 # number of overall hits -system.cpu.l2cache.ReadReq_misses 43650 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 131413 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 175063 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 175063 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1494729000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4516151000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 6010880000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 6010880000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 146739 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 161514 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 143470 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 290209 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 290209 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.297467 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.915962 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.603231 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.603231 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34243.505155 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34366.090113 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34335.524925 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34335.524925 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 3306.185097 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15749.723508 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.100897 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.480643 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 109176 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 161690 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 12067 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 121243 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 121243 # number of overall hits +system.cpu.l2cache.ReadReq_misses 44033 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 131396 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 175429 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 175429 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1515312500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 4525725000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 6041037500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 6041037500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 153209 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 161690 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 143463 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 296672 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 296672 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.287405 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.915888 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.591323 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.591323 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34413.110622 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34443.400104 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34435.797388 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34435.797388 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,27 +477,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 120512 # number of writebacks +system.cpu.l2cache.writebacks 120514 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 43650 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 131413 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 175063 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 175063 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 44033 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 131396 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 175429 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 175429 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1357396500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4107073000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5464469500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5464469500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1366746000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118762500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 5485508500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 5485508500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.297467 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.603231 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.603231 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31097.285223 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31253.171300 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31214.302851 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287405 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915888 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.591323 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.591323 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31039.129744 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31346.178727 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31269.108870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31269.108870 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini index 9419f3f42..0a9838614 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,7 +494,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout index 8322d7ab6..396b675df 100755 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,17 +1,11 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 15:12:09 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 03:29:41 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 36348210000 because target called exit() +Exiting @ tick 36244603000 because target called exit() diff --git a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt index d8be31630..0a5fb1fb1 100644 --- a/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.036348 # Number of seconds simulated -sim_ticks 36348210000 # Number of ticks simulated +sim_seconds 0.036245 # Number of seconds simulated +sim_ticks 36244603000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54516 # Simulator instruction rate (inst/s) -host_tick_rate 19691005 # Simulator tick rate (ticks/s) -host_mem_usage 264076 # Number of bytes of host memory used -host_seconds 1845.93 # Real time elapsed on the host -sim_insts 100633035 # Number of instructions simulated +host_inst_rate 68946 # Simulator instruction rate (inst/s) +host_tick_rate 24831957 # Simulator tick rate (ticks/s) +host_mem_usage 266536 # Number of bytes of host memory used +host_seconds 1459.60 # Real time elapsed on the host +sim_insts 100633890 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,296 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 72696421 # number of cpu cycles simulated +system.cpu.numCycles 72489207 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17573172 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11453458 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 851549 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14915035 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 9554942 # Number of BTB hits +system.cpu.BPredUnit.lookups 18012293 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11774570 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 831874 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 15324494 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 9861947 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1842823 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 176515 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 11675232 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87296891 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17573172 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11397765 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22503406 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 923751 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 11675232 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 177839 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 71670018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.692121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.915842 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1962775 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 178630 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 13228591 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90356599 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18012293 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11824722 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 23464914 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3236873 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 32247240 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1180 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12447619 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 228695 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 71274247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.770511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.958690 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 49181996 68.62% 68.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2373056 3.31% 71.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2569214 3.58% 75.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2298620 3.21% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1644656 2.29% 81.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1723119 2.40% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 990721 1.38% 84.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1380652 1.93% 86.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9507984 13.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 47826013 67.10% 67.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2503425 3.51% 70.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2625051 3.68% 74.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2508744 3.52% 77.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1756176 2.46% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1729968 2.43% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1023399 1.44% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1314592 1.84% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9986879 14.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 71670018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.241734 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.200842 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 25114154 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 22709447 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21527142 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 497633 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1821642 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3527413 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 94287 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118399354 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 324192 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1821642 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 26632137 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2439992 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16812666 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20410601 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3552980 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115899857 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 27143 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2453549 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 118034319 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 532748209 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 532647632 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 100577 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99142525 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18891789 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 756618 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 756606 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 10359843 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29552116 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22027852 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13146932 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 13132796 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 110916590 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 749122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 106735970 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 111004 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10702418 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 27336640 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 48262 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 71670018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.489269 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.647816 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 71274247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248482 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.246483 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15570258 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 30538007 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21052115 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1880159 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2233708 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3555145 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100131 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123096705 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 322054 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2233708 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17831809 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3189949 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20082985 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20587918 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7347878 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 119869132 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 121794 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5771428 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 352 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 121512131 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 551578616 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 551477586 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 101030 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99143893 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 22368233 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 776347 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 776986 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 18154637 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30367199 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22985654 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 18156398 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16040246 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 114470256 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 775996 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107895562 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 172092 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14439119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 40080708 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 74965 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 71274247 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.513809 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.644216 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26697633 37.25% 37.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17182939 23.98% 61.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10552290 14.72% 75.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7611894 10.62% 86.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5202284 7.26% 93.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2658918 3.71% 97.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1053563 1.47% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 496311 0.69% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 214186 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 25395561 35.63% 35.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17825655 25.01% 60.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10968613 15.39% 76.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7406587 10.39% 86.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5364628 7.53% 93.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2359706 3.31% 97.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1195437 1.68% 98.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 581224 0.82% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 176836 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 71670018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 71274247 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 81861 4.61% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1408075 79.27% 83.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 286311 16.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 116212 6.09% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1547826 81.16% 87.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 243196 12.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56941286 53.35% 53.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86568 0.08% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28575402 26.77% 80.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21132684 19.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57756458 53.53% 53.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 87061 0.08% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28748785 26.65% 80.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21303228 19.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 106735970 # Type of FU issued -system.cpu.iq.rate 1.468242 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1776247 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016642 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 287029038 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122376660 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105058655 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 171 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 178 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 108512130 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1096048 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107895562 # Type of FU issued +system.cpu.iq.rate 1.488436 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1907234 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017677 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 289144533 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 129693775 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105980227 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 164 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 164 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109802713 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 83 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1086375 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2243776 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2146 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 9239 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1470884 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3058688 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1951 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 8954 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2428515 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 42 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1821642 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 971169 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 52846 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111742721 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 886869 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29552116 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22027852 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 732058 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3681 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5880 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 9239 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 680356 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 238968 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 919324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 105624762 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28223458 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1111208 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2233708 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1028781 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38378 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115325010 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 602761 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30367199 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22985654 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 758781 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5441 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5622 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 8954 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 689500 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 204403 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 893903 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106692632 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28420136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1202930 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 77009 # number of nop insts executed -system.cpu.iew.exec_refs 49234670 # number of memory reference insts executed -system.cpu.iew.exec_branches 14652571 # Number of branches executed -system.cpu.iew.exec_stores 21011212 # Number of stores executed -system.cpu.iew.exec_rate 1.452957 # Inst execution rate -system.cpu.iew.wb_sent 105223313 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105058729 # cumulative count of insts written-back -system.cpu.iew.wb_producers 51964381 # num instructions producing a value -system.cpu.iew.wb_consumers 99748825 # num instructions consuming a value +system.cpu.iew.exec_nop 78758 # number of nop insts executed +system.cpu.iew.exec_refs 49527893 # number of memory reference insts executed +system.cpu.iew.exec_branches 14765827 # Number of branches executed +system.cpu.iew.exec_stores 21107757 # Number of stores executed +system.cpu.iew.exec_rate 1.471842 # Inst execution rate +system.cpu.iew.wb_sent 106228534 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105980298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 55087779 # num instructions producing a value +system.cpu.iew.wb_consumers 106077594 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.445171 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.520952 # average fanout of values written-back +system.cpu.iew.wb_rate 1.462015 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.519316 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 100638587 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11026953 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 700860 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 821298 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 69848377 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.440815 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.128695 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 100639442 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 14606204 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 701031 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 796162 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 69040540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.457686 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.138867 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31252601 44.74% 44.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 20067748 28.73% 73.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4700774 6.73% 80.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4062261 5.82% 86.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3060219 4.38% 90.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1682719 2.41% 92.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 680213 0.97% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 487977 0.70% 94.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3853865 5.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30680365 44.44% 44.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19612880 28.41% 72.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4794365 6.94% 79.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4311364 6.24% 86.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3142866 4.55% 90.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1355731 1.96% 92.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 737162 1.07% 93.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 515807 0.75% 94.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3890000 5.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 69848377 # Number of insts commited each cycle -system.cpu.commit.count 100638587 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 69040540 # Number of insts commited each cycle +system.cpu.commit.count 100639442 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47865307 # Number of memory references committed -system.cpu.commit.loads 27308339 # Number of loads committed +system.cpu.commit.refs 47865649 # Number of memory references committed +system.cpu.commit.loads 27308510 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13669858 # Number of branches committed +system.cpu.commit.branches 13670029 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91477707 # Number of committed integer instructions. +system.cpu.commit.int_insts 91478391 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3853865 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3890000 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 177634753 # The number of ROB reads -system.cpu.rob.rob_writes 225156428 # The number of ROB writes -system.cpu.timesIdled 61363 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1026403 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 100633035 # Number of Instructions Simulated -system.cpu.committedInsts_total 100633035 # Number of Instructions Simulated -system.cpu.cpi 0.722391 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.722391 # CPI: Total CPI of All Threads -system.cpu.ipc 1.384291 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.384291 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 508078422 # number of integer regfile reads -system.cpu.int_regfile_writes 103555080 # number of integer regfile writes -system.cpu.fp_regfile_reads 153 # number of floating regfile reads -system.cpu.fp_regfile_writes 125 # number of floating regfile writes -system.cpu.misc_regfile_reads 144338885 # number of misc regfile reads -system.cpu.misc_regfile_writes 34300 # number of misc regfile writes -system.cpu.icache.replacements 23105 # number of replacements -system.cpu.icache.tagsinuse 1790.585512 # Cycle average of tags in use -system.cpu.icache.total_refs 11649212 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 25136 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 463.447327 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 180370887 # The number of ROB reads +system.cpu.rob.rob_writes 232731384 # The number of ROB writes +system.cpu.timesIdled 61980 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1214960 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 100633890 # Number of Instructions Simulated +system.cpu.committedInsts_total 100633890 # Number of Instructions Simulated +system.cpu.cpi 0.720326 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.720326 # CPI: Total CPI of All Threads +system.cpu.ipc 1.388260 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.388260 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 512693416 # number of integer regfile reads +system.cpu.int_regfile_writes 104594218 # number of integer regfile writes +system.cpu.fp_regfile_reads 142 # number of floating regfile reads +system.cpu.fp_regfile_writes 118 # number of floating regfile writes +system.cpu.misc_regfile_reads 148024846 # number of misc regfile reads +system.cpu.misc_regfile_writes 34642 # number of misc regfile writes +system.cpu.icache.replacements 27879 # number of replacements +system.cpu.icache.tagsinuse 1824.272906 # Cycle average of tags in use +system.cpu.icache.total_refs 12416599 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 29916 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 415.048770 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1790.585512 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.874309 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 11649212 # number of ReadReq hits -system.cpu.icache.demand_hits 11649212 # number of demand (read+write) hits -system.cpu.icache.overall_hits 11649212 # number of overall hits -system.cpu.icache.ReadReq_misses 26020 # number of ReadReq misses -system.cpu.icache.demand_misses 26020 # number of demand (read+write) misses -system.cpu.icache.overall_misses 26020 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 329928500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 329928500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 329928500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 11675232 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 11675232 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 11675232 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.002229 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.002229 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.002229 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 12679.803997 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 12679.803997 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 12679.803997 # average overall miss latency +system.cpu.icache.occ_blocks::0 1824.272906 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.890758 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 12416599 # number of ReadReq hits +system.cpu.icache.demand_hits 12416599 # number of demand (read+write) hits +system.cpu.icache.overall_hits 12416599 # number of overall hits +system.cpu.icache.ReadReq_misses 31020 # number of ReadReq misses +system.cpu.icache.demand_misses 31020 # number of demand (read+write) misses +system.cpu.icache.overall_misses 31020 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 368970500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 368970500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 368970500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 12447619 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 12447619 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 12447619 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.002492 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.002492 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.002492 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 11894.600258 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 11894.600258 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 11894.600258 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,145 +354,143 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 875 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 875 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 875 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 25145 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 25145 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 25145 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1093 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1093 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1093 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 29927 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 29927 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 29927 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 230769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 230769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 230769000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 251359000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 251359000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 251359000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.002154 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.002154 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.002154 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 9177.530324 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.002404 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.002404 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.002404 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 8399.071073 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 8399.071073 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 157197 # number of replacements -system.cpu.dcache.tagsinuse 4074.737833 # Cycle average of tags in use -system.cpu.dcache.total_refs 45133660 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 161293 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 279.824047 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 314597000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4074.737833 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.994809 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 26793039 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 18304159 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 19298 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 17149 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 45097198 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 45097198 # number of overall hits -system.cpu.dcache.ReadReq_misses 104208 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1545742 # number of WriteReq misses +system.cpu.dcache.replacements 157560 # number of replacements +system.cpu.dcache.tagsinuse 4075.609715 # Cycle average of tags in use +system.cpu.dcache.total_refs 45320510 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 161656 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 280.351549 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 305782000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4075.609715 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995022 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 26986553 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 18297687 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 18928 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 17320 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 45284240 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 45284240 # number of overall hits +system.cpu.dcache.ReadReq_misses 104971 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1552214 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 31 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 1649950 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1649950 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2387617500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 50445288500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 403500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 52832906000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 52832906000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 26897247 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 1657185 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1657185 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2340490500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 51751425000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 435500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 54091915500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 54091915500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 27091524 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 19329 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 17149 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46747148 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46747148 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.003874 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.077872 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.001604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.035295 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.035295 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 22912.036504 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 32634.998920 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 13016.129032 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 32020.913361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 32020.913361 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 18959 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 17320 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 46941425 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 46941425 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.003875 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.078198 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.001635 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.035303 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.035303 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 22296.543807 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33340.393142 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 14048.387097 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 32640.843056 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 32640.843056 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 170000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 165500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18888.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18388.888889 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 123219 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 49816 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1438831 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 123328 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 50205 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1445313 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 31 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1488647 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1488647 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 54392 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 106911 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 161303 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 161303 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 1495518 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1495518 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 54766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 106901 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 161667 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 161667 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1030956000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3651524500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4682480500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4682480500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1030464500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3652588500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4683053000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4683053000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003451 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003451 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18954.184439 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34154.806334 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate 0.005385 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.003444 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.003444 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18815.770734 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34167.954463 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 28967.278418 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 28967.278418 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 114546 # number of replacements -system.cpu.l2cache.tagsinuse 18280.291791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 68908 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 133392 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.516583 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 114937 # number of replacements +system.cpu.l2cache.tagsinuse 18374.975698 # Cycle average of tags in use +system.cpu.l2cache.total_refs 73734 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 133793 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.551105 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2302.452210 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15977.839581 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.070265 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487605 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 47261 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 123219 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 4298 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 51559 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 51559 # number of overall hits -system.cpu.l2cache.ReadReq_misses 32262 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 102605 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 134867 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 134867 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1107753000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 34000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3528908000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 4636661000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 4636661000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 79523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 123219 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 9 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 106903 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 186426 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 186426 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.405694 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.444444 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.959795 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.723434 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.723434 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34336.153989 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 8500 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34393.138736 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34379.507218 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34379.507218 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2397.200904 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15977.774794 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.073157 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487603 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 51991 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 123328 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 4303 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 56294 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 56294 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32687 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 7 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 102588 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 135275 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 135275 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1117411000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3525778500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4643189500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4643189500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 84678 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 123328 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 106891 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 191569 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 191569 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.386015 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.636364 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.959744 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.706142 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.706142 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34185.180653 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.332554 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34324.076880 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34324.076880 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,32 +499,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88455 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 63 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 32199 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102605 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 134804 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 134804 # number of overall MSHR misses +system.cpu.l2cache.writebacks 88452 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32606 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 102588 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 135194 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 135194 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1001736500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205255000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 4206991500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 4206991500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1012684500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 217000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3200382500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4213067000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4213067000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.404902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.444444 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959795 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.723097 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.723097 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31110.795366 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.385059 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.636364 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959744 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.705720 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.705720 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31058.225480 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.779787 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31196.460600 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.121144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.121144 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index 6cb2c5232..e32660b85 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout index a850d490c..1fce660ea 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 08:31:13 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/inorder-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 17:14:45 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1016488689500 because target called exit() +Exiting @ tick 1009857089500 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index a608e7e97..48a5816be 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.016489 # Number of seconds simulated -sim_ticks 1016488689500 # Number of ticks simulated +sim_seconds 1.009857 # Number of seconds simulated +sim_ticks 1009857089500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111625 # Simulator instruction rate (inst/s) -host_tick_rate 62351436 # Simulator tick rate (ticks/s) -host_mem_usage 193064 # Number of bytes of host memory used -host_seconds 16302.57 # Real time elapsed on the host +host_inst_rate 45175 # Simulator instruction rate (inst/s) +host_tick_rate 25069239 # Simulator tick rate (ticks/s) +host_mem_usage 245844 # Number of bytes of host memory used +host_seconds 40282.72 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444614416 # DTB read hits +system.cpu.dtb.read_hits 444614420 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449511494 # DTB read accesses -system.cpu.dtb.write_hits 160920901 # DTB write hits +system.cpu.dtb.read_accesses 449511498 # DTB read accesses +system.cpu.dtb.write_hits 160920903 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162622205 # DTB write accesses -system.cpu.dtb.data_hits 605535317 # DTB hits +system.cpu.dtb.write_accesses 162622207 # DTB write accesses +system.cpu.dtb.data_hits 605535323 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612133699 # DTB accesses -system.cpu.itb.fetch_hits 237932826 # ITB hits +system.cpu.dtb.data_accesses 612133705 # DTB accesses +system.cpu.itb.fetch_hits 233080732 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 237932848 # ITB accesses +system.cpu.itb.fetch_accesses 233080754 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2032977380 # number of cpu cycles simulated +system.cpu.numCycles 2019714180 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1759886457 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746235830 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533536 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 440243372 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1592734008 # Number of cycles cpu stages are processed. -system.cpu.activity 78.344896 # Percentage of cycles cpu is active +system.cpu.timesIdled 7533712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 442869413 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576844767 # Number of cycles cpu stages are processed. +system.cpu.activity 78.072669 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -61,85 +61,85 @@ system.cpu.comFloats 190 # Nu system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total) -system.cpu.cpi 1.117156 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.117156 # CPI: Total CPI of All Threads -system.cpu.ipc 0.895131 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901009 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.895131 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 338882102 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 262365824 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 145832523 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 223761389 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 153206045 # Number of BTB hits +system.cpu.ipc_total 0.901009 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 330376347 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 257464252 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140461747 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 220099806 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 142435401 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 68.468490 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 189687399 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 149194703 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667621622 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 64.714006 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 178933469 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 151442878 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1665721133 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043824239 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 226 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3041923750 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 571 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 655476684 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617179738 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 132311663 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 6922402 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 139234065 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 75965071 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 64.700104 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1137833135 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 654640669 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617252269 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 126684712 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 7178577 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133863289 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81336473 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.204199 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1137868323 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 823371490 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1209605890 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.499230 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1094712452 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 938264928 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.152256 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1056818268 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 976159112 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.016231 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1623201304 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409776076 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.156450 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 1008711848 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1024265532 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.382535 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 827214176 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1192500004 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.043008 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1086300254 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933413926 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.215149 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1046559994 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973154186 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.182767 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1609984436 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409729744 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.286521 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 997434545 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022279635 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.615065 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 664.417711 # Cycle average of tags in use -system.cpu.icache.total_refs 237931761 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 664.479191 # Cycle average of tags in use +system.cpu.icache.total_refs 233079667 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 277309.744755 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 664.417711 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.324423 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 237931761 # number of ReadReq hits -system.cpu.icache.demand_hits 237931761 # number of demand (read+write) hits -system.cpu.icache.overall_hits 237931761 # number of overall hits +system.cpu.icache.occ_blocks::0 664.479191 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.324453 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 233079667 # number of ReadReq hits +system.cpu.icache.demand_hits 233079667 # number of demand (read+write) hits +system.cpu.icache.overall_hits 233079667 # number of overall hits system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses system.cpu.icache.overall_misses 1062 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 58372500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 58372500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 58372500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 237932823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 237932823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 237932823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54964.689266 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54964.689266 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54964.689266 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 58337000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 58337000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 58337000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 233080729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 233080729 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 233080729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 54931.261770 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 54931.261770 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 54931.261770 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 81000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks @@ -150,97 +150,97 @@ system.cpu.icache.ReadReq_mshr_misses 858 # nu system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45874500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45874500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45874500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45872500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45872500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45872500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53466.783217 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53466.783217 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.698985 # Cycle average of tags in use -system.cpu.dcache.total_refs 595070238 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use +system.cpu.dcache.total_refs 595070081 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310172 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12613555000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4082.698985 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.996753 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 437271427 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 157798811 # number of WriteReq hits -system.cpu.dcache.demand_hits 595070238 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 595070238 # number of overall hits -system.cpu.dcache.ReadReq_misses 7324236 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 2929691 # number of WriteReq misses -system.cpu.dcache.demand_misses 10253927 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 10253927 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 180890019000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110280256500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 291170275500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 291170275500 # number of overall miss cycles +system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4082.611665 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.996731 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 437271428 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 157798653 # number of WriteReq hits +system.cpu.dcache.demand_hits 595070081 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 595070081 # number of overall hits +system.cpu.dcache.ReadReq_misses 7324235 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 2929849 # number of WriteReq misses +system.cpu.dcache.demand_misses 10254084 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 10254084 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 180892053500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110288339500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 291180393000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 291180393000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.018228 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.018229 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24697.459093 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37642.282582 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 28395.977024 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 28395.977024 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10999500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8090380500 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 28396.528934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 28396.528934 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208980 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.882651 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38713.659202 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 208994 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 3058572 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 101954 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1040525 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1142479 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1142479 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 101953 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1040683 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1142636 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1142636 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 156087353000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 59191861000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 215279214000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 215279214000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 59191835500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 215279506500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 215279506500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.916151 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.270960 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23627.332780 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2686299 # number of replacements -system.cpu.l2cache.tagsinuse 26362.253179 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 225759748000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15507.582634 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10854.670545 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.473254 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.331258 # Average percentage of cache occupancy +system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15511.274798 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10843.964569 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.473367 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.330932 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 5414817 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 3058572 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 1000333 # number of ReadExReq hits @@ -250,10 +250,10 @@ system.cpu.l2cache.ReadReq_misses 1807881 # nu system.cpu.l2cache.ReadExReq_misses 889275 # number of ReadExReq misses system.cpu.l2cache.demand_misses 2697156 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 2697156 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 94453448000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 46507349000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 140960797000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 140960797000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 94453509000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 46507390000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 140960899000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 140960899000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 7222698 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 3058572 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1889608 # number of ReadExReq accesses(hits+misses) @@ -263,10 +263,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.250305 # mi system.cpu.l2cache.ReadExReq_miss_rate 0.470613 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.295990 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.295990 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52245.390045 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.050659 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52262.752692 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52262.752692 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52245.423786 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.096764 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52262.790510 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52262.790510 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -283,19 +283,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 889275 # nu system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72354306000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671086000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 108025392000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 108025392000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 72354298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671113500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 108025412000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 108025412000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250305 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470613 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.295990 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.608723 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.547862 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.592121 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.604575 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 73cbafb08..d0874930c 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 96ed5aa20..ffc7fc253 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:58:23 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 17:16:45 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 701966325500 because target called exit() +Exiting @ tick 635013348500 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index ebab377c0..dda342878 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.701966 # Number of seconds simulated -sim_ticks 701966325500 # Number of ticks simulated +sim_seconds 0.635013 # Number of seconds simulated +sim_ticks 635013348500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187255 # Simulator instruction rate (inst/s) -host_tick_rate 75716158 # Simulator tick rate (ticks/s) -host_mem_usage 193592 # Number of bytes of host memory used -host_seconds 9271.02 # Real time elapsed on the host +host_inst_rate 68058 # Simulator instruction rate (inst/s) +host_tick_rate 24894495 # Simulator tick rate (ticks/s) +host_mem_usage 246392 # Number of bytes of host memory used +host_seconds 25508.18 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 563960671 # DTB read hits -system.cpu.dtb.read_misses 9341526 # DTB read misses +system.cpu.dtb.read_hits 603338361 # DTB read hits +system.cpu.dtb.read_misses 10295627 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 573302197 # DTB read accesses -system.cpu.dtb.write_hits 197357333 # DTB write hits -system.cpu.dtb.write_misses 6267768 # DTB write misses +system.cpu.dtb.read_accesses 613633988 # DTB read accesses +system.cpu.dtb.write_hits 208599183 # DTB write hits +system.cpu.dtb.write_misses 6680918 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 203625101 # DTB write accesses -system.cpu.dtb.data_hits 761318004 # DTB hits -system.cpu.dtb.data_misses 15609294 # DTB misses +system.cpu.dtb.write_accesses 215280101 # DTB write accesses +system.cpu.dtb.data_hits 811937544 # DTB hits +system.cpu.dtb.data_misses 16976545 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 776927298 # DTB accesses -system.cpu.itb.fetch_hits 346935606 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.dtb.data_accesses 828914089 # DTB accesses +system.cpu.itb.fetch_hits 391544242 # ITB hits +system.cpu.itb.fetch_misses 36 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 346935639 # ITB accesses +system.cpu.itb.fetch_accesses 391544278 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,244 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1403932652 # number of cpu cycles simulated +system.cpu.numCycles 1270026698 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 338874509 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 261227143 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19849428 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 299029010 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 292400183 # Number of BTB hits +system.cpu.BPredUnit.lookups 374312464 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 289169438 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19496445 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 340941395 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 334345011 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 23706003 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 138 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 346935606 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2804810127 # Number of instructions fetch has processed -system.cpu.fetch.Branches 338874509 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 316106186 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 547160939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26702024 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 346935606 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8134553 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1395248756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.010258 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.885668 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 24666648 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 1937 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 404704037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3147798119 # Number of instructions fetch has processed +system.cpu.fetch.Branches 374312464 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 359011659 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 616794499 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 137998027 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 125668111 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 951 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 391544242 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8927962 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1258617999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.500996 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.012045 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 848087817 60.78% 60.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47124000 3.38% 64.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30216424 2.17% 66.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 49573099 3.55% 69.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 121201096 8.69% 78.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 67474425 4.84% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 44590738 3.20% 86.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37036211 2.65% 89.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 149944946 10.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 641823500 50.99% 50.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53319636 4.24% 55.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 35799554 2.84% 58.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 54964384 4.37% 62.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 137079474 10.89% 73.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 75209346 5.98% 79.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 52974044 4.21% 83.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 43807155 3.48% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 163640906 13.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1395248756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.241375 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.997824 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 704925020 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 69300100 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 533426665 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3666895 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 83930076 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 53326576 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 734 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2753583044 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1732 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 83930076 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 721970868 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45015493 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 836 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 519735088 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24596395 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2693944594 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 493414 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2058465 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19605286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2019690549 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3482054752 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3481179365 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 875387 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1258617999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.294728 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.478529 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434225808 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 112156946 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 585871640 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 14914010 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 111449595 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58364893 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 867 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3066482661 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1948 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 111449595 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 456759816 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 64512146 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 4249 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 576631270 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49260923 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2982899565 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 509098 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7685931 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 38326944 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2232338965 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3854814610 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3853783957 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1030653 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 643487586 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 51588618 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 610412990 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 227416042 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58011440 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 46695485 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2439995648 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2302863011 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 443983 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 686898644 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 276282436 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1395248756 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.650504 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.793673 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 856136002 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 193 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 190 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103200080 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 676333170 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 252017068 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 107962644 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 56514638 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2687392423 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 179 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2469741583 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1752104 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 940434860 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416211296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 150 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1258617999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.962265 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.926131 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 526952247 37.77% 37.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 258740979 18.54% 56.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 229473715 16.45% 72.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 137779252 9.87% 82.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 109981774 7.88% 90.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 76286512 5.47% 95.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43503715 3.12% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10789596 0.77% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1740966 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 411515074 32.70% 32.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 202456949 16.09% 48.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 202249342 16.07% 64.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 156364195 12.42% 77.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 139152023 11.06% 88.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73667183 5.85% 94.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 48795801 3.88% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19364904 1.54% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5052528 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1395248756 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1258617999 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2979112 23.54% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 23.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7017383 55.45% 79.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2657829 21.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3576452 24.84% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9406298 65.33% 90.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1415397 9.83% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1511867682 65.65% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 234 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 136 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 584171534 25.37% 91.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 206823272 8.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1617611726 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 92 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 252 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 20 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 146 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 18 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 631548427 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 220580878 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2302863011 # Type of FU issued -system.cpu.iq.rate 1.640295 # Inst issue rate -system.cpu.iq.fu_busy_cnt 12654324 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005495 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6012429707 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3126227824 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2223790719 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1643378 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 858249 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 816998 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2314695639 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 821696 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 39718780 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2469741583 # Type of FU issued +system.cpu.iq.rate 1.944638 # Inst issue rate +system.cpu.iq.fu_busy_cnt 14398147 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005830 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6212471762 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3627257196 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2370962102 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1779654 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1040695 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 834376 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2483251910 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 887820 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 52535371 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 165817327 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 292481 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 198174 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 66687540 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 231737507 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 276679 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 497053 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 91288566 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162061 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 59 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 156775 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 83930076 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12833645 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 949861 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2568259823 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 23291799 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 610412990 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 227416042 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 698616 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16282 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 198174 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18296998 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3374280 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 21671278 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2265186271 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573302204 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 37676740 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 111449595 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23764552 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1337877 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2830649403 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12818049 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 676333170 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 252017068 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 179 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 569958 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 21987 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 497053 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 20334660 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2042240 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22376900 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2418005225 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 613634241 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 51736358 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 128264130 # number of nop insts executed -system.cpu.iew.exec_refs 776927311 # number of memory reference insts executed -system.cpu.iew.exec_branches 278210520 # Number of branches executed -system.cpu.iew.exec_stores 203625107 # Number of stores executed -system.cpu.iew.exec_rate 1.613458 # Inst execution rate -system.cpu.iew.wb_sent 2246216503 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2224607717 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1225810379 # num instructions producing a value -system.cpu.iew.wb_consumers 1505740839 # num instructions consuming a value +system.cpu.iew.exec_nop 143256801 # number of nop insts executed +system.cpu.iew.exec_refs 828914361 # number of memory reference insts executed +system.cpu.iew.exec_branches 295415710 # Number of branches executed +system.cpu.iew.exec_stores 215280120 # Number of stores executed +system.cpu.iew.exec_rate 1.903901 # Inst execution rate +system.cpu.iew.wb_sent 2397586638 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2371796478 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1365189773 # num instructions producing a value +system.cpu.iew.wb_consumers 1727887810 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.584554 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.814091 # average fanout of values written-back +system.cpu.iew.wb_rate 1.867517 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790092 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 560481052 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 780151578 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19848912 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1311318680 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.387748 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.144873 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19495666 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1147168404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.586323 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.463059 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 679377178 51.81% 51.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 251802247 19.20% 71.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 122784402 9.36% 80.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79744679 6.08% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 49330681 3.76% 90.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25797964 1.97% 92.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24618038 1.88% 94.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 13753662 1.05% 95.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 64109829 4.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 609653045 53.14% 53.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194676784 16.97% 70.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 91786029 8.00% 78.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52706326 4.59% 82.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 37714625 3.29% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27440530 2.39% 88.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24523987 2.14% 90.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 21129390 1.84% 92.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 87537688 7.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1311318680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1147168404 # Number of insts commited each cycle system.cpu.commit.count 1819780126 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 605324165 # Number of memory references committed @@ -288,50 +290,50 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 64109829 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 87537688 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3541690829 # The number of ROB reads -system.cpu.rob.rob_writes 4844528665 # The number of ROB writes -system.cpu.timesIdled 283673 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8683896 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3573783220 # The number of ROB reads +system.cpu.rob.rob_writes 5311487808 # The number of ROB writes +system.cpu.timesIdled 516531 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11408699 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.808697 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.808697 # CPI: Total CPI of All Threads -system.cpu.ipc 1.236558 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.236558 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3052265091 # number of integer regfile reads -system.cpu.int_regfile_writes 1775418368 # number of integer regfile writes -system.cpu.fp_regfile_reads 788 # number of floating regfile reads -system.cpu.fp_regfile_writes 457 # number of floating regfile writes +system.cpu.cpi 0.731564 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.731564 # CPI: Total CPI of All Threads +system.cpu.ipc 1.366935 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.366935 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3252607111 # number of integer regfile reads +system.cpu.int_regfile_writes 1898786107 # number of integer regfile writes +system.cpu.fp_regfile_reads 15156 # number of floating regfile reads +system.cpu.fp_regfile_writes 507 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 716.407669 # Cycle average of tags in use -system.cpu.icache.total_refs 346934350 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 913 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379993.811610 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 750.127276 # Cycle average of tags in use +system.cpu.icache.total_refs 391542886 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 943 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 415209.847296 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 716.407669 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.349808 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 346934350 # number of ReadReq hits -system.cpu.icache.demand_hits 346934350 # number of demand (read+write) hits -system.cpu.icache.overall_hits 346934350 # number of overall hits -system.cpu.icache.ReadReq_misses 1256 # number of ReadReq misses -system.cpu.icache.demand_misses 1256 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1256 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 44264500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 44264500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 44264500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 346935606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 346935606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 346935606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35242.436306 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35242.436306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35242.436306 # average overall miss latency +system.cpu.icache.occ_blocks::0 750.127276 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.366273 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 391542886 # number of ReadReq hits +system.cpu.icache.demand_hits 391542886 # number of demand (read+write) hits +system.cpu.icache.overall_hits 391542886 # number of overall hits +system.cpu.icache.ReadReq_misses 1356 # number of ReadReq misses +system.cpu.icache.demand_misses 1356 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1356 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 47427000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 47427000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 47427000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 391544242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 391544242 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 391544242 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34975.663717 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34975.663717 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34975.663717 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,169 +343,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 913 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 913 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 913 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 413 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 413 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 413 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 943 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 943 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 943 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 32355500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 32355500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 32355500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 33462000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 33462000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35438.663746 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35438.663746 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35484.623542 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35484.623542 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35484.623542 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9157179 # number of replacements -system.cpu.dcache.tagsinuse 4085.228479 # Cycle average of tags in use -system.cpu.dcache.total_refs 670151457 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9161275 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 73.150457 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7052593000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4085.228479 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997370 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 514173767 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 155977688 # number of WriteReq hits +system.cpu.dcache.replacements 9159383 # number of replacements +system.cpu.dcache.tagsinuse 4087.248136 # Cycle average of tags in use +system.cpu.dcache.total_refs 696439531 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9163479 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.001651 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5155151000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.248136 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997863 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 540576764 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 155862765 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 670151455 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 670151455 # number of overall hits -system.cpu.dcache.ReadReq_misses 9991104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 4750814 # number of WriteReq misses +system.cpu.dcache.demand_hits 696439529 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 696439529 # number of overall hits +system.cpu.dcache.ReadReq_misses 10153388 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 4865737 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 14741918 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 14741918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 163432688000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 130710984385 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 15019125 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 15019125 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 168572903500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 135364757471 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 294143672385 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 294143672385 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 524164871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 303937660971 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 303937660971 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 550730152 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 684893373 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 684893373 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.019061 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.029558 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 711458654 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 711458654 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.018436 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.030273 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.021524 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021524 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16357.820717 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27513.387050 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.021110 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021110 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16602.625990 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27819.990573 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19952.876714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19952.876714 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 118978242 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148369500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37718 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65111 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.415452 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32995.492313 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency 20236.708928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 20236.708928 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 117209937 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2148380000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37031 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65114 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3165.184224 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 32994.133366 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3077964 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2714607 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2866037 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5580644 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5580644 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7276497 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1884777 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks 3077410 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2875087 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 2980560 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 5855647 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 5855647 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7278301 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1885177 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9161274 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9161274 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 9163478 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9163478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 79873683500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38583654034 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 80739671500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38395339625 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 118457337534 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 118457337534 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 119135011125 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 119135011125 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.013882 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011726 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013216 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011729 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.013376 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.013376 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10976.941721 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20471.203773 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.012880 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.012880 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11093.203139 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20366.967996 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12930.225374 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13001.069149 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13001.069149 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2693244 # number of replacements -system.cpu.l2cache.tagsinuse 26559.957454 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7631725 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2717889 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.807961 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 146645124500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15818.650272 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10741.307183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.482747 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.327799 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5456843 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3077964 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 1001508 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6458351 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6458351 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1820566 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2703837 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2703837 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 62492759000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 30435881500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 92928640500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 92928640500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7277409 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3077964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1884779 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9162188 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9162188 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.250167 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.468634 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34326.005759 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34458.146481 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34369.172587 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34369.172587 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 17559500 # number of cycles access was blocked +system.cpu.l2cache.replacements 2693761 # number of replacements +system.cpu.l2cache.tagsinuse 26701.570875 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7632488 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2718396 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.807717 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 128397458500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15961.645382 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10739.925493 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.487111 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.327757 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5458441 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3077410 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 1001668 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6460109 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6460109 # number of overall hits +system.cpu.l2cache.ReadReq_misses 1820800 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 883513 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2704313 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2704313 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 62491098500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 30447807000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 92938905500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 92938905500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7279241 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3077410 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1885181 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9164422 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9164422 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.250136 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.468662 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.295088 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.295088 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34320.682392 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34462.205989 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34366.918881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34366.918881 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 17342500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1697 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1668 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10347.377725 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10397.182254 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1171773 # number of writebacks +system.cpu.l2cache.writebacks 1171800 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1820566 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2703837 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2703837 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 1820800 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 883513 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2704313 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2704313 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56685679500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 27620893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 84306572500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 84306572500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 56720900500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 27626952000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 84347852500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 84347852500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250167 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468634 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.294702 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31271.142152 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31180.345746 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468662 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.295088 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.295088 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31151.636918 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31269.434632 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31190.122038 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31190.122038 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini index 2386e9fa4..9b272f457 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout index 2decff9a6..fe3177229 100755 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 19:27:10 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 03:49:53 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -30,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 566011920000 because target called exit() +Exiting @ tick 524441606000 because target called exit() diff --git a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 974fb936f..f09bdc94a 100644 --- a/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.566012 # Number of seconds simulated -sim_ticks 566011920000 # Number of ticks simulated +sim_seconds 0.524442 # Number of seconds simulated +sim_ticks 524441606000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52057 # Simulator instruction rate (inst/s) -host_tick_rate 17100212 # Simulator tick rate (ticks/s) -host_mem_usage 255500 # Number of bytes of host memory used -host_seconds 33099.70 # Real time elapsed on the host -sim_insts 1723073884 # Number of instructions simulated +host_inst_rate 101251 # Simulator instruction rate (inst/s) +host_tick_rate 30817067 # Simulator tick rate (ticks/s) +host_mem_usage 257952 # Number of bytes of host memory used +host_seconds 17017.90 # Real time elapsed on the host +sim_insts 1723073904 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,297 +51,300 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1132023841 # number of cpu cycles simulated +system.cpu.numCycles 1048883213 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 287218932 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 236434259 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18348095 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 250920104 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 213740165 # Number of BTB hits +system.cpu.BPredUnit.lookups 317450426 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 259852467 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18436703 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 279904663 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 254677721 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18278609 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 393 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 265451297 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2081730004 # Number of instructions fetch has processed -system.cpu.fetch.Branches 287218932 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 232018774 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 452716467 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20281434 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 265451297 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5801201 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1120688032 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.061143 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.942664 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 20220648 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 4428 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 315501768 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2280935015 # Number of instructions fetch has processed +system.cpu.fetch.Branches 317450426 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 274898369 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 509081814 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 103935328 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 124227879 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 270 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 303015456 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6379891 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1031116877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.459992 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.013809 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 667971623 59.60% 59.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32961041 2.94% 62.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 55903718 4.99% 67.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 56895013 5.08% 72.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 45557119 4.07% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 54242890 4.84% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 48750643 4.35% 85.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18749981 1.67% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 139656004 12.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 522035116 50.63% 50.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 37818104 3.67% 54.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 65533745 6.36% 60.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 69512456 6.74% 67.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 53414736 5.18% 72.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61047606 5.92% 78.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 57075579 5.54% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19670108 1.91% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 145009427 14.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1120688032 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.253722 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.838945 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 546126816 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 71463989 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 435974123 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6702645 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60420459 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 43189829 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 635 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2259641783 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2302 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60420459 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 563998095 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40175582 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14256 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 424146965 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 31932675 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2194117520 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 11722 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3482918 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25684334 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2171048745 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10125608138 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10125607580 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 558 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706320007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 464728733 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 633 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 629 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66642282 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 598549667 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 212535274 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87730642 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 84698913 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112468775 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1975042527 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 852567 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 380766314 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 858455180 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1120688032 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.762348 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.680120 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1031116877 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.302656 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.174632 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 346461175 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 106173290 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 477865699 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18312225 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 82304488 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 48528259 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 664 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2473135818 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2289 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 82304488 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 368931509 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50902781 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20077 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 472181274 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56776748 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2411760057 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18939 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5901279 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 44092765 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2386823429 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 11134835710 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 11134834246 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1464 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706320039 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 680503385 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 855 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 848 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 119214990 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 651763451 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 230362141 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 123114303 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 108844207 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2285934828 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 851 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2067906375 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3040241 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 557691684 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1352307582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 383 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1031116877 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.005501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.810247 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 337912961 30.15% 30.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 234234895 20.90% 51.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 220010483 19.63% 70.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 141420525 12.62% 83.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 101836492 9.09% 92.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 53894209 4.81% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 20983167 1.87% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9353324 0.83% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1041976 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 302093175 29.30% 29.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 161453829 15.66% 44.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185974655 18.04% 62.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 152722281 14.81% 77.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 122859599 11.92% 89.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 63855935 6.19% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 30343304 2.94% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10954294 1.06% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 859805 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1120688032 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1031116877 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 517494 2.12% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 23433886 96.11% 98.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 430313 1.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 735734 3.76% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 145 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17865428 91.35% 95.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 956298 4.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219473147 61.74% 61.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1083372 0.05% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 566098039 28.66% 90.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 188387953 9.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1267972738 61.32% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1165735 0.06% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 9 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 605808033 29.30% 90.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192959848 9.33% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1975042527 # Type of FU issued -system.cpu.iq.rate 1.744700 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24381694 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5096007233 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2495143403 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1922135162 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 114 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1999424161 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 34829517 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2067906375 # Type of FU issued +system.cpu.iq.rate 1.971532 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19557605 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009458 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5189527225 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2846700346 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1993811028 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 248 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 105 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2087463854 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 48700640 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 112622888 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 463072 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1914554 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 37688221 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 165836668 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 182984 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3082033 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55515084 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 273360 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 451401 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60420459 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18632955 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1195402 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112469674 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6157143 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 598549667 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 212535274 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 546 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 334650 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1914554 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 16889121 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3256921 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 20146042 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1946822051 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 556717785 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 28220476 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 82304488 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22549936 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1320929 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2286019853 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6521602 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 651763451 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 230362141 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 777 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 333118 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 65136 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 3082033 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18892989 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1847041 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 20740030 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2026288483 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 583345448 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 41617892 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 283 # number of nop insts executed -system.cpu.iew.exec_refs 742905406 # number of memory reference insts executed -system.cpu.iew.exec_branches 235411550 # Number of branches executed -system.cpu.iew.exec_stores 186187621 # Number of stores executed -system.cpu.iew.exec_rate 1.719771 # Inst execution rate -system.cpu.iew.wb_sent 1926889510 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1922135210 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1211916900 # num instructions producing a value -system.cpu.iew.wb_consumers 1896005064 # num instructions consuming a value +system.cpu.iew.exec_nop 84174 # number of nop insts executed +system.cpu.iew.exec_refs 773137523 # number of memory reference insts executed +system.cpu.iew.exec_branches 241378100 # Number of branches executed +system.cpu.iew.exec_stores 189792075 # Number of stores executed +system.cpu.iew.exec_rate 1.931853 # Inst execution rate +system.cpu.iew.wb_sent 2004592772 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1993811133 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1313765556 # num instructions producing a value +system.cpu.iew.wb_consumers 2094642495 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.697964 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.639195 # average fanout of values written-back +system.cpu.iew.wb_rate 1.900890 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.627203 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1723073902 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 389560093 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 464 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18347567 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1060267574 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.625131 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.338631 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1723073922 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 563083903 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 468 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 18443845 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 948812390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.816032 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.570732 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 472290035 44.54% 44.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 255203775 24.07% 68.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110318720 10.40% 79.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55061761 5.19% 84.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28404469 2.68% 86.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27943387 2.64% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20897685 1.97% 91.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 17855453 1.68% 93.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 72292289 6.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 421119309 44.38% 44.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 219659546 23.15% 67.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 84920332 8.95% 76.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 40130029 4.23% 80.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24924955 2.63% 83.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30334777 3.20% 86.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 23612661 2.49% 89.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12752294 1.34% 90.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 91358487 9.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1060267574 # Number of insts commited each cycle -system.cpu.commit.count 1723073902 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 948812390 # Number of insts commited each cycle +system.cpu.commit.count 1723073922 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773831 # Number of memory references committed -system.cpu.commit.loads 485926778 # Number of loads committed +system.cpu.commit.refs 660773839 # Number of memory references committed +system.cpu.commit.loads 485926782 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462372 # Number of branches committed +system.cpu.commit.branches 213462376 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941881 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941897 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 72292289 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 91358487 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3100608681 # The number of ROB reads -system.cpu.rob.rob_writes 4285815110 # The number of ROB writes -system.cpu.timesIdled 696063 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11335809 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1723073884 # Number of Instructions Simulated -system.cpu.committedInsts_total 1723073884 # Number of Instructions Simulated -system.cpu.cpi 0.656979 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.656979 # CPI: Total CPI of All Threads -system.cpu.ipc 1.522118 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.522118 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9738255749 # number of integer regfile reads -system.cpu.int_regfile_writes 1902471542 # number of integer regfile writes -system.cpu.fp_regfile_reads 36 # number of floating regfile reads -system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.misc_regfile_reads 2800450937 # number of misc regfile reads -system.cpu.misc_regfile_writes 140 # number of misc regfile writes +system.cpu.rob.rob_reads 3143611129 # The number of ROB reads +system.cpu.rob.rob_writes 4654874733 # The number of ROB writes +system.cpu.timesIdled 997575 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17766336 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1723073904 # Number of Instructions Simulated +system.cpu.committedInsts_total 1723073904 # Number of Instructions Simulated +system.cpu.cpi 0.608728 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.608728 # CPI: Total CPI of All Threads +system.cpu.ipc 1.642770 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.642770 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10134733413 # number of integer regfile reads +system.cpu.int_regfile_writes 1980533280 # number of integer regfile writes +system.cpu.fp_regfile_reads 92 # number of floating regfile reads +system.cpu.fp_regfile_writes 35 # number of floating regfile writes +system.cpu.misc_regfile_reads 3028358925 # number of misc regfile reads +system.cpu.misc_regfile_writes 148 # number of misc regfile writes system.cpu.icache.replacements 9 # number of replacements -system.cpu.icache.tagsinuse 573.017722 # Cycle average of tags in use -system.cpu.icache.total_refs 265450383 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 717 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370223.686192 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 611.010403 # Cycle average of tags in use +system.cpu.icache.total_refs 303014437 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 739 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 410033.067659 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 573.017722 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.279794 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 265450383 # number of ReadReq hits -system.cpu.icache.demand_hits 265450383 # number of demand (read+write) hits -system.cpu.icache.overall_hits 265450383 # number of overall hits -system.cpu.icache.ReadReq_misses 914 # number of ReadReq misses -system.cpu.icache.demand_misses 914 # number of demand (read+write) misses -system.cpu.icache.overall_misses 914 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 32210500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 32210500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 32210500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 265451297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 265451297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 265451297 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 611.010403 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.298345 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 303014437 # number of ReadReq hits +system.cpu.icache.demand_hits 303014437 # number of demand (read+write) hits +system.cpu.icache.overall_hits 303014437 # number of overall hits +system.cpu.icache.ReadReq_misses 1019 # number of ReadReq misses +system.cpu.icache.demand_misses 1019 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1019 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 35224000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 35224000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 35224000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 303015456 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 303015456 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 303015456 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35241.247265 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35241.247265 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35241.247265 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 34567.222767 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34567.222767 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34567.222767 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,169 +354,169 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 197 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 197 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 197 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 717 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 717 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 717 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 280 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 280 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 280 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 739 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 739 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 739 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 24697500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 24697500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 24697500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 25462500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 25462500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 25462500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34445.606695 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34445.606695 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34455.345061 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34455.345061 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34455.345061 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9552367 # number of replacements -system.cpu.dcache.tagsinuse 4082.984998 # Cycle average of tags in use -system.cpu.dcache.total_refs 675087648 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9556463 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 70.641999 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 6495236000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4082.984998 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.996823 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 507131941 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 167955564 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 74 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 69 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 675087505 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 675087505 # number of overall hits -system.cpu.dcache.ReadReq_misses 10254687 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 4630483 # number of WriteReq misses +system.cpu.dcache.replacements 9572098 # number of replacements +system.cpu.dcache.tagsinuse 4088.159469 # Cycle average of tags in use +system.cpu.dcache.total_refs 687277052 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9576194 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 71.769333 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3603059000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4088.159469 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998086 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 519599165 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 167677732 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 82 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 73 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 687276897 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 687276897 # number of overall hits +system.cpu.dcache.ReadReq_misses 10430920 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 4908315 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 14885170 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 14885170 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 173914872000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 112892331168 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 15339235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 15339235 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 181621482000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 122280886057 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 286807203168 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 286807203168 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 517386628 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 303902368057 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 303902368057 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 530030085 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 77 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 69 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 689972675 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 689972675 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.019820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.026830 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.038961 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.021574 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.021574 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16959.549521 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 24380.249570 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses 85 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 73 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 702616132 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 702616132 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.019680 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.028440 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.035294 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.021832 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.021832 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 17411.837307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 24913.007021 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 19267.983044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 19267.983044 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 148361910 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 159500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35813 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4142.683104 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency 19812.094153 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19812.094153 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 267003640 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 90682 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2944.395139 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21777.777778 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3126452 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2590385 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2738322 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks 3128448 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 2747497 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 3015544 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5328707 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5328707 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7664302 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1892161 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9556463 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9556463 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 5763041 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 5763041 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 7683423 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1892771 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 9576194 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 9576194 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 89320855000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 42428124877 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 131748979877 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 131748979877 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 90753159500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 45245223293 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 135998382793 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 135998382793 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.014813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.010964 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.013850 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.013850 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11654.140847 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 22423.105051 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 13786.374716 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.014496 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.010967 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.013629 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.013629 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11811.553197 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23904.224702 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 14201.715503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 14201.715503 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2920822 # number of replacements -system.cpu.l2cache.tagsinuse 26404.864855 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7838163 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2948145 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.658676 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 129803245500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15746.128543 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10658.736312 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.480534 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.325279 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5643332 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3126452 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 980638 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6623970 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6623970 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2021685 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 911525 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2933210 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2933210 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 69338469500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 31601923000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 100940392500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 100940392500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7665017 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3126452 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1892163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9557180 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9557180 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.263755 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.481737 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.306912 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.306912 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34297.365564 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34669.288281 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34412.944351 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34412.944351 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 48964500 # number of cycles access was blocked +system.cpu.l2cache.replacements 2927988 # number of replacements +system.cpu.l2cache.tagsinuse 26803.816569 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7852126 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2955312 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.656953 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 105427800500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 15979.704689 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10824.111881 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.487662 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.330326 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 5656220 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 3128448 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 980310 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 6636530 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6636530 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2027940 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 912463 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 2940403 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 2940403 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 69613457000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 31659273500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 101272730500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 101272730500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 7684160 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 3128448 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1892773 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 9576933 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 9576933 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.263912 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.482077 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.307030 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.307030 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34327.177826 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34696.501118 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34441.785871 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34441.785871 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 56425500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 5689 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 6606 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8606.872913 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8541.553134 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1216359 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2021675 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 911525 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2933200 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2933200 # number of overall MSHR misses +system.cpu.l2cache.writebacks 1217599 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2027928 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 912463 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 2940391 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 2940391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 62968532000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 28735558500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 91704090500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 91704090500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 63193895000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 28814819500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 92008714500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 92008714500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263753 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.481737 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.306911 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.306911 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.713493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31524.706947 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31264.179224 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.263910 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482077 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.307028 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.307028 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.804068 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31579.164854 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.319590 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.319590 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 84850f694..e1977cd05 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -199,12 +200,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index d3c569634..90052853e 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 06:59:18 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 17:47:44 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 42094188000 because target called exit() +122 123 124 Exiting @ tick 41833966000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index d48c1814c..e905042e7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042094 # Number of seconds simulated -sim_ticks 42094188000 # Number of ticks simulated +sim_seconds 0.041834 # Number of seconds simulated +sim_ticks 41833966000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121365 # Simulator instruction rate (inst/s) -host_tick_rate 55588778 # Simulator tick rate (ticks/s) -host_mem_usage 196912 # Number of bytes of host memory used -host_seconds 757.24 # Real time elapsed on the host +host_inst_rate 47398 # Simulator instruction rate (inst/s) +host_tick_rate 21575287 # Simulator tick rate (ticks/s) +host_mem_usage 249684 # Number of bytes of host memory used +host_seconds 1938.98 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 26498119 # DT system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 26498152 # DTB accesses -system.cpu.itb.fetch_hits 10077672 # ITB hits +system.cpu.itb.fetch_hits 9991202 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 10077721 # ITB accesses +system.cpu.itb.fetch_accesses 9991251 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 84188377 # number of cpu cycles simulated +system.cpu.numCycles 83667933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 83816425 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 83292959 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10559 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7701629 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 76486748 # Number of cycles cpu stages are processed. -system.cpu.activity 90.851909 # Percentage of cycles cpu is active +system.cpu.timesIdled 10907 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7700653 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75967280 # Number of cycles cpu stages are processed. +system.cpu.activity 90.796172 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -61,129 +61,129 @@ system.cpu.comFloats 3775974 # Nu system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) -system.cpu.cpi 0.916056 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 0.916056 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091636 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads +system.cpu.ipc 1.098426 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 1.091636 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 13660151 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 10092693 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 4598416 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 8981993 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 4278316 # Number of BTB hits +system.cpu.ipc_total 1.098426 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 13542330 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 9941405 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 4410938 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 8655858 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 4135478 # Number of BTB hits system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 131 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 47.632146 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 6418014 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7242137 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73810840 # Number of Reads from Int. Register File +system.cpu.branch_predictor.RASInCorrect 132 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 47.776639 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 6269254 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7273076 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73609025 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136386312 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206031 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136184497 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206079 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8057919 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38650469 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26688179 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3946440 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 651118 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4597558 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5643144 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 44.894950 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57370437 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 8057967 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38654467 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26652325 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3861647 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 548433 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4410080 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5830622 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 43.064235 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57347630 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458254 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 27496111 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 56692266 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 67.339778 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34731944 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49456433 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 58.744965 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34177132 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 50011245 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.403978 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 66154944 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18033433 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.420336 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 30219873 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53968504 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.104459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7205 # number of replacements -system.cpu.icache.tagsinuse 1491.617776 # Cycle average of tags in use -system.cpu.icache.total_refs 10066620 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9090 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1107.438944 # Average number of references to valid blocks. +system.cpu.stage0.idleCycles 27446781 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 56221152 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 67.195579 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34307675 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49360258 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 58.995431 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33744588 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49923345 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.668434 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65638077 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18029856 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.549303 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29755825 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53912108 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.435807 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 7551 # number of replacements +system.cpu.icache.tagsinuse 1491.782957 # Cycle average of tags in use +system.cpu.icache.total_refs 9979713 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1491.617776 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.728329 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 10066620 # number of ReadReq hits -system.cpu.icache.demand_hits 10066620 # number of demand (read+write) hits -system.cpu.icache.overall_hits 10066620 # number of overall hits -system.cpu.icache.ReadReq_misses 11049 # number of ReadReq misses -system.cpu.icache.demand_misses 11049 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11049 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 285327000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 285327000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 285327000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 10077669 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 10077669 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 10077669 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 25823.784958 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 25823.784958 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 25823.784958 # average overall miss latency +system.cpu.icache.occ_blocks::0 1491.782957 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.728410 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 9979713 # number of ReadReq hits +system.cpu.icache.demand_hits 9979713 # number of demand (read+write) hits +system.cpu.icache.overall_hits 9979713 # number of overall hits +system.cpu.icache.ReadReq_misses 11486 # number of ReadReq misses +system.cpu.icache.demand_misses 11486 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11486 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 291407500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 291407500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 291407500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 9991199 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 9991199 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 9991199 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 25370.668640 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 25370.668640 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 25370.668640 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 13900 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1959 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1959 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1959 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 9090 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 9090 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 9090 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 2050 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2050 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2050 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 9436 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 9436 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 9436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 218831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 218831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 218831500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 222700000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 222700000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 222700000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000902 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000902 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000902 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 24073.872387 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 24073.872387 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000944 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000944 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000944 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.601089 # Cycle average of tags in use -system.cpu.dcache.total_refs 26491207 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use +system.cpu.dcache.total_refs 26491206 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11916.872245 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1441.601089 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.351953 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 19995646 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 1441.532122 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.351937 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 19995645 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits -system.cpu.dcache.demand_hits 26491207 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 26491207 # number of overall hits -system.cpu.dcache.ReadReq_misses 552 # number of ReadReq misses +system.cpu.dcache.demand_hits 26491206 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 26491206 # number of overall hits +system.cpu.dcache.ReadReq_misses 553 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses -system.cpu.dcache.demand_misses 6094 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 6094 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 28390000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 303795000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 332185000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 332185000 # number of overall miss cycles +system.cpu.dcache.demand_misses 6095 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 6095 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28393500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 303801000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 332194500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 332194500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses @@ -192,81 +192,81 @@ system.cpu.dcache.ReadReq_miss_rate 0.000028 # mi system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 51431.159420 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54816.853122 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54510.173942 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54510.173942 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54502.789171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54502.789171 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41040500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 41047000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 823 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 824 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49866.950182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 77 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 3794 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3871 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3871 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 3872 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3872 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 23213000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 92992000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 116205000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 116205000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 92997500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 116210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 116210500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53199.084668 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52273.954116 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2189.147121 # Cycle average of tags in use -system.cpu.l2cache.total_refs 6359 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3281 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.938129 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2189.253602 # Cycle average of tags in use +system.cpu.l2cache.total_refs 6704 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.042657 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2171.310088 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.837033 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.066263 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2171.415543 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.838059 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.066266 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 6350 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 6695 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6376 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6376 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3215 # number of ReadReq misses +system.cpu.l2cache.demand_hits 6721 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 6721 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 4937 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 4937 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 168259500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 90562500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 258822000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 258822000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 9565 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 4938 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 168327500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 90565000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 258892500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 258892500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 9911 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 11313 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 11313 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.336121 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 11659 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 11659 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.324488 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.436401 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.436401 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52335.769829 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52591.463415 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52424.954426 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52424.954426 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.423535 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.423535 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52428.614824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52428.614824 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,24 +278,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 4937 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 4937 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 129008000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 198352500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 198352500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 129053500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 69344000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 198397500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 198397500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.336121 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.324488 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.436401 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.436401 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40126.905132 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.744483 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40176.726757 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.423535 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.423535 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 9d0ac975a..9b349a51c 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index f701d0797..ba1de8238 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:11:56 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 18:07:05 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 34191076000 because target called exit() +122 123 124 Exiting @ tick 32092296500 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index f1b3177ca..5aa0ca1ff 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.034191 # Number of seconds simulated -sim_ticks 34191076000 # Number of ticks simulated +sim_seconds 0.032092 # Number of seconds simulated +sim_ticks 32092296500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184031 # Simulator instruction rate (inst/s) -host_tick_rate 74747519 # Simulator tick rate (ticks/s) -host_mem_usage 197584 # Number of bytes of host memory used -host_seconds 457.42 # Real time elapsed on the host +host_inst_rate 73581 # Simulator instruction rate (inst/s) +host_tick_rate 28051508 # Simulator tick rate (ticks/s) +host_mem_usage 250560 # Number of bytes of host memory used +host_seconds 1144.05 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24606273 # DTB read hits -system.cpu.dtb.read_misses 355468 # DTB read misses +system.cpu.dtb.read_hits 25665074 # DTB read hits +system.cpu.dtb.read_misses 532377 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 24961741 # DTB read accesses -system.cpu.dtb.write_hits 7276928 # DTB write hits -system.cpu.dtb.write_misses 1204 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7278132 # DTB write accesses -system.cpu.dtb.data_hits 31883201 # DTB hits -system.cpu.dtb.data_misses 356672 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 32239873 # DTB accesses -system.cpu.itb.fetch_hits 17397269 # ITB hits -system.cpu.itb.fetch_misses 74 # ITB misses +system.cpu.dtb.read_accesses 26197451 # DTB read accesses +system.cpu.dtb.write_hits 7413229 # DTB write hits +system.cpu.dtb.write_misses 1159 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 7414388 # DTB write accesses +system.cpu.dtb.data_hits 33078303 # DTB hits +system.cpu.dtb.data_misses 533536 # DTB misses +system.cpu.dtb.data_acv 5 # DTB access violations +system.cpu.dtb.data_accesses 33611839 # DTB accesses +system.cpu.itb.fetch_hits 19743768 # ITB hits +system.cpu.itb.fetch_misses 86 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 17397343 # ITB accesses +system.cpu.itb.fetch_accesses 19743854 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,243 +41,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 68382153 # number of cpu cycles simulated +system.cpu.numCycles 64184594 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 17634633 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 13040695 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1952481 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 14366532 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10847017 # Number of BTB hits +system.cpu.BPredUnit.lookups 19638238 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 14616795 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1934317 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 16315844 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 12540710 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1674129 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 1246 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 17397269 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 149130935 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17634633 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12521146 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27321847 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2202221 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 17397269 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 534330 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 68273622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.184313 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.130987 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1821712 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2747 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 21008427 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 166538758 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19638238 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14362422 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 30824536 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 9451370 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4886757 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1819 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 19743768 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 631936 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 64091521 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.598452 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.236190 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 40951775 59.98% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2771290 4.06% 64.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1819003 2.66% 66.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3013999 4.41% 71.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3778689 5.53% 76.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1379239 2.02% 78.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1617985 2.37% 81.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1572355 2.30% 83.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11369287 16.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 33266985 51.91% 51.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3147764 4.91% 56.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2102748 3.28% 60.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3556460 5.55% 65.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4397921 6.86% 72.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1522590 2.38% 74.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1866548 2.91% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1731844 2.70% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12498661 19.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 68273622 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257884 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.180846 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35496040 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 838288 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 26313036 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 25031 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5601227 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2813146 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13474 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 143267385 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49112 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5601227 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36404617 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 332303 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5077 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 25415273 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 515125 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 138778599 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 66062 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 424450 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 101591818 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 178909439 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 169177159 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9732280 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 64091521 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305965 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.594684 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23134324 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3873003 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 28813163 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 914553 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7356478 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3062607 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13804 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 160619110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 43067 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 7356478 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24847542 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1029661 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6037 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 27972484 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2879319 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 153930695 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 698435 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1852837 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 113010867 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 199187244 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 187702425 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 11484819 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33164457 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 469 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 457 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1208043 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 28836221 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9211316 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3033617 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 781499 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 116375063 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101956461 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 141538 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 30709271 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 24277340 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 68273622 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.493351 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698376 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 44583506 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 529 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 520 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 7678386 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 31845410 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9896316 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6196134 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1567027 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 129169470 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 502 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107327436 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 534587 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 44082208 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 35410789 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 113 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 64091521 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.674596 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.788065 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26699327 39.11% 39.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15011311 21.99% 61.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10325819 15.12% 76.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6572668 9.63% 85.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4677869 6.85% 92.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2930251 4.29% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1292691 1.89% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 652857 0.96% 99.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 110829 0.16% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23013905 35.91% 35.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13200417 20.60% 56.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9655349 15.06% 71.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7236543 11.29% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5456935 8.51% 91.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2848092 4.44% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1848148 2.88% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 707452 1.10% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124680 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 68273622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 64091521 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 211558 13.07% 13.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 411 0.03% 13.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1262 0.08% 13.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 831302 51.36% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469173 28.99% 93.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 104844 6.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206408 12.63% 12.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 196 0.01% 12.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 6500 0.40% 13.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5851 0.36% 13.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 847321 51.84% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 65.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 476077 29.13% 94.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 91992 5.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 61903709 60.72% 60.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 478641 0.47% 61.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2776827 2.72% 63.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 114478 0.11% 64.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2390013 2.34% 66.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 305170 0.30% 66.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 758780 0.74% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 320 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25831010 25.34% 92.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7397506 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 65553727 61.08% 61.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 486899 0.45% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2819079 2.63% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115045 0.11% 64.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2427572 2.26% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 312395 0.29% 66.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 763362 0.71% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 27299077 25.44% 92.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7549954 7.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101956461 # Type of FU issued -system.cpu.iq.rate 1.490981 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1618550 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015875 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 258930448 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 138886536 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90413703 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15016184 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8486129 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7008699 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 95648093 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7926911 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1076434 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107327436 # Type of FU issued +system.cpu.iq.rate 1.672168 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1634345 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015228 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 265519684 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 162160015 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 94997457 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15395641 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 11288937 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7141397 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 100830916 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8130858 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1254132 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8840023 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4810 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 361752 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2710213 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11849212 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 9154 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 349266 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3395213 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 9740 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10688 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5601227 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 54226 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20318 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 127570040 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1888225 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 28836221 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9211316 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3299 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 45 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 361752 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1627472 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 455682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2083154 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 99513467 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24962113 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2442994 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7356478 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94659 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 31189 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 141503695 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 872227 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 31845410 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9896316 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 502 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 12366 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 349266 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1814664 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 342809 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2157473 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104568587 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 26198042 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2758849 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11194543 # number of nop insts executed -system.cpu.iew.exec_refs 32240280 # number of memory reference insts executed -system.cpu.iew.exec_branches 12448390 # Number of branches executed -system.cpu.iew.exec_stores 7278167 # Number of stores executed -system.cpu.iew.exec_rate 1.455255 # Inst execution rate -system.cpu.iew.wb_sent 98290476 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97422402 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64595544 # num instructions producing a value -system.cpu.iew.wb_consumers 87558338 # num instructions consuming a value +system.cpu.iew.exec_nop 12333723 # number of nop insts executed +system.cpu.iew.exec_refs 33612538 # number of memory reference insts executed +system.cpu.iew.exec_branches 13292388 # Number of branches executed +system.cpu.iew.exec_stores 7414496 # Number of stores executed +system.cpu.iew.exec_rate 1.629185 # Inst execution rate +system.cpu.iew.wb_sent 103278074 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102138854 # cumulative count of insts written-back +system.cpu.iew.wb_producers 68941212 # num instructions producing a value +system.cpu.iew.wb_consumers 95281048 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.424676 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737743 # average fanout of values written-back +system.cpu.iew.wb_rate 1.591330 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.723556 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 35667755 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 49602328 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1939282 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 62672395 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.466404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.205429 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1920862 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 56735043 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.619864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.379821 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30204906 48.19% 48.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13903993 22.19% 70.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6182558 9.86% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3801476 6.07% 86.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2048830 3.27% 89.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1270161 2.03% 91.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 776463 1.24% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 847449 1.35% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3636559 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 26448220 46.62% 46.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12595125 22.20% 68.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5584191 9.84% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2979320 5.25% 83.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1760489 3.10% 87.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1489209 2.62% 89.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 769969 1.36% 91.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 774387 1.36% 92.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4334133 7.64% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 62672395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 56735043 # Number of insts commited each cycle system.cpu.commit.count 91903055 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 26497301 # Number of memory references committed @@ -287,50 +290,50 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3636559 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4334133 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 186605606 # The number of ROB reads -system.cpu.rob.rob_writes 260771760 # The number of ROB writes -system.cpu.timesIdled 2331 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 108531 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 193905253 # The number of ROB reads +system.cpu.rob.rob_writes 290432006 # The number of ROB writes +system.cpu.timesIdled 2283 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93073 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.812335 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.812335 # CPI: Total CPI of All Threads -system.cpu.ipc 1.231019 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.231019 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 134796814 # number of integer regfile reads -system.cpu.int_regfile_writes 73485618 # number of integer regfile writes -system.cpu.fp_regfile_reads 6139601 # number of floating regfile reads -system.cpu.fp_regfile_writes 5989352 # number of floating regfile writes -system.cpu.misc_regfile_reads 712206 # number of misc regfile reads +system.cpu.cpi 0.762471 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.762471 # CPI: Total CPI of All Threads +system.cpu.ipc 1.311525 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.311525 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 141097992 # number of integer regfile reads +system.cpu.int_regfile_writes 77269821 # number of integer regfile writes +system.cpu.fp_regfile_reads 6208793 # number of floating regfile reads +system.cpu.fp_regfile_writes 6125599 # number of floating regfile writes +system.cpu.misc_regfile_reads 715479 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8218 # number of replacements -system.cpu.icache.tagsinuse 1547.340406 # Cycle average of tags in use -system.cpu.icache.total_refs 17386201 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10134 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1715.630649 # Average number of references to valid blocks. +system.cpu.icache.replacements 8662 # number of replacements +system.cpu.icache.tagsinuse 1591.987817 # Cycle average of tags in use +system.cpu.icache.total_refs 19731988 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10590 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1863.266100 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1547.340406 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.755537 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 17386201 # number of ReadReq hits -system.cpu.icache.demand_hits 17386201 # number of demand (read+write) hits -system.cpu.icache.overall_hits 17386201 # number of overall hits -system.cpu.icache.ReadReq_misses 11068 # number of ReadReq misses -system.cpu.icache.demand_misses 11068 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11068 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 173520000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 173520000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 173520000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 17397269 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 17397269 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 17397269 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000636 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000636 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000636 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 15677.629201 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 15677.629201 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 15677.629201 # average overall miss latency +system.cpu.icache.occ_blocks::0 1591.987817 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.777338 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 19731988 # number of ReadReq hits +system.cpu.icache.demand_hits 19731988 # number of demand (read+write) hits +system.cpu.icache.overall_hits 19731988 # number of overall hits +system.cpu.icache.ReadReq_misses 11780 # number of ReadReq misses +system.cpu.icache.demand_misses 11780 # number of demand (read+write) misses +system.cpu.icache.overall_misses 11780 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 187835000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 187835000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 187835000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 19743768 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 19743768 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 19743768 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000597 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000597 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000597 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 15945.246180 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 15945.246180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 15945.246180 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,132 +343,140 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 934 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 934 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 934 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 10134 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 10134 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 10134 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1190 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1190 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1190 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 10590 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 10590 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 10590 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 120345000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 120345000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 120345000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 124617500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 124617500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 124617500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000583 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000583 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11875.370041 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11875.370041 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000536 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000536 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000536 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11767.469311 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11767.469311 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11767.469311 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 160 # number of replacements -system.cpu.dcache.tagsinuse 1459.544584 # Cycle average of tags in use -system.cpu.dcache.total_refs 30012261 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13380.410611 # Average number of references to valid blocks. +system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.tagsinuse 1458.064990 # Cycle average of tags in use +system.cpu.dcache.total_refs 30892362 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2241 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13785.078983 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1459.544584 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.356334 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 23519179 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 6493072 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits 30012251 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 30012251 # number of overall hits -system.cpu.dcache.ReadReq_misses 909 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8031 # number of WriteReq misses -system.cpu.dcache.demand_misses 8940 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 8940 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 26580000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 285129500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 311709500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 311709500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 23520088 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1458.064990 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.355973 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 24399260 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 6493052 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 50 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits 30892312 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 30892312 # number of overall hits +system.cpu.dcache.ReadReq_misses 942 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8051 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 8993 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 8993 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 28111000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 289250500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 317361500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 317361500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 24400202 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 30021191 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 30021191 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses 51 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 30901305 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 30901305 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.001235 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 29240.924092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35503.611007 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34866.834452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34866.834452 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.019608 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000291 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000291 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 29841.825902 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35927.276115 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35289.836540 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35289.836540 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 400 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6297 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6697 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6697 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 509 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1734 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses +system.cpu.dcache.writebacks 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 435 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6318 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6753 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6753 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 507 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1733 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2240 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2240 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16308500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 61467000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77775500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77775500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 16260000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 61635000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 77895000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 77895000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000021 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32040.275049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35448.096886 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34674.765938 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.019608 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32071.005917 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35565.493364 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34774.553571 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34774.553571 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2313.957791 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7266 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3457 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.101822 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2392.328540 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7626 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3548 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.149380 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2296.266103 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.691689 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.070076 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 25 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 7279 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 7279 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3389 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 1709 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5098 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5098 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 116176000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 59068500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 175244500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 175244500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 10643 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1734 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.318425 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.985582 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.411893 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.411893 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34280.318678 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34563.194851 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34375.147117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34375.147117 # average overall miss latency +system.cpu.l2cache.occ_blocks::0 2374.739172 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.589369 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.072471 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000537 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 7618 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 108 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 7644 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 7644 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3480 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1707 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5187 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5187 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 119535500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 59266000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 178801500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 178801500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 11098 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 12831 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 12831 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.313570 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.984997 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.404255 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.404255 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34349.281609 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34719.390744 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34471.081550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34471.081550 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,24 +488,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3389 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1709 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5098 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5098 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3480 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1707 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5187 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105338000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53777500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 159115500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 159115500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 108240500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53874500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 162115000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 162115000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318425 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.411893 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.411893 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.325170 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.232300 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31211.357395 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984997 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.404255 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.404255 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.591954 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31560.925600 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31254.096780 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31254.096780 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini index 6ac40b8d3..788c735d8 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing +cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout index 5262b1662..b0302ff58 100755 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,16 +1,10 @@ -Redirecting stdout to build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 16:39:45 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 9 2011 04:18:32 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +21,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 114583980000 because target called exit() +122 123 124 Exiting @ tick 110281184000 because target called exit() diff --git a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt index 5a112fddd..0fe4beed8 100644 --- a/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.114584 # Number of seconds simulated -sim_ticks 114583980000 # Number of ticks simulated +sim_seconds 0.110281 # Number of seconds simulated +sim_ticks 110281184000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 37904 # Simulator instruction rate (inst/s) -host_tick_rate 23020273 # Simulator tick rate (ticks/s) -host_mem_usage 259288 # Number of bytes of host memory used -host_seconds 4977.52 # Real time elapsed on the host -sim_insts 188668727 # Number of instructions simulated +host_inst_rate 65382 # Simulator instruction rate (inst/s) +host_tick_rate 38217412 # Simulator tick rate (ticks/s) +host_mem_usage 261804 # Number of bytes of host memory used +host_seconds 2885.63 # Real time elapsed on the host +sim_insts 188667677 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -51,296 +51,299 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 229167961 # number of cpu cycles simulated +system.cpu.numCycles 220562369 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 98244922 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 77066129 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 10346796 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 79994397 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 74750808 # Number of BTB hits +system.cpu.BPredUnit.lookups 104258409 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 82362571 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 9936095 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 86105898 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 80445450 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4424088 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 111792 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 36996487 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 401246546 # Number of instructions fetch has processed -system.cpu.fetch.Branches 98244922 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79174896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 102059455 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10739700 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 36996487 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2084614 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 229101172 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.893988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.602493 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 4758962 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 112969 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 46358647 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 433367935 # Number of instructions fetch has processed +system.cpu.fetch.Branches 104258409 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 85204412 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 111822484 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35665794 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36992864 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.CacheLines 42110119 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2232853 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 220504638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.132131 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.672325 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 127219261 55.53% 55.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4017584 1.75% 57.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29118578 12.71% 69.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 15726187 6.86% 76.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 9819635 4.29% 81.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13296507 5.80% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7877710 3.44% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4751479 2.07% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 17274231 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 108888253 49.38% 49.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4953673 2.25% 51.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33070296 15.00% 66.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 18447401 8.37% 74.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9377183 4.25% 79.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 12785261 5.80% 85.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 8550568 3.88% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4486115 2.03% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 19945888 9.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 229101172 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.428703 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.750884 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 79313906 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 32327887 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 94878595 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 682758 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21898026 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14316236 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166090 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 406876598 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 708405 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21898026 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 88099979 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 621468 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27861388 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 86740372 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3879939 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 372161493 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 76195 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1579800 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 635133998 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1589359787 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1572376571 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 16983216 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298063696 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 337070297 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2567300 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2531045 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 20595382 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 47397575 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16557205 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6544934 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4003679 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 318729231 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2207616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 261466746 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 554929 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 126483137 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 283584721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 571778 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 229101172 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.141272 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.407939 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 220504638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.472694 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.964832 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 55339748 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 35376598 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 103212898 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1403307 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 25172087 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14322485 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 170339 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 440125451 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 696276 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 25172087 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 64672455 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 776963 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 29575154 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 95204893 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5103086 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 403993606 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 69868 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2710880 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 687477122 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1728388844 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1709997227 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 18391617 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298062016 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 389415097 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2865354 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2816189 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 26097925 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 51690689 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 18730866 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8573671 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5359744 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 346939727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2374386 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 267717167 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 907172 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 158256505 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 384971202 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 738758 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 220504638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.214111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.476414 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108324411 47.28% 47.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46627729 20.35% 67.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34182087 14.92% 82.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 22115521 9.65% 92.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11617915 5.07% 97.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4157757 1.81% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1774100 0.77% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 189981 0.08% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 111671 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 103384796 46.89% 46.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 39397520 17.87% 64.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 35187917 15.96% 80.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 23179085 10.51% 91.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11803879 5.35% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4771097 2.16% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2229685 1.01% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 447825 0.20% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 102834 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 229101172 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 220504638 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 110643 6.25% 6.25% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5520 0.31% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 24 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1295953 73.23% 79.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 357680 20.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 341650 17.75% 17.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6050 0.31% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 35 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 4 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 93 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1226198 63.72% 81.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 350464 18.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 205127791 78.45% 78.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918034 0.35% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 10104 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 32866 0.01% 78.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 166342 0.06% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 251406 0.10% 78.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76052 0.03% 79.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 462257 0.18% 79.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 207196 0.08% 79.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71628 0.03% 79.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 324 0.00% 79.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 40426138 15.46% 94.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13716608 5.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 208615296 77.92% 77.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925342 0.35% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 6202 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33026 0.01% 78.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 166299 0.06% 78.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 260522 0.10% 78.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76108 0.03% 78.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 471200 0.18% 78.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 207528 0.08% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71629 0.03% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 327 0.00% 78.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 42633393 15.92% 94.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14250295 5.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 261466746 # Type of FU issued -system.cpu.iq.rate 1.140939 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1769820 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006769 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 750657753 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 445688656 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 241497013 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3701660 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2110445 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1822638 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 261381402 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1855164 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 983049 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 267717167 # Type of FU issued +system.cpu.iq.rate 1.213793 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1924494 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007189 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 754979573 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 505620151 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 248098864 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3791065 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2339721 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1843061 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 267732701 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1908960 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1050657 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17545646 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 834 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 453061 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3910128 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21838970 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7625 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 472350 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6083999 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21898026 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16044 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3524 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 320989557 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8588110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 47397575 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16557205 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2183565 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 259 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3132 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 453061 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9663378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2166474 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11829852 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 247483110 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 38551878 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 13983636 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 25172087 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44760 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3320 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 349368262 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3978827 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 51690689 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 18730866 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2350473 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 564 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2427 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 472350 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10008076 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1698961 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11707037 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 254915521 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 40541135 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 12801646 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 52710 # number of nop insts executed -system.cpu.iew.exec_refs 51991708 # number of memory reference insts executed -system.cpu.iew.exec_branches 51968856 # Number of branches executed -system.cpu.iew.exec_stores 13439830 # Number of stores executed -system.cpu.iew.exec_rate 1.079920 # Inst execution rate -system.cpu.iew.wb_sent 244574618 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 243319651 # cumulative count of insts written-back -system.cpu.iew.wb_producers 146548425 # num instructions producing a value -system.cpu.iew.wb_consumers 237755963 # num instructions consuming a value +system.cpu.iew.exec_nop 54149 # number of nop insts executed +system.cpu.iew.exec_refs 54377446 # number of memory reference insts executed +system.cpu.iew.exec_branches 53214768 # Number of branches executed +system.cpu.iew.exec_stores 13836311 # Number of stores executed +system.cpu.iew.exec_rate 1.155753 # Inst execution rate +system.cpu.iew.wb_sent 251638468 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 249941925 # cumulative count of insts written-back +system.cpu.iew.wb_producers 151812393 # num instructions producing a value +system.cpu.iew.wb_consumers 254020317 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.061752 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.616382 # average fanout of values written-back +system.cpu.iew.wb_rate 1.133203 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.597639 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 188683115 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 132297419 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1635838 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 10209212 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 207203147 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.910619 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.539035 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 188682065 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 160676887 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1635628 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9797761 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 195332552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.965953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.628775 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 117680182 56.79% 56.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 47355200 22.85% 79.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20289931 9.79% 89.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8457444 4.08% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5251466 2.53% 96.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1928686 0.93% 96.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2144986 1.04% 98.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 905505 0.44% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3189747 1.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 109939001 56.28% 56.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 42858902 21.94% 78.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20127469 10.30% 88.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8563678 4.38% 92.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5111696 2.62% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2060801 1.06% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1694385 0.87% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 852868 0.44% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4123752 2.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 207203147 # Number of insts commited each cycle -system.cpu.commit.count 188683115 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 195332552 # Number of insts commited each cycle +system.cpu.commit.count 188682065 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42499005 # Number of memory references committed -system.cpu.commit.loads 29851928 # Number of loads committed +system.cpu.commit.refs 42498585 # Number of memory references committed +system.cpu.commit.loads 29851718 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40284126 # Number of branches committed +system.cpu.commit.branches 40283916 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150115997 # Number of committed integer instructions. +system.cpu.commit.int_insts 150115157 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 3189747 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4123752 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 524988733 # The number of ROB reads -system.cpu.rob.rob_writes 663890510 # The number of ROB writes -system.cpu.timesIdled 1538 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 66789 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 188668727 # Number of Instructions Simulated -system.cpu.committedInsts_total 188668727 # Number of Instructions Simulated -system.cpu.cpi 1.214658 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.214658 # CPI: Total CPI of All Threads -system.cpu.ipc 0.823277 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.823277 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1105306330 # number of integer regfile reads -system.cpu.int_regfile_writes 405513282 # number of integer regfile writes -system.cpu.fp_regfile_reads 2915970 # number of floating regfile reads -system.cpu.fp_regfile_writes 2459492 # number of floating regfile writes -system.cpu.misc_regfile_reads 485972392 # number of misc regfile reads -system.cpu.misc_regfile_writes 824922 # number of misc regfile writes -system.cpu.icache.replacements 1867 # number of replacements -system.cpu.icache.tagsinuse 1275.783892 # Cycle average of tags in use -system.cpu.icache.total_refs 36992467 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 3528 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10485.393141 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 540562551 # The number of ROB reads +system.cpu.rob.rob_writes 723954086 # The number of ROB writes +system.cpu.timesIdled 1712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 57731 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 188667677 # Number of Instructions Simulated +system.cpu.committedInsts_total 188667677 # Number of Instructions Simulated +system.cpu.cpi 1.169052 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.169052 # CPI: Total CPI of All Threads +system.cpu.ipc 0.855394 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.855394 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1139481673 # number of integer regfile reads +system.cpu.int_regfile_writes 415646596 # number of integer regfile writes +system.cpu.fp_regfile_reads 2922802 # number of floating regfile reads +system.cpu.fp_regfile_writes 2492399 # number of floating regfile writes +system.cpu.misc_regfile_reads 524104390 # number of misc regfile reads +system.cpu.misc_regfile_writes 824502 # number of misc regfile writes +system.cpu.icache.replacements 1939 # number of replacements +system.cpu.icache.tagsinuse 1330.149475 # Cycle average of tags in use +system.cpu.icache.total_refs 42105837 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 3648 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11542.170230 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1275.783892 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.622941 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 36992467 # number of ReadReq hits -system.cpu.icache.demand_hits 36992467 # number of demand (read+write) hits -system.cpu.icache.overall_hits 36992467 # number of overall hits -system.cpu.icache.ReadReq_misses 4020 # number of ReadReq misses -system.cpu.icache.demand_misses 4020 # number of demand (read+write) misses -system.cpu.icache.overall_misses 4020 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 95473000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 95473000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 95473000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 36996487 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 36996487 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 36996487 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000109 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000109 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000109 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23749.502488 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23749.502488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23749.502488 # average overall miss latency +system.cpu.icache.occ_blocks::0 1330.149475 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.649487 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 42105837 # number of ReadReq hits +system.cpu.icache.demand_hits 42105837 # number of demand (read+write) hits +system.cpu.icache.overall_hits 42105837 # number of overall hits +system.cpu.icache.ReadReq_misses 4282 # number of ReadReq misses +system.cpu.icache.demand_misses 4282 # number of demand (read+write) misses +system.cpu.icache.overall_misses 4282 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 102623500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 102623500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 102623500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 42110119 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 42110119 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 42110119 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000102 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000102 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000102 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23966.254087 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23966.254087 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23966.254087 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -350,142 +353,139 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 491 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 491 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 491 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 3529 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 3529 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 3529 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 634 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 634 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 634 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 3648 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 3648 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 3648 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 71843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 71843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 71843000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 74999500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 74999500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 74999500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000095 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000095 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000095 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 20357.891754 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 20357.891754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 20357.891754 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000087 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000087 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000087 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20559.073465 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20559.073465 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 49 # number of replacements -system.cpu.dcache.tagsinuse 1395.560229 # Cycle average of tags in use -system.cpu.dcache.total_refs 49245913 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1834 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 26851.642857 # Average number of references to valid blocks. +system.cpu.dcache.replacements 53 # number of replacements +system.cpu.dcache.tagsinuse 1408.348450 # Cycle average of tags in use +system.cpu.dcache.total_refs 51108076 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1850 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 27625.987027 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1395.560229 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.340713 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 36836047 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 12356734 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 28275 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 24850 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 49192781 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 49192781 # number of overall hits -system.cpu.dcache.ReadReq_misses 1779 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7553 # number of WriteReq misses +system.cpu.dcache.occ_blocks::0 1408.348450 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343835 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 38699028 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 12356747 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 27661 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 24640 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 51055775 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 51055775 # number of overall hits +system.cpu.dcache.ReadReq_misses 1814 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7540 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 9332 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9332 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 57926000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 236821500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 64000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 294747500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 294747500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 36837826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 9354 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9354 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 59541500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 236790000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 296331500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 296331500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 38700842 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 28277 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 24850 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 49202113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 49202113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000048 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000071 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.000190 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000190 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32560.989320 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 31354.627300 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 32000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 31584.601372 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 31584.601372 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 27663 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 24640 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 51065129 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 51065129 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.000610 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.000183 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000183 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 32823.318633 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31404.509284 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 31679.655762 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 31679.655762 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1036 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6461 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 1053 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6451 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 7497 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 7497 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 743 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1092 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1835 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1835 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits 7504 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 7504 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 761 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1089 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1850 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1850 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23910500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 38348500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 62259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 62259000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 24275500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 38318500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 62594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 62594000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32181.022880 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35117.673993 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 33928.610354 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 33928.610354 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31899.474376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35186.868687 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 33834.594595 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 1850.961242 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1671 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2592 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.644676 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 1929.340531 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1711 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2692 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.635587 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1847.906973 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3.054268 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.056394 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1926.279074 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3.061457 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.058785 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1671 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 1711 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 17 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 9 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1680 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1680 # number of overall hits -system.cpu.l2cache.ReadReq_misses 2600 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1082 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 3682 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 3682 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 89152000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 37162000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 126314000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 126314000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 4271 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1719 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1719 # number of overall hits +system.cpu.l2cache.ReadReq_misses 2698 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 1081 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 3779 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 3779 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 92484500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 37157500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 129642000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 129642000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 4409 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 17 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1091 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 5362 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 5362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.608757 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.991751 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.686684 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.686684 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34289.230769 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34345.656192 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34305.812059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34305.812059 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses 1089 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 5498 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 5498 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.611930 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.992654 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.687341 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.687341 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34278.910304 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34373.265495 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34305.901032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34305.901032 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,31 +495,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 2584 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1082 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 3666 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 3666 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 2683 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1081 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 3764 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 3764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 80301000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 33586500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 113887500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 113887500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 83387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 33564500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 116951500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 116951500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.605011 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.991751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.683700 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.683700 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31076.238390 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31041.127542 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31065.875614 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31065.875614 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608528 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992654 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.684613 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.684613 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.761461 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.491212 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31071.068013 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 15faea73a..733a1cda5 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 46cb2af0c..13ca71321 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 9 2011 00:22:05 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 106734154000 because target called exit() +122 123 124 Exiting @ tick 105045070000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 934f22237..05846252d 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,248 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.106734 # Number of seconds simulated -sim_ticks 106734154000 # Number of ticks simulated +sim_seconds 0.105045 # Number of seconds simulated +sim_ticks 105045070000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152335 # Simulator instruction rate (inst/s) -host_tick_rate 73451239 # Simulator tick rate (ticks/s) -host_mem_usage 239116 # Number of bytes of host memory used -host_seconds 1453.13 # Real time elapsed on the host +host_inst_rate 49247 # Simulator instruction rate (inst/s) +host_tick_rate 23369426 # Simulator tick rate (ticks/s) +host_mem_usage 262348 # Number of bytes of host memory used +host_seconds 4494.98 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 213468309 # number of cpu cycles simulated +system.cpu.numCycles 210090141 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25050494 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25050494 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3072725 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 22404993 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 19578906 # Number of BTB hits +system.cpu.BPredUnit.lookups 25989444 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 25989444 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2880460 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23775424 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 20999107 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27480404 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 261552197 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25050494 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 19578906 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 69713468 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3100277 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 27480404 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 444252 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 213378820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.014955 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.225944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30913045 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 262360842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 25989444 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 20999107 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70912631 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26788053 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 84314801 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 386 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28891572 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 510286 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 210004513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.080616 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.257688 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 145514774 68.20% 68.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3945621 1.85% 70.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3133148 1.47% 71.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4337653 2.03% 73.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4594142 2.15% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4407004 2.07% 77.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5010346 2.35% 80.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3238927 1.52% 81.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39197205 18.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140976557 67.13% 67.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4102515 1.95% 69.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3266952 1.56% 70.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4494510 2.14% 72.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4287341 2.04% 74.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4445757 2.12% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5469335 2.60% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3067811 1.46% 81.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39893735 19.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 213378820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.117350 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.225251 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 66958522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57001085 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 60412397 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5858231 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23148585 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 419968775 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23148585 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 74832356 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 18068346 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22426 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57435303 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 39871804 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 409779933 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21501033 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 16352489 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 430797248 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1054244247 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1043122682 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11121565 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 210004513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123706 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.248801 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45877800 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73040488 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 56067682 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11154952 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23863591 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 425695349 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 23863591 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 54978073 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 20531962 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 57215372 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53391627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 414341081 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 29904351 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20832303 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 439740854 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1072087884 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1060055510 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 12032374 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 196433839 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1310 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 83098346 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104980766 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37095594 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90430174 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30425407 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 395507957 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 281825994 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 65208 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 173816854 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 357698242 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 213378820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.320778 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.372811 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 205377445 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1472 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1467 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 107891206 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105317858 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38075077 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 93159528 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 32053194 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 401973184 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1452 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 281949896 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 93319 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 180405521 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 380338666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 210004513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.342590 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373881 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72508898 33.98% 33.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 65573468 30.73% 64.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36643591 17.17% 81.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20570957 9.64% 91.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12013670 5.63% 97.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3959812 1.86% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1477782 0.69% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 513095 0.24% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 117547 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69632726 33.16% 33.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 64637798 30.78% 63.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 36965443 17.60% 81.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20500342 9.76% 91.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11980383 5.70% 97.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4341078 2.07% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1469899 0.70% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 380882 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95962 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 213378820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 210004513 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 68694 2.44% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2379905 84.54% 86.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 366520 13.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 107259 3.58% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2493480 83.26% 86.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 394104 13.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1200241 0.43% 0.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187039988 66.37% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1589434 0.56% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68492447 24.30% 91.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23503884 8.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1205058 0.43% 0.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187553155 66.52% 66.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1592331 0.56% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67840384 24.06% 91.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23758968 8.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 281825994 # Type of FU issued -system.cpu.iq.rate 1.320224 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2815119 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009989 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 774676274 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 563666202 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 273457668 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5234861 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5690969 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2532279 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 280803234 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2637638 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 16340040 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 281949896 # Type of FU issued +system.cpu.iq.rate 1.342042 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2994843 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010622 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 771774380 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 576023644 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 274192966 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5218087 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 6409815 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2516754 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 281110852 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2628829 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 16405664 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 48331176 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20419 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34128 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16579878 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 48668268 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6062 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61115 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17559361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45973 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 45288 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23148585 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 533368 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 548562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 395509381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 255580 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104980766 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37095594 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 479390 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13059 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34128 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2541200 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 744980 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3286180 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 278309942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67077031 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3516052 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23863591 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 694538 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 427795 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 401974636 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 134263 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105317858 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38075077 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1452 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 312662 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61115 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2496230 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 580255 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3076485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 278882390 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66609586 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3067506 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90250007 # number of memory reference insts executed -system.cpu.iew.exec_branches 15873940 # Number of branches executed -system.cpu.iew.exec_stores 23172976 # Number of stores executed -system.cpu.iew.exec_rate 1.303753 # Inst execution rate -system.cpu.iew.wb_sent 277022685 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 275989947 # cumulative count of insts written-back -system.cpu.iew.wb_producers 222941067 # num instructions producing a value -system.cpu.iew.wb_consumers 371922286 # num instructions consuming a value +system.cpu.iew.exec_refs 90001503 # number of memory reference insts executed +system.cpu.iew.exec_branches 15748098 # Number of branches executed +system.cpu.iew.exec_stores 23391917 # Number of stores executed +system.cpu.iew.exec_rate 1.327442 # Inst execution rate +system.cpu.iew.wb_sent 277747224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 276709720 # cumulative count of insts written-back +system.cpu.iew.wb_producers 222890509 # num instructions producing a value +system.cpu.iew.wb_consumers 374197573 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.292885 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.599429 # average fanout of values written-back +system.cpu.iew.wb_rate 1.317100 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.595649 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 174164320 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 180623719 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3072754 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 190230235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.163658 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.518986 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2880510 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 186140922 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189223 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.544912 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74059520 38.93% 38.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 71187215 37.42% 76.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18215863 9.58% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12685132 6.67% 92.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5921003 3.11% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2781558 1.46% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1922219 1.01% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1098236 0.58% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2359489 1.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71104558 38.20% 38.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70002292 37.61% 75.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18277000 9.82% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12672001 6.81% 92.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5444041 2.92% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2973709 1.60% 96.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2048209 1.10% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1096137 0.59% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2522975 1.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 190230235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 186140922 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -252,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2359489 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2522975 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 583398083 # The number of ROB reads -system.cpu.rob.rob_writes 814214435 # The number of ROB writes -system.cpu.timesIdled 1914 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 89489 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 585604683 # The number of ROB reads +system.cpu.rob.rob_writes 827851683 # The number of ROB writes +system.cpu.timesIdled 1839 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 85628 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.964336 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.964336 # CPI: Total CPI of All Threads -system.cpu.ipc 1.036983 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.036983 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516519288 # number of integer regfile reads -system.cpu.int_regfile_writes 284023651 # number of integer regfile writes -system.cpu.fp_regfile_reads 3512884 # number of floating regfile reads -system.cpu.fp_regfile_writes 2186553 # number of floating regfile writes -system.cpu.misc_regfile_reads 145156303 # number of misc regfile reads +system.cpu.cpi 0.949075 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.949075 # CPI: Total CPI of All Threads +system.cpu.ipc 1.053657 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.053657 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516476198 # number of integer regfile reads +system.cpu.int_regfile_writes 284804952 # number of integer regfile writes +system.cpu.fp_regfile_reads 3512787 # number of floating regfile reads +system.cpu.fp_regfile_writes 2173928 # number of floating regfile writes +system.cpu.misc_regfile_reads 145108967 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 3419 # number of replacements -system.cpu.icache.tagsinuse 1603.937064 # Cycle average of tags in use -system.cpu.icache.total_refs 27474068 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 5377 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5109.553282 # Average number of references to valid blocks. +system.cpu.icache.replacements 4263 # number of replacements +system.cpu.icache.tagsinuse 1631.686111 # Cycle average of tags in use +system.cpu.icache.total_refs 28884352 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6229 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4637.076898 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1603.937064 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.783172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 27474068 # number of ReadReq hits -system.cpu.icache.demand_hits 27474068 # number of demand (read+write) hits -system.cpu.icache.overall_hits 27474068 # number of overall hits -system.cpu.icache.ReadReq_misses 6336 # number of ReadReq misses -system.cpu.icache.demand_misses 6336 # number of demand (read+write) misses -system.cpu.icache.overall_misses 6336 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 161881500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 161881500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 161881500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 27480404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 27480404 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 27480404 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000231 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000231 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000231 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 25549.479167 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 25549.479167 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 25549.479167 # average overall miss latency +system.cpu.icache.occ_blocks::0 1631.686111 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.796722 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28884352 # number of ReadReq hits +system.cpu.icache.demand_hits 28884352 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28884352 # number of overall hits +system.cpu.icache.ReadReq_misses 7220 # number of ReadReq misses +system.cpu.icache.demand_misses 7220 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7220 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 170089500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 170089500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 170089500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28891572 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28891572 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28891572 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000250 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000250 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000250 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23558.102493 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23558.102493 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23558.102493 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 957 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 957 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 957 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 5379 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 5379 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 5379 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 990 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 990 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 990 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6230 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6230 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6230 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 120710000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 120710000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 120710000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125517500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22440.974159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000216 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000216 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000216 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20147.271268 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 48 # number of replacements -system.cpu.dcache.tagsinuse 1400.553684 # Cycle average of tags in use -system.cpu.dcache.total_refs 71034499 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36334.782097 # Average number of references to valid blocks. +system.cpu.dcache.replacements 50 # number of replacements +system.cpu.dcache.tagsinuse 1406.909972 # Cycle average of tags in use +system.cpu.dcache.total_refs 70508700 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1965 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 35882.290076 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1400.553684 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.341932 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 50525866 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20508631 # number of WriteReq hits -system.cpu.dcache.demand_hits 71034497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 71034497 # number of overall hits -system.cpu.dcache.ReadReq_misses 700 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7099 # number of WriteReq misses -system.cpu.dcache.demand_misses 7799 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 7799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 23034500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 187834000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 210868500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 210868500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 50526566 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1406.909972 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343484 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 50000081 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20508618 # number of WriteReq hits +system.cpu.dcache.demand_hits 70508699 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 70508699 # number of overall hits +system.cpu.dcache.ReadReq_misses 707 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7112 # number of WriteReq misses +system.cpu.dcache.demand_misses 7819 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 7819 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 23625000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 187799500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 211424500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 211424500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 50000788 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 71042296 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 71042296 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 70516518 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 70516518 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32906.428571 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 26459.219608 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27037.889473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27037.889473 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate 0.000347 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000111 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000111 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33415.841584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 26406.003937 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27039.838854 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27039.838854 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 5530 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5842 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5842 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 303 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 5550 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 5853 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 5853 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1562 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1966 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1966 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 13276000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 55641500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 68917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 68917500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 13769000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 54860000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 68629000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 68629000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34216.494845 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35463.033779 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34081.683168 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35121.638924 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2429.026594 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2107 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3661 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.575526 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2506.517035 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2870 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3766 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.762082 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2428.011682 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.014912 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.074097 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2505.502143 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.014892 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076462 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2107 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 2870 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2113 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2113 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3657 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5219 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5219 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 125400000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53945500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 179345500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 179345500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5764 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits 2876 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2876 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3762 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5318 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5318 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128883000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53194000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 182077000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 182077000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6632 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 7332 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 7332 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.634455 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1562 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8194 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8194 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.567250 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.711811 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.711811 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34290.401969 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34536.171575 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34363.958613 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34363.958613 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.996159 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.649011 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.649011 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34259.170654 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34186.375321 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34237.871380 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34237.871380 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3657 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5219 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5219 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3762 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5318 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 113519000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48964500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162483500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162483500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116744500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48343500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 165088000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 165088000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634455 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567250 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.711811 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.711811 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.564124 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.649011 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.649011 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.562467 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.311140 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.087404 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini index 258f4e533..56fbbd75c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -204,7 +205,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index cdb09d17e..d51796d4d 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 23:40:02 -gem5 started Jun 20 2011 08:26:33 -gem5 executing on zooks +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:20:58 +gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21228000 because target called exit() +Exiting @ tick 21216000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 3184d80aa..118e4e630 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21228000 # Number of ticks simulated +sim_ticks 21216000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45998 # Simulator instruction rate (inst/s) -host_tick_rate 152436103 # Simulator tick rate (ticks/s) -host_mem_usage 157012 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 29106 # Simulator instruction rate (inst/s) +host_tick_rate 96412699 # Simulator tick rate (ticks/s) +host_mem_usage 242900 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 2084 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2094 # DTB accesses -system.cpu.itb.fetch_hits 932 # ITB hits +system.cpu.itb.fetch_hits 929 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 949 # ITB accesses +system.cpu.itb.fetch_accesses 946 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42457 # number of cpu cycles simulated +system.cpu.numCycles 42433 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35048 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7409 # Number of cycles cpu stages are processed. -system.cpu.activity 17.450597 # Percentage of cycles cpu is active +system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7383 # Number of cycles cpu stages are processed. +system.cpu.activity 17.399194 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -61,79 +61,79 @@ system.cpu.comFloats 2 # Nu system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) -system.cpu.cpi 6.629763 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.629763 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150835 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150835 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1674 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1207 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 720 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1422 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 419 # Number of BTB hits +system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1670 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.465541 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 570 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1104 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5167 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9747 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 3004 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2137 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 369 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 290 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 659 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 393 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.642586 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4444 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2138 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 4447 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 37460 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4997 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.769555 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38535 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3922 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.237582 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38269 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4188 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.864098 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41117 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.156134 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 37979 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4478 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.547142 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.808044 # Cycle average of tags in use -system.cpu.icache.total_refs 584 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use +system.cpu.icache.total_refs 581 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.940199 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 138.808044 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.067777 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 584 # number of ReadReq hits -system.cpu.icache.demand_hits 584 # number of demand (read+write) hits -system.cpu.icache.overall_hits 584 # number of overall hits +system.cpu.icache.occ_blocks::0 138.882502 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.067814 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 581 # number of ReadReq hits +system.cpu.icache.demand_hits 581 # number of demand (read+write) hits +system.cpu.icache.overall_hits 581 # number of overall hits system.cpu.icache.ReadReq_misses 348 # number of ReadReq misses system.cpu.icache.demand_misses 348 # number of demand (read+write) misses system.cpu.icache.overall_misses 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19242000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19242000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19242000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 932 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 932 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.373391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.373391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.373391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55293.103448 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55293.103448 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55293.103448 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 19241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 929 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 929 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.374596 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.374596 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.374596 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55290.229885 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55290.229885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55290.229885 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -150,28 +150,28 @@ system.cpu.icache.ReadReq_mshr_misses 302 # nu system.cpu.icache.demand_mshr_misses 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16050000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16050000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16050000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 16049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16049000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.324034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.324034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.324034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53145.695364 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.325081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.325081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.325081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.384106 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.626911 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.626911 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.025055 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 102.671807 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.025066 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 615 # number of WriteReq hits system.cpu.dcache.demand_hits 1703 # number of demand (read+write) hits @@ -181,9 +181,9 @@ system.cpu.dcache.WriteReq_misses 250 # nu system.cpu.dcache.demand_misses 347 # number of demand (read+write) misses system.cpu.dcache.overall_misses 347 # number of overall misses system.cpu.dcache.ReadReq_miss_latency 5508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 13555000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19063500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19063500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency 13555500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19064000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19064000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses @@ -193,9 +193,9 @@ system.cpu.dcache.WriteReq_miss_rate 0.289017 # mi system.cpu.dcache.demand_miss_rate 0.169268 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.169268 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 56788.659794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54220 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54938.040346 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54938.040346 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 54222 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54939.481268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54939.481268 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,30 +215,30 @@ system.cpu.dcache.demand_mshr_misses 168 # nu system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3909500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9023500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9023500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3910000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9024000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53831.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.111607 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 195.111607 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005954 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 195.209568 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005957 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 1 # number of overall hits @@ -246,8 +246,8 @@ system.cpu.l2cache.ReadReq_misses 396 # nu system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 20702500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 20702000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3822000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency 24524000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency 24524000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses) @@ -258,8 +258,8 @@ system.cpu.l2cache.ReadReq_miss_rate 0.997481 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52279.040404 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52349.315068 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52277.777778 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.164384 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency 52289.978678 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 52289.978678 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -278,19 +278,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 73 # nu system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15876500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 15877000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18819000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18819000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18819500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40092.171717 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40093.434343 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 08baf7c22..03a16a5ea 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 6caee1c6f..f022a446d 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:04:58 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:20:58 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12357500 because target called exit() +Exiting @ tick 12002500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 42ab89f68..50d6ec22a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12357500 # Number of ticks simulated +sim_ticks 12002500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108363 # Simulator instruction rate (inst/s) -host_tick_rate 209619317 # Simulator tick rate (ticks/s) -host_mem_usage 192840 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 25819 # Simulator instruction rate (inst/s) +host_tick_rate 48521023 # Simulator tick rate (ticks/s) +host_mem_usage 243716 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1750 # DTB read hits -system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.read_hits 1863 # DTB read hits +system.cpu.dtb.read_misses 45 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1786 # DTB read accesses -system.cpu.dtb.write_hits 1011 # DTB write hits -system.cpu.dtb.write_misses 25 # DTB write misses +system.cpu.dtb.read_accesses 1908 # DTB read accesses +system.cpu.dtb.write_hits 1047 # DTB write hits +system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1036 # DTB write accesses -system.cpu.dtb.data_hits 2761 # DTB hits -system.cpu.dtb.data_misses 61 # DTB misses +system.cpu.dtb.write_accesses 1075 # DTB write accesses +system.cpu.dtb.data_hits 2910 # DTB hits +system.cpu.dtb.data_misses 73 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2822 # DTB accesses -system.cpu.itb.fetch_hits 1711 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.dtb.data_accesses 2983 # DTB accesses +system.cpu.itb.fetch_hits 2044 # ITB hits +system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1744 # ITB accesses +system.cpu.itb.fetch_accesses 2073 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,243 +41,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24716 # number of cpu cycles simulated +system.cpu.numCycles 24006 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2180 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits +system.cpu.BPredUnit.lookups 2516 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1462 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1947 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 723 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 372 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7155 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14481 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2516 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1095 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2626 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1554 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.149103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.531397 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10590 82.00% 82.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 233 1.80% 83.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 211 1.63% 85.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 179 1.39% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 229 1.77% 88.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 156 1.21% 89.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 218 1.69% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 125 0.97% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 974 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9976 79.16% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.17% 81.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 231 1.83% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 220 1.75% 84.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 235 1.86% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 176 1.40% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.04% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.12% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1092 8.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2228 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2118 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.104807 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.603224 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7976 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2455 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 976 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 216 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13403 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 976 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8164 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2326 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12866 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9599 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16086 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16069 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5016 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2397 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1265 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 11578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9768 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4900 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2850 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.775115 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8516 67.58% 67.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1470 11.66% 79.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1066 8.46% 87.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 684 5.43% 93.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 441 3.50% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.02% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 129 1.02% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.24% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12602 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13 12.38% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 54 51.43% 63.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 36.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6583 67.39% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2078 21.27% 88.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1102 11.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.rate 0.368506 # Inst issue rate -system.cpu.iq.fu_busy_cnt 88 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9768 # Type of FU issued +system.cpu.iq.rate 0.406898 # Inst issue rate +system.cpu.iq.fu_busy_cnt 105 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010749 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32267 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16511 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8987 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9860 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 959 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 330 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1212 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 400 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 976 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11685 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2397 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1265 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 445 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9324 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1918 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 82 # number of nop insts executed -system.cpu.iew.exec_refs 2832 # number of memory reference insts executed -system.cpu.iew.exec_branches 1424 # Number of branches executed -system.cpu.iew.exec_stores 1038 # Number of stores executed -system.cpu.iew.exec_rate 0.357542 # Inst execution rate -system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8559 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4429 # num instructions producing a value -system.cpu.iew.wb_consumers 5952 # num instructions consuming a value +system.cpu.iew.exec_nop 80 # number of nop insts executed +system.cpu.iew.exec_refs 2995 # number of memory reference insts executed +system.cpu.iew.exec_branches 1503 # Number of branches executed +system.cpu.iew.exec_stores 1077 # Number of stores executed +system.cpu.iew.exec_rate 0.388403 # Inst execution rate +system.cpu.iew.wb_sent 9127 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4717 # num instructions producing a value +system.cpu.iew.wb_consumers 6401 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374781 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736916 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5279 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.550748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.411308 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8945 76.94% 76.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1414 12.16% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 463 3.98% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 244 2.10% 95.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 156 1.34% 96.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 87 0.75% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.95% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.38% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 163 1.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11626 # Number of insts commited each cycle system.cpu.commit.count 6403 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2050 # Number of memory references committed @@ -287,50 +289,50 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 163 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22264 # The number of ROB reads -system.cpu.rob.rob_writes 22135 # The number of ROB writes -system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22794 # The number of ROB reads +system.cpu.rob.rob_writes 24351 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads -system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11291 # number of integer regfile reads -system.cpu.int_regfile_writes 6385 # number of integer regfile writes +system.cpu.cpi 3.759161 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.759161 # CPI: Total CPI of All Threads +system.cpu.ipc 0.266017 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.266017 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11850 # number of integer regfile reads +system.cpu.int_regfile_writes 6735 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use -system.cpu.icache.total_refs 1301 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.654959 # Cycle average of tags in use +system.cpu.icache.total_refs 1612 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.183280 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits -system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1301 # number of overall hits -system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses -system.cpu.icache.demand_misses 410 # number of demand (read+write) misses -system.cpu.icache.overall_misses 410 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency +system.cpu.icache.occ_blocks::0 159.654959 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.077957 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1612 # number of ReadReq hits +system.cpu.icache.demand_hits 1612 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1612 # number of overall hits +system.cpu.icache.ReadReq_misses 432 # number of ReadReq misses +system.cpu.icache.demand_misses 432 # number of demand (read+write) misses +system.cpu.icache.overall_misses 432 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15402000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15402000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15402000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2044 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2044 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2044 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.211350 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.211350 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.211350 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35652.777778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35652.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35652.777778 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,59 +342,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10985500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10985500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10985500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.152153 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.152153 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.152153 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.151125 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use -system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.289403 # Cycle average of tags in use +system.cpu.dcache.total_refs 2155 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.385057 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 109.289403 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1646 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits -system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2064 # number of overall hits -system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses +system.cpu.dcache.demand_hits 2155 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2155 # number of overall hits +system.cpu.dcache.ReadReq_misses 155 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 506 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5502500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 17970000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 17970000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1801 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2666 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2666 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.086063 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.191673 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191673 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35166.340509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35166.340509 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,63 +404,63 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6265500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056080 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.065266 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.065266 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.186144 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 411 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002433 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 221.186144 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses 411 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 484 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 484 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 14128000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16641500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16641500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 412 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997573 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.997938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997938 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34374.695864 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34383.264463 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34383.264463 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,24 +472,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 411 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 484 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12819000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15105000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997573 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.997938 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997938 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.781022 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 838834423..1c3640f5b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr index 0659d557a..27f858d8f 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 8a87312b4..74424d63b 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,16 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:29:56 -M5 started Apr 21 2011 13:15:23 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:21:09 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7289000 because target called exit() +Exiting @ tick 6921000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index b8b5c99cd..5e52ef944 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,494 +1,496 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 66320 # Simulator instruction rate (inst/s) -host_mem_usage 205872 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 201598879 # Simulator tick rate (ticks/s) +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 6921000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 33894 # Simulator instruction rate (inst/s) +host_tick_rate 98227338 # Simulator tick rate (ticks/s) +host_mem_usage 242788 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7289000 # Number of ticks simulated +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 720 # DTB read hits +system.cpu.dtb.read_misses 34 # DTB read misses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 354 # DTB write hits +system.cpu.dtb.write_misses 22 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 376 # DTB write accesses +system.cpu.dtb.data_hits 1074 # DTB hits +system.cpu.dtb.data_misses 56 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 1130 # DTB accesses +system.cpu.itb.fetch_hits 976 # ITB hits +system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 1006 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 13843 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 1112 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 583 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 236 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 781 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 240 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 197 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 687 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 223 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 485 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 931 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 146 # The number of times a branch was mispredicted -system.cpu.commit.branches 396 # Number of branches committed -system.cpu.commit.bw_lim_events 41 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3787 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6697 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1112 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 455 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1166 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 814 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 253 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 781 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 976 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 159 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.021351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.437035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5391 82.22% 82.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 67 1.02% 83.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 123 1.88% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 97 1.48% 86.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 146 2.23% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 50 0.76% 89.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 61 0.93% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 83 1.27% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 539 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 6557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080329 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.483782 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4673 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 269 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1132 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 476 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 152 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6020 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 476 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4772 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 89 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1039 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 34 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5743 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 11 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4153 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6495 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6483 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 2385 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 8 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 961 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 458 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4907 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 3996 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2355 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1385 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6557 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.609425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.316967 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4952 75.52% 75.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 578 8.82% 84.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 360 5.49% 89.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 270 4.12% 93.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 209 3.19% 97.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 109 1.66% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 54 0.82% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17 0.26% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6557 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 2.27% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20 45.45% 47.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2819 70.55% 70.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 794 19.87% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 382 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 3996 # Type of FU issued +system.cpu.iq.rate 0.288666 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011011 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14670 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7267 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3636 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 4033 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 546 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 164 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 476 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 79 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5242 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 961 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 458 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 137 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3843 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 329 # number of nop insts executed +system.cpu.iew.exec_refs 1131 # number of memory reference insts executed +system.cpu.iew.exec_branches 644 # Number of branches executed +system.cpu.iew.exec_stores 376 # Number of stores executed +system.cpu.iew.exec_rate 0.277613 # Inst execution rate +system.cpu.iew.wb_sent 3725 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3642 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1733 # num instructions producing a value +system.cpu.iew.wb_consumers 2231 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.263093 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.776782 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 2657 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1995 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 6308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.408370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.199072 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 159 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.423615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.271187 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5350 84.81% 84.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 259 4.11% 88.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 343 5.44% 94.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 133 2.11% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.14% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 64 1.01% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 26 0.41% 99.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.32% 99.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 41 0.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5177 85.13% 85.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 230 3.78% 88.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 323 5.31% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 118 1.94% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 67 1.10% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 52 0.86% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 37 0.61% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.33% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 57 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6081 # Number of insts commited each cycle system.cpu.commit.count 2576 # Number of instructions committed -system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. -system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.int_insts 2367 # Number of committed integer instructions. +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 709 # Number of memory references committed system.cpu.commit.loads 415 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 709 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branches 396 # Number of branches committed +system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. +system.cpu.commit.int_insts 2367 # Number of committed integer instructions. +system.cpu.commit.function_calls 71 # Number of function calls committed. +system.cpu.commit.bw_lim_events 57 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 11010 # The number of ROB reads +system.cpu.rob.rob_writes 10947 # The number of ROB writes +system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7286 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.107667 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.107667 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 589 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33939.814815 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35704.918033 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 481 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3665500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.183362 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 108 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2178000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.103565 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 38819.444444 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36145.833333 # average WriteReq mshr miss latency +system.cpu.cpi 5.799330 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.799330 # CPI: Total CPI of All Threads +system.cpu.ipc 0.172434 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.172434 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4649 # number of integer regfile reads +system.cpu.int_regfile_writes 2817 # number of integer regfile writes +system.cpu.fp_regfile_reads 6 # number of floating regfile reads +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 92.452549 # Cycle average of tags in use +system.cpu.icache.total_refs 735 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3.972973 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 92.452549 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.045143 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 735 # number of ReadReq hits +system.cpu.icache.demand_hits 735 # number of demand (read+write) hits +system.cpu.icache.overall_hits 735 # number of overall hits +system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses +system.cpu.icache.demand_misses 241 # number of demand (read+write) misses +system.cpu.icache.overall_misses 241 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 8775500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8775500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8775500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 976 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.246926 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.246926 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.246926 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36412.863071 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36412.863071 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36412.863071 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 185 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 6554000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6554000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6554000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.189549 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.189549 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.189549 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35427.027027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 45.779373 # Cycle average of tags in use +system.cpu.dcache.total_refs 794 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.341176 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 45.779373 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011177 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 572 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2795000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.demand_hits 794 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 794 # number of overall hits +system.cpu.dcache.ReadReq_misses 116 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 867500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.270588 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 188 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3872000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 6688500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 6688500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 982 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 982 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.168605 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.191446 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191446 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33379.310345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35577.127660 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35577.127660 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 883 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35891.666667 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency -system.cpu.dcache.demand_hits 703 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 6460500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.203851 # miss rate for demand accesses -system.cpu.dcache.demand_misses 180 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3045500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.096263 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 103 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 46.556735 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011366 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 883 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35891.666667 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 703 # number of overall hits -system.cpu.dcache.overall_miss_latency 6460500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.203851 # miss rate for overall accesses -system.cpu.dcache.overall_misses 180 # number of overall misses -system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3045500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.096263 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 2165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3037500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3037500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.088663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.086558 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.086558 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.556735 # Cycle average of tags in use -system.cpu.dcache.total_refs 703 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 217 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 5047 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 5111 # Number of cycles decode is idle -system.cpu.decode.RunCycles 977 # Number of cycles decode is running -system.cpu.decode.SquashCycles 374 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 3 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1010 # DTB accesses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 964 # DTB hits -system.cpu.dtb.data_misses 46 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 644 # DTB read accesses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 617 # DTB read hits -system.cpu.dtb.read_misses 27 # DTB read misses -system.cpu.dtb.write_accesses 366 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 347 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses -system.cpu.fetch.Branches 931 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 777 # Number of cache lines fetched -system.cpu.fetch.Cycles 986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 113 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5745 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 246 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.063859 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 777 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 371 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.394060 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.859773 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.273067 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5696 85.24% 85.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43 0.64% 85.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 112 1.68% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72 1.08% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 53 0.79% 91.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 50 0.75% 92.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 59 0.88% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 474 7.09% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6682 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 6 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 777 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36200.431034 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35306.629834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 545 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8398500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.298584 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 232 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6390500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.232947 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.011050 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 777 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36200.431034 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency -system.cpu.icache.demand_hits 545 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8398500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.298584 # miss rate for demand accesses -system.cpu.icache.demand_misses 232 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6390500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.232947 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 90.511194 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.044195 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 777 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36200.431034 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 545 # number of overall hits -system.cpu.icache.overall_miss_latency 8398500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.298584 # miss rate for overall accesses -system.cpu.icache.overall_misses 232 # number of overall misses -system.cpu.icache.overall_mshr_hits 51 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6390500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.232947 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 90.511194 # Cycle average of tags in use -system.cpu.icache.total_refs 545 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7897 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 171 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 600 # Number of branches executed -system.cpu.iew.exec_nop 311 # number of nop insts executed -system.cpu.iew.exec_rate 0.241855 # Inst execution rate -system.cpu.iew.exec_refs 1011 # number of memory reference insts executed -system.cpu.iew.exec_stores 366 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 48 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 779 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 58 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4585 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 645 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 109 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3526 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 374 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 364 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 1995 # num instructions consuming a value -system.cpu.iew.wb_count 3404 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.790977 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1578 # num instructions producing a value -system.cpu.iew.wb_rate 0.233487 # insts written-back per cycle -system.cpu.iew.wb_sent 3463 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 4291 # number of integer regfile reads -system.cpu.int_regfile_writes 2610 # number of integer regfile writes -system.cpu.ipc 0.163729 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.163729 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2594 71.36% 71.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 669 18.40% 89.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 371 10.21% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3635 # Type of FU issued -system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 32 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008803 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 3.12% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9 28.12% 31.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 68.75% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 3660 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 14000 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 3398 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 5975 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 4268 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3635 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1704 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 959 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 6682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.543999 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.232060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5130 76.77% 76.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 639 9.56% 86.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 335 5.01% 91.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 242 3.62% 94.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 178 2.66% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 94 1.41% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39 0.58% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 16 0.24% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6682 # Number of insts issued each cycle -system.cpu.iq.rate 0.249331 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 806 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 777 # ITB hits -system.cpu.itb.fetch_misses 29 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 121.331762 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 121.331762 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003703 # Average percentage of cache occupancy +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34326.446281 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.628099 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8307000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 270 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 8443500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 9274500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 9274500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7537000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34323.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34350 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34350 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34351.503759 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9137500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8293000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 119.871330 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003658 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34351.503759 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9137500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8293000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 242 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 7659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8415500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8415500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.178862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 119.871330 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 14579 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 55 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 5189 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 5515 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 4879 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 3490 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 901 # Number of cycles rename is running -system.cpu.rename.SquashCycles 374 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 17 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 1722 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 5503 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 146 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.skidInsts 74 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 10591 # The number of ROB reads -system.cpu.rob.rob_writes 9519 # The number of ROB writes -system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index 92bf445c8..b56607812 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 7a48bdd9d..357a5d59d 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -1,17 +1,11 @@ -Redirecting stdout to build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 15:11:56 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 8 2011 15:23:20 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10758500 because target called exit() +Exiting @ tick 9834500 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index b65280987..d884999d2 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10758500 # Number of ticks simulated +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 9834500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88454 # Simulator instruction rate (inst/s) -host_tick_rate 165780634 # Simulator tick rate (ticks/s) -host_mem_usage 251164 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 38040 # Simulator instruction rate (inst/s) +host_tick_rate 65174027 # Simulator tick rate (ticks/s) +host_mem_usage 253652 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,242 +51,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 21518 # number of cpu cycles simulated +system.cpu.numCycles 19670 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2191 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1669 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 732 # Number of BTB hits +system.cpu.BPredUnit.lookups 2538 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1884 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1886 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 760 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 242 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 63 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1618 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11168 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2191 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 974 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2422 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 514 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1618 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.190999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.598414 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6290 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12764 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1028 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2852 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1670 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1030 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2054 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.423857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.772019 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9243 79.24% 79.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.94% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 153 1.31% 82.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 215 1.84% 84.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 195 1.67% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 261 2.24% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 124 1.06% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 97 0.83% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1151 9.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8482 74.84% 74.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 284 2.51% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 192 1.69% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 246 2.17% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 242 2.14% 83.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 324 2.86% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 124 1.09% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 120 1.06% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1320 11.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.101822 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.519007 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7384 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1181 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2267 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 786 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 350 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12143 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 552 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 786 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7644 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 280 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 712 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2054 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 189 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11385 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 38 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11181 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51901 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51381 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 11334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129029 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.648907 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6573 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1079 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2654 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 60 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14169 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6862 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2422 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13321 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12898 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 60750 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 59430 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5492 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 15 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 7209 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 493 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2353 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1452 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10217 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8487 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3978 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 11076 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 11665 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.727561 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.389080 # Number of insts issued each cycle +system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2701 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1759 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11506 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9339 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14048 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.823981 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.484525 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8112 69.54% 69.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1403 12.03% 81.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 820 7.03% 88.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 520 4.46% 93.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 393 3.37% 96.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 236 2.02% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 143 1.23% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.26% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7613 67.17% 67.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1341 11.83% 79.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 855 7.54% 86.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 564 4.98% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 476 4.20% 95.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 284 2.51% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 147 1.30% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 42 0.37% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11334 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 6.01% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 116 63.39% 69.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56 30.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.79% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 138 64.19% 66.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5246 61.81% 61.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2078 24.48% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1154 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5727 61.32% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.07% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2324 24.88% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1278 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8487 # Type of FU issued -system.cpu.iq.rate 0.394414 # Inst issue rate -system.cpu.iq.fu_busy_cnt 183 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021562 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28807 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14215 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7753 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 9339 # Type of FU issued +system.cpu.iq.rate 0.474784 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023022 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30256 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16705 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8361 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8650 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 9514 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1500 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 514 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 786 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10244 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2353 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1452 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 19 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11534 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 218 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2701 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1759 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 243 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 371 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8154 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1932 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 333 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 95 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8897 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 3 # number of nop insts executed -system.cpu.iew.exec_refs 3053 # number of memory reference insts executed -system.cpu.iew.exec_branches 1361 # Number of branches executed -system.cpu.iew.exec_stores 1121 # Number of stores executed -system.cpu.iew.exec_rate 0.378939 # Inst execution rate -system.cpu.iew.wb_sent 7896 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7769 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3570 # num instructions producing a value -system.cpu.iew.wb_consumers 7022 # num instructions consuming a value +system.cpu.iew.exec_refs 3351 # number of memory reference insts executed +system.cpu.iew.exec_branches 1479 # Number of branches executed +system.cpu.iew.exec_stores 1222 # Number of stores executed +system.cpu.iew.exec_rate 0.452313 # Inst execution rate +system.cpu.iew.wb_sent 8556 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8377 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3980 # num instructions producing a value +system.cpu.iew.wb_consumers 7830 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.361047 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.508402 # average fanout of values written-back +system.cpu.iew.wb_rate 0.425877 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.508301 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4400 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5640 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 334 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.289859 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 351 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.553583 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.355703 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8406 77.26% 77.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1187 10.91% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 477 4.38% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 317 2.91% 95.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.56% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 153 1.41% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 62 0.57% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 34 0.31% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 74 0.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8010 77.26% 77.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1098 10.59% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 433 4.18% 92.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 284 2.74% 94.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.77% 96.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.62% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.65% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.38% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 84 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10367 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed @@ -296,49 +298,49 @@ system.cpu.commit.branches 945 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 20788 # The number of ROB reads -system.cpu.rob.rob_writes 21080 # The number of ROB writes -system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9853 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21505 # The number of ROB reads +system.cpu.rob.rob_writes 23748 # The number of ROB writes +system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8336 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.749434 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.749434 # CPI: Total CPI of All Threads -system.cpu.ipc 0.266707 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.266707 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 37248 # number of integer regfile reads -system.cpu.int_regfile_writes 7653 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 13970 # number of misc regfile reads +system.cpu.cpi 3.427426 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.427426 # CPI: Total CPI of All Threads +system.cpu.ipc 0.291764 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.291764 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40468 # number of integer regfile reads +system.cpu.int_regfile_writes 8226 # number of integer regfile writes +system.cpu.fp_regfile_reads 29 # number of floating regfile reads +system.cpu.misc_regfile_reads 15801 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 146.709916 # Cycle average of tags in use -system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 285 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.519298 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 150.859133 # Cycle average of tags in use +system.cpu.icache.total_refs 1688 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.702703 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 146.709916 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.071636 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits -system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1288 # number of overall hits -system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses -system.cpu.icache.demand_misses 330 # number of demand (read+write) misses -system.cpu.icache.overall_misses 330 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 11562500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 11562500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 11562500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1618 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1618 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1618 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.203956 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.203956 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.203956 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35037.878788 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35037.878788 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35037.878788 # average overall miss latency +system.cpu.icache.occ_blocks::0 150.859133 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.073662 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1688 # number of ReadReq hits +system.cpu.icache.demand_hits 1688 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1688 # number of overall hits +system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses +system.cpu.icache.demand_misses 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 12656500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 12656500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 12656500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2054 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2054 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2054 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.178189 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.178189 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.178189 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34580.601093 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34580.601093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34580.601093 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -348,67 +350,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9568500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9568500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9568500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 9940500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9940500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9940500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.176143 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.176143 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.176143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33573.684211 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.144109 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.144109 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.144109 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33582.770270 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.574063 # Cycle average of tags in use -system.cpu.dcache.total_refs 2279 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.295302 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.281770 # Cycle average of tags in use +system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.512821 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.574063 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021869 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1637 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits +system.cpu.dcache.occ_blocks::0 92.281770 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022530 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1791 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 2259 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2259 # number of overall hits -system.cpu.dcache.ReadReq_misses 159 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses +system.cpu.dcache.demand_hits 2400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2400 # number of overall hits +system.cpu.dcache.ReadReq_misses 178 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 450 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5132500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10420500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5526000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 15553000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 15553000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 16231500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16231500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1969 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.088530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 2882 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2882 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.090401 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.166113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.166113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32279.874214 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35809.278351 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.167245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.167245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31044.943820 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34562.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34562.222222 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33675.311203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33675.311203 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,64 +420,64 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 64 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 107 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 326 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 114 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 149 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 149 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3099500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1507500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4607000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4607000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.057897 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.055002 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.055002 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28967.289720 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35892.857143 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.054129 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.054129 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.420659 # Cycle average of tags in use -system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 347 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.112392 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 190.940380 # Cycle average of tags in use +system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 185.420659 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005659 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses 353 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 190.940380 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005827 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits +system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 43 # number of overall hits +system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 395 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 395 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12138500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1447000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 13585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 13585500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 392 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 409 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 12612500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 14063000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 14063000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.900510 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 452 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.895122 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.910138 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.910138 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34386.685552 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34452.380952 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34393.670886 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34393.670886 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34366.485014 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34383.863081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34383.863081 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,27 +487,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 347 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10837500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 12152500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 12152500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11305500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 12622500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 12622500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.882927 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.896313 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.896313 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31231.988473 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.893805 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.893805 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31230.662983 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 15c18bd45..ba028db41 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 14:43:48 -gem5 started Jun 19 2011 14:43:49 -gem5 executing on zooks -command line: build/MIPS_SE/gem5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing +gem5 compiled Jul 8 2011 15:04:50 +gem5 started Jul 8 2011 15:22:23 +gem5 executing on u200439-lin.austin.arm.com +command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 19782000 because target called exit() +Exiting @ tick 19785000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 340c12899..bde2424c6 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19782000 # Number of ticks simulated +sim_ticks 19785000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56447 # Simulator instruction rate (inst/s) -host_tick_rate 191567423 # Simulator tick rate (ticks/s) -host_mem_usage 158160 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 27579 # Simulator instruction rate (inst/s) +host_tick_rate 93627553 # Simulator tick rate (ticks/s) +host_mem_usage 243928 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,16 +27,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 39565 # number of cpu cycles simulated +system.cpu.numCycles 39571 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9153 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9159 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34165 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5400 # Number of cycles cpu stages are processed. -system.cpu.activity 13.648427 # Percentage of cycles cpu is active +system.cpu.idleCycles 34166 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5405 # Number of cycles cpu stages are processed. +system.cpu.activity 13.658993 # Percentage of cycles cpu is active system.cpu.comLoads 1164 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 916 # Number of Branches instructions committed @@ -47,79 +47,79 @@ system.cpu.comFloats 0 # Nu system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) -system.cpu.cpi 6.789943 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.789943 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147277 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads +system.cpu.ipc 0.147254 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147277 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1173 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 886 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 609 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1011 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 413 # Number of BTB hits +system.cpu.ipc_total 0.147254 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1185 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 896 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 611 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1035 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 443 # Number of BTB hits system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 40.850643 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 506 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 667 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5107 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 42.801932 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 536 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 649 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5108 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8515 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8516 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1342 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2229 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 313 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 287 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 600 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 316 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 65.502183 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3130 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 1344 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2228 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 317 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 285 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 602 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 314 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 65.720524 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3132 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 35845 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3720 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.402249 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36724 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2841 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.180589 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36774 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.054215 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 38322 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 35846 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3725 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.413459 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36723 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2848 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.197190 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36778 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2793 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.058199 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38328 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.141666 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36660 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.141189 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36666 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.342348 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.341235 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.154290 # Cycle average of tags in use -system.cpu.icache.total_refs 442 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 148.138598 # Cycle average of tags in use +system.cpu.icache.total_refs 443 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.385580 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 148.154290 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.072341 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 442 # number of ReadReq hits -system.cpu.icache.demand_hits 442 # number of demand (read+write) hits -system.cpu.icache.overall_hits 442 # number of overall hits +system.cpu.icache.occ_blocks::0 148.138598 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.072333 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 443 # number of ReadReq hits +system.cpu.icache.demand_hits 443 # number of demand (read+write) hits +system.cpu.icache.overall_hits 443 # number of overall hits system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses system.cpu.icache.demand_misses 341 # number of demand (read+write) misses system.cpu.icache.overall_misses 341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19026500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19026500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19026500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 783 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 783 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 783 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.435504 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.435504 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.435504 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55796.187683 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55796.187683 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55796.187683 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 19027500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19027500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19027500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 784 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 784 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 784 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.434949 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.434949 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.434949 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55799.120235 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55799.120235 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55799.120235 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,28 +136,28 @@ system.cpu.icache.ReadReq_mshr_misses 319 # nu system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16952000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16952000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16952000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 16952500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16952500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16952500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.407407 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.407407 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.407407 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53141.065831 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53141.065831 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53141.065831 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.406888 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.406888 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.406888 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.737794 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.737794 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021909 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 89.732679 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021907 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits @@ -167,9 +167,9 @@ system.cpu.dcache.WriteReq_misses 162 # nu system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses system.cpu.dcache.overall_misses 251 # number of overall misses system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 8910500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13983000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13983000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency 8912000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 13984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 13984500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses @@ -179,9 +179,9 @@ system.cpu.dcache.WriteReq_miss_rate 0.175135 # mi system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55003.086420 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55709.163347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55709.163347 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 55715.139442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 55715.139442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -201,30 +201,30 @@ system.cpu.dcache.demand_mshr_misses 138 # nu system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7448000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7448000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2746000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7448500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7448500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53971.014493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53971.014493 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53843.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.489748 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 205.489748 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006271 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 205.469583 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006270 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits @@ -232,10 +232,10 @@ system.cpu.l2cache.ReadReq_misses 404 # nu system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 21170000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2682000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 23852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 23852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 21170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2682500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 23853000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 23853000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses @@ -244,10 +244,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.995074 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52400.990099 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52588.235294 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52421.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52421.978022 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52424.175824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52424.175824 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index 5fbba49b2..8bda4905e 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index b9191e12f..d2612b5d7 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 07:04:09 -gem5 started Jun 19 2011 07:04:15 -gem5 executing on m60-009.pool -command line: build/MIPS_SE/gem5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing +gem5 compiled Jul 8 2011 15:04:50 +gem5 started Jul 8 2011 15:22:25 +gem5 executing on u200439-lin.austin.arm.com +command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12793500 because target called exit() +Exiting @ tick 12285500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index ad65ae514..39498f791 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12793500 # Number of ticks simulated +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12285500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95916 # Simulator instruction rate (inst/s) -host_tick_rate 237306997 # Simulator tick rate (ticks/s) -host_mem_usage 193796 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 28817 # Simulator instruction rate (inst/s) +host_tick_rate 68479139 # Simulator tick rate (ticks/s) +host_mem_usage 244744 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,241 +27,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 25588 # number of cpu cycles simulated +system.cpu.numCycles 24572 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1716 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 380 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1503 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 531 # Number of BTB hits +system.cpu.BPredUnit.lookups 1982 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1348 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1584 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 496 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1531 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 10867 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1716 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2794 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 387 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1531 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 211 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12856 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.845286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.112165 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7946 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12305 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1982 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3034 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1194 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1787 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.971422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.277830 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10062 78.27% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1173 9.12% 87.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 132 1.03% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 122 0.95% 89.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 273 2.12% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 123 0.96% 92.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 157 1.22% 93.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 97 0.75% 94.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 717 5.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9633 76.05% 76.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1253 9.89% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 111 0.88% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 138 1.09% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 289 2.28% 90.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 132 1.04% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 144 1.14% 93.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 875 6.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12856 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.067063 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.424691 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8753 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 742 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2688 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 37 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 636 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 89 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10279 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 153 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 636 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8904 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 238 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2577 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9880 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 71 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6029 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 11929 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 11924 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080661 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.500773 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8135 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2867 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 743 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 743 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8306 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2750 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11058 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 6730 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13185 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13180 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2619 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 15 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 193 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2109 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1127 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2359 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 7965 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7293 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 12856 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.567284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 8691 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 7857 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3019 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12667 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.620273 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.285525 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9298 73.40% 73.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1326 10.47% 83.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 831 6.56% 90.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 513 4.05% 94.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 361 2.85% 97.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 205 1.62% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 85 0.67% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33 0.26% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12667 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 2.07% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 90 62.07% 64.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 35.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1952 26.77% 85.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1047 14.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4616 58.75% 58.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2141 27.25% 86.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1092 13.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7293 # Type of FU issued -system.cpu.iq.rate 0.285016 # Inst issue rate -system.cpu.iq.fu_busy_cnt 143 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 27612 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 10338 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7857 # Type of FU issued +system.cpu.iq.rate 0.319754 # Inst issue rate +system.cpu.iq.fu_busy_cnt 145 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018455 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 28573 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11730 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7154 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8000 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 945 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 202 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1195 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 743 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 9195 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1127 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions +system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10089 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2359 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7077 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1877 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 216 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7573 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2041 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1220 # number of nop insts executed -system.cpu.iew.exec_refs 2915 # number of memory reference insts executed -system.cpu.iew.exec_branches 1171 # Number of branches executed -system.cpu.iew.exec_stores 1038 # Number of stores executed -system.cpu.iew.exec_rate 0.276575 # Inst execution rate -system.cpu.iew.wb_sent 6801 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6732 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2555 # num instructions producing a value -system.cpu.iew.wb_consumers 3566 # num instructions consuming a value +system.cpu.iew.exec_nop 1385 # number of nop insts executed +system.cpu.iew.exec_refs 3109 # number of memory reference insts executed +system.cpu.iew.exec_branches 1276 # Number of branches executed +system.cpu.iew.exec_stores 1068 # Number of stores executed +system.cpu.iew.exec_rate 0.308196 # Inst execution rate +system.cpu.iew.wb_sent 7250 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7156 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2771 # num instructions producing a value +system.cpu.iew.wb_consumers 3964 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.263092 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.716489 # average fanout of values written-back +system.cpu.iew.wb_rate 0.291226 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.699041 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4255 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12220 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476759 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.488594 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.274116 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9523 79.86% 79.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 968 8.12% 87.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 656 5.50% 93.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 322 2.70% 96.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 146 1.22% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.35% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11924 # Number of insts commited each cycle system.cpu.commit.count 5826 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2089 # Number of memory references committed @@ -271,49 +274,49 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 77 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21319 # The number of ROB reads -system.cpu.rob.rob_writes 19020 # The number of ROB writes -system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21891 # The number of ROB reads +system.cpu.rob.rob_writes 20916 # The number of ROB writes +system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11905 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.950281 # CPI: Total CPI of All Threads -system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9689 # number of integer regfile reads -system.cpu.int_regfile_writes 4703 # number of integer regfile writes +system.cpu.cpi 4.753724 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.753724 # CPI: Total CPI of All Threads +system.cpu.ipc 0.210361 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.210361 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10347 # number of integer regfile reads +system.cpu.int_regfile_writes 5013 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 134 # number of misc regfile reads -system.cpu.icache.replacements 15 # number of replacements -system.cpu.icache.tagsinuse 158.750706 # Cycle average of tags in use -system.cpu.icache.total_refs 1129 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.431611 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 154 # number of misc regfile reads +system.cpu.icache.replacements 17 # number of replacements +system.cpu.icache.tagsinuse 161.262110 # Cycle average of tags in use +system.cpu.icache.total_refs 1367 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.068452 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.077515 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1129 # number of ReadReq hits -system.cpu.icache.demand_hits 1129 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1129 # number of overall hits -system.cpu.icache.ReadReq_misses 402 # number of ReadReq misses -system.cpu.icache.demand_misses 402 # number of demand (read+write) misses -system.cpu.icache.overall_misses 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 14594000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 14594000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 14594000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1531 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.262573 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.262573 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.262573 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36303.482587 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36303.482587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency +system.cpu.icache.occ_blocks::0 161.262110 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.078741 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits +system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1367 # number of overall hits +system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses +system.cpu.icache.demand_misses 420 # number of demand (read+write) misses +system.cpu.icache.overall_misses 420 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15216000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15216000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15216000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1787 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1787 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1787 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.235031 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.235031 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.235031 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36228.571429 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36228.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36228.571429 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,59 +326,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 84 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 84 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 84 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11520500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11520500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11520500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11782000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11782000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11782000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.214892 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.214892 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.214892 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35016.717325 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.188025 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.188025 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.188025 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35065.476190 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35065.476190 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35065.476190 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.720291 # Cycle average of tags in use -system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.950355 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.136669 # Cycle average of tags in use +system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.838028 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022393 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1670 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits -system.cpu.dcache.demand_hits 2249 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2249 # number of overall hits -system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses -system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4624500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 11828500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 16453000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16453000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 92.136669 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022494 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1813 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits +system.cpu.dcache.demand_hits 2391 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2391 # number of overall hits +system.cpu.dcache.ReadReq_misses 135 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses +system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4832000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11507500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 16339500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16339500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1948 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2723 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.071190 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.174073 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.174073 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 36128.906250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 34186.416185 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34710.970464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency +system.cpu.dcache.demand_accesses 2873 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2873 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.069302 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.167769 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.167769 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35792.592593 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33162.824207 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33899.377593 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33899.377593 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,63 +388,63 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 340 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1846500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5081000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5081000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1836500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5108500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5108500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.050056 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.046715 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.051781 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.051781 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36205.882353 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.049426 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.049426 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36009.803922 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35975.352113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35975.352113 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 218.141494 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.568003 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006657 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 221.568003 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006762 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses 424 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 467 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1769000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16045000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16045000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 475 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 475 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 14561000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1761000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16322000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16322000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 427 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.992974 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34686.274510 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34357.601713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.993724 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.993724 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34529.411765 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34362.105263 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34362.105263 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,24 +456,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12950000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14556000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14556000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 13198500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1599500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14798000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14798000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.807692 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.537736 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31362.745098 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31153.684211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31153.684211 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini index 228222f47..a3775a1dd 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 7f3c6560c..e45cd058f 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 34160904. This will break if not /dev/zero. -For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index cc20667bc..3b8650bce 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -1,15 +1,11 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 13:26:57 -M5 started Apr 21 2011 13:27:10 -M5 executing on maize -command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing +gem5 compiled Jul 8 2011 15:06:16 +gem5 started Jul 8 2011 15:22:37 +gem5 executing on u200439-lin.austin.arm.com +command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11695000 because target called exit() +Exiting @ tick 11010500 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 082e541b8..d012d707f 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,480 +1,481 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 98738 # Simulator instruction rate (inst/s) -host_mem_usage 204672 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 198408181 # Simulator tick rate (ticks/s) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11010500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 36368 # Simulator instruction rate (inst/s) +host_tick_rate 69032646 # Simulator tick rate (ticks/s) +host_mem_usage 241332 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11695000 # Number of ticks simulated +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.numCycles 22022 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 2367 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1975 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 402 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1913 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 679 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1865 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 388 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1734 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2075 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 187 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 240 # The number of times a branch was mispredicted -system.cpu.commit.branches 1038 # Number of branches committed -system.cpu.commit.bw_lim_events 42 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6529 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13348 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2367 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 869 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2278 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1276 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 941 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1754 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 10610 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.258058 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.653017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8332 78.53% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 151 1.42% 79.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 185 1.74% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 141 1.33% 83.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 226 2.13% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 137 1.29% 86.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 283 2.67% 89.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 123 1.16% 90.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1032 9.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 10610 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.107483 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.606121 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6699 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1011 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2107 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 711 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 304 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 152 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11818 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 428 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 711 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6902 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 350 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1977 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 278 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11283 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 220 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9842 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18439 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18368 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 71 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 4835 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 566 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1897 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1627 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 44 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8750 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4202 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3778 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 10610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.824694 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535023 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7338 69.16% 69.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1037 9.77% 78.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 771 7.27% 86.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 497 4.68% 90.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 457 4.31% 95.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 303 2.86% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 135 1.27% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 49 0.46% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 23 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 10610 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 6.45% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 68 43.87% 50.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 49.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5520 63.09% 63.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1751 20.01% 83.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1477 16.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 8750 # Type of FU issued +system.cpu.iq.rate 0.397330 # Inst issue rate +system.cpu.iq.fu_busy_cnt 155 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017714 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 28255 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14489 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8028 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 74 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 30 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8867 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 38 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 935 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 581 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 711 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10327 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1897 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1627 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 60 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 239 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 301 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8358 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1644 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 392 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3035 # number of memory reference insts executed +system.cpu.iew.exec_branches 1315 # Number of branches executed +system.cpu.iew.exec_stores 1391 # Number of stores executed +system.cpu.iew.exec_rate 0.379530 # Inst execution rate +system.cpu.iew.wb_sent 8174 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8058 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4233 # num instructions producing a value +system.cpu.iew.wb_consumers 6765 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.365907 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.625721 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 4533 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3301 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 10395 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.557961 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.275569 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 9899 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.585918 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.365203 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7869 75.70% 75.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1103 10.61% 86.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 649 6.24% 92.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 257 2.47% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 223 2.15% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 132 1.27% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 100 0.96% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.19% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 42 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7502 75.79% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 985 9.95% 85.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 645 6.52% 92.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 262 2.65% 94.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 188 1.90% 96.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 118 1.19% 97.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 77 0.78% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.41% 99.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 81 0.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 9899 # Number of insts commited each cycle system.cpu.commit.count 5800 # Number of instructions committed -system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. -system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.int_insts 5706 # Number of committed integer instructions. +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 2008 # Number of memory references committed system.cpu.commit.loads 962 # Number of loads committed system.cpu.commit.membars 7 # Number of memory barriers committed -system.cpu.commit.refs 2008 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branches 1038 # Number of branches committed +system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. +system.cpu.commit.int_insts 5706 # Number of committed integer instructions. +system.cpu.commit.function_calls 103 # Number of function calls committed. +system.cpu.commit.bw_lim_events 81 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 20151 # The number of ROB reads +system.cpu.rob.rob_writes 21378 # The number of ROB writes +system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11412 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.032931 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.032931 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1431 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33954.022989 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1344 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2954000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.060797 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039133 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33770.226537 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36291.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 737 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10435000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.295411 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 309 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 261 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1742000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.009615 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2477 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33810.606061 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2081 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13389000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.159871 # miss rate for demand accesses -system.cpu.dcache.demand_misses 396 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 292 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3672000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.041986 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 104 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 66.459259 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.016225 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 2477 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33810.606061 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2081 # number of overall hits -system.cpu.dcache.overall_miss_latency 13389000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.159871 # miss rate for overall accesses -system.cpu.dcache.overall_misses 396 # number of overall misses -system.cpu.dcache.overall_mshr_hits 292 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3672000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.041986 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 104 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.459259 # Cycle average of tags in use -system.cpu.dcache.total_refs 2081 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 887 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 265 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 10261 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 7524 # Number of cycles decode is idle -system.cpu.decode.RunCycles 1914 # Number of cycles decode is running -system.cpu.decode.SquashCycles 549 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 421 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2075 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1460 # Number of cache lines fetched -system.cpu.fetch.Cycles 2040 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 218 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11548 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 402 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.088709 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1460 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 866 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.493694 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 10944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.055190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.449465 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8904 81.36% 81.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 156 1.43% 82.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 186 1.70% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 150 1.37% 85.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 199 1.82% 87.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.22% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 272 2.49% 91.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 75 0.69% 92.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 869 7.94% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 10944 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 25 # number of floating regfile reads +system.cpu.cpi 3.796897 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.796897 # CPI: Total CPI of All Threads +system.cpu.ipc 0.263373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.263373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13256 # number of integer regfile reads +system.cpu.int_regfile_writes 7085 # number of integer regfile writes +system.cpu.fp_regfile_reads 28 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 1460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36594.488189 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34774.774775 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1079 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13942500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.260959 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11580000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.228082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 333 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.240240 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 169.489368 # Cycle average of tags in use +system.cpu.icache.total_refs 1334 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3.800570 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 169.489368 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.082758 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1334 # number of ReadReq hits +system.cpu.icache.demand_hits 1334 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1334 # number of overall hits +system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses +system.cpu.icache.demand_misses 420 # number of demand (read+write) misses +system.cpu.icache.overall_misses 420 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15114500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15114500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15114500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.239453 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.239453 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.239453 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35986.904762 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35986.904762 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35986.904762 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1460 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36594.488189 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency -system.cpu.icache.demand_hits 1079 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13942500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.260959 # miss rate for demand accesses -system.cpu.icache.demand_misses 381 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11580000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.228082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 333 # number of demand (read+write) MSHR misses +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 161.104076 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.078664 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1460 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36594.488189 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1079 # number of overall hits -system.cpu.icache.overall_miss_latency 13942500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.260959 # miss rate for overall accesses -system.cpu.icache.overall_misses 381 # number of overall misses -system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11580000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.228082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 333 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 351 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 351 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 333 # Sample count of references to valid blocks. +system.cpu.icache.ReadReq_mshr_miss_latency 12207500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12207500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12207500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.200114 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.200114 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.200114 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 161.104076 # Cycle average of tags in use -system.cpu.icache.total_refs 1079 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12447 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 1262 # Number of branches executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_rate 0.332008 # Inst execution rate -system.cpu.iew.exec_refs 2790 # number of memory reference insts executed -system.cpu.iew.exec_stores 1305 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 130 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1666 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 100 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1436 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9097 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1485 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 549 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 704 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 390 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 5916 # num instructions consuming a value -system.cpu.iew.wb_count 7563 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.645030 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 3816 # num instructions producing a value -system.cpu.iew.wb_rate 0.323329 # insts written-back per cycle -system.cpu.iew.wb_sent 7623 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 12407 # number of integer regfile reads -system.cpu.int_regfile_writes 6585 # number of integer regfile writes -system.cpu.ipc 0.247959 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.247959 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5116 63.51% 63.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1580 19.62% 83.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1357 16.85% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8055 # Type of FU issued -system.cpu.iq.fp_alu_accesses 31 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 59 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018870 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 7.24% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 72 47.37% 54.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69 45.39% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 8176 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 27162 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 7536 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 11998 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 9075 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8055 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 2924 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2633 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 10944 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.736020 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.423307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7700 70.36% 70.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1176 10.75% 81.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 793 7.25% 88.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 485 4.43% 92.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 365 3.34% 96.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 233 2.13% 98.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 138 1.26% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 47 0.43% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 10944 # Number of insts issued each cycle -system.cpu.iq.rate 0.344363 # Inst issue rate -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 66.389041 # Cycle average of tags in use +system.cpu.dcache.total_refs 2180 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 105 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 20.761905 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 66.389041 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.016208 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1445 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 735 # number of WriteReq hits +system.cpu.dcache.demand_hits 2180 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2180 # number of overall hits +system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu.dcache.demand_misses 401 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 401 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3011000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10558500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 13569500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 13569500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 2581 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2581 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.058632 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.297323 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.155366 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.155366 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33455.555556 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33950.160772 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33839.152120 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33839.152120 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 296 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 57 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 105 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1963500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1750500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3714000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3714000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.037134 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.040682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.040682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34447.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35371.428571 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35371.428571 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 200.598447 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.022556 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 200.598447 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006122 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 9 # number of ReadReq hits +system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 9 # number of overall hits +system.cpu.l2cache.ReadReq_misses 399 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 447 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 447 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 13714000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1678000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 15392000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 15392000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34937.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31770.833333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1677000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_accesses 456 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 456 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.977941 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1525000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 389 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34322.834646 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.981627 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13077000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.979434 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 381 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11867000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979434 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 381 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.020997 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate 0.980263 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.980263 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34370.927318 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34958.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34434.004474 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34434.004474 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 437 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34391.608392 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14754000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981693 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 429 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13392000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981693 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 429 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 191.979751 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005859 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 437 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34391.608392 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14754000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981693 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 429 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13392000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981693 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 429 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 447 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 381 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 12433500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1526000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13959500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13959500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977941 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.980263 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.980263 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.654135 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.306488 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.306488 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 191.979751 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1666 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1436 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23391 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 314 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 7703 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 16001 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 9789 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 8584 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 1797 # Number of cycles rename is running -system.cpu.rename.SquashCycles 549 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 244 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 3577 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 15946 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 337 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.skidInsts 471 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 19454 # The number of ROB reads -system.cpu.rob.rob_writes 18753 # The number of ROB writes -system.cpu.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini index 37073b2df..f7a4ddc40 100644 --- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -204,7 +205,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/arm/scratch/sysexplr/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout index ca819dade..002338518 100755 --- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 20 2011 19:27:12 -gem5 started Jun 20 2011 19:28:17 -gem5 executing on zooks +gem5 compiled Jul 9 2011 14:58:11 +gem5 started Jul 9 2011 15:02:19 +gem5 executing on nadc-0321 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 18208500 because target called exit() +Hello World!Exiting @ tick 18201500 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 50ad2ecd7..1b5682411 100644 --- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,24 +1,24 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18208500 # Number of ticks simulated +sim_ticks 18201500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40053 # Simulator instruction rate (inst/s) -host_tick_rate 136538838 # Simulator tick rate (ticks/s) -host_mem_usage 158968 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 63270 # Simulator instruction rate (inst/s) +host_tick_rate 215616708 # Simulator tick rate (ticks/s) +host_mem_usage 249768 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 36418 # number of cpu cycles simulated +system.cpu.numCycles 36404 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9732 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9720 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30132 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6286 # Number of cycles cpu stages are processed. -system.cpu.activity 17.260695 # Percentage of cycles cpu is active +system.cpu.idleCycles 30130 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6274 # Number of cycles cpu stages are processed. +system.cpu.activity 17.234370 # Percentage of cycles cpu is active system.cpu.comLoads 716 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1116 # Number of Branches instructions committed @@ -29,79 +29,79 @@ system.cpu.comFloats 0 # Nu system.cpu.committedInsts 5340 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5340 # Number of Instructions Simulated (Total) -system.cpu.cpi 6.819850 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.819850 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146631 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146687 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.146631 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1667 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1128 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 904 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1481 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 657 # Number of BTB hits +system.cpu.ipc_total 0.146687 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1662 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1123 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1455 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 643 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 44.361918 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 724 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 943 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5610 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 44.192440 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 710 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 952 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9610 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9612 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1749 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1747 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 1473 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 407 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 434 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 841 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 275 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 75.358423 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3970 # Number of Instructions Executed. +system.cpu.execution_unit.predictedTakenIncorrect 394 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 442 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3977 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 31732 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4686 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.867263 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33196 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3222 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.847273 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33369 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3049 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.372234 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35435 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 31738 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4666 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.817273 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33193 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3211 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.820459 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33357 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3047 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 8.369959 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35421 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.699215 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33245 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3173 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.712724 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.700253 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 33233 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3171 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.710581 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.664121 # Cycle average of tags in use +system.cpu.icache.tagsinuse 136.669321 # Cycle average of tags in use system.cpu.icache.total_refs 791 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 136.664121 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.066731 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 136.669321 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.066733 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits 791 # number of ReadReq hits system.cpu.icache.demand_hits 791 # number of demand (read+write) hits system.cpu.icache.overall_hits 791 # number of overall hits system.cpu.icache.ReadReq_misses 347 # number of ReadReq misses system.cpu.icache.demand_misses 347 # number of demand (read+write) misses system.cpu.icache.overall_misses 347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19112000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19112000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19112000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency 19110500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19110500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19110500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses 1138 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses 1138 # number of demand (read+write) accesses system.cpu.icache.overall_accesses 1138 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.304921 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.304921 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.304921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55077.809798 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55077.809798 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55077.809798 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55073.487032 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55073.487032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55073.487032 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -118,28 +118,28 @@ system.cpu.icache.ReadReq_mshr_misses 291 # nu system.cpu.icache.demand_mshr_misses 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15471500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15470000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15470000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15470000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.255712 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.255712 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.255712 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53166.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53166.666667 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53161.512027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.862842 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 82.862842 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020230 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 82.859932 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.020229 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 657 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 392 # number of WriteReq hits system.cpu.dcache.demand_hits 1049 # number of demand (read+write) hits @@ -200,12 +200,12 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 162.289874 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 162.289874 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 162.297266 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.004953 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits @@ -214,10 +214,10 @@ system.cpu.l2cache.ReadReq_misses 342 # nu system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 17920000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 17918500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 22150500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 22150500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 22149000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 22149000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 345 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 426 # number of demand (read+write) accesses @@ -226,10 +226,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.991304 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.992958 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52397.660819 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52393.274854 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52365.248227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52365.248227 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52361.702128 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52361.702128 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini index cd8df9d09..7ab760d62 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 5486afb8d..e361952bb 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 8 2011 15:23:04 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 11369000 because target called exit() +Exiting @ tick 11102000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index aabbd6e7a..a1f123e22 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,249 +1,251 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11369000 # Number of ticks simulated +sim_ticks 11102000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90859 # Simulator instruction rate (inst/s) -host_tick_rate 105280911 # Simulator tick rate (ticks/s) -host_mem_usage 225572 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 58378 # Simulator instruction rate (inst/s) +host_tick_rate 66066423 # Simulator tick rate (ticks/s) +host_mem_usage 248304 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 9809 # Number of instructions simulated system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 22739 # number of cpu cycles simulated +system.cpu.numCycles 22205 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2757 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2757 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2530 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 929 # Number of BTB hits +system.cpu.BPredUnit.lookups 3070 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3070 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2745 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 1002 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1700 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12836 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2757 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3597 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 5900 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14062 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3070 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3986 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2234 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1500 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1700 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 237 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13282 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.734377 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.109101 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1900 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.933552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.219407 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9775 73.60% 73.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 168 1.26% 74.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 126 0.95% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 77.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 192 1.45% 78.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 168 1.26% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 259 1.95% 82.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 168 1.26% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2200 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9243 70.43% 70.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 169 1.29% 71.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.34% 73.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 241 1.84% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 234 1.78% 76.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 195 1.49% 78.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 280 2.13% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.07% 81.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2444 18.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13282 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121245 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.564493 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7076 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1369 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3285 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1475 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 22079 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1475 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7317 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 565 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 440 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3105 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 380 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 21002 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 52 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 248 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 19737 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 44285 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 44269 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.138257 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.633281 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6251 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1454 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3582 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 112 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1724 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24194 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1724 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6540 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 523 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 524 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3382 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 430 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22801 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 271 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21341 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 47863 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 47847 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10369 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1483 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2081 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1618 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 18991 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 16049 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8636 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10887 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13282 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.208327 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.917321 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 11973 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1611 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2253 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1786 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 20643 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17013 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10307 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13151 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.296426 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.004622 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8198 61.72% 61.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1295 9.75% 71.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 980 7.38% 78.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 727 5.47% 84.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 779 5.87% 90.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 582 4.38% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 507 3.82% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 167 1.26% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8026 61.16% 61.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1107 8.44% 69.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1007 7.67% 77.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 730 5.56% 82.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 676 5.15% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 728 5.55% 93.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 620 4.72% 98.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 194 1.48% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 35 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13282 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13123 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 101 68.71% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27 18.37% 87.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 12.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 95 66.90% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24 16.90% 83.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 16.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 12887 80.30% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1771 11.03% 91.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1387 8.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13681 80.41% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1854 10.90% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1474 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16049 # Type of FU issued -system.cpu.iq.rate 0.705792 # Inst issue rate -system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009159 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 45572 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 27668 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15040 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 17013 # Type of FU issued +system.cpu.iq.rate 0.766179 # Inst issue rate +system.cpu.iq.fu_busy_cnt 142 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 47348 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30994 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15803 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 16187 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 17147 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1025 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1197 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 684 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 852 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1475 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 19024 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 215 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2081 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1618 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1724 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20678 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 15 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2253 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1786 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 498 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 15360 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1657 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 689 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16148 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1748 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 865 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 2952 # number of memory reference insts executed -system.cpu.iew.exec_branches 1546 # Number of branches executed -system.cpu.iew.exec_stores 1295 # Number of stores executed -system.cpu.iew.exec_rate 0.675491 # Inst execution rate -system.cpu.iew.wb_sent 15177 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15044 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9950 # num instructions producing a value -system.cpu.iew.wb_consumers 14675 # num instructions consuming a value +system.cpu.iew.exec_refs 3114 # number of memory reference insts executed +system.cpu.iew.exec_branches 1606 # Number of branches executed +system.cpu.iew.exec_stores 1366 # Number of stores executed +system.cpu.iew.exec_rate 0.727224 # Inst execution rate +system.cpu.iew.wb_sent 15964 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15807 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10570 # num instructions producing a value +system.cpu.iew.wb_consumers 15744 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.661595 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.678024 # average fanout of values written-back +system.cpu.iew.wb_rate 0.711867 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.671367 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9214 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10868 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11807 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.830778 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.597683 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 497 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11399 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.860514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.681683 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8187 69.34% 69.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1225 10.38% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 582 4.93% 84.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 958 8.11% 92.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 396 3.35% 96.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 132 1.12% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 128 1.08% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 58 0.49% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 141 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7958 69.81% 69.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1091 9.57% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 577 5.06% 84.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 889 7.80% 92.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 346 3.04% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 149 1.31% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 139 1.22% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.58% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 184 1.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11807 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11399 # Number of insts commited each cycle system.cpu.commit.count 9809 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1990 # Number of memory references committed @@ -253,48 +255,48 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 141 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 30689 # The number of ROB reads -system.cpu.rob.rob_writes 39546 # The number of ROB writes -system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9457 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 31892 # The number of ROB reads +system.cpu.rob.rob_writes 43113 # The number of ROB writes +system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9082 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.318177 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.318177 # CPI: Total CPI of All Threads -system.cpu.ipc 0.431373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.431373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 22959 # number of integer regfile reads -system.cpu.int_regfile_writes 13989 # number of integer regfile writes +system.cpu.cpi 2.263737 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.263737 # CPI: Total CPI of All Threads +system.cpu.ipc 0.441747 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.441747 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23720 # number of integer regfile reads +system.cpu.int_regfile_writes 14686 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 6812 # number of misc regfile reads +system.cpu.misc_regfile_reads 7234 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.881621 # Cycle average of tags in use -system.cpu.icache.total_refs 1339 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.538983 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 145.121253 # Cycle average of tags in use +system.cpu.icache.total_refs 1536 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.154362 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 144.881621 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.070743 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1339 # number of ReadReq hits -system.cpu.icache.demand_hits 1339 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1339 # number of overall hits -system.cpu.icache.ReadReq_misses 361 # number of ReadReq misses -system.cpu.icache.demand_misses 361 # number of demand (read+write) misses -system.cpu.icache.overall_misses 361 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 13205500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 13205500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 13205500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1700 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1700 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.212353 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.212353 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.212353 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36580.332410 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36580.332410 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36580.332410 # average overall miss latency +system.cpu.icache.occ_blocks::0 145.121253 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.070860 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1536 # number of ReadReq hits +system.cpu.icache.demand_hits 1536 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1536 # number of overall hits +system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses +system.cpu.icache.demand_misses 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 13311000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 13311000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 13311000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1900 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.191579 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.191579 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.191579 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36568.681319 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36568.681319 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36568.681319 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,56 +309,56 @@ system.cpu.icache.writebacks 0 # nu system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses 298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 298 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10355500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10355500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10355500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10465000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10465000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10465000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.173529 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.173529 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.173529 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35103.389831 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35103.389831 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35103.389831 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.156842 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.156842 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.156842 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35117.449664 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35117.449664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35117.449664 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.872025 # Cycle average of tags in use -system.cpu.dcache.total_refs 2039 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 14.258741 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.500276 # Cycle average of tags in use +system.cpu.dcache.total_refs 2118 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 14.606897 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 85.872025 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020965 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1418 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits -system.cpu.dcache.demand_hits 2039 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2039 # number of overall hits +system.cpu.dcache.occ_blocks::0 85.500276 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.020874 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1500 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 618 # number of WriteReq hits +system.cpu.dcache.demand_hits 2118 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2118 # number of overall hits system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses -system.cpu.dcache.demand_misses 426 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 426 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10668500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 14567500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 14567500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses 316 # number of WriteReq misses +system.cpu.dcache.demand_misses 429 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 429 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3938500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10704500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 14643000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 14643000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2465 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2465 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.073808 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.172819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.172819 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34196.009390 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34196.009390 # average overall miss latency +system.cpu.dcache.demand_accesses 2547 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2547 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.070056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.338330 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.168433 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.168433 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 34853.982301 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33875 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 34132.867133 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 34132.867133 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,63 +368,63 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 282 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 239 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 69 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2354500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2772000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5126500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5126500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2421500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2762000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5183500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5183500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.043762 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.042777 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.058418 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.058418 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.057322 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.057322 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35094.202899 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35870.129870 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.189347 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.583785 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005495 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 178.189347 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005438 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 178.583785 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005450 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses 365 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12329000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2664000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 14993000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 14993000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 442 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 442 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 12493000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2653500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 15146500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 15146500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 367 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.994550 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34247.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34597.402597 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34308.924485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34308.924485 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.995495 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.995495 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34227.397260 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34461.038961 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34268.099548 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34268.099548 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,24 +436,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 365 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 442 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13592000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13592000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2409500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13737500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994550 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.995495 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.995495 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.616438 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31292.207792 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 2e792694f..62bbba21e 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -517,7 +518,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 5cdcc3460..f562f208e 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,18 +1,14 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:29:56 -M5 started Apr 21 2011 13:15:44 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:21:20 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 14058000 because target called exit() +Exiting @ tick 13218000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index fe96eb65d..ba1ddb358 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,791 +1,790 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 78127 # Simulator instruction rate (inst/s) -host_mem_usage 207556 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -host_tick_rate 85893759 # Simulator tick rate (ticks/s) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13218000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 47211 # Simulator instruction rate (inst/s) +host_tick_rate 48851159 # Simulator tick rate (ticks/s) +host_mem_usage 244284 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14058000 # Number of ticks simulated +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 3714 # DTB read hits +system.cpu.dtb.read_misses 89 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 3803 # DTB read accesses +system.cpu.dtb.write_hits 1992 # DTB write hits +system.cpu.dtb.write_misses 59 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 2051 # DTB write accesses +system.cpu.dtb.data_hits 5706 # DTB hits +system.cpu.dtb.data_misses 148 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 5854 # DTB accesses +system.cpu.itb.fetch_hits 4085 # ITB hits +system.cpu.itb.fetch_misses 56 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 4141 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload0.num_syscalls 17 # Number of system calls +system.cpu.workload1.num_syscalls 17 # Number of system calls +system.cpu.numCycles 26437 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 5187 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2958 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1247 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 3609 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 1000 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 845 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 4555 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1551 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 3023 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5318 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 660 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 1135 # The number of times a branch was mispredicted -system.cpu.commit.branches::0 1051 # Number of branches committed -system.cpu.commit.branches::1 1051 # Number of branches committed -system.cpu.commit.branches::total 2102 # Number of branches committed -system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits -system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits -system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits +system.cpu.BPredUnit.usedRAS 740 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 156 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1108 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 29051 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5187 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1740 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5000 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1319 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4085 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 640 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 20361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.426796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.797497 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 15361 75.44% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 451 2.22% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 362 1.78% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 388 1.91% 81.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 391 1.92% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 325 1.60% 84.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 409 2.01% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 323 1.59% 88.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2351 11.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 20361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.196202 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.098877 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 28250 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5561 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4330 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 453 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 485 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 311 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 25978 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 552 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 28803 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2995 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 772 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4141 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1883 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24541 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 1746 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 18357 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 30569 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 30535 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9191 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 52 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 40 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2306 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1192 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2327 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1184 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 22275 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 19420 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8699 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4701 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 20361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.953784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.476295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12146 59.65% 59.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2930 14.39% 74.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2237 10.99% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1382 6.79% 91.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 875 4.30% 96.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 479 2.35% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 226 1.11% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 69 0.34% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 20361 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.44% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 103 57.22% 61.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69 38.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6596 67.90% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2046 21.06% 89.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1068 10.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 9715 # Type of FU issued +system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6577 67.77% 67.79% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2049 21.11% 88.93% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1074 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::total 9705 # Type of FU issued +system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 13173 67.83% 67.85% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 67.86% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4095 21.09% 88.97% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2142 11.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type::total 19420 # Type of FU issued +system.cpu.iq.rate 0.734577 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 90 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 90 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 180 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004634 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004634 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.009269 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 59410 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31025 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17735 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 19574 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1121 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 327 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread1.squashedLoads 1142 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 319 # Number of stores squashed +system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1204 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 22464 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 427 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4633 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2376 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 214 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 883 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1097 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 18405 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 1891 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 1918 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 3809 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1015 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp::0 0 # number of swp insts executed +system.cpu.iew.exec_swp::1 0 # number of swp insts executed +system.cpu.iew.exec_swp::total 0 # number of swp insts executed +system.cpu.iew.exec_nop::0 75 # number of nop insts executed +system.cpu.iew.exec_nop::1 65 # number of nop insts executed +system.cpu.iew.exec_nop::total 140 # number of nop insts executed +system.cpu.iew.exec_refs::0 2925 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 2953 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 5878 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1521 # Number of branches executed +system.cpu.iew.exec_branches::1 1527 # Number of branches executed +system.cpu.iew.exec_branches::total 3048 # Number of branches executed +system.cpu.iew.exec_stores::0 1034 # Number of stores executed +system.cpu.iew.exec_stores::1 1035 # Number of stores executed +system.cpu.iew.exec_stores::total 2069 # Number of stores executed +system.cpu.iew.exec_rate 0.696183 # Inst execution rate +system.cpu.iew.wb_sent::0 9003 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9003 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 18006 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 8892 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 8863 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 17755 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4543 # num instructions producing a value +system.cpu.iew.wb_producers::1 4543 # num instructions producing a value +system.cpu.iew.wb_producers::total 9086 # num instructions producing a value +system.cpu.iew.wb_consumers::0 5945 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 5949 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 11894 # num instructions consuming a value +system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate::0 0.336347 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.335250 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.671597 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.764172 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.763658 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 1.527829 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9583 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 10106 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 22336 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.573379 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.337408 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 951 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20336 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.629770 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.428976 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16656 74.57% 74.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2886 12.92% 87.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1149 5.14% 92.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 571 2.56% 95.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 362 1.62% 96.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 238 1.07% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 197 0.88% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 126 0.56% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 151 0.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14766 72.61% 72.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2895 14.24% 86.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1050 5.16% 92.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 514 2.53% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 350 1.72% 96.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 235 1.16% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 212 1.04% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 89 0.44% 98.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 225 1.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22336 # Number of insts commited each cycle -system.cpu.commit.count::0 6404 # Number of instructions committed -system.cpu.commit.count::1 6403 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 20336 # Number of insts commited each cycle +system.cpu.commit.count::0 6403 # Number of instructions committed +system.cpu.commit.count::1 6404 # Number of instructions committed system.cpu.commit.count::total 12807 # Number of instructions committed -system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. -system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. -system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. -system.cpu.commit.function_calls::0 127 # Number of function calls committed. -system.cpu.commit.function_calls::1 127 # Number of function calls committed. -system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions. -system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions. -system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions. +system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed +system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed +system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed +system.cpu.commit.refs::0 2050 # Number of memory references committed +system.cpu.commit.refs::1 2050 # Number of memory references committed +system.cpu.commit.refs::total 4100 # Number of memory references committed system.cpu.commit.loads::0 1185 # Number of loads committed system.cpu.commit.loads::1 1185 # Number of loads committed system.cpu.commit.loads::total 2370 # Number of loads committed system.cpu.commit.membars::0 0 # Number of memory barriers committed system.cpu.commit.membars::1 0 # Number of memory barriers committed system.cpu.commit.membars::total 0 # Number of memory barriers committed -system.cpu.commit.refs::0 2050 # Number of memory references committed -system.cpu.commit.refs::1 2050 # Number of memory references committed -system.cpu.commit.refs::total 4100 # Number of memory references committed -system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed -system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed -system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed -system.cpu.committedInsts::0 6387 # Number of Instructions Simulated -system.cpu.committedInsts::1 6386 # Number of Instructions Simulated +system.cpu.commit.branches::0 1051 # Number of branches committed +system.cpu.commit.branches::1 1051 # Number of branches committed +system.cpu.commit.branches::total 2102 # Number of branches committed +system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. +system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. +system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. +system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions. +system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions. +system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions. +system.cpu.commit.function_calls::0 127 # Number of function calls committed. +system.cpu.commit.function_calls::1 127 # Number of function calls committed. +system.cpu.commit.function_calls::total 254 # Number of function calls committed. +system.cpu.commit.bw_lim_events 225 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits +system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits +system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 101662 # The number of ROB reads +system.cpu.rob.rob_writes 46661 # The number of ROB writes +system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6076 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts::0 6386 # Number of Instructions Simulated +system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.402223 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.402913 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.201284 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3727 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 36433.554817 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36433.554817 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36821.782178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3426 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::0 10966500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10966500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.080762 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 301 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::0 99 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 99 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::0 7438000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7438000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.054199 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054199 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::0 202 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 32498.595506 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32498.595506 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 35993.150685 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1018 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::0 23139000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23139000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 712 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::0 566 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::0 5255000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5255000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.770115 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5457 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 33667.818361 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33667.818361 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36474.137931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 4444 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::0 34105500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34105500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.185633 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1013 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::0 665 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 665 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::0 12693000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12693000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.063771 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063771 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::0 348 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 220.347711 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.053796 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 5457 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 33667.818361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33667.818361 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36474.137931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4444 # number of overall hits -system.cpu.dcache.overall_miss_latency::0 34105500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34105500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.185633 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1013 # number of overall misses -system.cpu.dcache.overall_mshr_hits::0 665 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 665 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::0 12693000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12693000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.063771 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063771 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::0 348 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements::0 0 # number of replacements -system.cpu.dcache.replacements::1 0 # number of replacements -system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 220.347711 # Cycle average of tags in use -system.cpu.dcache.total_refs 4444 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::0 0 # number of writebacks -system.cpu.dcache.writebacks::1 0 # number of writebacks -system.cpu.dcache.writebacks::total 0 # number of writebacks -system.cpu.decode.BlockedCycles 4700 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 432 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 582 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 26467 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 33032 # Number of cycles decode is idle -system.cpu.decode.RunCycles 4744 # Number of cycles decode is running -system.cpu.decode.SquashCycles 1971 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 600 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 114 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 6011 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 5860 # DTB hits -system.cpu.dtb.data_misses 151 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 3932 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3840 # DTB read hits -system.cpu.dtb.read_misses 92 # DTB read misses -system.cpu.dtb.write_accesses 2079 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2020 # DTB write hits -system.cpu.dtb.write_misses 59 # DTB write misses -system.cpu.fetch.Branches 5318 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3965 # Number of cache lines fetched -system.cpu.fetch.Cycles 5044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 29681 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1624 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.189138 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3965 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1505 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.055625 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 22371 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.326762 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.728526 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17327 77.45% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 412 1.84% 79.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 325 1.45% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 422 1.89% 82.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 410 1.83% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 313 1.40% 85.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 439 1.96% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 270 1.21% 89.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2453 10.97% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 22371 # Number of instructions fetched each cycle (Total) +system.cpu.cpi::0 4.139837 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.139189 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.069757 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.241555 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.241593 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.483149 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23349 # number of integer regfile reads +system.cpu.int_regfile_writes 13299 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 3965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 36242.350061 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36242.350061 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35491.100324 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3148 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::0 29610000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29610000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206053 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 817 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits::0 199 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency::0 21933500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21933500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.155864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::0 618 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 618 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.093851 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.misc_regfile_reads 2 # number of misc regfile reads +system.cpu.misc_regfile_writes 2 # number of misc regfile writes +system.cpu.icache.replacements::0 6 # number of replacements +system.cpu.icache.replacements::1 0 # number of replacements +system.cpu.icache.replacements::total 6 # number of replacements +system.cpu.icache.tagsinuse 314.403866 # Cycle average of tags in use +system.cpu.icache.total_refs 3230 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.159744 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 314.403866 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.153518 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 3230 # number of ReadReq hits +system.cpu.icache.demand_hits 3230 # number of demand (read+write) hits +system.cpu.icache.overall_hits 3230 # number of overall hits +system.cpu.icache.ReadReq_misses 855 # number of ReadReq misses +system.cpu.icache.demand_misses 855 # number of demand (read+write) misses +system.cpu.icache.overall_misses 855 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::0 30717000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30717000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::0 30717000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30717000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::0 30717000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30717000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4085 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4085 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4085 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.209302 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.209302 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.209302 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::0 35926.315789 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35926.315789 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::0 35926.315789 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35926.315789 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 35926.315789 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35926.315789 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3965 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 36242.350061 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36242.350061 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::0 35491.100324 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 3148 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::0 29610000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29610000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206053 # miss rate for demand accesses -system.cpu.icache.demand_misses 817 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits::0 199 # number of demand (read+write) MSHR hits +system.cpu.icache.writebacks::0 0 # number of writebacks +system.cpu.icache.writebacks::1 0 # number of writebacks +system.cpu.icache.writebacks::total 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::0 229 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::0 229 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency::0 21933500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::0 229 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::0 626 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::0 626 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::0 626 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::0 22275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::0 22275500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21933500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.155864 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency::total 22275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::0 22275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.153244 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153244 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.153244 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.155864 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::0 618 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 618 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 318.780075 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.155654 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 3965 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 36242.350061 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36242.350061 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::0 35491.100324 # average overall mshr miss latency +system.cpu.icache.demand_mshr_miss_rate::total 0.153244 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.153244 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153244 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35583.865815 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35583.865815 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35583.865815 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3148 # number of overall hits -system.cpu.icache.overall_miss_latency::0 29610000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29610000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206053 # miss rate for overall accesses -system.cpu.icache.overall_misses 817 # number of overall misses -system.cpu.icache.overall_mshr_hits::0 199 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 199 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency::0 21933500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21933500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.155864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.155864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::0 618 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 618 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements::0 6 # number of replacements -system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.sampled_refs 618 # Sample count of references to valid blocks. +system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 318.780075 # Cycle average of tags in use -system.cpu.icache.total_refs 3148 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks::0 0 # number of writebacks -system.cpu.icache.writebacks::1 0 # number of writebacks -system.cpu.icache.writebacks::total 0 # number of writebacks -system.cpu.idleCycles 5746 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 1313 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches::0 1549 # Number of branches executed -system.cpu.iew.exec_branches::1 1545 # Number of branches executed -system.cpu.iew.exec_branches::total 3094 # Number of branches executed -system.cpu.iew.exec_nop::0 67 # number of nop insts executed -system.cpu.iew.exec_nop::1 70 # number of nop insts executed -system.cpu.iew.exec_nop::total 137 # number of nop insts executed -system.cpu.iew.exec_rate 0.665505 # Inst execution rate -system.cpu.iew.exec_refs::0 3042 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 2988 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6030 # number of memory reference insts executed -system.cpu.iew.exec_stores::0 1059 # Number of stores executed -system.cpu.iew.exec_stores::1 1037 # Number of stores executed -system.cpu.iew.exec_stores::total 2096 # Number of stores executed -system.cpu.iew.exec_swp::0 0 # number of swp insts executed -system.cpu.iew.exec_swp::1 0 # number of swp insts executed -system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 965 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4691 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 813 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2450 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 22978 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts::0 1983 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 1951 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 3934 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1099 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 18712 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 1178 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 386 # Number of stores squashed -system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.squashedLoads 1143 # Number of loads squashed -system.cpu.iew.lsq.thread1.squashedStores 334 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1056 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 257 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers::0 5857 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 5876 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 11733 # num instructions consuming a value -system.cpu.iew.wb_count::0 9007 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9010 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18017 # cumulative count of insts written-back -system.cpu.iew.wb_fanout::0 0.769336 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.769401 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 1.538737 # average fanout of values written-back -system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers::0 4506 # num instructions producing a value -system.cpu.iew.wb_producers::1 4521 # num instructions producing a value -system.cpu.iew.wb_producers::total 9027 # num instructions producing a value -system.cpu.iew.wb_rate::0 0.320340 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.320447 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.640787 # insts written-back per cycle -system.cpu.iew.wb_sent::0 9150 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9113 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18263 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 23704 # number of integer regfile reads -system.cpu.int_regfile_writes 13551 # number of integer regfile writes -system.cpu.ipc::0 0.227158 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.227122 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.454280 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6672 67.35% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2121 21.41% 88.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1109 11.19% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9907 # Type of FU issued -system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6738 68.03% 68.05% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 68.06% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2064 20.84% 88.92% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1097 11.08% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 9904 # Type of FU issued -system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13410 67.69% 67.71% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 67.72% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 67.72% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4185 21.12% 88.86% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2206 11.14% 100.00% # Type of FU issued -system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 19811 # Type of FU issued -system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt::0 76 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 88 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 164 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.003836 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004442 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008278 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 6.10% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 90 54.88% 60.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 39.02% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 19949 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 62191 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 17997 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 31607 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 22795 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 19811 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8766 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4974 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 22371 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.885566 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.449509 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13920 62.22% 62.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3143 14.05% 76.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2295 10.26% 86.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1308 5.85% 92.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 818 3.66% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 557 2.49% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 231 1.03% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 81 0.36% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 22371 # Number of insts issued each cycle -system.cpu.iq.rate 0.704592 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4020 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 3965 # ITB hits -system.cpu.itb.fetch_misses 55 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements::0 0 # number of replacements +system.cpu.dcache.replacements::1 0 # number of replacements +system.cpu.dcache.replacements::total 0 # number of replacements +system.cpu.dcache.tagsinuse 216.203520 # Cycle average of tags in use +system.cpu.dcache.total_refs 4314 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.432277 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 216.203520 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.052784 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 3294 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 1020 # number of WriteReq hits +system.cpu.dcache.demand_hits 4314 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 4314 # number of overall hits +system.cpu.dcache.ReadReq_misses 306 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 710 # number of WriteReq misses +system.cpu.dcache.demand_misses 1016 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1016 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::0 11205000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11205000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::0 24076500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24076500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::0 35281500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35281500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::0 35281500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35281500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 3600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 5330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 5330 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.085000 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.410405 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.190619 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.190619 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::0 36617.647059 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36617.647059 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33910.563380 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33910.563380 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 34725.885827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34725.885827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 34725.885827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34725.885827 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::0 0 # number of writebacks +system.cpu.dcache.writebacks::1 0 # number of writebacks +system.cpu.dcache.writebacks::total 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::0 105 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::0 564 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::0 669 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 669 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::0 669 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 669 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::0 201 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::0 347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::0 347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7390000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7390000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::0 5293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::0 12683000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12683000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::0 12683000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12683000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.055833 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055833 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.065103 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.065103 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.065103 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.065103 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36766.169154 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36253.424658 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36550.432277 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36550.432277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements::0 0 # number of replacements +system.cpu.l2cache.replacements::1 0 # number of replacements +system.cpu.l2cache.replacements::total 0 # number of replacements +system.cpu.l2cache.tagsinuse 435.485428 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 435.485428 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.013290 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses 825 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 971 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 971 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::0 28485000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28485000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::0 5065500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5065500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::0 33550500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33550500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::0 33550500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33550500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 827 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34506.849315 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34506.849315 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31441.780822 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency::0 5038000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5038000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 973 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997582 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4590500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4590500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 820 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34518.948655 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34518.948655 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31380.195599 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::0 28236500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28236500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997561 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 818 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25669000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25669000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997561 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997561 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::0 818 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 818 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002445 # Average number of references to valid blocks. +system.cpu.l2cache.demand_miss_rate 0.997945 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997945 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34527.272727 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34527.272727 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34695.205479 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34695.205479 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::0 34552.523172 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34552.523172 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::0 34552.523172 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34552.523172 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::0 34517.116183 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34517.116183 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31389.522822 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::0 33274500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33274500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997930 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 964 # number of demand (read+write) misses +system.cpu.l2cache.writebacks::0 0 # number of writebacks +system.cpu.l2cache.writebacks::1 0 # number of writebacks +system.cpu.l2cache.writebacks::total 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::0 30259500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30259500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::0 0.997930 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997930 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::0 964 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 441.662390 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.013478 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::0 34517.116183 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34517.116183 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31389.522822 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency::0 33274500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33274500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997930 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 964 # number of overall misses system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::0 30259500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30259500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::0 0.997930 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997930 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::0 964 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::0 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::0 971 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::0 971 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 964 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements::0 0 # number of replacements -system.cpu.l2cache.replacements::1 0 # number of replacements -system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.sampled_refs 818 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::0 30518500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30518500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::0 30518500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30518500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::0 0.997945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997945 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::0 0.997945 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997945 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31599.315068 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31429.969104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31429.969104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 441.662390 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::0 0 # number of writebacks -system.cpu.l2cache.writebacks::1 0 # number of writebacks -system.cpu.l2cache.writebacks::total 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2363 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1251 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2328 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1199 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 2 # number of misc regfile reads -system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.numCycles 28117 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 2820 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 33480 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 1251 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 31536 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 25241 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 18899 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 4323 # Number of cycles rename is running -system.cpu.rename.SquashCycles 1971 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 1300 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 9733 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 31502 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 667 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.skidInsts 3351 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 106938 # The number of ROB reads -system.cpu.rob.rob_writes 47804 # The number of ROB writes -system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload0.num_syscalls 17 # Number of system calls -system.cpu.workload1.num_syscalls 17 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini index e8057b6e2..7ee142626 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -204,7 +205,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/arm/scratch/sysexplr/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout index 2a38cfdfa..64331370b 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 20 2011 19:27:12 -gem5 started Jun 20 2011 20:17:56 -gem5 executing on zooks +gem5 compiled Jul 9 2011 14:58:11 +gem5 started Jul 9 2011 15:02:19 +gem5 executing on nadc-0321 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25074500 because target called exit() +Exiting @ tick 25058500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 99673e355..10d7a8655 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,24 +1,24 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25074500 # Number of ticks simulated +sim_ticks 25058500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12169 # Simulator instruction rate (inst/s) -host_tick_rate 20106315 # Simulator tick rate (ticks/s) -host_mem_usage 158720 # Number of bytes of host memory used -host_seconds 1.25 # Real time elapsed on the host +host_inst_rate 66853 # Simulator instruction rate (inst/s) +host_tick_rate 110387436 # Simulator tick rate (ticks/s) +host_mem_usage 249432 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 50150 # number of cpu cycles simulated +system.cpu.numCycles 50118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 22024 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21993 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32481 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17669 # Number of cycles cpu stages are processed. -system.cpu.activity 35.232303 # Percentage of cycles cpu is active +system.cpu.idleCycles 32493 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17625 # Number of cycles cpu stages are processed. +system.cpu.activity 35.167006 # Percentage of cycles cpu is active system.cpu.comLoads 2226 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3359 # Number of Branches instructions committed @@ -29,79 +29,79 @@ system.cpu.comFloats 0 # Nu system.cpu.committedInsts 15175 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 15175 # Number of Instructions Simulated (Total) -system.cpu.cpi 3.304778 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.302669 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 3.304778 # CPI: Total CPI of All Threads -system.cpu.ipc 0.302592 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.302669 # CPI: Total CPI of All Threads +system.cpu.ipc 0.302785 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.302592 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 5200 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 3649 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 2386 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 4558 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2986 # Number of BTB hits +system.cpu.ipc_total 0.302785 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 5166 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3601 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 2377 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 4346 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2912 # Number of BTB hits system.cpu.branch_predictor.usedRAS 172 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 65.511189 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 3158 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2042 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14332 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 67.004142 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 3084 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2082 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14334 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25443 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25445 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 5213 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3843 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 1633 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 690 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 2323 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 1036 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 69.157487 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 11042 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 5192 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3845 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 1598 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 716 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 2314 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 1045 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 68.889550 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 11051 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 36479 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13671 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 27.260219 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 40783 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9367 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 18.677966 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 41319 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8831 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.609172 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47266 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 36528 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13590 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 27.116006 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40773 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9345 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 18.645995 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 41295 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8823 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.604453 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47234 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.750748 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40819 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9331 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.606181 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 5.754420 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40795 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9323 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.602099 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 165.662451 # Cycle average of tags in use -system.cpu.icache.total_refs 3061 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.645515 # Cycle average of tags in use +system.cpu.icache.total_refs 3085 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.237458 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10.317726 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 165.662451 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.080890 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 3061 # number of ReadReq hits -system.cpu.icache.demand_hits 3061 # number of demand (read+write) hits -system.cpu.icache.overall_hits 3061 # number of overall hits +system.cpu.icache.occ_blocks::0 165.645515 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.080882 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 3085 # number of ReadReq hits +system.cpu.icache.demand_hits 3085 # number of demand (read+write) hits +system.cpu.icache.overall_hits 3085 # number of overall hits system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses system.cpu.icache.demand_misses 366 # number of demand (read+write) misses system.cpu.icache.overall_misses 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 20101500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 20101500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 20101500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 3427 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 3427 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 3427 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.106799 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.106799 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.106799 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54922.131148 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54922.131148 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54922.131148 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 20100000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 20100000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 20100000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 3451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 3451 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 3451 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.106056 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.106056 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.106056 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 54918.032787 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 54918.032787 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 54918.032787 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 19500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -118,28 +118,28 @@ system.cpu.icache.ReadReq_mshr_misses 301 # nu system.cpu.icache.demand_mshr_misses 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15873500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15873500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15873500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15872000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15872000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15872000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.087832 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.087832 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.087832 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52735.880399 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52735.880399 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52735.880399 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.087221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.087221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.087221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52730.897010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52730.897010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52730.897010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.092985 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.082868 # Cycle average of tags in use system.cpu.dcache.total_refs 3316 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 97.092985 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.023704 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 97.082868 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.023702 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 2168 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 1142 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits @@ -149,10 +149,10 @@ system.cpu.dcache.ReadReq_misses 58 # nu system.cpu.dcache.WriteReq_misses 300 # number of WriteReq misses system.cpu.dcache.demand_misses 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3281500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3282500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 16398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19679500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19679500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency 19680500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19680500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) @@ -162,10 +162,10 @@ system.cpu.dcache.ReadReq_miss_rate 0.026056 # mi system.cpu.dcache.WriteReq_miss_rate 0.208044 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.097601 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.097601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56577.586207 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56594.827586 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 54660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54970.670391 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54970.670391 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 54973.463687 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54973.463687 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -184,30 +184,30 @@ system.cpu.dcache.WriteReq_mshr_misses 85 # nu system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2838000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 4545000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7382000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7382000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7383000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53528.301887 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53547.169811 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53470.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53492.753623 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53492.753623 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53500 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 196.326094 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.307447 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 196.326094 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 196.307447 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.005991 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits @@ -248,19 +248,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 85 # nu system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 14049000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 14048500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 3416000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17465000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17464500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17464500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39911.931818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39910.511364 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40188.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 39965.675057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 39965.675057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 8343b4558..9574fc9f3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/chips/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 99d6fe91b..636722350 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 10 2011 22:06:52 -gem5 started Jun 10 2011 22:07:32 -gem5 executing on zooks +gem5 compiled Jul 8 2011 15:08:13 +gem5 started Jul 8 2011 15:22:48 +gem5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 19016500 because target called exit() +Exiting @ tick 18121000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 9c30078fb..34c9dc344 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,247 +1,249 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19016500 # Number of ticks simulated +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18121000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51742 # Simulator instruction rate (inst/s) -host_tick_rate 68090181 # Simulator tick rate (ticks/s) -host_mem_usage 162768 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 13353 # Simulator instruction rate (inst/s) +host_tick_rate 16745708 # Simulator tick rate (ticks/s) +host_mem_usage 246680 # Number of bytes of host memory used +host_seconds 1.08 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 38034 # number of cpu cycles simulated +system.cpu.numCycles 36243 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 5148 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3432 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 838 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4682 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2465 # Number of BTB hits +system.cpu.BPredUnit.lookups 5652 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3765 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 848 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5024 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 337 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 167 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4256 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 23684 # Number of instructions fetch has processed -system.cpu.fetch.Branches 5148 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2802 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 937 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 4256 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 353 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 29221 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.810513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.905949 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 10750 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 25938 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5652 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8192 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2326 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6715 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 4621 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 374 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.937066 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.038861 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21526 73.67% 73.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3882 13.28% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 537 1.84% 88.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 503 1.72% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 680 2.33% 92.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 525 1.80% 94.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 239 0.82% 95.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 0.66% 96.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1137 3.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19488 70.40% 70.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4056 14.65% 85.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 538 1.94% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 473 1.71% 88.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 725 2.62% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 641 2.32% 93.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 275 0.99% 94.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 240 0.87% 95.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 4.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 29221 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.135353 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.622706 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13502 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6935 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7417 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 107 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1260 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 23270 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1260 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13958 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6236 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7103 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 421 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 21729 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 19486 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40358 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 40358 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 27680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155947 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.715669 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11171 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7401 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7541 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1378 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24386 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11668 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6686 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7269 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 454 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22625 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 20272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41976 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 41976 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5654 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 629 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 601 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2349 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3050 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1902 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6440 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 639 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 632 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2436 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3146 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2001 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 18598 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18016 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3968 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3549 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 95 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 29221 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.616543 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.185129 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 19436 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18669 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4953 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4052 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 27680 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.674458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.255150 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 20388 69.77% 69.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 4239 14.51% 84.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1899 6.50% 90.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1712 5.86% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 440 1.51% 98.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 282 0.97% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 168 0.57% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 79 0.27% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19155 69.20% 69.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3456 12.49% 81.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2226 8.04% 89.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1550 5.60% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 660 2.38% 97.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 386 1.39% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 29221 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27680 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 26 21.14% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 29 23.58% 44.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 68 55.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13295 73.80% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2920 16.21% 90.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1801 10.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13814 73.99% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2983 15.98% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1872 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18016 # Type of FU issued -system.cpu.iq.rate 0.473681 # Inst issue rate -system.cpu.iq.fu_busy_cnt 123 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006827 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 65447 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 23160 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17101 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18669 # Type of FU issued +system.cpu.iq.rate 0.515106 # Inst issue rate +system.cpu.iq.fu_busy_cnt 139 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007445 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 65238 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 25029 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17501 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18139 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18808 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 824 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 454 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 920 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 553 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1260 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20254 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 413 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3050 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1902 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispatchedInsts 21162 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3146 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2001 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 372 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 925 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17560 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2852 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 456 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 577 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 948 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17934 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2892 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 735 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1086 # number of nop insts executed -system.cpu.iew.exec_refs 4598 # number of memory reference insts executed -system.cpu.iew.exec_branches 3866 # Number of branches executed -system.cpu.iew.exec_stores 1746 # Number of stores executed -system.cpu.iew.exec_rate 0.461692 # Inst execution rate -system.cpu.iew.wb_sent 17276 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 17101 # cumulative count of insts written-back -system.cpu.iew.wb_producers 7938 # num instructions producing a value -system.cpu.iew.wb_consumers 9273 # num instructions consuming a value +system.cpu.iew.exec_nop 1111 # number of nop insts executed +system.cpu.iew.exec_refs 4666 # number of memory reference insts executed +system.cpu.iew.exec_branches 3968 # Number of branches executed +system.cpu.iew.exec_stores 1774 # Number of stores executed +system.cpu.iew.exec_rate 0.494827 # Inst execution rate +system.cpu.iew.wb_sent 17667 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 17501 # cumulative count of insts written-back +system.cpu.iew.wb_producers 8169 # num instructions producing a value +system.cpu.iew.wb_consumers 9773 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.449624 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.856034 # average fanout of values written-back +system.cpu.iew.wb_rate 0.482879 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.835874 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5063 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5911 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 838 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 27978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.542390 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.183434 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 848 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 26319 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.576580 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.276701 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20215 72.25% 72.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4492 16.06% 88.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1466 5.24% 93.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 768 2.75% 96.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 366 1.31% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 259 0.93% 98.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 283 1.01% 99.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.15% 99.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 87 0.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19114 72.62% 72.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4004 15.21% 87.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1216 4.62% 92.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 789 3.00% 95.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 371 1.41% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 322 1.22% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 345 1.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 56 0.21% 99.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 27978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 26319 # Number of insts commited each cycle system.cpu.commit.count 15175 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 3674 # Number of memory references committed @@ -251,48 +253,48 @@ system.cpu.commit.branches 3359 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12186 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 87 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 47306 # The number of ROB reads -system.cpu.rob.rob_writes 41741 # The number of ROB writes -system.cpu.timesIdled 186 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8813 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 46480 # The number of ROB reads +system.cpu.rob.rob_writes 43556 # The number of ROB writes +system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8563 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.632293 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.632293 # CPI: Total CPI of All Threads -system.cpu.ipc 0.379897 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.379897 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28130 # number of integer regfile reads -system.cpu.int_regfile_writes 15668 # number of integer regfile writes -system.cpu.misc_regfile_reads 6217 # number of misc regfile reads +system.cpu.cpi 2.508340 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.508340 # CPI: Total CPI of All Threads +system.cpu.ipc 0.398670 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.398670 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28668 # number of integer regfile reads +system.cpu.int_regfile_writes 15998 # number of integer regfile writes +system.cpu.misc_regfile_reads 6298 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 195.108308 # Cycle average of tags in use -system.cpu.icache.total_refs 3800 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 193.254298 # Cycle average of tags in use +system.cpu.icache.total_refs 4159 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.445783 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12.527108 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 195.108308 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.095268 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 3800 # number of ReadReq hits -system.cpu.icache.demand_hits 3800 # number of demand (read+write) hits -system.cpu.icache.overall_hits 3800 # number of overall hits -system.cpu.icache.ReadReq_misses 456 # number of ReadReq misses -system.cpu.icache.demand_misses 456 # number of demand (read+write) misses -system.cpu.icache.overall_misses 456 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15987000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15987000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15987000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4256 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4256 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4256 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.107143 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.107143 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.107143 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35059.210526 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35059.210526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35059.210526 # average overall miss latency +system.cpu.icache.occ_blocks::0 193.254298 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.094362 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 4159 # number of ReadReq hits +system.cpu.icache.demand_hits 4159 # number of demand (read+write) hits +system.cpu.icache.overall_hits 4159 # number of overall hits +system.cpu.icache.ReadReq_misses 462 # number of ReadReq misses +system.cpu.icache.demand_misses 462 # number of demand (read+write) misses +system.cpu.icache.overall_misses 462 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16041500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16041500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16041500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4621 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4621 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.099978 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.099978 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.099978 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34721.861472 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34721.861472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34721.861472 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,61 +304,61 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 130 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 130 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11676000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.078008 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.078008 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.078008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35168.674699 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35168.674699 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35168.674699 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.071846 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.071846 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.071846 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.568719 # Cycle average of tags in use -system.cpu.dcache.total_refs 3697 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.161362 # Cycle average of tags in use +system.cpu.dcache.total_refs 3736 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.321918 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.589041 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.568719 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.025041 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 2657 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 102.161362 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.024942 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 2696 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.demand_hits 3691 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 3691 # number of overall hits -system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses +system.cpu.dcache.demand_hits 3730 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 3730 # number of overall hits +system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses -system.cpu.dcache.demand_misses 523 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 523 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4005000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 14642500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18647500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18647500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 2772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3994500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 14649500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 18644000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 18644000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 2810 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 4214 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 4214 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.041486 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 4252 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 4252 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.040569 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.124110 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.124110 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 34826.086957 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35888.480392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35654.875717 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35654.875717 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.122766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.122766 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35716.475096 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35716.475096 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,40 +368,40 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 377 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 377 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2242500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2973500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5216000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5216000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2241500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2985000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5226500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5226500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.022727 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.022420 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.034646 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.034646 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35595.238095 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35825.301205 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35726.027397 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35726.027397 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.034337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.034337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 230.191737 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 228.417094 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 230.191737 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.007025 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 228.417094 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006971 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits @@ -407,10 +409,10 @@ system.cpu.l2cache.ReadReq_misses 393 # nu system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 476 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 13493000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2870000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16363000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16363000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 13475000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2872000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16347000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16347000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses @@ -419,10 +421,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.994937 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34578.313253 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34376.050420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34376.050420 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34287.531807 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34602.409639 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34342.436975 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34342.436975 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -439,19 +441,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 83 # nu system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12217500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14827500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14827500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12215000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2608500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14823500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14823500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31087.786260 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31445.783133 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.210084 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.210084 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.424936 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31427.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 138610412..14fd2a611 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus mem_mode=timing +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -456,7 +457,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index e4939da40..c3cdcc73a 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,33 +1,33 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 10 2011 22:06:52 -gem5 started Jun 10 2011 22:06:57 -gem5 executing on zooks +gem5 compiled Jul 8 2011 15:08:13 +gem5 started Jul 8 2011 15:22:59 +gem5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 2] Got lock [Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 Iteration 3 completed [Iteration 4, Thread 1] Got lock [Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 @@ -45,17 +45,17 @@ Iteration 4 completed Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 @@ -64,19 +64,19 @@ Iteration 7 completed [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 Iteration 9 completed +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 117354500 because target called exit() +Exiting @ tick 104204500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 0e7434ae8..80611aaa5 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,693 +1,698 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000117 # Number of seconds simulated -sim_ticks 117354500 # Number of ticks simulated +sim_seconds 0.000104 # Number of seconds simulated +sim_ticks 104204500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90067 # Simulator instruction rate (inst/s) -host_tick_rate 9199514 # Simulator tick rate (ticks/s) -host_mem_usage 171836 # Number of bytes of host memory used -host_seconds 12.76 # Real time elapsed on the host -sim_insts 1148940 # Number of instructions simulated +host_inst_rate 98850 # Simulator instruction rate (inst/s) +host_tick_rate 10137150 # Simulator tick rate (ticks/s) +host_mem_usage 260004 # Number of bytes of host memory used +host_seconds 10.28 # Real time elapsed on the host +sim_insts 1016120 # Number of instructions simulated system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 234710 # number of cpu cycles simulated +system.cpu0.numCycles 208410 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 91844 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 90062 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1094 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 91032 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 88645 # Number of BTB hits +system.cpu0.BPredUnit.lookups 80590 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 78618 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1041 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 79686 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 77242 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 397 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 414 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 5189 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 547166 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 91844 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 89042 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 180871 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1241 # Number of cycles fetch has spent squashing -system.cpu0.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.CacheLines 5189 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 438 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 216259 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.530142 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.183723 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 16537 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 478571 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 80590 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77656 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 158025 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3261 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 12770 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1227 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5521 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 190625 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.510536 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.192774 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35388 16.36% 16.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 90011 41.62% 57.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 494 0.23% 58.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 785 0.36% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 592 0.27% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 86207 39.86% 98.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 812 0.38% 99.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 223 0.10% 99.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 1747 0.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32600 17.10% 17.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78462 41.16% 58.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 548 0.29% 58.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1030 0.54% 59.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 642 0.34% 59.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 74529 39.10% 98.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 776 0.41% 98.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 250 0.13% 99.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 1788 0.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 216259 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391308 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.331243 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20008 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 13629 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 180385 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 202 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2035 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 546099 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2035 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 20667 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1184 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11729 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 179959 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 685 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 543550 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 277 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 370143 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1084537 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1084537 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 360120 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10023 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 796 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 810 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3593 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 175288 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 88379 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 85877 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 85749 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 454609 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 808 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 453072 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8037 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 6746 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 216259 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.095043 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.058701 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 190625 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.386690 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.296296 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16909 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14231 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 157125 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 299 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2061 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 476395 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2061 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17525 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1226 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12360 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 156835 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 618 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 473886 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 214 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 323802 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 945058 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 945058 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 313352 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10450 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 798 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 821 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3525 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 151968 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 76679 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 74216 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 74111 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 396475 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 848 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 394743 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8405 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 7242 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 289 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 190625 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.070783 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.085610 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33498 15.49% 15.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5606 2.59% 18.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 87868 40.63% 58.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 86822 40.15% 98.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1462 0.68% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 715 0.33% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 184 0.09% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 95 0.04% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 31655 16.61% 16.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5136 2.69% 19.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 75959 39.85% 59.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 75246 39.47% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1565 0.82% 99.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 775 0.41% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 215 0.11% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 66 0.03% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 8 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 216259 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 190625 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 33 15.71% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 75 35.71% 51.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 102 48.57% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 35 15.42% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 74 32.60% 48.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 118 51.98% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 190073 41.95% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 175045 38.64% 80.59% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 87954 19.41% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 166789 42.25% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 151686 38.43% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 76268 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 453072 # Type of FU issued -system.cpu0.iq.rate 1.930348 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 210 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000464 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1122705 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 463496 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 451578 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 394743 # Type of FU issued +system.cpu0.iq.rate 1.894069 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 227 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000575 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 980437 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405782 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 393268 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 453282 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 394970 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 85551 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 73850 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1644 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1708 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1051 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1043 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2035 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 809 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 541811 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 507 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 175288 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 88379 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 716 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2061 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 862 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 472051 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 355 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 151968 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 76679 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 747 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 486 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 773 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1259 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 452172 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 174750 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 900 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 747 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1203 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 393858 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 151382 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 885 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 86394 # number of nop insts executed -system.cpu0.iew.exec_refs 262594 # number of memory reference insts executed -system.cpu0.iew.exec_branches 89995 # Number of branches executed -system.cpu0.iew.exec_stores 87844 # Number of stores executed -system.cpu0.iew.exec_rate 1.926514 # Inst execution rate -system.cpu0.iew.wb_sent 451822 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 451578 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 267957 # num instructions producing a value -system.cpu0.iew.wb_consumers 269862 # num instructions consuming a value +system.cpu0.iew.exec_nop 74728 # number of nop insts executed +system.cpu0.iew.exec_refs 227540 # number of memory reference insts executed +system.cpu0.iew.exec_branches 78360 # Number of branches executed +system.cpu0.iew.exec_stores 76158 # Number of stores executed +system.cpu0.iew.exec_rate 1.889823 # Inst execution rate +system.cpu0.iew.wb_sent 393529 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 393268 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 233079 # num instructions producing a value +system.cpu0.iew.wb_consumers 235200 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.923983 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.992941 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.886992 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990982 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 532525 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 9290 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 462373 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 9639 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1094 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 214241 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.485635 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.121796 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1041 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 188581 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.451854 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.134496 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33798 15.78% 15.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 90322 42.16% 57.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2486 1.16% 59.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 740 0.35% 59.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 737 0.34% 59.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 85412 39.87% 99.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 444 0.21% 99.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 77 0.04% 99.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 225 0.11% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32178 17.06% 17.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 78251 41.49% 58.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2149 1.14% 59.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 733 0.39% 60.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 648 0.34% 60.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 73572 39.01% 99.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 474 0.25% 99.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 279 0.15% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 297 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 214241 # Number of insts commited each cycle -system.cpu0.commit.count 532525 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 188581 # Number of insts commited each cycle +system.cpu0.commit.count 462373 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 260972 # Number of memory references committed -system.cpu0.commit.loads 173644 # Number of loads committed +system.cpu0.commit.refs 225896 # Number of memory references committed +system.cpu0.commit.loads 150260 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 89216 # Number of branches committed +system.cpu0.commit.branches 77524 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 358450 # Number of committed integer instructions. +system.cpu0.commit.int_insts 311682 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 225 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 297 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 754670 # The number of ROB reads -system.cpu0.rob.rob_writes 1085676 # The number of ROB writes -system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18451 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 446494 # Number of Instructions Simulated -system.cpu0.committedInsts_total 446494 # Number of Instructions Simulated -system.cpu0.cpi 0.525673 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.525673 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.902322 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.902322 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 809682 # number of integer regfile reads -system.cpu0.int_regfile_writes 364308 # number of integer regfile writes +system.cpu0.rob.rob_reads 659135 # The number of ROB reads +system.cpu0.rob.rob_writes 946098 # The number of ROB writes +system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 17785 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 388034 # Number of Instructions Simulated +system.cpu0.committedInsts_total 388034 # Number of Instructions Simulated +system.cpu0.cpi 0.537092 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.537092 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.861878 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.861878 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 704687 # number of integer regfile reads +system.cpu0.int_regfile_writes 317694 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 264341 # number of misc regfile reads +system.cpu0.misc_regfile_reads 229306 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 291 # number of replacements -system.cpu0.icache.tagsinuse 245.354699 # Cycle average of tags in use -system.cpu0.icache.total_refs 4480 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 576 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.777778 # Average number of references to valid blocks. +system.cpu0.icache.replacements 294 # number of replacements +system.cpu0.icache.tagsinuse 244.310261 # Cycle average of tags in use +system.cpu0.icache.total_refs 4819 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.294320 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 245.354699 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.479208 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 4480 # number of ReadReq hits -system.cpu0.icache.demand_hits 4480 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 4480 # number of overall hits -system.cpu0.icache.ReadReq_misses 709 # number of ReadReq misses -system.cpu0.icache.demand_misses 709 # number of demand (read+write) misses -system.cpu0.icache.overall_misses 709 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 27352000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 27352000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 27352000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses 5189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses 5189 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses 5189 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.136635 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.136635 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.136635 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency 38578.279267 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency 38578.279267 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 38578.279267 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 16000 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::0 244.310261 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.477168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits 4819 # number of ReadReq hits +system.cpu0.icache.demand_hits 4819 # number of demand (read+write) hits +system.cpu0.icache.overall_hits 4819 # number of overall hits +system.cpu0.icache.ReadReq_misses 702 # number of ReadReq misses +system.cpu0.icache.demand_misses 702 # number of demand (read+write) misses +system.cpu0.icache.overall_misses 702 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 27601000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 27601000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 27601000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses 5521 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses 5521 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses 5521 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate 0.127151 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate 0.127151 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate 0.127151 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency 39317.663818 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency 39317.663818 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency 39317.663818 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 132 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 577 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 577 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 577 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 120 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 582 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 582 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 582 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 21152000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 21152000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 21152000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 21371000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 21371000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 21371000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.111197 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate 0.111197 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate 0.111197 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36658.578856 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 36658.578856 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 36658.578856 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate 0.105416 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate 0.105416 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate 0.105416 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36719.931271 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 36719.931271 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 36719.931271 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 140.104909 # Cycle average of tags in use -system.cpu0.dcache.total_refs 105362 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 139.593674 # Cycle average of tags in use +system.cpu0.dcache.total_refs 95831 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 605.528736 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 550.752874 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 141.224248 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.119339 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.275829 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.002186 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 88681 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits 86746 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits 175427 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 175427 # number of overall hits -system.cpu0.dcache.ReadReq_misses 467 # number of ReadReq misses +system.cpu0.dcache.occ_blocks::0 140.420812 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -0.827138 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.274259 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::1 -0.001616 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits 76983 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits 75054 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits 23 # number of SwapReq hits +system.cpu0.dcache.demand_hits 152037 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits 152037 # number of overall hits +system.cpu0.dcache.ReadReq_misses 495 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses 1007 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses 1007 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 13105000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 24852484 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency 437000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency 37957484 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 37957484 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 89148 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses 87286 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_misses 19 # number of SwapReq misses +system.cpu0.dcache.demand_misses 1035 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses 1035 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 13943500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 24690984 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency 375000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency 38634484 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 38634484 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses 77478 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses 75594 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 176434 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 176434 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate 0.005238 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate 0.006187 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate 0.005708 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate 0.005708 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency 28062.098501 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency 46023.118519 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency 16807.692308 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency 37693.628600 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 37693.628600 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 173500 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses 153072 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses 153072 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate 0.006389 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate 0.007143 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate 0.452381 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate 0.006762 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate 0.006762 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency 28168.686869 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency 45724.044444 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency 19736.842105 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency 37328.003865 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency 37328.003865 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6673.076923 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 284 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 365 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 649 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 649 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 183 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 175 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits 308 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 369 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 677 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 677 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 187 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 171 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses 19 # number of SwapReq MSHR misses system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 5054000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6424000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency 359000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 11478000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 11478000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency 5126500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6255000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency 318000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 11381500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 11381500 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002053 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002005 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate 0.002029 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate 0.002029 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27617.486339 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36708.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13807.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 32061.452514 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 32061.452514 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002414 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002262 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate 0.452381 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate 0.002339 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate 0.002339 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27414.438503 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36578.947368 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16736.842105 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 31791.899441 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 31791.899441 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 199395 # number of cpu cycles simulated +system.cpu1.numCycles 174065 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 54492 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 52165 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1102 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 53937 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 51730 # Number of BTB hits +system.cpu1.BPredUnit.lookups 53680 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 51050 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1082 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 49680 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 47696 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 504 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 674 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 21267 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 303560 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 54492 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 52234 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 111140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 1177 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.CacheLines 21267 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 240 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 196288 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.546503 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.023941 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 25860 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 302062 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 53680 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 48370 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 105407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3162 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 31070 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 6439 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 670 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 17358 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 181 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 171455 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.761757 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.155300 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 85148 43.38% 43.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 57550 29.32% 72.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7358 3.75% 76.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2678 1.36% 77.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1913 0.97% 78.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 37446 19.08% 97.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2461 1.25% 99.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 260 0.13% 99.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1474 0.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66048 38.52% 38.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 53266 31.07% 69.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5206 3.04% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3414 1.99% 74.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 592 0.35% 74.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 38163 22.26% 97.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1383 0.81% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 403 0.24% 98.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 2980 1.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 196288 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.273287 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.522405 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 56178 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 20903 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 104877 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 5862 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1747 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 302339 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1747 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 56804 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 7350 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12853 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 110244 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 569 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 300619 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 45 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 206640 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 572225 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 572225 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 198555 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 8085 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 945 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1003 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2692 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 86261 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 40322 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 42289 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 35840 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 247735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7474 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 252580 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 6388 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5920 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 555 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 196288 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.286783 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.284176 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 171455 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.308391 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.735340 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 30212 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 28102 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 100316 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4382 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2004 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 299336 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2004 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 30858 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 13502 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13779 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 96392 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 8481 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 297385 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 208391 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 574206 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 574206 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 198747 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 9644 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1073 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1204 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 11164 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 85765 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 40966 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 40880 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 36423 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 247992 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5619 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 250090 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 8378 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 7678 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 171455 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.458633 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.309488 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 81418 41.48% 41.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 28257 14.40% 55.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 42150 21.47% 77.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 39998 20.38% 97.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2642 1.35% 99.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1578 0.80% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 154 0.08% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 63066 36.78% 36.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 20362 11.88% 48.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 40913 23.86% 72.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 42366 24.71% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3338 1.95% 99.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1156 0.67% 99.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 160 0.09% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 40 0.02% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 196288 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 171455 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 11 5.79% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 48 25.26% 31.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 131 68.95% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 12 4.58% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 60 22.90% 27.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 190 72.52% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 120684 47.78% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 91955 36.41% 84.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 39941 15.81% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 120097 48.02% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 89434 35.76% 83.78% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 40559 16.22% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 252580 # Type of FU issued -system.cpu1.iq.rate 1.266732 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 190 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.000752 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 701640 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 261627 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 251253 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 250090 # Type of FU issued +system.cpu1.iq.rate 1.436762 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 262 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001048 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 671900 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 262020 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 248980 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 252770 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 250352 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 35691 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 36283 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1436 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1818 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 758 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 31 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 869 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1747 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1477 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 298452 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 533 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 86261 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 40322 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 920 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2004 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1662 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 295488 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 85765 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 40966 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1025 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 178 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1203 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 251613 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 85566 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 967 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 608 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1239 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 249342 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 84980 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 748 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 43243 # number of nop insts executed -system.cpu1.iew.exec_refs 125476 # number of memory reference insts executed -system.cpu1.iew.exec_branches 52279 # Number of branches executed -system.cpu1.iew.exec_stores 39910 # Number of stores executed -system.cpu1.iew.exec_rate 1.261882 # Inst execution rate -system.cpu1.iew.wb_sent 251386 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 251253 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 141847 # num instructions producing a value -system.cpu1.iew.wb_consumers 145498 # num instructions consuming a value +system.cpu1.iew.exec_nop 41877 # number of nop insts executed +system.cpu1.iew.exec_refs 125494 # number of memory reference insts executed +system.cpu1.iew.exec_branches 50909 # Number of branches executed +system.cpu1.iew.exec_stores 40514 # Number of stores executed +system.cpu1.iew.exec_rate 1.432465 # Inst execution rate +system.cpu1.iew.wb_sent 249148 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 248980 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 142220 # num instructions producing a value +system.cpu1.iew.wb_consumers 146685 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.260077 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.974907 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.430385 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.969561 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 290439 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 8011 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6919 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1102 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 187821 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.546361 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.941498 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 285859 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 9624 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4971 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1082 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 163013 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.753596 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.061352 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 80077 42.63% 42.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 52511 27.96% 70.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 7488 3.99% 74.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7738 4.12% 78.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 2462 1.31% 80.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 36475 19.42% 99.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 459 0.24% 99.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 127 0.07% 99.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 484 0.26% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61328 37.62% 37.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 49151 30.15% 67.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5963 3.66% 71.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5859 3.59% 75.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1587 0.97% 76.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 36625 22.47% 98.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 608 0.37% 98.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1052 0.65% 99.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 840 0.52% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 187821 # Number of insts commited each cycle -system.cpu1.commit.count 290439 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 163013 # Number of insts commited each cycle +system.cpu1.commit.count 285859 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 124389 # Number of memory references committed -system.cpu1.commit.loads 84825 # Number of loads committed -system.cpu1.commit.membars 6207 # Number of memory barriers committed -system.cpu1.commit.branches 51732 # Number of branches committed +system.cpu1.commit.refs 124044 # Number of memory references committed +system.cpu1.commit.loads 83947 # Number of loads committed +system.cpu1.commit.membars 4259 # Number of memory barriers committed +system.cpu1.commit.branches 50321 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 198246 # Number of committed integer instructions. +system.cpu1.commit.int_insts 196488 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 484 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 840 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 485200 # The number of ROB reads -system.cpu1.rob.rob_writes 598649 # The number of ROB writes -system.cpu1.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 3107 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 241708 # Number of Instructions Simulated -system.cpu1.committedInsts_total 241708 # Number of Instructions Simulated -system.cpu1.cpi 0.824942 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.824942 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.212207 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.212207 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 433901 # number of integer regfile reads -system.cpu1.int_regfile_writes 201135 # number of integer regfile writes +system.cpu1.rob.rob_reads 457069 # The number of ROB reads +system.cpu1.rob.rob_writes 592971 # The number of ROB writes +system.cpu1.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2610 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 240487 # Number of Instructions Simulated +system.cpu1.committedInsts_total 240487 # Number of Instructions Simulated +system.cpu1.cpi 0.723802 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.723802 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.381593 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.381593 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 434614 # number of integer regfile reads +system.cpu1.int_regfile_writes 202365 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 127021 # number of misc regfile reads +system.cpu1.misc_regfile_reads 127051 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 335 # number of replacements -system.cpu1.icache.tagsinuse 81.445548 # Cycle average of tags in use -system.cpu1.icache.total_refs 20780 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 442 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 47.013575 # Average number of references to valid blocks. +system.cpu1.icache.replacements 317 # number of replacements +system.cpu1.icache.tagsinuse 84.485339 # Cycle average of tags in use +system.cpu1.icache.total_refs 16887 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 39.548009 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 81.445548 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.159073 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits 20780 # number of ReadReq hits -system.cpu1.icache.demand_hits 20780 # number of demand (read+write) hits -system.cpu1.icache.overall_hits 20780 # number of overall hits -system.cpu1.icache.ReadReq_misses 487 # number of ReadReq misses -system.cpu1.icache.demand_misses 487 # number of demand (read+write) misses -system.cpu1.icache.overall_misses 487 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7348000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7348000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7348000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses 21267 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses 21267 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses 21267 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate 0.022899 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate 0.022899 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate 0.022899 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency 15088.295688 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency 15088.295688 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency 15088.295688 # average overall miss latency +system.cpu1.icache.occ_blocks::0 84.485339 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.165010 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits 16887 # number of ReadReq hits +system.cpu1.icache.demand_hits 16887 # number of demand (read+write) hits +system.cpu1.icache.overall_hits 16887 # number of overall hits +system.cpu1.icache.ReadReq_misses 471 # number of ReadReq misses +system.cpu1.icache.demand_misses 471 # number of demand (read+write) misses +system.cpu1.icache.overall_misses 471 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7156000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7156000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7156000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses 17358 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses 17358 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses 17358 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate 0.027134 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate 0.027134 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate 0.027134 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency 15193.205945 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency 15193.205945 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency 15193.205945 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,67 +702,67 @@ system.cpu1.icache.avg_blocked_cycles::no_targets no_value system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 442 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 442 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 44 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 44 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 427 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 427 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5515000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5515000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5515000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5329000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5329000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5329000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.020783 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate 0.020783 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate 0.020783 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12477.375566 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12477.375566 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12477.375566 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate 0.024600 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate 0.024600 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate 0.024600 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12480.093677 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 12480.093677 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 12480.093677 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 15.853389 # Cycle average of tags in use -system.cpu1.dcache.total_refs 45287 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 18.326142 # Cycle average of tags in use +system.cpu1.dcache.total_refs 46034 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1561.620690 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1587.379310 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 24.109583 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -8.256194 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.047089 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::1 -0.016125 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 49422 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 39377 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits 88799 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 88799 # number of overall hits -system.cpu1.dcache.ReadReq_misses 438 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses 121 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses 52 # number of SwapReq misses -system.cpu1.dcache.demand_misses 559 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses 559 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 9255000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 2991000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency 1250500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency 12246000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 12246000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 49860 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 39498 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.occ_blocks::0 24.418432 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -6.092290 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.047692 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::1 -0.011899 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits 48212 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits 39908 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits 88120 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits 88120 # number of overall hits +system.cpu1.dcache.ReadReq_misses 470 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses 123 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses 54 # number of SwapReq misses +system.cpu1.dcache.demand_misses 593 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses 593 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 9944500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 2927000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency 1215000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency 12871500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 12871500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses 48682 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses 40031 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 89358 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 89358 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.008785 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate 0.003063 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate 0.787879 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.006256 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.006256 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency 21130.136986 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency 24719.008264 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency 24048.076923 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency 21906.976744 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 21906.976744 # average overall miss latency +system.cpu1.dcache.demand_accesses 88713 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses 88713 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate 0.009654 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate 0.003073 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate 0.818182 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate 0.006684 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate 0.006684 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency 21158.510638 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency 23796.747967 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency 22500 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency 21705.733558 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency 21705.733558 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,391 +772,394 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets no_value system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 282 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits 318 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 300 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 300 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 103 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 259 # number of overall MSHR misses +system.cpu1.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 336 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 152 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2111500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1675000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency 1094500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 3786500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 3786500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency 1992500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 1603000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency 1053000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 3595500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 3595500 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003129 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002608 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.787879 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate 0.002898 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate 0.002898 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13535.256410 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16262.135922 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 21048.076923 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14619.691120 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14619.691120 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003122 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002623 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.818182 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate 0.002897 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate 0.002897 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13108.552632 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15266.666667 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19500 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 13990.272374 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 13990.272374 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 199106 # number of cpu cycles simulated +system.cpu2.numCycles 173778 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 57971 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 55658 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 57356 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 55221 # Number of BTB hits +system.cpu2.BPredUnit.lookups 50805 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 48180 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1153 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 47027 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 44960 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 508 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 640 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 18228 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 327195 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 57971 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 55729 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 116612 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1192 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.CacheLines 18228 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 237 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 193972 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.686816 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.080601 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 27007 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 283163 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 50805 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45600 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 99886 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3304 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 32566 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 6449 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 18144 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 200 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 168765 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.677854 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.125811 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 77360 39.88% 39.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 59528 30.69% 70.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5848 3.01% 73.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 2830 1.46% 75.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1905 0.98% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 42329 21.82% 97.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 2448 1.26% 99.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 264 0.14% 99.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1460 0.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 68879 40.81% 40.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 50491 29.92% 70.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5634 3.34% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3757 2.23% 76.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 707 0.42% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 34670 20.54% 97.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1324 0.78% 98.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 413 0.24% 98.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2890 1.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 193972 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.291156 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.643321 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 48904 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 20328 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 111841 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4382 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1806 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 325997 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1806 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 49533 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6147 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13457 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 115712 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 606 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 324330 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 65 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 45 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 224740 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 625107 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 625107 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 216561 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 8179 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 949 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1011 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 2760 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 94652 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 45182 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 45774 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 40713 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 269361 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6099 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 272571 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6651 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 6299 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 621 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 193972 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.405208 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.293243 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 168765 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.292356 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.629453 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 31662 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 29441 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 94497 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4642 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2074 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 280431 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2074 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 32376 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14418 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 14186 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90338 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 8924 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278200 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 53 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 195247 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 534109 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 534109 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 184829 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10418 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1050 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1186 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11541 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79019 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37409 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 37644 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 32854 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 231381 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 5925 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 233568 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8776 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 8266 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 641 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 168765 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.383984 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.307813 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73708 38.00% 38.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23872 12.31% 50.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 47052 24.26% 74.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 44924 23.16% 97.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2620 1.35% 99.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1535 0.79% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 168 0.09% 99.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 84 0.04% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 66154 39.20% 39.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 21382 12.67% 51.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37723 22.35% 74.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38911 23.06% 97.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3386 2.01% 99.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 949 0.56% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 160 0.09% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 42 0.02% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 58 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 193972 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 168765 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 12 5.97% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 58 28.86% 34.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 131 65.17% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19 7.28% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 52 19.92% 27.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 190 72.80% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 128963 47.31% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 98810 36.25% 83.56% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 44798 16.44% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 113638 48.65% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 82927 35.50% 84.16% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 37003 15.84% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 272571 # Type of FU issued -system.cpu2.iq.rate 1.368974 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 201 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.000737 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 739316 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 282139 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 271248 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 233568 # Type of FU issued +system.cpu2.iq.rate 1.344060 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 261 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001117 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 636165 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 246114 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 232313 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 272772 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 233829 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 40559 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 32721 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1552 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1885 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 752 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 861 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1806 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1706 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 322227 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 522 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 94652 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 45182 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 927 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2074 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1817 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 62 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275982 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 400 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79019 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37409 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 998 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 1035 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1222 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 271613 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 93867 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 958 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 681 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 621 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1302 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 232725 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 78144 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 843 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 46767 # number of nop insts executed -system.cpu2.iew.exec_refs 138637 # number of memory reference insts executed -system.cpu2.iew.exec_branches 55708 # Number of branches executed -system.cpu2.iew.exec_stores 44770 # Number of stores executed -system.cpu2.iew.exec_rate 1.364163 # Inst execution rate -system.cpu2.iew.wb_sent 271381 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 271248 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 155012 # num instructions producing a value -system.cpu2.iew.wb_consumers 158673 # num instructions consuming a value +system.cpu2.iew.exec_nop 38676 # number of nop insts executed +system.cpu2.iew.exec_refs 115111 # number of memory reference insts executed +system.cpu2.iew.exec_branches 47758 # Number of branches executed +system.cpu2.iew.exec_stores 36967 # Number of stores executed +system.cpu2.iew.exec_rate 1.339209 # Inst execution rate +system.cpu2.iew.wb_sent 232494 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 232313 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131935 # num instructions producing a value +system.cpu2.iew.wb_consumers 136342 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.362330 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.976927 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.336838 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.967677 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 313840 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 8384 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5478 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1119 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 185456 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.692261 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.994391 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 265754 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 10224 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5284 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1153 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 160243 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.658444 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.033027 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 70838 38.20% 38.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 55984 30.19% 68.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 7465 4.03% 72.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6288 3.39% 75.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 2454 1.32% 77.12% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 41414 22.33% 99.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 401 0.22% 99.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 126 0.07% 99.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 64923 40.52% 40.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46026 28.72% 69.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5970 3.73% 72.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6149 3.84% 76.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1628 1.02% 77.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 33154 20.69% 98.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 514 0.32% 98.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1057 0.66% 99.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 185456 # Number of insts commited each cycle -system.cpu2.commit.count 313840 # Number of instructions committed +system.cpu2.commit.committed_per_cycle::total 160243 # Number of insts commited each cycle +system.cpu2.commit.count 265754 # Number of instructions committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 137530 # Number of memory references committed -system.cpu2.commit.loads 93100 # Number of loads committed -system.cpu2.commit.membars 4761 # Number of memory barriers committed -system.cpu2.commit.branches 55156 # Number of branches committed +system.cpu2.commit.refs 113682 # Number of memory references committed +system.cpu2.commit.loads 77134 # Number of loads committed +system.cpu2.commit.membars 4565 # Number of memory barriers committed +system.cpu2.commit.branches 47078 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 214804 # Number of committed integer instructions. +system.cpu2.commit.int_insts 182876 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 486 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 506607 # The number of ROB reads -system.cpu2.rob.rob_writes 646257 # The number of ROB writes -system.cpu2.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5134 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.committedInsts 263136 # Number of Instructions Simulated -system.cpu2.committedInsts_total 263136 # Number of Instructions Simulated -system.cpu2.cpi 0.756666 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.756666 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.321587 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.321587 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 473358 # number of integer regfile reads -system.cpu2.int_regfile_writes 219156 # number of integer regfile writes +system.cpu2.rob.rob_reads 434812 # The number of ROB reads +system.cpu2.rob.rob_writes 554033 # The number of ROB writes +system.cpu2.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5013 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.committedInsts 223326 # Number of Instructions Simulated +system.cpu2.committedInsts_total 223326 # Number of Instructions Simulated +system.cpu2.cpi 0.778136 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.778136 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.285122 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.285122 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 403849 # number of integer regfile reads +system.cpu2.int_regfile_writes 188623 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 140181 # number of misc regfile reads +system.cpu2.misc_regfile_reads 116687 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 333 # number of replacements -system.cpu2.icache.tagsinuse 86.095246 # Cycle average of tags in use -system.cpu2.icache.total_refs 17739 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 40.500000 # Average number of references to valid blocks. +system.cpu2.icache.replacements 323 # number of replacements +system.cpu2.icache.tagsinuse 85.152335 # Cycle average of tags in use +system.cpu2.icache.total_refs 17658 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 41.160839 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 86.095246 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.168155 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits 17739 # number of ReadReq hits -system.cpu2.icache.demand_hits 17739 # number of demand (read+write) hits -system.cpu2.icache.overall_hits 17739 # number of overall hits -system.cpu2.icache.ReadReq_misses 489 # number of ReadReq misses -system.cpu2.icache.demand_misses 489 # number of demand (read+write) misses -system.cpu2.icache.overall_misses 489 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency 10440000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency 10440000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency 10440000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses 18228 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses 18228 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses 18228 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate 0.026827 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate 0.026827 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate 0.026827 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency 21349.693252 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency 21349.693252 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency 21349.693252 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked +system.cpu2.icache.occ_blocks::0 85.152335 # Average occupied blocks per context +system.cpu2.icache.occ_percent::0 0.166313 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits 17658 # number of ReadReq hits +system.cpu2.icache.demand_hits 17658 # number of demand (read+write) hits +system.cpu2.icache.overall_hits 17658 # number of overall hits +system.cpu2.icache.ReadReq_misses 486 # number of ReadReq misses +system.cpu2.icache.demand_misses 486 # number of demand (read+write) misses +system.cpu2.icache.overall_misses 486 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency 10409000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency 10409000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency 10409000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses 18144 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses 18144 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses 18144 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate 0.026786 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate 0.026786 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate 0.026786 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency 21417.695473 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency 21417.695473 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency 21417.695473 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits 51 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses 438 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses 438 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses 438 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits 57 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits 57 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses 429 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses 429 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses 429 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.ReadReq_mshr_miss_latency 8036500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency 8036500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency 8036500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency 7965500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency 7965500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency 7965500 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.024029 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate 0.024029 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate 0.024029 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18348.173516 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 18348.173516 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 18348.173516 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_rate 0.023644 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate 0.023644 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate 0.023644 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18567.599068 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 18567.599068 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 18567.599068 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 18.718664 # Cycle average of tags in use -system.cpu2.dcache.total_refs 50172 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1672.400000 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 18.333268 # Cycle average of tags in use +system.cpu2.dcache.total_refs 42495 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1370.806452 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 27.030706 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -8.312042 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.052794 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::1 -0.016234 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 52844 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 44237 # number of WriteReq hits +system.cpu2.dcache.occ_blocks::0 26.478684 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -8.145416 # Average occupied blocks per context +system.cpu2.dcache.occ_percent::0 0.051716 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::1 -0.015909 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits 44951 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits 36350 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits 97081 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 97081 # number of overall hits -system.cpu2.dcache.ReadReq_misses 446 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses 122 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses 59 # number of SwapReq misses -system.cpu2.dcache.demand_misses 568 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses 568 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency 10164500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency 2987000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency 1380500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency 13151500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 13151500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 53290 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 44359 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 97649 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 97649 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate 0.008369 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate 0.002750 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate 0.830986 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.005817 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.005817 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency 22790.358744 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency 24483.606557 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency 23398.305085 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency 23154.049296 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 23154.049296 # average overall miss latency +system.cpu2.dcache.demand_hits 81301 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits 81301 # number of overall hits +system.cpu2.dcache.ReadReq_misses 454 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses 125 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses 61 # number of SwapReq misses +system.cpu2.dcache.demand_misses 579 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses 579 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency 10292500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency 2895500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency 1389500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency 13188000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency 13188000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses 45405 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses 36475 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses 81880 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses 81880 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate 0.009999 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate 0.003427 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate 0.835616 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate 0.007071 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate 0.007071 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency 22670.704846 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency 23164 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency 22778.688525 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency 22777.202073 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency 22777.202073 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1161,321 +1169,324 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets no_value system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits 286 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits 289 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits 304 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits 304 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses 160 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses 104 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses 59 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses +system.cpu2.dcache.demand_mshr_hits 307 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits 307 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses 61 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses 272 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses 272 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 2394500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency 1669000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency 1203500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency 4063500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 4063500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency 2342500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency 1563000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency 1206500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency 3905500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency 3905500 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003002 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002345 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.830986 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate 0.002704 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate 0.002704 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14965.625000 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16048.076923 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 20398.305085 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 15392.045455 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 15392.045455 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003634 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002934 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate 0.835616 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate 0.003322 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate 0.003322 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14196.969697 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 14607.476636 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19778.688525 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 14358.455882 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 14358.455882 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 198838 # number of cpu cycles simulated +system.cpu3.numCycles 173512 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 46930 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 44609 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 46370 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 44223 # Number of BTB hits +system.cpu3.BPredUnit.lookups 40530 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 37937 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1057 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 36753 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 34800 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 506 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 627 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 25370 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 254105 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 46930 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 44729 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 98091 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1197 # Number of cycles fetch has spent squashing -system.cpu3.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.CacheLines 25370 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 195684 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.298548 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 1.898359 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 33125 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 215867 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 40530 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 35427 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 83007 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3046 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 45401 # Number of cycles fetch has spent blocked +system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.NoActiveThreadStallCycles 6445 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 706 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24871 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 170604 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.265310 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 1.931210 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 97593 49.87% 49.87% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 52035 26.59% 76.46% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 9385 4.80% 81.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 2730 1.40% 82.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1923 0.98% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 27840 14.23% 97.86% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2474 1.26% 99.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 258 0.13% 99.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 1446 0.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 87597 51.35% 51.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 43833 25.69% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8987 5.27% 82.31% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3510 2.06% 84.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 653 0.38% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 21422 12.56% 97.30% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1319 0.77% 98.08% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 370 0.22% 98.29% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2913 1.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 195684 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.236021 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.277950 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 66043 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 23415 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 90085 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7606 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1806 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 252876 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1806 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 66691 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 9403 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13294 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 97176 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 585 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 251157 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 61 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 39 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 170213 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 465014 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 465014 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 162080 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 8133 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 958 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1016 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 2718 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69072 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 30693 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 34709 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 26217 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 203693 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 9545 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 210364 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 6179 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 195684 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.075019 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.244116 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 170604 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.233586 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.244104 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 41023 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 38920 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 74503 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7798 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1915 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 213126 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1915 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 41660 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 23650 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 14461 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 67213 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 15260 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 211303 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 145000 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 387654 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 387654 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 135623 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 9377 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1053 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1194 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 17810 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 55847 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 24229 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 27736 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 19680 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 171446 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9173 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 177208 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 8093 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 7434 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 618 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 170604 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.038710 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.248224 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 94148 48.11% 48.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 34086 17.42% 65.53% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 32603 16.66% 82.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 30459 15.57% 97.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 2587 1.32% 99.08% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1559 0.80% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 152 0.08% 99.95% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 80 0.04% 99.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 84759 49.68% 49.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 31065 18.21% 67.89% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24373 14.29% 82.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 25865 15.16% 97.34% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3284 1.92% 99.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1031 0.60% 99.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 132 0.08% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 41 0.02% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 195684 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 170604 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 52 26.80% 32.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 131 67.53% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 11 4.47% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 45 18.29% 22.76% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 190 77.24% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 103392 49.15% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 76648 36.44% 85.58% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 30324 14.42% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 90240 50.92% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 63111 35.61% 86.54% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 23857 13.46% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 210364 # Type of FU issued -system.cpu3.iq.rate 1.057967 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 194 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.000922 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 616608 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 219792 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 209060 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 177208 # Type of FU issued +system.cpu3.iq.rate 1.021301 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 246 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001388 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 525269 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 188741 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 176086 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 210558 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 177454 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 26077 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 19589 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1504 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1676 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 734 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 799 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1806 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1713 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 248952 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 576 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69072 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 30693 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 930 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 49 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1915 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1524 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 209347 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 55847 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 24229 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 987 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1047 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 172 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1219 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 209414 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 68288 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 950 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 624 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 548 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1172 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 176425 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 55052 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 783 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 35714 # number of nop insts executed -system.cpu3.iew.exec_refs 98584 # number of memory reference insts executed -system.cpu3.iew.exec_branches 44648 # Number of branches executed -system.cpu3.iew.exec_stores 30296 # Number of stores executed -system.cpu3.iew.exec_rate 1.053189 # Inst execution rate -system.cpu3.iew.wb_sent 209192 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 209060 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 114958 # num instructions producing a value -system.cpu3.iew.wb_consumers 118605 # num instructions consuming a value +system.cpu3.iew.exec_nop 28728 # number of nop insts executed +system.cpu3.iew.exec_refs 78879 # number of memory reference insts executed +system.cpu3.iew.exec_branches 37783 # Number of branches executed +system.cpu3.iew.exec_stores 23827 # Number of stores executed +system.cpu3.iew.exec_rate 1.016788 # Inst execution rate +system.cpu3.iew.wb_sent 176246 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 176086 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 95644 # num instructions producing a value +system.cpu3.iew.wb_consumers 99967 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.051409 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.969251 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.014835 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.956756 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 240668 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 8282 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 8898 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1124 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 187150 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.285963 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.815684 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 200126 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 9211 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 8555 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1057 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 162245 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.233480 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.839252 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 94628 50.56% 50.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 44931 24.01% 74.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 7495 4.00% 78.58% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 9690 5.18% 83.75% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 2458 1.31% 85.07% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 26940 14.39% 99.46% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 395 0.21% 99.67% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 129 0.07% 99.74% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 484 0.26% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 86736 53.46% 53.46% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 36031 22.21% 75.67% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6002 3.70% 79.37% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 9421 5.81% 85.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1631 1.01% 86.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 19977 12.31% 98.49% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 548 0.34% 98.83% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1061 0.65% 99.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 838 0.52% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 187150 # Number of insts commited each cycle -system.cpu3.commit.count 240668 # Number of instructions committed +system.cpu3.commit.committed_per_cycle::total 162245 # Number of insts commited each cycle +system.cpu3.commit.count 200126 # Number of instructions committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 97527 # Number of memory references committed -system.cpu3.commit.loads 67568 # Number of loads committed -system.cpu3.commit.membars 8180 # Number of memory barriers committed -system.cpu3.commit.branches 44100 # Number of branches committed +system.cpu3.commit.refs 77601 # Number of memory references committed +system.cpu3.commit.loads 54171 # Number of loads committed +system.cpu3.commit.membars 7839 # Number of memory barriers committed +system.cpu3.commit.branches 37226 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 163745 # Number of committed integer instructions. +system.cpu3.commit.int_insts 136949 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 484 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 838 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 435029 # The number of ROB reads -system.cpu3.rob.rob_writes 499708 # The number of ROB writes -system.cpu3.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 3154 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.committedInsts 197602 # Number of Instructions Simulated -system.cpu3.committedInsts_total 197602 # Number of Instructions Simulated -system.cpu3.cpi 1.006255 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.006255 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.993784 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.993784 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 353198 # number of integer regfile reads -system.cpu3.int_regfile_writes 164587 # number of integer regfile writes +system.cpu3.rob.rob_reads 370157 # The number of ROB reads +system.cpu3.rob.rob_writes 420591 # The number of ROB writes +system.cpu3.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.committedInsts 164273 # Number of Instructions Simulated +system.cpu3.committedInsts_total 164273 # Number of Instructions Simulated +system.cpu3.cpi 1.056242 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.056242 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.946753 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.946753 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 294835 # number of integer regfile reads +system.cpu3.int_regfile_writes 139001 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 100115 # number of misc regfile reads +system.cpu3.misc_regfile_reads 80433 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 334 # number of replacements -system.cpu3.icache.tagsinuse 83.539668 # Cycle average of tags in use -system.cpu3.icache.total_refs 24889 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 440 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 56.565909 # Average number of references to valid blocks. +system.cpu3.icache.replacements 318 # number of replacements +system.cpu3.icache.tagsinuse 80.013522 # Cycle average of tags in use +system.cpu3.icache.total_refs 24405 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 57.288732 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 83.539668 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.163163 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits 24889 # number of ReadReq hits -system.cpu3.icache.demand_hits 24889 # number of demand (read+write) hits -system.cpu3.icache.overall_hits 24889 # number of overall hits -system.cpu3.icache.ReadReq_misses 481 # number of ReadReq misses -system.cpu3.icache.demand_misses 481 # number of demand (read+write) misses -system.cpu3.icache.overall_misses 481 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency 6766000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency 6766000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency 6766000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses 25370 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses 25370 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses 25370 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate 0.018959 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate 0.018959 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate 0.018959 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency 14066.528067 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency 14066.528067 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency 14066.528067 # average overall miss latency +system.cpu3.icache.occ_blocks::0 80.013522 # Average occupied blocks per context +system.cpu3.icache.occ_percent::0 0.156276 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits 24405 # number of ReadReq hits +system.cpu3.icache.demand_hits 24405 # number of demand (read+write) hits +system.cpu3.icache.overall_hits 24405 # number of overall hits +system.cpu3.icache.ReadReq_misses 466 # number of ReadReq misses +system.cpu3.icache.demand_misses 466 # number of demand (read+write) misses +system.cpu3.icache.overall_misses 466 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency 6656500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency 6656500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency 6656500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses 24871 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses 24871 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses 24871 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate 0.018737 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate 0.018737 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate 0.018737 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency 14284.334764 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency 14284.334764 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency 14284.334764 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1485,67 +1496,67 @@ system.cpu3.icache.avg_blocked_cycles::no_targets no_value system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits 41 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses 440 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses 440 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses 440 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits 40 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses 426 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.ReadReq_mshr_miss_latency 5068000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency 5068000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency 5068000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency 4959000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency 4959000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency 4959000 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.017343 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate 0.017343 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate 0.017343 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11518.181818 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11518.181818 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11518.181818 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_rate 0.017128 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate 0.017128 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate 0.017128 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11640.845070 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11640.845070 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11640.845070 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 16.417900 # Cycle average of tags in use -system.cpu3.dcache.total_refs 35718 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1190.600000 # Average number of references to valid blocks. +system.cpu3.dcache.tagsinuse 15.701328 # Cycle average of tags in use +system.cpu3.dcache.total_refs 29297 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1010.241379 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::0 24.989455 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -8.571555 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.048808 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::1 -0.016741 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 41747 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 29763 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits 71510 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 71510 # number of overall hits -system.cpu3.dcache.ReadReq_misses 446 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses 124 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses -system.cpu3.dcache.demand_misses 570 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses 570 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency 9927500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency 2778000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency 1471000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency 12705500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency 12705500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 42193 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 29887 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 72080 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 72080 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate 0.010570 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate 0.004149 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate 0.007908 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate 0.007908 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency 22258.968610 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency 22403.225806 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency 25362.068966 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency 22290.350877 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency 22290.350877 # average overall miss latency +system.cpu3.dcache.occ_blocks::0 23.466885 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -7.765557 # Average occupied blocks per context +system.cpu3.dcache.occ_percent::0 0.045834 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::1 -0.015167 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits 35023 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits 23239 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits 16 # number of SwapReq hits +system.cpu3.dcache.demand_hits 58262 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits 58262 # number of overall hits +system.cpu3.dcache.ReadReq_misses 421 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses 121 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses 54 # number of SwapReq misses +system.cpu3.dcache.demand_misses 542 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses 542 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency 8723500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency 2943500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency 1375000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency 11667000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency 11667000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses 35444 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses 23360 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses 58804 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses 58804 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate 0.011878 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate 0.005180 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate 0.771429 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate 0.009217 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate 0.009217 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency 20720.902613 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency 24326.446281 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency 25462.962963 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency 21525.830258 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency 21525.830258 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1555,178 +1566,178 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets no_value system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_hits 272 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits 256 # number of ReadReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits 291 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits 291 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses 279 # number of overall MSHR misses +system.cpu3.dcache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits 275 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 2494000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency 1504000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency 1297000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency 3998000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency 3998000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency 2157000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency 1669000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency 1213000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency 3826000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency 3826000 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004124 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003513 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate 0.003871 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate 0.003871 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14333.333333 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14323.809524 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22362.068966 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 14329.749104 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 14329.749104 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004655 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.004366 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.771429 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate 0.004541 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate 0.004541 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13072.727273 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16362.745098 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22462.962963 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 14329.588015 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 14329.588015 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 428.707153 # Cycle average of tags in use -system.l2c.total_refs 1488 # Total number of references to valid blocks. -system.l2c.sampled_refs 521 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.856046 # Average number of references to valid blocks. +system.l2c.tagsinuse 428.144160 # Cycle average of tags in use +system.l2c.total_refs 1448 # Total number of references to valid blocks. +system.l2c.sampled_refs 527 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.747628 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 348.158908 # Average occupied blocks per context -system.l2c.occ_blocks::1 9.356931 # Average occupied blocks per context -system.l2c.occ_blocks::2 63.539276 # Average occupied blocks per context -system.l2c.occ_blocks::3 2.442412 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.209626 # Average occupied blocks per context -system.l2c.occ_percent::0 0.005312 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.000143 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000970 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 347.119372 # Average occupied blocks per context +system.l2c.occ_blocks::1 10.560700 # Average occupied blocks per context +system.l2c.occ_blocks::2 63.080596 # Average occupied blocks per context +system.l2c.occ_blocks::3 2.422702 # Average occupied blocks per context +system.l2c.occ_blocks::4 4.960789 # Average occupied blocks per context +system.l2c.occ_percent::0 0.005297 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.000161 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.000963 # Average percentage of cache occupancy system.l2c.occ_percent::3 0.000037 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.000079 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 232 # number of ReadReq hits -system.l2c.ReadReq_hits::1 440 # number of ReadReq hits -system.l2c.ReadReq_hits::2 370 # number of ReadReq hits -system.l2c.ReadReq_hits::3 449 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1491 # number of ReadReq hits +system.l2c.occ_percent::4 0.000076 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 233 # number of ReadReq hits +system.l2c.ReadReq_hits::1 425 # number of ReadReq hits +system.l2c.ReadReq_hits::2 360 # number of ReadReq hits +system.l2c.ReadReq_hits::3 433 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1451 # number of ReadReq hits system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::0 232 # number of demand (read+write) hits -system.l2c.demand_hits::1 440 # number of demand (read+write) hits -system.l2c.demand_hits::2 370 # number of demand (read+write) hits -system.l2c.demand_hits::3 449 # number of demand (read+write) hits -system.l2c.demand_hits::total 1491 # number of demand (read+write) hits -system.l2c.overall_hits::0 232 # number of overall hits -system.l2c.overall_hits::1 440 # number of overall hits -system.l2c.overall_hits::2 370 # number of overall hits -system.l2c.overall_hits::3 449 # number of overall hits -system.l2c.overall_hits::total 1491 # number of overall hits -system.l2c.ReadReq_misses::0 425 # number of ReadReq misses +system.l2c.demand_hits::0 233 # number of demand (read+write) hits +system.l2c.demand_hits::1 425 # number of demand (read+write) hits +system.l2c.demand_hits::2 360 # number of demand (read+write) hits +system.l2c.demand_hits::3 433 # number of demand (read+write) hits +system.l2c.demand_hits::total 1451 # number of demand (read+write) hits +system.l2c.overall_hits::0 233 # number of overall hits +system.l2c.overall_hits::1 425 # number of overall hits +system.l2c.overall_hits::2 360 # number of overall hits +system.l2c.overall_hits::3 433 # number of overall hits +system.l2c.overall_hits::total 1451 # number of overall hits +system.l2c.ReadReq_misses::0 429 # number of ReadReq misses system.l2c.ReadReq_misses::1 15 # number of ReadReq misses -system.l2c.ReadReq_misses::2 82 # number of ReadReq misses -system.l2c.ReadReq_misses::3 4 # number of ReadReq misses -system.l2c.ReadReq_misses::total 526 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 26 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 25 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 93 # number of UpgradeReq misses +system.l2c.ReadReq_misses::2 83 # number of ReadReq misses +system.l2c.ReadReq_misses::3 6 # number of ReadReq misses +system.l2c.ReadReq_misses::total 533 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 23 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 24 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::0 519 # number of demand (read+write) misses +system.l2c.demand_misses::0 523 # number of demand (read+write) misses system.l2c.demand_misses::1 27 # number of demand (read+write) misses -system.l2c.demand_misses::2 95 # number of demand (read+write) misses -system.l2c.demand_misses::3 16 # number of demand (read+write) misses -system.l2c.demand_misses::total 657 # number of demand (read+write) misses -system.l2c.overall_misses::0 519 # number of overall misses +system.l2c.demand_misses::2 96 # number of demand (read+write) misses +system.l2c.demand_misses::3 18 # number of demand (read+write) misses +system.l2c.demand_misses::total 664 # number of demand (read+write) misses +system.l2c.overall_misses::0 523 # number of overall misses system.l2c.overall_misses::1 27 # number of overall misses -system.l2c.overall_misses::2 95 # number of overall misses -system.l2c.overall_misses::3 16 # number of overall misses -system.l2c.overall_misses::total 657 # number of overall misses -system.l2c.ReadReq_miss_latency 27341000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 156000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6879000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 34220000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 34220000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 455 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 452 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 453 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::2 96 # number of overall misses +system.l2c.overall_misses::3 18 # number of overall misses +system.l2c.overall_misses::total 664 # number of overall misses +system.l2c.ReadReq_miss_latency 27698500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 157500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6878000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 34576500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 34576500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 662 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 440 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 443 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 439 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1984 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 29 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 96 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 23 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 751 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 465 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 465 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2148 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 751 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 465 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 465 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2148 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.646880 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.032967 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.181416 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.008830 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.870093 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.896552 # miss rate for UpgradeReq accesses +system.l2c.demand_accesses::0 756 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 452 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 456 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 451 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2115 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 756 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 452 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 456 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 451 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2115 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.648036 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.034091 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.187359 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.013667 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.883154 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.875000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 3.896552 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 3.875000 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.691079 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.057816 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.204301 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.034409 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.987604 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.691079 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.057816 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.204301 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.034409 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.987604 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 64331.764706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 1822733.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 333426.829268 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 6835250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9055741.927308 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 6000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 6240 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 6782.608696 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 8210.526316 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 27233.135011 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 73180.851064 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 573250 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 529153.846154 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 573250 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1748834.697218 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 65934.489403 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1267407.407407 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 360210.526316 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 2138750 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3832302.423126 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 65934.489403 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1267407.407407 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 360210.526316 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 2138750 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3832302.423126 # average overall miss latency +system.l2c.demand_miss_rate::0 0.691799 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.059735 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.210526 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.039911 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 1.001971 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.691799 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.059735 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.210526 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.039911 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 1.001971 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 64565.268065 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1846566.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 333716.867470 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 4616416.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 6861265.468868 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 7500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 6847.826087 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 8289.473684 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 6562.500000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29199.799771 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 73170.212766 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 573166.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 529076.923077 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 573166.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1748580.469176 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::0 66111.854685 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1280611.111111 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 360171.875000 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1920916.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3627811.507462 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 66111.854685 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1280611.111111 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 360171.875000 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1920916.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3627811.507462 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1736,51 +1747,51 @@ system.l2c.avg_blocked_cycles::no_targets no_value # a system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks 0 # number of writebacks -system.l2c.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 7 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 519 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 93 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 8 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 8 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 525 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 87 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 650 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 650 # number of overall MSHR misses +system.l2c.demand_mshr_misses 656 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 656 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 20754000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 3720500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency 20993500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 3480000 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency 5279000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 26033000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 26033000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency 26272500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 26272500 # number of overall MSHR miss cycles system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.789954 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 1.140659 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 1.148230 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 1.145695 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 4.224539 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 3.206897 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 3.720000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 4.043478 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 4.894737 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 15.865112 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.793051 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 1.193182 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 1.185102 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 1.195900 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 4.367235 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 3.625000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 3.782609 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 4.578947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 3.625000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 15.611556 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.865513 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.391863 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.397849 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.397849 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 5.053075 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.865513 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.391863 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.397849 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.397849 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 5.053075 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 39988.439306 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.376344 # average UpgradeReq mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.867725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.451327 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.438596 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.454545 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 5.212194 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.867725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.451327 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.438596 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.454545 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 5.212194 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 39987.619048 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40050.769231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40050.769231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40049.542683 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40049.542683 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |