mem: Change AbstractMemory defaults to match the common case

This patch changes the default parameter value of conf_table_reported
to match the common case. It also simplifies the regression and config
scripts to reflect this change.

3 files changed, 3 insertions, 6 deletions

diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index 9a0eb9395..e9487546d 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -228,8 +228,7 @@ class BaseFSSystem(BaseSystem):
 
         # create the memory controllers and connect them, stick with
         # the physmem name to avoid bumping all the reference stats
-        system.physmem = [self.mem_class(range = r,
-                                         conf_table_reported = True)
+        system.physmem = [self.mem_class(range = r)
                           for r in system.mem_ranges]
         for i in xrange(len(system.physmem)):
             system.physmem[i].port = system.membus.master
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index fcbfd6b7f..57f9b6679 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -89,8 +89,7 @@ for (i, cpu) in enumerate(system.cpu):
     # Set access_phys_mem to True for ruby port
     system.ruby._cpu_ruby_ports[i].access_phys_mem = True
 
-system.physmem = [DDR3_1600_x64(range = r,
-                                conf_table_reported = True)
+system.physmem = [DDR3_1600_x64(range = r)
                   for r in system.mem_ranges]
 for i in xrange(len(system.physmem)):
     system.physmem[i].port = system.piobus.master
diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index 68bf048b6..96357f40c 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -45,8 +45,7 @@ cpu.connectAllPorts(system.membus)
 
 # create the memory controllers and connect them, stick with
 # the physmem name to avoid bumping all the reference stats
-system.physmem = [SimpleMemory(range = r,
-                               conf_table_reported = True)
+system.physmem = [SimpleMemory(range = r)
                   for r in system.mem_ranges]
 for i in xrange(len(system.physmem)):
     system.physmem[i].port = system.membus.master