diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-05-18 13:36:47 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-05-18 13:36:47 -0700 |
| commit | a13d5af274a1847eaad649af226e643e86a3322d (patch) | |
| tree | 6b3bdd0b269802b324b4744e6ed8362d1917e1a0 /tests | |
| parent | 6a6e62014ec72f9dd29a42c3e92fbc91d6b1f648 (diff) | |
| parent | a8278c3bde2ba9abc2820afafa9d0e766e36b2c8 (diff) | |
| download | gem5-a13d5af274a1847eaad649af226e643e86a3322d.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86
--HG--
extra : convert_revision : 3f17fc418ee5a30da2b08a515fb394cc8fcdd237
Diffstat (limited to 'tests')
235 files changed, 9415 insertions, 18712 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index f56edef4a..15a4f8f05 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 10 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 331e2c569..1ac9bd2e4 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -35,7 +35,7 @@ m5.AddToPath('../configs/common') # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -47,7 +47,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -73,6 +73,7 @@ for cpu in cpus: L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) + cpu.clock = '2GHz' # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index 5600d9f22..366a3eb0d 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -33,13 +33,14 @@ m5.AddToPath('../configs/common') class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 cpu = DerivO3CPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), MyCache(size = '2MB')) +cpu.clock = '2GHz' system = System(cpu = cpu, physmem = PhysicalMemory(), diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index f9e4e2767..de0793d1c 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -72,6 +72,7 @@ for cpu in cpus: L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) + cpu.clock = '2GHz' # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py index a8a876994..cc303886b 100644 --- a/tests/configs/simple-atomic.py +++ b/tests/configs/simple-atomic.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0), membus = Bus()) system.physmem.port = system.membus.port system.cpu.connectMemPorts(system.membus) +system.cpu.clock = '2GHz' root = Root(system = system) diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 0d99d8714..1fd0e8c3c 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -72,6 +72,7 @@ for cpu in cpus: L1(size = '32kB', assoc = 4)) # connect cpu level-1 caches to shared level-2 cache cpu.connectMemPorts(system.toL2Bus) + cpu.clock = '2GHz' # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index d7d505a5a..0ed985a17 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,17 +32,18 @@ from m5.objects import * class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 cpu = TimingSimpleCPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), - MyCache(size = '2MB')) + MyCache(size = '2MB', latency='10ns')) system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) system.physmem.port = system.membus.port cpu.connectMemPorts(system.membus) +cpu.clock = '2GHz' root = Root(system = system) diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 7ed854f44..131095055 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -31,12 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) - -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 4859f30cf..595b1aeda 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -31,10 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = AtomicSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 0c8c3d523..47fba30ff 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -31,11 +31,51 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + + diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 9f532e3ae..999bde087 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -31,10 +31,50 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = TimingSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index fa5ac1725..4de44cbb3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -64,12 +23,13 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -131,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -155,7 +114,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -307,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -331,7 +289,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -346,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -379,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -388,7 +346,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing egid=100 env= euid=100 @@ -403,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out index 8744b6907..24d41aaa7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -31,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -170,9 +168,10 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -251,9 +250,9 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -282,16 +281,15 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -320,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -358,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -366,40 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 +block_size=64 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 8303336ed..21eca8681 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 97621780 # Number of BTB hits -global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups -global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted -global.BPredUnit.lookups 108029652 # Number of BP lookups -global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target. -host_inst_rate 64442 # Simulator instruction rate (inst/s) -host_mem_usage 296420 # Number of bytes of host memory used -host_seconds 8776.17 # Real time elapsed on the host -host_tick_rate 192322 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 65796417 # Number of BTB hits +global.BPredUnit.BTBLookups 73152793 # Number of BTB lookups +global.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4224786 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70143727 # Number of conditional branches predicted +global.BPredUnit.lookups 75959317 # Number of BP lookups +global.BPredUnit.usedRAS 1707904 # Number of times the RAS was used to get a target. +host_inst_rate 95235 # Simulator instruction rate (inst/s) +host_mem_usage 154544 # Number of bytes of host memory used +host_seconds 5938.47 # Real time elapsed on the host +host_tick_rate 31305923 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 11533351 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 9283325 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 125815870 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 42503953 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.001688 # Number of seconds simulated -sim_ticks 1687849017 # Number of ticks simulated +sim_seconds 0.185909 # Number of seconds simulated +sim_ticks 185909249000 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 21750592 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 701581491 +system.cpu.commit.COM:committed_per_cycle.samples 363164843 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 480309675 6846.10% - 1 104094392 1483.71% - 2 40244499 573.63% - 3 11990473 170.91% - 4 15113210 215.42% - 5 17360338 247.45% - 6 10367558 147.77% - 7 4968492 70.82% - 8 17132854 244.20% + 0 150226418 4136.59% + 1 99566964 2741.65% + 2 34056070 937.76% + 3 10333475 284.54% + 4 20301573 559.02% + 5 15829471 435.88% + 6 8882909 244.60% + 7 2217371 61.06% + 8 21750592 598.92% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4224164 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 52370845 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses +system.cpu.cpi 0.657443 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.657443 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 115591547 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3246.088003 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2434.144734 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 115095381 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1610598500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004292 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 496166 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 273177 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 542787500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001929 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 222989 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 3474.707454 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2824.359825 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38691611 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2639770000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.019257 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 759710 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 502007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 727846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006532 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 257703 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 427.272727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 319.928337 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 1210 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 517000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency -system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 155042868 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3384.385481 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153786992 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4250368500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008100 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1255876 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 775184 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1270633500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003100 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 480692 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 155042868 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3384.385481 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 152421092 # number of overall hits -system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1949244 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses +system.cpu.dcache.overall_hits 153786992 # number of overall hits +system.cpu.dcache.overall_miss_latency 4250368500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008100 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1255876 # number of overall misses +system.cpu.dcache.overall_mshr_hits 775184 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1270633500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003100 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 480692 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 476534 # number of replacements -system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 476596 # number of replacements +system.cpu.dcache.sampled_refs 480692 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use -system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 337990 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched -system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.610639 # Cycle average of tags in use +system.cpu.dcache.total_refs 153786992 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 28323000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338024 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 44010110 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 636 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3910489 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 686828869 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 203536444 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 106139742 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8653682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1958 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 9478548 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 75959317 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65390933 # Number of cache lines fetched +system.cpu.fetch.Cycles 182129217 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2901518 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 693889852 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4411999 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.204291 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65390933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67504321 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.866206 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 755178522 +system.cpu.fetch.rateDist.samples 371818526 system.cpu.fetch.rateDist.min_value 0 - 0 512314112 6784.01% - 1 11453310 151.66% - 2 16801464 222.48% - 3 16318450 216.09% - 4 18767749 248.52% - 5 15201778 201.30% - 6 32935567 436.13% - 7 7297838 96.64% - 8 124088254 1643.16% + 0 255080243 6860.34% + 1 9944321 267.45% + 2 12043396 323.91% + 3 10077209 271.02% + 4 7005486 188.41% + 5 3160802 85.01% + 6 3551742 95.52% + 7 3151910 84.77% + 8 67803417 1823.56% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 65390933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5347.983454 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4573.991031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65389966 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 5171500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 967 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4080000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 892 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 73307.136771 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency -system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 65390933 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5347.983454 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency +system.cpu.icache.demand_hits 65389966 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 5171500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000015 # miss rate for demand accesses +system.cpu.icache.demand_misses 967 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4080000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 892 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency +system.cpu.icache.overall_accesses 65390933 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5347.983454 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 167526954 # number of overall hits -system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_misses 1230 # number of overall misses -system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses +system.cpu.icache.overall_hits 65389966 # number of overall hits +system.cpu.icache.overall_miss_latency 5171500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000015 # miss rate for overall accesses +system.cpu.icache.overall_misses 967 # number of overall misses +system.cpu.icache.overall_mshr_hits 75 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4080000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 892 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,81 +215,81 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 47 # number of replacements -system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks. +system.cpu.icache.replacements 33 # number of replacements +system.cpu.icache.sampled_refs 892 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use -system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 761.711791 # Cycle average of tags in use +system.cpu.icache.total_refs 65389966 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 92484798 # Number of branches executed -system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate -system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 51400640 # Number of stores executed +system.cpu.idleCycles 2468 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67136036 # Number of branches executed +system.cpu.iew.EXEC:nop 41949449 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.608660 # Inst execution rate +system.cpu.iew.EXEC:refs 164353457 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41112797 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value -system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back +system.cpu.iew.WB:consumers 478961290 # num instructions consuming a value +system.cpu.iew.WB:count 594114153 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.812310 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 394011709 # num instructions producing a value -system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle -system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 389064913 # num instructions producing a value +system.cpu.iew.WB:rate 1.597861 # insts written-back per cycle +system.cpu.iew.WB:sent 594699658 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4485637 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10981 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 125815870 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6586227 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 42503953 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 654225210 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 123240660 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4346710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 598129643 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 518 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8653682 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4417 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 2615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 7105932 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1847 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 530187 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4208331 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 296430 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5860 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 10766360 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2691430 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 296430 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 519296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3966341 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.521044 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.521044 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 602476353 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 496182294 65.92% # Type of FU issued - IntMult 8208 0.00% # Type of FU issued + IntAlu 435905994 72.35% # Type of FU issued + IntMult 6492 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 33 0.00% # Type of FU issued - FloatCmp 6 0.00% # Type of FU issued + FloatAdd 27 0.00% # Type of FU issued + FloatCmp 5 0.00% # Type of FU issued FloatCvt 5 0.00% # Type of FU issued - FloatMult 5 0.00% # Type of FU issued + FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 204178453 27.13% # Type of FU issued - MemWrite 52346873 6.95% # Type of FU issued + MemRead 124769613 20.71% # Type of FU issued + MemWrite 41794213 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 3485464 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005785 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 2723724 78.58% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available + IntAlu 2980889 85.52% # attempts to use FU when none available + IntMult 104 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available @@ -297,80 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 683243 19.71% # attempts to use FU when none available - MemWrite 59353 1.71% # attempts to use FU when none available + MemRead 331227 9.50% # attempts to use FU when none available + MemWrite 173244 4.97% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522 +system.cpu.iq.ISSUE:issued_per_cycle.samples 371818526 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 450030250 5959.26% - 1 91846319 1216.22% - 2 83470092 1105.30% - 3 53962116 714.56% - 4 57175468 757.11% - 5 10089384 133.60% - 6 7448894 98.64% - 7 1047122 13.87% - 8 108877 1.44% + 0 125625601 3378.68% + 1 89616652 2410.23% + 2 55904072 1503.53% + 3 46310572 1245.52% + 4 27240019 732.62% + 5 12675210 340.90% + 6 11517465 309.76% + 7 2752555 74.03% + 8 176380 4.74% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate -system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 337990 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 337990 # number of Writeback hits +system.cpu.iq.ISSUE:rate 1.620351 # Inst issue rate +system.cpu.iq.iqInstsAdded 612275739 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 602476353 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 42659982 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 2623 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 21979774 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 481584 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 6174.721472 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2416.099471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 455285 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 162389000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.054609 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26299 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 63541000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054609 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26299 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338024 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 338024 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 30.164987 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 481584 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 6174.721472 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 455285 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 162389000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.054609 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26299 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 63541000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.054609 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26299 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 819608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 6174.721472 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 793226 # number of overall hits -system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26319 # number of overall misses +system.cpu.l2cache.overall_hits 793309 # number of overall hits +system.cpu.l2cache.overall_miss_latency 162389000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.032087 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26299 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 63541000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.032087 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -382,32 +382,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 934 # number of replacements -system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 931 # number of replacements +system.cpu.l2cache.sampled_refs 26299 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use -system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 25071.267749 # Cycle average of tags in use +system.cpu.l2cache.total_refs 793309 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 907 # number of writebacks -system.cpu.numCycles 755178522 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 904 # number of writebacks +system.cpu.numCycles 371818526 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 11517489 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 32462126 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 206624315 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 21712 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 889109667 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 674900294 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 515718683 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 111518348 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8653682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 33504424 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 51863794 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 268 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 59569309 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.timesIdled 32 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 841e8766f..e7acc71a6 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -74,7 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic egid=100 env= euid=100 @@ -89,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -100,14 +60,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out index b5a24e5fb..589507187 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -30,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -49,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -57,51 +56,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index b8593d3a3..5453dc099 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 970342 # Simulator instruction rate (inst/s) -host_mem_usage 144620 # Number of bytes of host memory used -host_seconds 620.25 # Real time elapsed on the host -host_tick_rate 970342 # Simulator tick rate (ticks/s) +host_inst_rate 963880 # Simulator instruction rate (inst/s) +host_mem_usage 148548 # Number of bytes of host memory used +host_seconds 624.41 # Real time elapsed on the host +host_tick_rate 481939681 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.000602 # Number of seconds simulated -sim_ticks 601856964 # Number of ticks simulated +sim_seconds 0.300928 # Number of seconds simulated +sim_ticks 300928482000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 601856965 # number of cpu cycles simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index 48a760b08..f82815f7b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -77,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -116,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -155,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -188,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -197,7 +154,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing egid=100 env= euid=100 @@ -212,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -223,14 +181,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out index eddb9ff53..5cab10662 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -30,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -49,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -63,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -100,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -138,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -176,53 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 5e7441c54..9d4ab211d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 549029 # Simulator instruction rate (inst/s) -host_mem_usage 300652 # Number of bytes of host memory used -host_seconds 1096.22 # Real time elapsed on the host -host_tick_rate 1916109 # Simulator tick rate (ticks/s) +host_inst_rate 494073 # Simulator instruction rate (inst/s) +host_mem_usage 153964 # Number of bytes of host memory used +host_seconds 1218.16 # Real time elapsed on the host +host_tick_rate 624626994 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.002100 # Number of seconds simulated -sim_ticks 2100480012 # Number of ticks simulated +sim_seconds 0.760893 # Number of seconds simulated +sim_ticks 760892614000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2845.396229 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1845.396229 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12040.967639 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11040.967639 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 572584774 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2423028000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 371352774 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2221796000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3026.723012 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2026.723012 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12166.766996 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11166.766996 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 769281001 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3092342000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 515118001 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2838179000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2946.597514 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12111.178208 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1341865775 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5515370000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 886470775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5059975000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2946.597514 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1946.597514 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12111.178208 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.overall_miss_latency 1341865775 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5515370000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_misses 455395 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 886470775 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5059975000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4053.427393 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.250869 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 33693000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 257148000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4085.659119 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3085.659119 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13969.811321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12969.811321 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3248099 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 11106000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2453099 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10311000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4085.659119 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13969.811321 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3248099 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 11106000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2453099 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10311000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4085.659119 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3085.659119 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13969.811321 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601856171 # number of overall hits -system.cpu.icache.overall_miss_latency 3248099 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 11106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2453099 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10311000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,23 +138,23 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 642.094524 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.943506 # Cycle average of tags in use system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3251.348149 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1946.946471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 84853684 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 339274000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 50811409 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 287078000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 325723 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 325723 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 28.960648 # Average number of references to valid blocks. @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3251.348149 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 84853684 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 339274000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 50811409 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 287078000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3251.348149 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1946.946471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 755815 # number of overall hits -system.cpu.l2cache.overall_miss_latency 84853684 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 339274000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses system.cpu.l2cache.overall_misses 26098 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 50811409 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 287078000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 903 # number of replacements system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24085.007455 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24875.090462 # Cycle average of tags in use system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 883 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2100480012 # number of cpu cycles simulated +system.cpu.numCycles 760892614000 # number of cpu cycles simulated system.cpu.num_insts 601856965 # Number of instructions executed system.cpu.num_refs 154862034 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 1cf7e8a9b..144c9c7fe 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out index f6ace951d..9c608a7e6 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt index 6cf88af9d..bdafc8603 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 713136 # Simulator instruction rate (inst/s) -host_mem_usage 148308 # Number of bytes of host memory used -host_seconds 2088.68 # Real time elapsed on the host -host_tick_rate 713136 # Simulator tick rate (ticks/s) +host_inst_rate 723585 # Simulator instruction rate (inst/s) +host_mem_usage 149576 # Number of bytes of host memory used +host_seconds 2058.52 # Real time elapsed on the host +host_tick_rate 361792205 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514860 # Number of instructions simulated -sim_seconds 0.001490 # Number of seconds simulated -sim_ticks 1489514859 # Number of ticks simulated +sim_seconds 0.744757 # Number of seconds simulated +sim_ticks 744757429500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1489514860 # number of cpu cycles simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr index e74a68c71..6fe2fe04f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr @@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0xb4000 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout index 3f5dab90b..b335083d4 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 21 2007 00:46:54 -M5 started Wed Mar 21 00:47:20 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 13:02:33 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1489514859 because target called exit() +Exiting @ tick 744757429500 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 75db6656a..ad1db1010 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out index 11cb72660..d8a055b90 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index f83fd185e..fc8b89b1e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 531377 # Simulator instruction rate (inst/s) -host_mem_usage 154376 # Number of bytes of host memory used -host_seconds 2803.12 # Real time elapsed on the host -host_tick_rate 1212716 # Simulator tick rate (ticks/s) +host_inst_rate 529254 # Simulator instruction rate (inst/s) +host_mem_usage 154916 # Number of bytes of host memory used +host_seconds 2814.36 # Real time elapsed on the host +host_tick_rate 733354350 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514860 # Number of instructions simulated -sim_seconds 0.003399 # Number of seconds simulated -sim_ticks 3399390003 # Number of ticks simulated +sim_seconds 2.063927 # Number of seconds simulated +sim_ticks 2063926516000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2848.782706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1848.782706 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12044.273310 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11044.273310 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 551182478 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2330326000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 357702478 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2136846000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3103.285714 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2103.285714 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 12285.714286 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11285.714286 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 21723 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 86000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 14723 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 79000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3023.717816 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2023.717816 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12168.472925 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11168.472925 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 785395584 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3160700000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 525650584 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2900955000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2949.038694 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12115.452590 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1336578062 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5491026000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 883353062 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5037801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2949.038694 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1949.038694 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12115.452590 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568905105 # number of overall hits -system.cpu.dcache.overall_miss_latency 1336578062 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5491026000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_misses 453225 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 883353062 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5037801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 449136 # number of replacements system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4068.114109 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.630445 # Cycle average of tags in use system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 33495000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 274426000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316447 # number of writebacks system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3979.992714 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2979.992714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13859.744991 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12859.744991 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4370032 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 15218000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 3272032 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 14120000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3979.992714 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13859.744991 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4370032 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 15218000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3272032 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 14120000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3979.992714 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2979.992714 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13859.744991 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1489513763 # number of overall hits -system.cpu.icache.overall_miss_latency 4370032 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 15218000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1098 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3272032 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 14120000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 865.251814 # Cycle average of tags in use +system.cpu.icache.tagsinuse 891.684170 # Cycle average of tags in use system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3215.864263 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1941.261615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 87423270 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 353405000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 52773197 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 299035000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3215.864263 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 87423270 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 353405000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 52773197 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 299035000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3214.799956 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1941.261615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12995.697580 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 743583 # number of overall hits -system.cpu.l2cache.overall_miss_latency 87423270 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 353405000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses system.cpu.l2cache.overall_misses 27194 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 52773197 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 299035000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2632 # number of replacements system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 23773.580402 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24267.041661 # Cycle average of tags in use system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 2531 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3399390003 # number of cpu cycles simulated +system.cpu.numCycles 2063926516000 # number of cpu cycles simulated system.cpu.num_insts 1489514860 # Number of instructions executed system.cpu.num_refs 569359656 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr index e74a68c71..6fe2fe04f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0xb4000 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index 8d54e9042..3741c6499 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 03:54:03 -M5 started Thu Mar 29 03:54:23 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 13:36:53 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 3399390003 because target called exit() +Exiting @ tick 2063926516000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 73a28200e..9b8d69888 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out index 2b86e6bfb..8a5c9fd62 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt index 41e6bfc52..530572b5d 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 624449 # Simulator instruction rate (inst/s) -host_mem_usage 148644 # Number of bytes of host memory used -host_seconds 2753.78 # Real time elapsed on the host -host_tick_rate 624449 # Simulator tick rate (ticks/s) +host_inst_rate 686638 # Simulator instruction rate (inst/s) +host_mem_usage 149820 # Number of bytes of host memory used +host_seconds 2504.37 # Real time elapsed on the host +host_tick_rate 343319148 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1719594534 # Number of instructions simulated -sim_seconds 0.001720 # Number of seconds simulated -sim_ticks 1719594533 # Number of ticks simulated +sim_seconds 0.859797 # Number of seconds simulated +sim_ticks 859797266500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1719594534 # number of cpu cycles simulated diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr index 9c09fd847..cf178f133 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr @@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0xa2000 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout index 6711761e8..bd861b307 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -25,9 +25,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 23 2007 22:37:06 -M5 started Fri Mar 23 22:37:22 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 14:23:47 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1719594533 because target called exit() +Exiting @ tick 859797266500 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index dfb81664a..9beb527ea 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out index e5ed0b288..5d5cc71c1 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index b11288b2d..c95331047 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 446147 # Simulator instruction rate (inst/s) -host_mem_usage 154148 # Number of bytes of host memory used -host_seconds 3854.32 # Real time elapsed on the host -host_tick_rate 13681801 # Simulator tick rate (ticks/s) +host_inst_rate 480485 # Simulator instruction rate (inst/s) +host_mem_usage 155316 # Number of bytes of host memory used +host_seconds 3578.87 # Real time elapsed on the host +host_tick_rate 745845171 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1719594534 # Number of instructions simulated -sim_seconds 0.052734 # Number of seconds simulated -sim_ticks 52734070003 # Number of ticks simulated +sim_seconds 2.669285 # Number of seconds simulated +sim_ticks 2669284585000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3420.154300 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2420.154300 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12893.226605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11893.226605 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 44693656366 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 168485217000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 31625925366 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 155417486000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3631.818182 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2631.818182 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 13090.909091 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 12090.909091 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 39950 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 144000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 28950 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 133000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3255.499606 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2255.499606 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12404.292450 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11404.292450 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5557128061 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 21174090000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3850131061 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 19467093000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3401.130933 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12836.737637 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 50250784427 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 189659307000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 35476056427 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 174884579000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3401.130933 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2401.130933 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12836.737637 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 760003458 # number of overall hits -system.cpu.dcache.overall_miss_latency 50250784427 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 189659307000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses system.cpu.dcache.overall_misses 14774728 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 35476056427 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 174884579000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 14770643 # number of replacements system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.978951 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.628585 # Cycle average of tags in use system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35437000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 3913237000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 4191356 # number of writebacks system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4032.295228 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3032.295228 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13991.120977 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12991.120977 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3633098 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 12606000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2732098 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11705000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4032.295228 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13991.120977 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3633098 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 12606000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 901 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2732098 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11705000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4032.295228 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3032.295228 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13991.120977 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1719593634 # number of overall hits -system.cpu.icache.overall_miss_latency 3633098 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 12606000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 901 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2732098 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11705000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 31 # number of replacements system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 750.163929 # Cycle average of tags in use +system.cpu.icache.tagsinuse 737.715884 # Cycle average of tags in use system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3097.556051 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1926.730191 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.785859 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.785859 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19151739918 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 80375791000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11912693395 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 68010081000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3097.556051 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.785859 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19151739918 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 80375791000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 11912693395 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 68010081000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3083.976361 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1926.730191 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12942.794779 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 12756915 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19151739918 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 80375791000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses system.cpu.l2cache.overall_misses 6210080 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 11912693395 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 68010081000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 6150087 # number of replacements system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 27594.660688 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 26129.060966 # Cycle average of tags in use system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 12316534000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 806915893000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1069081 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 52734070003 # number of cpu cycles simulated +system.cpu.numCycles 2669284585000 # number of cpu cycles simulated system.cpu.num_insts 1719594534 # Number of instructions executed system.cpu.num_refs 774793634 # Number of memory references system.cpu.workload.PROG:num_syscalls 632 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr index 9c09fd847..cf178f133 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr @@ -2,6 +2,5 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0xa2000 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index 7d97093d4..272fc2ce1 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -25,9 +25,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 15:41:48 -M5 started Thu Mar 29 15:42:11 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 15:05:32 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 52734070003 because target called exit() +Exiting @ tick 2669284585000 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 915a6967f..af33f850b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -64,12 +23,13 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -131,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -155,7 +114,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -307,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -331,7 +289,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -346,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -379,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -388,7 +346,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing egid=100 env= euid=100 @@ -403,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -417,12 +376,3 @@ range=0:134217727 zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out index 80e067401..cea0c0402 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -31,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -170,9 +168,10 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -251,9 +250,9 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -282,16 +281,15 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -320,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -358,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -366,52 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 +block_size=64 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 9d00cb146..f3f9842a2 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 38046005 # Number of BTB hits -global.BPredUnit.BTBLookups 46765160 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1072 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 5897447 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 36345249 # Number of conditional branches predicted -global.BPredUnit.lookups 64275681 # Number of BP lookups -global.BPredUnit.usedRAS 12928446 # Number of times the RAS was used to get a target. -host_inst_rate 88491 # Simulator instruction rate (inst/s) -host_mem_usage 183984 # Number of bytes of host memory used -host_seconds 4244.22 # Real time elapsed on the host -host_tick_rate 69460 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 64217134 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 49870920 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 126084683 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 92646936 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 36408912 # Number of BTB hits +global.BPredUnit.BTBLookups 43706931 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1105 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 5391565 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 33884568 # Number of conditional branches predicted +global.BPredUnit.lookups 59377619 # Number of BP lookups +global.BPredUnit.usedRAS 11768977 # Number of times the RAS was used to get a target. +host_inst_rate 72337 # Simulator instruction rate (inst/s) +host_mem_usage 157124 # Number of bytes of host memory used +host_seconds 5192.02 # Real time elapsed on the host +host_tick_rate 28301038 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 55015552 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 43012918 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 120933927 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 90962569 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574675 # Number of instructions simulated -sim_seconds 0.000295 # Number of seconds simulated -sim_ticks 294803028 # Number of ticks simulated -system.cpu.commit.COM:branches 44587523 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 16167573 # number cycles where commit BW limit reached +sim_insts 375574819 # Number of instructions simulated +sim_seconds 0.146939 # Number of seconds simulated +sim_ticks 146939447000 # Number of ticks simulated +system.cpu.commit.COM:branches 44587532 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 12019969 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 260352657 +system.cpu.commit.COM:committed_per_cycle.samples 280687503 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 139362663 5352.84% - 1 37755491 1450.17% - 2 23927219 919.03% - 3 17243764 662.32% - 4 9550787 366.84% - 5 7718539 296.46% - 6 5199548 199.71% - 7 3427073 131.63% - 8 16167573 620.99% + 0 153383398 5464.56% + 1 43042738 1533.48% + 2 19983570 711.95% + 3 20747693 739.17% + 4 12078292 430.31% + 5 11042042 393.39% + 6 5000100 178.14% + 7 3389701 120.76% + 8 12019969 428.23% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 398664447 # Number of instructions committed -system.cpu.commit.COM:loads 100651988 # Number of loads committed +system.cpu.commit.COM:count 398664594 # Number of instructions committed +system.cpu.commit.COM:loads 100651995 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 174183388 # Number of memory references committed +system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5893264 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 398664447 # The number of committed instructions +system.cpu.commit.branchMispredicts 5387368 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 98024957 # The number of squashed insts skipped by commit -system.cpu.committedInsts 375574675 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574675 # Number of Instructions Simulated -system.cpu.cpi 0.784939 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.784939 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 94465294 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5573.350269 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5155.812183 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94463621 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 9324215 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1673 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 688 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5078475 # number of ReadReq MSHR miss cycles +system.cpu.commit.commitSquashedInsts 80492961 # The number of squashed insts skipped by commit +system.cpu.committedInsts 375574819 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated +system.cpu.cpi 0.782478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.782478 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 96341397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5402.232747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4689.672802 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 96339919 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 7984500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1478 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 4586500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 5442.694460 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5169.706416 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73508218 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 68082665 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000170 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 12509 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 9314 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 16517212 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_misses 978 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 5858.789942 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4984.052533 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73511622 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 53356000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000124 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 9107 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5909 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 15939000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2708.631579 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3690.984252 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40184.650478 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 19 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 2032 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 51464 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 7500080 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 3198 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40673.261734 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 167986021 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5458.107460 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency -system.cpu.dcache.demand_hits 167971839 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 77406880 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_misses 14182 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 10002 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 21595687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 169862126 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5795.040151 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169851541 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 61340500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000062 # miss rate for demand accesses +system.cpu.dcache.demand_misses 10585 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6409 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20525500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4180 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 167986021 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5458.107460 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 169862126 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5795.040151 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 167971839 # number of overall hits -system.cpu.dcache.overall_miss_latency 77406880 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_misses 14182 # number of overall misses -system.cpu.dcache.overall_mshr_hits 10002 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 21595687 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 169851541 # number of overall hits +system.cpu.dcache.overall_miss_latency 61340500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000062 # miss rate for overall accesses +system.cpu.dcache.overall_misses 10585 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6409 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20525500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4180 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 784 # number of replacements -system.cpu.dcache.sampled_refs 4180 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 781 # number of replacements +system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3190.140908 # Cycle average of tags in use -system.cpu.dcache.total_refs 167971839 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3294.483088 # Cycle average of tags in use +system.cpu.dcache.total_refs 169851541 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 637 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 19324711 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4274 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11555430 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 538406721 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 137426232 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 102617017 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 16124012 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12594 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 984698 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 64275681 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66044385 # Number of cache lines fetched -system.cpu.fetch.Cycles 172472243 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1233740 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 552850318 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6527825 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.232481 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66044385 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50974451 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.999627 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 7091571 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4262 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 10528111 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 508290393 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 182764130 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 90473414 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 13191511 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12840 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 358389 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 59377619 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 61063139 # Number of cache lines fetched +system.cpu.fetch.Cycles 154416855 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2298760 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 522129068 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 5723447 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.202048 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 61063139 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 48177889 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.776680 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 276476670 +system.cpu.fetch.rateDist.samples 293879015 system.cpu.fetch.rateDist.min_value 0 - 0 170048750 6150.56% - 1 11707777 423.46% - 2 11563595 418.25% - 3 7250668 262.25% - 4 16393688 592.95% - 5 9178756 331.99% - 6 6871715 248.55% - 7 4129243 149.35% - 8 39332478 1422.63% + 0 200525300 6823.40% + 1 7846897 267.01% + 2 7291722 248.12% + 3 6200462 210.99% + 4 13845529 471.13% + 5 7438768 253.12% + 6 7492914 254.97% + 7 2335483 79.47% + 8 40901940 1391.80% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 66044384 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4697.455355 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3736.572860 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66039333 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 23726847 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 5051 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1160 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 14539005 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000059 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3891 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 5023.260870 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16972.329221 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_accesses 61063139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5151.654640 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4230.492813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 61059120 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 20704500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4019 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 16482000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 15672.258727 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 69 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 346605 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66044384 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4697.455355 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency -system.cpu.icache.demand_hits 66039333 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 23726847 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses -system.cpu.icache.demand_misses 5051 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1160 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 14539005 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000059 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3891 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 61063139 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5151.654640 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency +system.cpu.icache.demand_hits 61059120 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 20704500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000066 # miss rate for demand accesses +system.cpu.icache.demand_misses 4019 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 16482000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 66044384 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4697.455355 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66039333 # number of overall hits -system.cpu.icache.overall_miss_latency 23726847 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses -system.cpu.icache.overall_misses 5051 # number of overall misses -system.cpu.icache.overall_mshr_hits 1160 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 14539005 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000059 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3891 # number of overall MSHR misses +system.cpu.icache.overall_accesses 61063139 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5151.654640 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 61059120 # number of overall hits +system.cpu.icache.overall_miss_latency 20704500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000066 # miss rate for overall accesses +system.cpu.icache.overall_misses 4019 # number of overall misses +system.cpu.icache.overall_mshr_hits 123 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 16482000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1971 # number of replacements -system.cpu.icache.sampled_refs 3891 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1976 # number of replacements +system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1776.887115 # Cycle average of tags in use -system.cpu.icache.total_refs 66039333 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1822.947356 # Cycle average of tags in use +system.cpu.icache.total_refs 61059120 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 18326359 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 51280930 # Number of branches executed -system.cpu.iew.EXEC:nop 27455299 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.521589 # Inst execution rate -system.cpu.iew.EXEC:refs 191354897 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 79285920 # Number of stores executed +system.cpu.idleCycles 6367 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 50329288 # Number of branches executed +system.cpu.iew.EXEC:nop 26718868 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.409679 # Inst execution rate +system.cpu.iew.EXEC:refs 190324589 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 79889528 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 293982680 # num instructions consuming a value -system.cpu.iew.WB:count 415403944 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.694108 # average fanout of values written-back +system.cpu.iew.WB:consumers 266244037 # num instructions consuming a value +system.cpu.iew.WB:count 411128901 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.717332 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 204055700 # num instructions producing a value -system.cpu.iew.WB:rate 1.502492 # insts written-back per cycle -system.cpu.iew.WB:sent 416259284 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6316593 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2856011 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126084683 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 7411275 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92646936 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 496689311 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 112068977 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8996952 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 420683841 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 114816 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 190985280 # num instructions producing a value +system.cpu.iew.WB:rate 1.398973 # insts written-back per cycle +system.cpu.iew.WB:sent 411485990 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6032644 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1137801 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 120933927 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 222 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6771454 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 90962569 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 479157588 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 110435061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10298797 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 414275208 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1986 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 16124012 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 416926 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 183286 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 727659 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 9888553 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 47660 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 21083 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 13191511 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 115109 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 7097511 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3223 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 81366 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 183286 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 25432695 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 19115536 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 81366 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 996952 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5319641 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.273985 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.273985 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 429680793 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 404889 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176320 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 20281932 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 17431167 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 404889 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 802823 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5229821 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.277991 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.277991 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 424574005 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 33581 0.01% # Type of FU issued - IntAlu 167723328 39.03% # Type of FU issued - IntMult 2137299 0.50% # Type of FU issued + IntAlu 163144501 38.43% # Type of FU issued + IntMult 2125088 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 34928239 8.13% # Type of FU issued - FloatCmp 8071357 1.88% # Type of FU issued - FloatCvt 3141242 0.73% # Type of FU issued - FloatMult 16626981 3.87% # Type of FU issued - FloatDiv 1577676 0.37% # Type of FU issued + FloatAdd 34659405 8.16% # Type of FU issued + FloatCmp 7790033 1.83% # Type of FU issued + FloatCvt 2881594 0.68% # Type of FU issued + FloatMult 16618307 3.91% # Type of FU issued + FloatDiv 1566111 0.37% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 114426564 26.63% # Type of FU issued - MemWrite 81014526 18.85% # Type of FU issued + MemRead 113765764 26.80% # Type of FU issued + MemWrite 81989621 19.31% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 9055324 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.021075 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 9576176 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.022555 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 66610 0.74% # attempts to use FU when none available + IntAlu 12415 0.13% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 110487 1.22% # attempts to use FU when none available - FloatCmp 35273 0.39% # attempts to use FU when none available - FloatCvt 2828 0.03% # attempts to use FU when none available - FloatMult 2149754 23.74% # attempts to use FU when none available - FloatDiv 664669 7.34% # attempts to use FU when none available + FloatAdd 46832 0.49% # attempts to use FU when none available + FloatCmp 11338 0.12% # attempts to use FU when none available + FloatCvt 25702 0.27% # attempts to use FU when none available + FloatMult 2984764 31.17% # attempts to use FU when none available + FloatDiv 331535 3.46% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 4545406 50.20% # attempts to use FU when none available - MemWrite 1480297 16.35% # attempts to use FU when none available + MemRead 4942933 51.62% # attempts to use FU when none available + MemWrite 1220657 12.75% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 276476670 +system.cpu.iq.ISSUE:issued_per_cycle.samples 293879015 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 105552217 3817.76% - 1 55104063 1993.08% - 2 43517427 1574.00% - 3 31483356 1138.73% - 4 21726208 785.82% - 5 11633875 420.79% - 6 4624667 167.27% - 7 2409257 87.14% - 8 425600 15.39% + 0 129735390 4414.59% + 1 52072154 1771.89% + 2 39787134 1353.86% + 3 29621395 1007.95% + 4 21763636 740.56% + 5 12600620 428.77% + 6 4911147 167.11% + 7 2561440 87.16% + 8 826099 28.11% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.554130 # Inst issue rate -system.cpu.iq.iqInstsAdded 469233772 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 429680793 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 93305351 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1513608 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 71392848 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:rate 1.444724 # Inst issue rate +system.cpu.iq.iqInstsAdded 452438498 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 424574005 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 222 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 75756994 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1109878 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 55099010 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4399.297838 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2193.473956 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 717 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 32348037 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.911152 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7353 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16128614 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7353 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 637 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 637 # number of WriteReqNoAck|Writeback hits +system.cpu.l2cache.ReadReq_avg_miss_latency 4677.770224 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2436.233855 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 715 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 34405000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.911400 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7355 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 17918500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911400 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7355 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 637 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 637 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.184143 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.183821 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4399.297838 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 32348037 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.911152 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7353 # number of demand (read+write) misses +system.cpu.l2cache.demand_avg_miss_latency 4677.770224 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 715 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 34405000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.911400 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7355 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 16128614 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.911152 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7353 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.911400 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7355 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4399.297838 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 4677.770224 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1354 # number of overall hits -system.cpu.l2cache.overall_miss_latency 32348037 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.844493 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7353 # number of overall misses +system.cpu.l2cache.overall_hits 1352 # number of overall hits +system.cpu.l2cache.overall_miss_latency 34405000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.844723 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7355 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 16128614 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.844493 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7353 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.844723 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7355 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,31 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7353 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7355 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6415.706550 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1354 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 6644.823451 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1352 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 276476670 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8743693 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 259532206 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 653030 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 142074266 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8196045 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 687565953 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 524563034 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 338654872 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 98656303 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 16124012 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 9950983 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 79122666 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 927413 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 40317 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 23109451 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 249 # count of temporary serializing insts renamed -system.cpu.timesIdled 6216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 293879015 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 3715266 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 115195 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 185747540 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2602652 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 654991501 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 496454048 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 320284080 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 87805227 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 13191511 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 3048084 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 60751739 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 371387 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37057 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 7965999 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 243 # count of temporary serializing insts renamed +system.cpu.timesIdled 133 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr index d414f5cfe..4bb0d9bbe 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr @@ -1,10 +1,11 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 039e2d4ce..50ed34325 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index 088cd1a9f..58022eaf1 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -74,7 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic egid=100 env= euid=100 @@ -89,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -100,14 +60,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out index bec900d0f..b7319250f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -30,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -49,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -57,51 +56,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index a308f5e36..2e2beec40 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 841426 # Simulator instruction rate (inst/s) -host_mem_usage 147172 # Number of bytes of host memory used -host_seconds 473.80 # Real time elapsed on the host -host_tick_rate 841425 # Simulator tick rate (ticks/s) +host_inst_rate 828868 # Simulator instruction rate (inst/s) +host_mem_usage 151076 # Number of bytes of host memory used +host_seconds 480.97 # Real time elapsed on the host +host_tick_rate 414433819 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664450 # Number of instructions simulated -sim_seconds 0.000399 # Number of seconds simulated -sim_ticks 398664449 # Number of ticks simulated +sim_insts 398664597 # Number of instructions simulated +sim_seconds 0.199332 # Number of seconds simulated +sim_ticks 199332298000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 398664450 # number of cpu cycles simulated -system.cpu.num_insts 398664450 # Number of instructions executed -system.cpu.num_refs 174183390 # Number of memory references +system.cpu.numCycles 398664597 # number of cpu cycles simulated +system.cpu.num_insts 398664597 # Number of instructions executed +system.cpu.num_refs 174183399 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr index 1d6957eca..4bb0d9bbe 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr @@ -1,9 +1,11 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout index 039e2d4ce..5f057b8dd 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.183333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index 452538e49..ca3706b7b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -62,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -101,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -140,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -173,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -182,11 +154,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin output=cout @@ -197,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out index 602da9705..c3af4f4b3 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,15 +20,16 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -64,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -101,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -139,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -177,25 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 328856ce7..28c7cc183 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 689508 # Simulator instruction rate (inst/s) -host_mem_usage 185012 # Number of bytes of host memory used -host_seconds 578.19 # Real time elapsed on the host -host_tick_rate 1033135 # Simulator tick rate (ticks/s) +host_inst_rate 579996 # Simulator instruction rate (inst/s) +host_mem_usage 156556 # Number of bytes of host memory used +host_seconds 687.36 # Real time elapsed on the host +host_tick_rate 824955659 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664450 # Number of instructions simulated -sim_seconds 0.000597 # Number of seconds simulated -sim_ticks 597346012 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94753532 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3758780 # number of ReadReq miss cycles +sim_insts 398664611 # Number of instructions simulated +sim_seconds 0.567040 # Number of seconds simulated +sim_ticks 567040254000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13741.052632 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 13054000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 12104000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 13962.523423 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12962.523423 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 44708000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 41506000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13911.849711 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 57762000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 53610000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168271057 # number of overall hits -system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles +system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13911.849711 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 168271068 # number of overall hits +system.cpu.dcache.overall_miss_latency 57762000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4152 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 53610000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,54 +76,54 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3289.654807 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks -system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 398664612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 13745.167438 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12745.167438 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 398660939 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 50486000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 46813000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 108538.235502 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency -system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 398664612 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 13745.167438 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency +system.cpu.icache.demand_hits 398660939 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 50486000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses -system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses +system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 46813000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 398660777 # number of overall hits -system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles +system.cpu.icache.overall_accesses 398664612 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 13745.167438 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 398660939 # number of overall hits +system.cpu.icache.overall_miss_latency 50486000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.overall_misses 3674 # number of overall misses +system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 46813000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,60 +135,60 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1770 # number of replacements -system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1769 # number of replacements +system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use -system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1795.458615 # Cycle average of tags in use +system.cpu.icache.total_refs 398660939 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 93262000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 78914000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks. +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.177865 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 93262000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 78914000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1276 # number of overall hits -system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7175 # number of overall misses +system.cpu.l2cache.overall_miss_latency 93262000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7174 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 78914000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -201,16 +201,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 6483.455048 # Cycle average of tags in use system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 597346012 # number of cpu cycles simulated -system.cpu.num_insts 398664450 # Number of instructions executed -system.cpu.num_refs 174183390 # Number of memory references +system.cpu.numCycles 567040254000 # number of cpu cycles simulated +system.cpu.num_insts 398664611 # Number of instructions executed +system.cpu.num_refs 174183401 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr index 8534c55aa..4bb0d9bbe 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr @@ -1,10 +1,11 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera opening surfaces file chair.surfaces reading data +warn: Increasing stack size by one page. processing 8parts Grid measure is 6 by 3.0001 by 6 cell dimension is 0.863065 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 039e2d4ce..f9d497506 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.000000 +OO-style eon Time= 0.566667 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index 59c6e25e2..1b858fca2 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -59,11 +33,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin output=cout @@ -74,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out index c6e4aa136..0e4ea1cb5 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,15 +20,16 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -50,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -58,23 +56,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt index 9db3f64bc..0f58a9003 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1149393 # Simulator instruction rate (inst/s) -host_mem_usage 177516 # Number of bytes of host memory used -host_seconds 1747.87 # Real time elapsed on the host -host_tick_rate 1149393 # Simulator tick rate (ticks/s) +host_inst_rate 855891 # Simulator instruction rate (inst/s) +host_mem_usage 151228 # Number of bytes of host memory used +host_seconds 2347.25 # Real time elapsed on the host +host_tick_rate 427945543 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987607 # Number of instructions simulated -sim_seconds 0.002009 # Number of seconds simulated -sim_ticks 2008987606 # Number of ticks simulated +sim_seconds 1.004494 # Number of seconds simulated +sim_ticks 1004493803000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2008987607 # number of cpu cycles simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr index bc72461c8..a6133a5ee 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr @@ -1,3 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) +warn: Increasing stack size by one page. diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 5f64dcebd..dd36bbf60 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -62,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -101,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -140,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -173,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -182,11 +154,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin output=cout @@ -197,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out index 6998f4828..676b65128 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,15 +20,16 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -64,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -101,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -139,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -177,25 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 45f793ab7..6aa1ee5aa 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,35 +1,35 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 752631 # Simulator instruction rate (inst/s) -host_mem_usage 230876 # Number of bytes of host memory used -host_seconds 2669.29 # Real time elapsed on the host -host_tick_rate 2836913 # Simulator tick rate (ticks/s) +host_inst_rate 622738 # Simulator instruction rate (inst/s) +host_mem_usage 156744 # Number of bytes of host memory used +host_seconds 3226.05 # Real time elapsed on the host +host_tick_rate 852686846 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987607 # Number of instructions simulated -sim_seconds 0.007573 # Number of seconds simulated -sim_ticks 7572532003 # Number of ticks simulated +sim_seconds 2.750814 # Number of seconds simulated +sim_ticks 2750814393000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3107.171986 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171986 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13971.031250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12971.031250 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4530853333 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 20372446000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3072661333 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 18914254000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3884.267929 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.267929 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13873.860351 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12873.860351 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 279480846 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 998252000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 207528846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 926300000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3143.713388 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13966.461980 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4810334179 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 21370698000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3280190179 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 19840554000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3143.713388 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 13966.461980 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 720334778 # number of overall hits -system.cpu.dcache.overall_miss_latency 4810334179 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 21370698000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_misses 1530144 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3280190179 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 19840554000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,22 +76,22 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.479154 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.422371 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35165000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 702832000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3103.627312 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.627312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12448.659872 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11448.659872 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32886035 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 131906000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 22290035 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 121310000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3103.627312 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12448.659872 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32886035 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 131906000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 22290035 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 121310000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3103.627312 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 12448.659872 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2008977012 # number of overall hits -system.cpu.icache.overall_miss_latency 32886035 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 131906000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses system.cpu.icache.overall_misses 10596 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 22290035 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 121310000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1471.254279 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.610505 # Cycle average of tags in use system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2153.828221 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.659139 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3245521901 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19589206000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1675116913 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 16575482000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) @@ -159,8 +159,8 @@ system.cpu.l2cache.Writeback_miss_rate 0.014399 # mi system.cpu.l2cache.Writeback_misses 1074 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 0.014399 # mshr miss rate for Writeback accesses system.cpu.l2cache.Writeback_mshr_misses 1074 # number of Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.071269 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2153.828221 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3245521901 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 19589206000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1675116913 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 16575482000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2152.294196 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 12990.740986 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 107393 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3245521901 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 19589206000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses system.cpu.l2cache.overall_misses 1507936 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1675116913 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 16575482000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 1474094 # number of replacements system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32444.706916 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32753.638584 # Cycle average of tags in use system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 164189000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 2394479000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66804 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 7572532003 # number of cpu cycles simulated +system.cpu.numCycles 2750814393000 # number of cpu cycles simulated system.cpu.num_insts 2008987607 # Number of instructions executed system.cpu.num_refs 722390435 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr index bc72461c8..a6133a5ee 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr @@ -1,3 +1,4 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 0, ...) +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index cf4e15676..8c32bfa79 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -64,12 +23,13 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -131,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -155,7 +114,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -307,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -331,7 +289,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -346,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -379,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -388,7 +346,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing egid=100 env= euid=100 @@ -403,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out index 52c225902..071b401c0 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -31,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -170,9 +168,10 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -251,9 +250,9 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -282,16 +281,15 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -320,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -358,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -366,40 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 +block_size=64 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 3069385f0..bf6f402cd 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 13202034 # Number of BTB hits -global.BPredUnit.BTBLookups 22107115 # Number of BTB lookups -global.BPredUnit.RASInCorrect 30370 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 454360 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 16498204 # Number of conditional branches predicted -global.BPredUnit.lookups 27047110 # Number of BP lookups -global.BPredUnit.usedRAS 4878193 # Number of times the RAS was used to get a target. -host_inst_rate 69520 # Simulator instruction rate (inst/s) -host_mem_usage 239908 # Number of bytes of host memory used -host_seconds 1144.87 # Real time elapsed on the host -host_tick_rate 987535 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 14725847 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11490673 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 28863760 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 16312214 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 7411086 # Number of BTB hits +global.BPredUnit.BTBLookups 13158968 # Number of BTB lookups +global.BPredUnit.RASInCorrect 32147 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 450892 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 9746581 # Number of conditional branches predicted +global.BPredUnit.lookups 14988034 # Number of BP lookups +global.BPredUnit.usedRAS 1776543 # Number of times the RAS was used to get a target. +host_inst_rate 99683 # Simulator instruction rate (inst/s) +host_mem_usage 159476 # Number of bytes of host memory used +host_seconds 798.45 # Real time elapsed on the host +host_tick_rate 35303213 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 9747985 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 9298064 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 21418262 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 15459606 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.001131 # Number of seconds simulated -sim_ticks 1130602014 # Number of ticks simulated +sim_seconds 0.028188 # Number of seconds simulated +sim_ticks 28187684500 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3893678 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3230574 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 89505192 +system.cpu.commit.COM:committed_per_cycle.samples 55590975 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 62882698 7025.59% - 1 8753972 978.04% - 2 5175203 578.20% - 3 3243621 362.39% - 4 2169519 242.39% - 5 1432847 160.09% - 6 1161882 129.81% - 7 791772 88.46% - 8 3893678 435.02% + 0 26501535 4767.24% + 1 10970497 1973.43% + 2 5466463 983.34% + 3 3506601 630.79% + 4 2372940 426.86% + 5 1558557 280.36% + 6 1098347 197.58% + 7 885461 159.28% + 8 3230574 581.13% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 359967 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 355366 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 21665941 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4551161 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 14.205014 # CPI: Cycles Per Instruction -system.cpu.cpi_total 14.205014 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 19540231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4453.766964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3237.815878 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19382637 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 701886951 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.008065 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 157594 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 95950 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 199591922 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003155 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61644 # number of ReadReq MSHR misses +system.cpu.cpi 0.708309 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.708309 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 20049834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4729.134904 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3349.390829 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19907503 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 673102500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007099 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 142331 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 80854 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 205910500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003066 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61477 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4830.124895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3999.409028 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13942631 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3239786953 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.045899 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 670746 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 527274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 573803212 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 3029.723364 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4119.889460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14053363 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1696687500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.038322 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 560014 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 416536 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 591113500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143472 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3332.672727 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3759.399862 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 162.470348 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 125901 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 366594 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 473312202 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 143478 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 165.699134 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34153608 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4758.521747 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33325268 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3941673904 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.024253 # miss rate for demand accesses -system.cpu.dcache.demand_misses 828340 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 623224 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 773395134 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006006 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 205116 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34663211 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3374.111014 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33960866 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2369790000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020262 # miss rate for demand accesses +system.cpu.dcache.demand_misses 702345 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 497390 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 797024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005913 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 204955 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34153608 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4758.521747 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34663211 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3374.111014 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33325268 # number of overall hits -system.cpu.dcache.overall_miss_latency 3941673904 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.024253 # miss rate for overall accesses -system.cpu.dcache.overall_misses 828340 # number of overall misses -system.cpu.dcache.overall_mshr_hits 623224 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 773395134 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006006 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 205116 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33960866 # number of overall hits +system.cpu.dcache.overall_miss_latency 2369790000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020262 # miss rate for overall accesses +system.cpu.dcache.overall_misses 702345 # number of overall misses +system.cpu.dcache.overall_mshr_hits 497390 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 797024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005913 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 204955 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 201020 # number of replacements -system.cpu.dcache.sampled_refs 205116 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200859 # number of replacements +system.cpu.dcache.sampled_refs 204955 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4057.039034 # Cycle average of tags in use -system.cpu.dcache.total_refs 33325268 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 27784000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147771 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 11948269 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95198 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3558048 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 131593428 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 51674084 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 25481309 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 4702945 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 281359 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 401531 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 27047110 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 22733117 # Number of cache lines fetched -system.cpu.fetch.Cycles 51481541 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 159026 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 148267180 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 3966980 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.287100 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 22733117 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 18080227 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.573826 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4080.110580 # Cycle average of tags in use +system.cpu.dcache.total_refs 33960866 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 144827000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147753 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 583473 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 97307 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3380270 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 95203508 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37386702 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 17614461 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 784542 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 292514 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 6340 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 14988034 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 12416477 # Number of cache lines fetched +system.cpu.fetch.Cycles 30119953 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 260035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 96279919 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 467393 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.265861 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 12416477 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9187629 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.707832 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 94208138 +system.cpu.fetch.rateDist.samples 56375518 system.cpu.fetch.rateDist.min_value 0 - 0 65459635 6948.41% - 1 1687117 179.08% - 2 1748812 185.63% - 3 1938924 205.81% - 4 6981531 741.08% - 5 6100701 647.58% - 6 758078 80.47% - 7 1979150 210.08% - 8 7554190 801.86% + 0 38672046 6859.72% + 1 1321940 234.49% + 2 1201428 213.11% + 3 1338454 237.42% + 4 3789980 672.27% + 5 1624217 288.11% + 6 592859 105.16% + 7 975150 172.97% + 8 6859444 1216.74% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 22733116 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3345.551905 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2359.548288 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 22631700 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 339292492 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.004461 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 101416 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 13878 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 206550138 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.003851 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 87538 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 12416477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3477.694454 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2488.876340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 12330467 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 299116500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006927 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 86010 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1011 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 211552000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006846 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 84999 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3731.567010 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 258.538675 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 145.066024 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 97 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 361962 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 22733116 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3345.551905 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency -system.cpu.icache.demand_hits 22631700 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 339292492 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.004461 # miss rate for demand accesses -system.cpu.icache.demand_misses 101416 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 13878 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 206550138 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.003851 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 87538 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 12416477 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3477.694454 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency +system.cpu.icache.demand_hits 12330467 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 299116500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006927 # miss rate for demand accesses +system.cpu.icache.demand_misses 86010 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1011 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 211552000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006846 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 84999 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 22733116 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3345.551905 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency +system.cpu.icache.overall_accesses 12416477 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3477.694454 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 22631700 # number of overall hits -system.cpu.icache.overall_miss_latency 339292492 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.004461 # miss rate for overall accesses -system.cpu.icache.overall_misses 101416 # number of overall misses -system.cpu.icache.overall_mshr_hits 13878 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 206550138 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.003851 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 87538 # number of overall MSHR misses +system.cpu.icache.overall_hits 12330467 # number of overall hits +system.cpu.icache.overall_miss_latency 299116500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006927 # miss rate for overall accesses +system.cpu.icache.overall_misses 86010 # number of overall misses +system.cpu.icache.overall_mshr_hits 1011 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 211552000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006846 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 84999 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 85490 # number of replacements -system.cpu.icache.sampled_refs 87537 # Sample count of references to valid blocks. +system.cpu.icache.replacements 82951 # number of replacements +system.cpu.icache.sampled_refs 84999 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1835.330854 # Cycle average of tags in use -system.cpu.icache.total_refs 22631700 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1918.432617 # Cycle average of tags in use +system.cpu.icache.total_refs 12330467 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 24669337000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1036393877 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14379719 # Number of branches executed -system.cpu.iew.EXEC:nop 9265977 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.989418 # Inst execution rate -system.cpu.iew.EXEC:refs 43156162 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15338261 # Number of stores executed +system.cpu.idleCycles 25301 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14196900 # Number of branches executed +system.cpu.iew.EXEC:nop 9006488 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.455602 # Inst execution rate +system.cpu.iew.EXEC:refs 36045074 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15052480 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 46157981 # num instructions consuming a value -system.cpu.iew.WB:count 86105601 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.741496 # average fanout of values written-back +system.cpu.iew.WB:consumers 39431808 # num instructions consuming a value +system.cpu.iew.WB:count 81784655 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.769564 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 34225955 # num instructions producing a value -system.cpu.iew.WB:rate 0.913993 # insts written-back per cycle -system.cpu.iew.WB:sent 86171133 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 389534 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3213991 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 28863760 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4784 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1402526 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16312214 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 110003367 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 27817901 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 453087 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 93211232 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 28742 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 30345313 # num instructions producing a value +system.cpu.iew.WB:rate 1.450712 # insts written-back per cycle +system.cpu.iew.WB:sent 81828309 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 387091 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10156 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 21418262 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4652 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 597409 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 15459606 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 92891480 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 20992594 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 333391 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 82060341 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 141 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 12962 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 4702945 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 194395 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 1528 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 6922047 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1365052 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5008 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 784542 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 478 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 828061 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 554 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3825 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1528 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 8484361 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1467595 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3825 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 102872 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 286662 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.070398 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.070398 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 93664319 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 19340 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1425 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1038863 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 614987 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19340 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 103732 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 283359 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.411814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.411814 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 82393732 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 49995908 53.38% # Type of FU issued - IntMult 43196 0.05% # Type of FU issued + IntAlu 45892607 55.70% # Type of FU issued + IntMult 44107 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 123595 0.13% # Type of FU issued - FloatCmp 86 0.00% # Type of FU issued - FloatCvt 122386 0.13% # Type of FU issued - FloatMult 51 0.00% # Type of FU issued - FloatDiv 37853 0.04% # Type of FU issued + FloatAdd 116900 0.14% # Type of FU issued + FloatCmp 87 0.00% # Type of FU issued + FloatCvt 120453 0.15% # Type of FU issued + FloatMult 50 0.00% # Type of FU issued + FloatDiv 37768 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 27919833 29.81% # Type of FU issued - MemWrite 15421411 16.46% # Type of FU issued + MemRead 21065064 25.57% # Type of FU issued + MemWrite 15116696 18.35% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1229792 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013130 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 898002 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010899 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 83895 6.82% # attempts to use FU when none available + IntAlu 168043 18.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 589327 47.92% # attempts to use FU when none available - MemWrite 556570 45.26% # attempts to use FU when none available + MemRead 309725 34.49% # attempts to use FU when none available + MemWrite 420234 46.80% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 94208138 +system.cpu.iq.ISSUE:issued_per_cycle.samples 56375518 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 54322746 5766.25% - 1 13333515 1415.33% - 2 10626230 1127.95% - 3 8813553 935.54% - 4 4440243 471.32% - 5 1597603 169.58% - 6 685526 72.77% - 7 334234 35.48% - 8 54488 5.78% + 0 22612550 4011.06% + 1 13769796 2442.51% + 2 7834961 1389.78% + 3 4029672 714.79% + 4 3712649 658.56% + 5 1993297 353.57% + 6 1449259 257.07% + 7 434309 77.04% + 8 539025 95.61% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.994227 # Inst issue rate -system.cpu.iq.iqInstsAdded 100732606 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 93664319 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4784 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 20911338 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 73995 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 16334966 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 292646 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3929.598028 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2043.469607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 122985 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 666699531 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.579748 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 169661 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 346697097 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 169661 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147771 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147307 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 1.461516 # Inst issue rate +system.cpu.iq.iqInstsAdded 83880340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 82393732 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4652 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4104955 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 35761 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 69 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2730801 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 289883 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4226.385671 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2218.670959 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 120272 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 716841500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.585102 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 169611 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 376311000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.585102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 169611 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147292 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.003120 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 461 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.003120 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 461 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.593139 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.577516 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 292646 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3929.598028 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 122985 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 666699531 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.579748 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 169661 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 289883 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4226.385671 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 120272 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 716841500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.585102 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 169611 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 346697097 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.579748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 169661 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 376311000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.585102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 169611 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 440417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3918.880417 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 437636 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4214.929559 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 270292 # number of overall hits -system.cpu.l2cache.overall_miss_latency 666699531 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.386282 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 170125 # number of overall misses +system.cpu.l2cache.overall_hits 267564 # number of overall hits +system.cpu.l2cache.overall_miss_latency 716841500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.388615 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 170072 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 346697097 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.385228 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 169661 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 376311000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.387562 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 169611 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 136892 # number of replacements -system.cpu.l2cache.sampled_refs 169660 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 136843 # number of replacements +system.cpu.l2cache.sampled_refs 169611 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30349.297230 # Cycle average of tags in use -system.cpu.l2cache.total_refs 270292 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 625483000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115938 # number of writebacks -system.cpu.numCycles 94208138 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7563765 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 32058.525051 # Cycle average of tags in use +system.cpu.l2cache.total_refs 267564 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 13792867000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115936 # number of writebacks +system.cpu.numCycles 56375518 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 238131 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 87866 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 52361095 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 3315491 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3509 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 154857350 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 130101763 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 82913656 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 25182526 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 4702945 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 3542613 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 30366775 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 855194 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 4773 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 6398047 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 4771 # count of temporary serializing insts renamed -system.cpu.timesIdled 275758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31030 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 37626801 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 240022 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 113729051 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 94390828 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 56605918 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 17378620 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 784542 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 281505 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4059037 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 65919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 4656 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 641192 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 4654 # count of temporary serializing insts renamed +system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg index 327142d7c..472b08431 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg @@ -134,7 +134,7 @@ DB Handle Chunk's StackPtr = 20797 DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 40054800 + KERNEL in CORE[ 1] Restored @ 4005c800 OPEN File ./input/lendian.wnv *Status = 0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 179e8ea77..5339d79af 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -59,11 +33,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout @@ -74,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out index 725aaed50..bf2c5c795 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,15 +20,16 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -50,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -58,23 +56,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index 9c60e1316..16fb6367e 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1347543 # Simulator instruction rate (inst/s) -host_mem_usage 179988 # Number of bytes of host memory used -host_seconds 65.56 # Real time elapsed on the host -host_tick_rate 1347535 # Simulator tick rate (ticks/s) +host_inst_rate 840697 # Simulator instruction rate (inst/s) +host_mem_usage 152968 # Number of bytes of host memory used +host_seconds 105.08 # Real time elapsed on the host +host_tick_rate 420346781 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 88340673 # Number of ticks simulated +sim_seconds 0.044170 # Number of seconds simulated +sim_ticks 44170336500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 88340674 # number of cpu cycles simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 0e1a3c9f1..4c8661842 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -62,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -101,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -140,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -173,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -182,11 +154,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout @@ -197,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out index 0dc85858d..c0cb264bc 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,15 +20,16 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -64,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -101,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -139,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -177,25 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 9a9778162..107c46644 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,35 +1,35 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 704446 # Simulator instruction rate (inst/s) -host_mem_usage 275648 # Number of bytes of host memory used -host_seconds 125.40 # Real time elapsed on the host -host_tick_rate 9716991 # Simulator tick rate (ticks/s) +host_inst_rate 585395 # Simulator instruction rate (inst/s) +host_mem_usage 158604 # Number of bytes of host memory used +host_seconds 150.91 # Real time elapsed on the host +host_tick_rate 839295251 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.001219 # Number of seconds simulated -sim_ticks 1218558003 # Number of ticks simulated +sim_seconds 0.126657 # Number of seconds simulated +sim_ticks 126656575000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12987.854851 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11987.854851 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 789207000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 728442000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13826.199000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.199000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1985138000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1841560000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13576.902561 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2774345000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2570002000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 13576.902561 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34685672 # number of overall hits -system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2774345000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_misses 204343 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2570002000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,22 +76,22 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4081.697925 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 661090000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12197.393898 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11197.393898 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 932320000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 855884000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12197.393898 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 932320000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 855884000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 12197.393898 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88264239 # number of overall hits -system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 932320000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 855884000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1878.885583 # Cycle average of tags in use system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.768790 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.768790 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2192775000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1855419000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) @@ -159,8 +159,8 @@ system.cpu.l2cache.Writeback_miss_rate 0.002965 # mi system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.768790 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2192775000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1855419000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 12966.100192 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 259377 # number of overall hits -system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2192775000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses system.cpu.l2cache.overall_misses 169116 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1855419000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 135910 # number of replacements system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31979.717205 # Cycle average of tags in use system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 61925078000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 115911 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1218558003 # number of cpu cycles simulated +system.cpu.numCycles 126656575000 # number of cpu cycles simulated system.cpu.num_insts 88340674 # Number of instructions executed system.cpu.num_refs 35224019 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 7dbc37b58..da377104f 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out index ee1fc877f..4d97fe26f 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt index 323b8a93c..9dd2e7465 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 638506 # Simulator instruction rate (inst/s) -host_mem_usage 150340 # Number of bytes of host memory used -host_seconds 213.38 # Real time elapsed on the host -host_tick_rate 638505 # Simulator tick rate (ticks/s) +host_inst_rate 672762 # Simulator instruction rate (inst/s) +host_mem_usage 151516 # Number of bytes of host memory used +host_seconds 202.52 # Real time elapsed on the host +host_tick_rate 336380340 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.000136 # Number of seconds simulated -sim_ticks 136246935 # Number of ticks simulated +sim_seconds 0.068123 # Number of seconds simulated +sim_ticks 68123467500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 136246936 # number of cpu cycles simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr index c0f1c1fbb..08cfb2451 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x1838c0 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout index 8e5f7bf90..13addb638 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 21 2007 00:48:18 -M5 started Wed Mar 21 00:48:40 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:40:43 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 136246935 because target called exit() +Exiting @ tick 68123467500 because target called exit() diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 770dac1b9..ff1b40886 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out index 30db17922..c2fb507ae 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 78f34213e..bf74220de 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 473146 # Simulator instruction rate (inst/s) -host_mem_usage 156372 # Number of bytes of host memory used -host_seconds 287.96 # Real time elapsed on the host -host_tick_rate 4801122 # Simulator tick rate (ticks/s) +host_inst_rate 480067 # Simulator instruction rate (inst/s) +host_mem_usage 157016 # Number of bytes of host memory used +host_seconds 283.81 # Real time elapsed on the host +host_tick_rate 698858124 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.001383 # Number of seconds simulated -sim_ticks 1382530003 # Number of ticks simulated +sim_seconds 0.198342 # Number of seconds simulated +sim_ticks 198341876000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3575.086285 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2575.086285 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 162627100 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 117138100 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3413.933333 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2413.933333 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 51209 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 36209 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4579.703729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3579.703729 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 481665760 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 376491760 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4276.384116 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 644292860 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 493629860 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4276.384116 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3276.384116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57944942 # number of overall hits -system.cpu.dcache.overall_miss_latency 644292860 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_misses 150663 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 493629860 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4060.510189 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 33018000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107279 # number of writebacks system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2909.600795 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1909.600795 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 544165179 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 357141179 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2909.600795 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 544165179 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 357141179 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2909.600795 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1909.600795 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136059913 # number of overall hits -system.cpu.icache.overall_miss_latency 544165179 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 357141179 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1952.728312 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 1000315000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3564.034868 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1961.482636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 480000652 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 264170520 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3564.034868 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 480000652 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 264170520 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3550.642088 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1961.482636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 309728 # number of overall hits -system.cpu.l2cache.overall_miss_latency 480000652 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses system.cpu.l2cache.overall_misses 135187 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 264170520 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 101911 # number of replacements system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30685.350019 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 319451000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 82918 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1382530003 # number of cpu cycles simulated +system.cpu.numCycles 198341876000 # number of cpu cycles simulated system.cpu.num_insts 136246936 # Number of instructions executed system.cpu.num_refs 58111522 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index c0f1c1fbb..08cfb2451 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x1838c0 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index dc2b61804..c635e0e4b 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 03:55:17 -M5 started Thu Mar 29 03:55:38 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:44:06 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1382530003 because target called exit() +Exiting @ tick 198341876000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 9ae62655d..105e8c6e2 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -64,12 +23,13 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -131,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -155,7 +114,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -307,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -331,7 +289,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -346,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -379,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -388,7 +346,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing egid=100 env= euid=100 @@ -403,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out index 690cc5723..ea4848b9b 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -31,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -170,9 +168,10 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -251,9 +250,9 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -282,16 +281,15 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -320,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -358,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -366,40 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 +block_size=64 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index bc6866525..dccb62bee 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 1060300638 # Number of BTB hits -global.BPredUnit.BTBLookups 1075264664 # Number of BTB lookups -global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 20658855 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted -global.BPredUnit.lookups 1098978166 # Number of BP lookups -global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target. -host_inst_rate 28281 # Simulator instruction rate (inst/s) -host_mem_usage 1256892 # Number of bytes of host memory used -host_seconds 61385.49 # Real time elapsed on the host -host_tick_rate 405833 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 389309694 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 236329759 # Number of BTB hits +global.BPredUnit.BTBLookups 244099867 # Number of BTB lookups +global.BPredUnit.RASInCorrect 116 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 19342549 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 203388054 # Number of conditional branches predicted +global.BPredUnit.lookups 265702680 # Number of BP lookups +global.BPredUnit.usedRAS 19620183 # Number of times the RAS was used to get a target. +host_inst_rate 104740 # Simulator instruction rate (inst/s) +host_mem_usage 154596 # Number of bytes of host memory used +host_seconds 16574.74 # Real time elapsed on the host +host_tick_rate 38540500 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 53067106 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 26767467 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 497279728 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 174034666 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.024912 # Number of seconds simulated -sim_ticks 24912272090 # Number of ticks simulated +sim_seconds 0.638799 # Number of seconds simulated +sim_ticks 638798750000 # Number of ticks simulated system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 72343657 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 60317471 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 5678957793 +system.cpu.commit.COM:committed_per_cycle.samples 1240430038 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 5103057521 8985.90% - 1 193842571 341.33% - 2 126727829 223.15% - 3 63255233 111.39% - 4 47590442 83.80% - 5 34302037 60.40% - 6 22774532 40.10% - 7 15063971 26.53% - 8 72343657 127.39% + 0 616961832 4973.77% + 1 236071207 1903.14% + 2 130159070 1049.31% + 3 77572840 625.37% + 4 40072787 323.06% + 5 42334502 341.29% + 6 22413470 180.69% + 7 14526859 117.11% + 8 60317471 486.26% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 445666361 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 20658355 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19342064 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3012390712 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 213160886 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 14.350025 # CPI: Cycles Per Instruction -system.cpu.cpi_total 14.350025 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 466176479 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5764.172372 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5678.042412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 454097633 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 69624550394 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.025910 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 12078846 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 4784670 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 41416640690 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7294176 # number of ReadReq MSHR misses +system.cpu.cpi 0.735925 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.735925 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 460303357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3955.169300 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2868.381634 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 451791924 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 33664158500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.018491 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 8511433 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1219244 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 20916781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.015842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7292189 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 157574910 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 35156809407 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.019621 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3153592 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1270515 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 26783900812 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1883077 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 972.020892 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 2881.979981 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 66.650940 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 659829 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 896062 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 641367573 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2582432746 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 6699.535635 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8433.632873 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 157310932 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22896132000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.021263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 3417570 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1533904 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 15886147500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1883666 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 1092.259997 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 571.397227 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 66.381046 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 62416 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 56970 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 68174500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 32552500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 626904981 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 6878.830546 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency -system.cpu.dcache.demand_hits 611672543 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 104781359801 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.024298 # miss rate for demand accesses -system.cpu.dcache.demand_misses 15232438 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6055185 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 68200541502 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014639 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9177253 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 621031859 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4741.409697 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency +system.cpu.dcache.demand_hits 609102856 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 56560290500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.019208 # miss rate for demand accesses +system.cpu.dcache.demand_misses 11929003 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2753148 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 36802928500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.014775 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9175855 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 626904981 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 6878.830546 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 621031859 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4741.409697 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 611672543 # number of overall hits -system.cpu.dcache.overall_miss_latency 104781359801 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.024298 # miss rate for overall accesses -system.cpu.dcache.overall_misses 15232438 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6055185 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 68200541502 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014639 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9177253 # number of overall MSHR misses +system.cpu.dcache.overall_hits 609102856 # number of overall hits +system.cpu.dcache.overall_miss_latency 56560290500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.019208 # miss rate for overall accesses +system.cpu.dcache.overall_misses 11929003 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2753148 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 36802928500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.014775 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9175855 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9173157 # number of replacements -system.cpu.dcache.sampled_refs 9177253 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9171759 # number of replacements +system.cpu.dcache.sampled_refs 9175855 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4093.061614 # Cycle average of tags in use -system.cpu.dcache.total_refs 611672543 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 39716000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2244715 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3168036062 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 48557069 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 6641345328 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 1298412925 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1202046298 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 501929792 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1629 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 10462509 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1098978166 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 541280485 # Number of cache lines fetched -system.cpu.fetch.Cycles 1955627258 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 11328270 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 7938391391 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 242391708 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.177803 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 541280485 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1081038949 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.284345 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4081.309726 # Cycle average of tags in use +system.cpu.dcache.total_refs 609102856 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8881811000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2245633 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 27333658 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 501 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 42431183 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2163062948 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 823856490 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 388659524 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 37167487 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1638 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 580367 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 265702680 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 277957843 # Number of cache lines fetched +system.cpu.fetch.Cycles 672748425 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10624598 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2197044125 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 19810424 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.207971 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 277957843 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 255949942 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.719668 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6180887586 +system.cpu.fetch.rateDist.samples 1277597526 system.cpu.fetch.rateDist.min_value 0 - 0 4766540797 7711.74% - 1 80764415 130.67% - 2 63598055 102.89% - 3 58203597 94.17% - 4 424384465 686.61% - 5 69131012 111.85% - 6 94422767 152.77% - 7 44649271 72.24% - 8 579193207 937.07% + 0 882806946 6909.90% + 1 27356477 214.12% + 2 16416749 128.50% + 3 27123610 212.30% + 4 80197027 627.72% + 5 46838848 366.62% + 6 25144427 196.81% + 7 24073126 188.42% + 8 147640316 1155.61% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 541280484 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5378.819380 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4616.750831 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 541279194 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6938677 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1290 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 387 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4168926 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 277957843 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5447.729673 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4641.891892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 277956896 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 5159000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 947 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4122000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 888 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 4207.523810 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 599423.249169 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 313014.522523 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 21 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 88358 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 541280484 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5378.819380 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency -system.cpu.icache.demand_hits 541279194 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6938677 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_misses 1290 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 387 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4168926 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 277957843 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5447.729673 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency +system.cpu.icache.demand_hits 277956896 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 5159000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses +system.cpu.icache.demand_misses 947 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4122000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 888 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 541280484 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5378.819380 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency +system.cpu.icache.overall_accesses 277957843 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5447.729673 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 541279194 # number of overall hits -system.cpu.icache.overall_miss_latency 6938677 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_misses 1290 # number of overall misses -system.cpu.icache.overall_mshr_hits 387 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4168926 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses +system.cpu.icache.overall_hits 277956896 # number of overall hits +system.cpu.icache.overall_miss_latency 5159000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses +system.cpu.icache.overall_misses 947 # number of overall misses +system.cpu.icache.overall_mshr_hits 59 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4122000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 888 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,79 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 888 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 716.132429 # Cycle average of tags in use -system.cpu.icache.total_refs 541279194 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 691.554117 # Cycle average of tags in use +system.cpu.icache.total_refs 277956896 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 18731384505 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 250098653 # Number of branches executed -system.cpu.iew.EXEC:nop 147895912 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.440971 # Inst execution rate -system.cpu.iew.EXEC:refs 918923683 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 177016651 # Number of stores executed +system.cpu.idleCycles 973 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 231142223 # Number of branches executed +system.cpu.iew.EXEC:nop 101615397 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.460942 # Inst execution rate +system.cpu.iew.EXEC:refs 650877785 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 168419462 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1839076786 # num instructions consuming a value -system.cpu.iew.WB:count 2471794731 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.797100 # average fanout of values written-back +system.cpu.iew.WB:consumers 1210814193 # num instructions consuming a value +system.cpu.iew.WB:count 1847797148 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.819076 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1465928228 # num instructions producing a value -system.cpu.iew.WB:rate 0.399909 # insts written-back per cycle -system.cpu.iew.WB:sent 2475054397 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21956654 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2471410228 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 938731548 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 111073783 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 389309694 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4831881465 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 741907032 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 286170200 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2725595031 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1536928 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 991749121 # num instructions producing a value +system.cpu.iew.WB:rate 1.446306 # insts written-back per cycle +system.cpu.iew.WB:sent 1849274792 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 20085867 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1985372 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 497279728 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 38 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 27992821 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 174034666 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2032941045 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 482458323 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 14098084 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1866495371 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 77 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 161620 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 501929792 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 6153373 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 8 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 233590575 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 41593346 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 516978 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 1402 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 37167487 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 36044 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 409084 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 20784106 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 401249 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 47985 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 8 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 726441 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 21230213 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 306932 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 51613367 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 13129684 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 306932 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 672336 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 19413531 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.358835 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.358835 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1880593455 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 1970711875 65.43% # Type of FU issued - IntMult 679 0.00% # Type of FU issued + IntAlu 1224165146 65.09% # Type of FU issued + IntMult 78 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 206 0.00% # Type of FU issued + FloatAdd 199 0.00% # Type of FU issued FloatCmp 15 0.00% # Type of FU issued - FloatCvt 146 0.00% # Type of FU issued - FloatMult 12 0.00% # Type of FU issued + FloatCvt 141 0.00% # Type of FU issued + FloatMult 13 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 862446019 28.64% # Type of FU issued - MemWrite 178606255 5.93% # Type of FU issued + MemRead 487297898 25.91% # Type of FU issued + MemWrite 169129941 8.99% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 11307551 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.003754 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 14841221 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007892 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 509990 4.51% # attempts to use FU when none available + IntAlu 753308 5.08% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 9173598 81.13% # attempts to use FU when none available - MemWrite 1623963 14.36% # attempts to use FU when none available + MemRead 10126775 68.23% # attempts to use FU when none available + MemWrite 3961138 26.69% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6180887586 +system.cpu.iq.ISSUE:issued_per_cycle.samples 1277597526 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 4878979324 7893.65% - 1 360055339 582.53% - 2 481197713 778.53% - 3 280796976 454.30% - 4 94854448 153.46% - 5 50760526 82.12% - 6 26723872 43.24% - 7 6795220 10.99% - 8 724168 1.17% + 0 550473495 4308.66% + 1 242915598 1901.35% + 2 174612702 1366.73% + 3 111937959 876.16% + 4 91216702 713.97% + 5 63235343 494.96% + 6 32411117 253.69% + 7 9228529 72.23% + 8 1566081 12.26% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.487271 # Inst issue rate -system.cpu.iq.iqInstsAdded 4683985508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3011765231 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 2916477755 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 6096386 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3050829124 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 9178154 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 7336.712513 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2076.036854 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7008989 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 15914539999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.236340 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2169165 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2244715 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2215400 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.013060 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 29315 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.013060 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 29315 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 1.471976 # Inst issue rate +system.cpu.iq.iqInstsAdded 1931325610 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1880593455 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 179510503 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 87058 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 101093002 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 9176743 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5323.405393 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2210.600583 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7008183 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 11544124000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.236310 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2168560 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4793820000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236310 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2168560 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2245633 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2216502 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.012972 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 29131 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.012972 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 29131 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.253830 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9178154 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 7336.712513 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7008989 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15914539999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.236340 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2169165 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9176743 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5323.405393 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7008183 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 11544124000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.236310 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2168560 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4503266483 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.236340 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2169165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4793820000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.236310 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2168560 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 11422869 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 7238.883228 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 11422376 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5252.842188 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 9224389 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15914539999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.192463 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2198480 # number of overall misses +system.cpu.l2cache.overall_hits 9224685 # number of overall hits +system.cpu.l2cache.overall_miss_latency 11544124000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.192402 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2197691 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4503266483 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.189897 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2169165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4793820000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.189852 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2168560 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2136397 # number of replacements -system.cpu.l2cache.sampled_refs 2169165 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2135792 # number of replacements +system.cpu.l2cache.sampled_refs 2168560 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32623.472165 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9224389 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 520424000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1039341 # number of writebacks -system.cpu.numCycles 6180887586 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2894504060 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 31406.160078 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9224685 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 53019662000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1039396 # number of writebacks +system.cpu.numCycles 1277597526 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 16292159 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6511750 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 1451413065 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 266047107 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 3125053 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 8501370508 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 6112671585 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 4584914520 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1056218413 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 501929792 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 276756270 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 3208711557 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 65986 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 1117979447 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed -system.cpu.timesIdled 7293390 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 4365074 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 834284464 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 6221923 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 448 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 2711841153 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2114466649 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1591248178 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 378627043 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 37167487 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11225904 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 215045215 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 469 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 45 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 21611838 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.timesIdled 27 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr index cdd59eda7..d0a887867 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7006 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index ad57a5293..ab96f2ec5 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -74,7 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic egid=100 env= euid=100 @@ -89,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -100,14 +60,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out index 891519c26..fc081bf5e 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -30,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -49,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -57,51 +56,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt index 7422e3ae7..4bc7b8152 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 927424 # Simulator instruction rate (inst/s) -host_mem_usage 144704 # Number of bytes of host memory used -host_seconds 1962.19 # Real time elapsed on the host -host_tick_rate 927424 # Simulator tick rate (ticks/s) +host_inst_rate 918892 # Simulator instruction rate (inst/s) +host_mem_usage 148632 # Number of bytes of host memory used +host_seconds 1980.41 # Real time elapsed on the host +host_tick_rate 459446111 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780129 # Number of instructions simulated -sim_seconds 0.001820 # Number of seconds simulated -sim_ticks 1819780128 # Number of ticks simulated +sim_seconds 0.909890 # Number of seconds simulated +sim_ticks 909890064000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1819780129 # number of cpu cycles simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr index 87866a2a5..d0a887867 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr @@ -1 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 0a123d4a4..41806d538 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -53,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -77,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -116,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -155,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -188,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -197,7 +154,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing egid=100 env= euid=100 @@ -212,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -223,14 +181,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out index 4692c5d40..55a09db2b 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -30,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -49,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -63,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -100,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -138,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -176,53 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index 45b7beb7c..009ee213d 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 486900 # Simulator instruction rate (inst/s) -host_mem_usage 1198232 # Number of bytes of host memory used -host_seconds 3737.50 # Real time elapsed on the host -host_tick_rate 8500130 # Simulator tick rate (ticks/s) +host_inst_rate 637714 # Simulator instruction rate (inst/s) +host_mem_usage 154060 # Number of bytes of host memory used +host_seconds 2853.60 # Real time elapsed on the host +host_tick_rate 886477792 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780129 # Number of instructions simulated -sim_seconds 0.031769 # Number of seconds simulated -sim_ticks 31769223012 # Number of ticks simulated +sim_seconds 2.529655 # Number of seconds simulated +sim_ticks 2529654621000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3121.340330 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2121.340330 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12378.042992 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11378.042992 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 22543612099 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 89399351000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 15321198099 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 82176937000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3602.533807 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.533807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12836.520018 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11836.520018 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6806339173 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24252294000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4917019173 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 22362974000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3221.115901 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12473.108302 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 29349951272 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 113651645000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 20238217272 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 104539911000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3221.115901 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2221.115901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12473.108302 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 596212431 # number of overall hits -system.cpu.dcache.overall_miss_latency 29349951272 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 113651645000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_misses 9111734 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 20238217272 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 104539911000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4091.845274 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.970916 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 75264000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40631938000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4089.753117 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3089.753117 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13987.531172 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12987.531172 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3279982 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 11218000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2477982 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10416000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4089.753117 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13987.531172 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3279982 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 11218000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2477982 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10416000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4089.753117 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3089.753117 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13987.531172 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1819779328 # number of overall hits -system.cpu.icache.overall_miss_latency 3279982 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 11218000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2477982 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10416000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,27 +138,27 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 625.996248 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.364745 # Cycle average of tags in use system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3215.890455 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1919.394872 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12996.354425 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10996.354425 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 6946815413 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 28074114000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4146186590 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 23753808000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 2244708 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 2215611 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.012962 # miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_misses 29097 # number of WriteReqNoAck|Writeback misses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.012962 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 29097 # number of WriteReqNoAck|Writeback MSHR misses +system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2215611 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.012962 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 29097 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.012962 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 29097 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 4.244141 # Average number of references to valid blocks. @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3215.890455 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12996.354425 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6946815413 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 28074114000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4146186590 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 23753808000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3173.148527 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1919.394872 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12823.621788 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 9167994 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6946815413 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 28074114000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses system.cpu.l2cache.overall_misses 2189250 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4146186590 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 23753808000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2127385 # number of replacements system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32563.117941 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31194.155037 # Cycle average of tags in use system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 748591000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 245730069000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1038202 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 31769223012 # number of cpu cycles simulated +system.cpu.numCycles 2529654621000 # number of cpu cycles simulated system.cpu.num_insts 1819780129 # Number of instructions executed system.cpu.num_refs 606571345 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr index 87866a2a5..d0a887867 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr @@ -1 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 5604f880f..72c4312d9 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -1,11 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=System @@ -27,12 +23,13 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 commitToRenameDelay=1 commitWidth=8 +cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 @@ -94,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -118,7 +114,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -270,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -294,7 +289,7 @@ split=false split_size=0 store_compressed=false subblock_size=0 -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -309,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -342,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -351,11 +346,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing egid=100 env= euid=100 -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin output=cout @@ -366,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out index a78c52d7f..e3bf50f10 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,15 +20,16 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess cmd=twolf smred -executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing system=system uid=100 euid=100 @@ -170,9 +168,10 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 +cpu_id=0 activity=0 workload=system.cpu.workload checker=null @@ -251,9 +250,9 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -282,16 +281,15 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 -tgts_per_mshr=5 +tgts_per_mshr=20 write_buffers=8 prioritizeRequests=false protocol=null @@ -320,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -358,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -366,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index c77face31..8dcfd61cf 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 11848811 # Number of BTB hits -global.BPredUnit.BTBLookups 15227898 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1227 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2015952 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 12943595 # Number of conditional branches predicted -global.BPredUnit.lookups 17560137 # Number of BP lookups -global.BPredUnit.usedRAS 1685355 # Number of times the RAS was used to get a target. -host_inst_rate 110871 # Simulator instruction rate (inst/s) -host_mem_usage 184176 # Number of bytes of host memory used -host_seconds 759.26 # Real time elapsed on the host -host_tick_rate 138735 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9867030 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 3328836 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 29553768 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 9396457 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 11874522 # Number of BTB hits +global.BPredUnit.BTBLookups 15445749 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1158 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1931947 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 13190559 # Number of conditional branches predicted +global.BPredUnit.lookups 17824174 # Number of BP lookups +global.BPredUnit.usedRAS 1655464 # Number of times the RAS was used to get a target. +host_inst_rate 74830 # Simulator instruction rate (inst/s) +host_mem_usage 156844 # Number of bytes of host memory used +host_seconds 1124.95 # Real time elapsed on the host +host_tick_rate 39347975 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 14674251 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 4294265 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 31675298 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10012759 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 105335101 # Number of ticks simulated +sim_seconds 0.044264 # Number of seconds simulated +sim_ticks 44264420500 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3300349 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2948022 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 65617496 +system.cpu.commit.COM:committed_per_cycle.samples 81602250 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 32041205 4883.03% - 1 13628356 2076.94% - 2 7878182 1200.62% - 3 3859920 588.25% - 4 2040157 310.92% - 5 1456623 221.99% - 6 796888 121.44% - 7 615816 93.85% - 8 3300349 502.97% + 0 44887304 5500.74% + 1 17052684 2089.73% + 2 8186225 1003.19% + 3 3991011 489.08% + 4 1764745 216.26% + 5 1325913 162.48% + 6 892255 109.34% + 7 554091 67.90% + 8 2948022 361.27% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2003468 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1919652 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 39205061 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 46410426 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 1.251312 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.251312 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 23022109 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5495.207331 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4910.485944 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23021236 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4797316 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 873 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 375 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2445422 # number of ReadReq MSHR miss cycles +system.cpu.cpi 1.051666 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051666 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 23047695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5314.424635 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4545.725646 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23047078 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3279000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 617 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 114 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2286500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 503 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4880.722363 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.932720 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6495178 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 28918280 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000911 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5925 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 4186 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 7962764 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 3836.081210 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4946.808511 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493764 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28153000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001129 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7339 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5600 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8602500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2807.125000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 3125.260571 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13194.641931 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 8 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 875 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 22457 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2734603 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13176.111508 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29523212 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4959.634598 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29516414 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 33715596 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses -system.cpu.dcache.demand_misses 6798 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 4561 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10408186 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 29548798 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3950.729010 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29540842 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 31432000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000269 # miss rate for demand accesses +system.cpu.dcache.demand_misses 7956 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5714 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2237 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 29523212 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4959.634598 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29516414 # number of overall hits -system.cpu.dcache.overall_miss_latency 33715596 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses -system.cpu.dcache.overall_misses 6798 # number of overall misses -system.cpu.dcache.overall_mshr_hits 4561 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10408186 # number of overall MSHR miss cycles +system.cpu.dcache.overall_accesses 29548798 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3950.729010 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 29540842 # number of overall hits +system.cpu.dcache.overall_miss_latency 31432000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000269 # miss rate for overall accesses +system.cpu.dcache.overall_misses 7956 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5714 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 158 # number of replacements -system.cpu.dcache.sampled_refs 2237 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 163 # number of replacements +system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1400.647488 # Cycle average of tags in use -system.cpu.dcache.total_refs 29516414 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1457.683096 # Cycle average of tags in use +system.cpu.dcache.total_refs 29540842 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2047370 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12661 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 2829477 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 146297095 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 36266329 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 27223403 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 6075840 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45354 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 80395 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 17560137 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 17576948 # Number of cache lines fetched -system.cpu.fetch.Cycles 45711428 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 479088 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 150837354 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2061309 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.244934 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 17576948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 13534166 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.103924 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 107 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 2294607 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12777 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 2890400 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 151561971 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 53136009 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 26139582 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 6926673 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 40541 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 32053 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 17824174 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 18016265 # Number of cache lines fetched +system.cpu.fetch.Cycles 44691424 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 975254 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 154588435 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2011658 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.201337 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 18016265 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13529986 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.746191 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 71693337 +system.cpu.fetch.rateDist.samples 88528924 system.cpu.fetch.rateDist.min_value 0 - 0 43559639 6075.83% - 1 2788432 388.94% - 2 2133609 297.60% - 3 3200202 446.37% - 4 4098889 571.73% - 5 1363717 190.22% - 6 1885995 263.06% - 7 1651845 230.40% - 8 11011009 1535.85% + 0 61853767 6986.84% + 1 2838595 320.64% + 2 1299355 146.77% + 3 1865057 210.67% + 4 3537974 399.64% + 5 1231942 139.16% + 6 1400771 158.23% + 7 1171977 132.38% + 8 13329486 1505.66% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 17576948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3407.568545 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2506.978423 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 17563424 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 46083957 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000769 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 13524 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 3467 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 25212682 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10057 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets 3513.269231 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1746.387988 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_accesses 18016265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3877.692156 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2918.898279 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 18006143 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 39250000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000562 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10122 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 28666500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000545 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 9821 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1833.432746 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 26 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 91345 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 17576948 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3407.568545 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency -system.cpu.icache.demand_hits 17563424 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 46083957 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000769 # miss rate for demand accesses -system.cpu.icache.demand_misses 13524 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 3467 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25212682 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10057 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 18016265 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3877.692156 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency +system.cpu.icache.demand_hits 18006143 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 39250000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000562 # miss rate for demand accesses +system.cpu.icache.demand_misses 10122 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 28666500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000545 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 9821 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 17576948 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3407.568545 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 17563424 # number of overall hits -system.cpu.icache.overall_miss_latency 46083957 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000769 # miss rate for overall accesses -system.cpu.icache.overall_misses 13524 # number of overall misses -system.cpu.icache.overall_mshr_hits 3467 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25212682 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10057 # number of overall MSHR misses +system.cpu.icache.overall_accesses 18016265 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3877.692156 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 18006143 # number of overall hits +system.cpu.icache.overall_miss_latency 39250000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000562 # miss rate for overall accesses +system.cpu.icache.overall_misses 10122 # number of overall misses +system.cpu.icache.overall_mshr_hits 301 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 28666500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000545 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 9821 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8145 # number of replacements -system.cpu.icache.sampled_refs 10057 # Sample count of references to valid blocks. +system.cpu.icache.replacements 7904 # number of replacements +system.cpu.icache.sampled_refs 9821 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1487.085502 # Cycle average of tags in use -system.cpu.icache.total_refs 17563424 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1549.418815 # Cycle average of tags in use +system.cpu.icache.total_refs 18006143 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 33641765 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12581618 # Number of branches executed -system.cpu.iew.EXEC:nop 11617565 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.388001 # Inst execution rate -system.cpu.iew.EXEC:refs 31473535 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7134398 # Number of stores executed +system.cpu.idleCycles 7902 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12543861 # Number of branches executed +system.cpu.iew.EXEC:nop 11949352 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.130385 # Inst execution rate +system.cpu.iew.EXEC:refs 31528912 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7145648 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 88408054 # num instructions consuming a value -system.cpu.iew.WB:count 97920299 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.731090 # average fanout of values written-back +system.cpu.iew.WB:consumers 87529341 # num instructions consuming a value +system.cpu.iew.WB:count 98214425 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.729574 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 64634219 # num instructions producing a value -system.cpu.iew.WB:rate 1.365821 # insts written-back per cycle -system.cpu.iew.WB:sent 98494929 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2154192 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 104376 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 29553768 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2191495 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 9396457 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 131107086 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24339137 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2193063 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 99510422 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 16363 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 63859133 # num instructions producing a value +system.cpu.iew.WB:rate 1.109405 # insts written-back per cycle +system.cpu.iew.WB:sent 99107976 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2078247 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 190251 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 31675298 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 411 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2578287 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10012759 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 138313092 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24383264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1412890 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 100071797 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 38223 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 879 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 6075840 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 34734 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread.0.blockedLoads 9915 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 36009 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 941599 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3004 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6926673 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 64568 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 828690 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 779 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 23070 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9915 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 9519355 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2893762 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 23070 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 196104 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1958088 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.799161 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.799161 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 101703485 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 84249 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9673 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11640885 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3510064 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 84249 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 193948 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1884299 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.950872 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.950872 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 101484687 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 7 0.00% # Type of FU issued - IntAlu 62578225 61.53% # Type of FU issued - IntMult 472394 0.46% # Type of FU issued + IntAlu 62609480 61.69% # Type of FU issued + IntMult 467679 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2776755 2.73% # Type of FU issued - FloatCmp 115486 0.11% # Type of FU issued - FloatCvt 2376016 2.34% # Type of FU issued - FloatMult 302348 0.30% # Type of FU issued - FloatDiv 754954 0.74% # Type of FU issued - FloatSqrt 321 0.00% # Type of FU issued - MemRead 25019338 24.60% # Type of FU issued - MemWrite 7307641 7.19% # Type of FU issued + FloatAdd 2780950 2.74% # Type of FU issued + FloatCmp 115557 0.11% # Type of FU issued + FloatCvt 2364134 2.33% # Type of FU issued + FloatMult 305451 0.30% # Type of FU issued + FloatDiv 755050 0.74% # Type of FU issued + FloatSqrt 320 0.00% # Type of FU issued + MemRead 24826231 24.46% # Type of FU issued + MemWrite 7259828 7.15% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1392706 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013694 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1739512 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017141 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist -(null) 0 0.00% # attempts to use FU when none available -IntAlu 193189 13.87% # attempts to use FU when none available -IntMult 0 0.00% # attempts to use FU when none available -IntDiv 0 0.00% # attempts to use FU when none available -FloatAdd 1883 0.14% # attempts to use FU when none available -FloatCmp 96 0.01% # attempts to use FU when none available -FloatCvt 2836 0.20% # attempts to use FU when none available -FloatMult 2464 0.18% # attempts to use FU when none available -FloatDiv 659899 47.38% # attempts to use FU when none available -FloatSqrt 0 0.00% # attempts to use FU when none available -MemRead 465101 33.40% # attempts to use FU when none available -MemWrite 67238 4.83% # attempts to use FU when none available -IprAccess 0 0.00% # attempts to use FU when none available -InstPrefetch 0 0.00% # attempts to use FU when none available + (null) 0 0.00% # attempts to use FU when none available + IntAlu 236478 13.59% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 1 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 223 0.01% # attempts to use FU when none available + FloatMult 1629 0.09% # attempts to use FU when none available + FloatDiv 705159 40.54% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 710061 40.82% # attempts to use FU when none available + MemWrite 85961 4.94% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 71693337 +system.cpu.iq.ISSUE:issued_per_cycle.samples 88528924 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 27977053 3902.32% - 1 15408153 2149.18% - 2 12854527 1792.99% - 3 7056557 984.27% - 4 4494209 626.87% - 5 2427532 338.60% - 6 1097338 153.06% - 7 305661 42.63% - 8 72307 10.09% + 0 43673541 4933.25% + 1 18286123 2065.55% + 2 11155754 1260.13% + 3 6962814 786.50% + 4 4628513 522.82% + 5 2073707 234.24% + 6 1255435 141.81% + 7 360879 40.76% + 8 132158 14.93% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.418590 # Inst issue rate -system.cpu.iq.iqInstsAdded 119489085 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 101703485 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 34413373 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 132312 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 28441004 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 12293 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3855.809345 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2071.040418 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19556665 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.412593 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 5072 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10504317 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 5072 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.444401 # Average number of references to valid blocks. +system.cpu.iq.ISSUE:rate 1.146345 # Inst issue rate +system.cpu.iq.iqInstsAdded 126363329 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 101484687 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 411 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 41115515 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 151595 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 37587907 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 12063 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4597.386006 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.176887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 6975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 23391500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.421786 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5088 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12466500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.421786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5088 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.391903 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12293 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3855.809345 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19556665 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.412593 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5072 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12063 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4597.386006 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6975 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 23391500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.421786 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5088 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 10504317 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.412593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5072 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12466500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.421786 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5088 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12398 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3855.809345 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7326 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19556665 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.409098 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5072 # number of overall misses +system.cpu.l2cache.overall_accesses 12170 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4597.386006 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 7082 # number of overall hits +system.cpu.l2cache.overall_miss_latency 23391500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.418077 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5088 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 10504317 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.409098 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5072 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12466500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.418077 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5088 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,31 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 5072 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5088 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3261.872945 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7326 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3405.740601 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7082 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 71693337 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 812700 # Number of cycles rename is blocking +system.cpu.numCycles 88528924 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1217757 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 369396 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 37208342 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 772307 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 122 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 182866276 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 141908898 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 104156212 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 26334995 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 6075840 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1200845 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 35728851 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 60615 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 555 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2896644 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 544 # count of temporary serializing insts renamed -system.cpu.timesIdled 10380 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 511469 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 54000366 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 581686 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 190129267 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 147303303 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 108348051 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 25314451 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 6926673 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1065045 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 39920690 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 4632 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 447 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2624388 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 437 # count of temporary serializing insts renamed +system.cpu.timesIdled 98 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out index 00387ae5c..98777e0af 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out @@ -66,7 +66,7 @@ The rand generator seed was at utemp() : 1 I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 @@ -103,7 +103,7 @@ The rand generator seed was at utemp() : 1 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 789f77815..3cb797e6a 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -59,7 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic egid=100 env= euid=100 @@ -74,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out index b4087eb1c..47defa937 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -31,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic system=system uid=100 euid=100 @@ -50,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -58,23 +56,3 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 - diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index 2cd5a06bf..acfa7c9dd 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1013473 # Simulator instruction rate (inst/s) -host_mem_usage 151596 # Number of bytes of host memory used -host_seconds 90.68 # Real time elapsed on the host -host_tick_rate 1013469 # Simulator tick rate (ticks/s) +host_inst_rate 935813 # Simulator instruction rate (inst/s) +host_mem_usage 150648 # Number of bytes of host memory used +host_seconds 98.21 # Real time elapsed on the host +host_tick_rate 467904361 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated -sim_seconds 0.000092 # Number of seconds simulated -sim_ticks 91903056 # Number of ticks simulated +sim_seconds 0.045952 # Number of seconds simulated +sim_ticks 45951528000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 91903057 # number of cpu cycles simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out index 00387ae5c..98777e0af 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out @@ -66,7 +66,7 @@ The rand generator seed was at utemp() : 1 I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 @@ -103,7 +103,7 @@ The rand generator seed was at utemp() : 1 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index e2265235e..7edcc9166 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -1,33 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -38,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -62,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -101,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -140,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -173,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -182,7 +154,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing egid=100 env= euid=100 @@ -197,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out index fcf06c7db..3ed492885 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -31,7 +29,7 @@ executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf input=cin output=cout env= -cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing system=system uid=100 euid=100 @@ -50,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -64,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -101,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -139,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -177,25 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[statsreset] -reset_cycle=0 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index 5cdae9c4a..9f5824722 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 607322 # Simulator instruction rate (inst/s) -host_mem_usage 157212 # Number of bytes of host memory used -host_seconds 151.33 # Real time elapsed on the host -host_tick_rate 1013960 # Simulator tick rate (ticks/s) +host_inst_rate 651405 # Simulator instruction rate (inst/s) +host_mem_usage 156232 # Number of bytes of host memory used +host_seconds 141.08 # Real time elapsed on the host +host_tick_rate 840119018 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated -sim_seconds 0.000153 # Number of seconds simulated -sim_ticks 153438012 # Number of ticks simulated +sim_seconds 0.118528 # Number of seconds simulated +sim_ticks 118527938000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3701.356540 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2701.356540 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13776.371308 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12776.371308 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1754443 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 6530000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1280443 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6056000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3869.070366 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2869.070366 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13970.251716 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12970.251716 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6763135 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24420000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 5015135 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 22672000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3833.293429 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13928.892889 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8517578 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 30950000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6295578 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 28728000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3833.293429 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2833.293429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13928.892889 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26495079 # number of overall hits -system.cpu.dcache.overall_miss_latency 8517578 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 30950000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_misses 2222 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6295578 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 28728000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1398.130089 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.614290 # Cycle average of tags in use system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3117.603760 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2117.603760 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12615.981199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11615.981199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 26530808 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 107362000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 18020808 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 98852000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3117.603760 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12615.981199 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 26530808 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 107362000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 18020808 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 98852000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3117.603760 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2117.603760 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12615.981199 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 91894548 # number of overall hits -system.cpu.icache.overall_miss_latency 26530808 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 107362000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 18020808 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 98852000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1374.520503 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.637331 # Cycle average of tags in use system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2892.483207 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1885.503778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13779790 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 61932000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8982540 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 52404000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2892.483207 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13779790 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 61932000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8982540 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 52404000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2892.483207 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1885.503778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 6072 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13779790 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 61932000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4764 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8982540 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 52404000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3073.845977 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3172.809799 # Cycle average of tags in use system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 153438012 # number of cpu cycles simulated +system.cpu.numCycles 118527938000 # number of cpu cycles simulated system.cpu.num_insts 91903057 # Number of instructions executed system.cpu.num_refs 26537109 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out index 00387ae5c..98777e0af 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out @@ -66,7 +66,7 @@ The rand generator seed was at utemp() : 1 I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 @@ -103,7 +103,7 @@ The rand generator seed was at utemp() : 1 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr index eb1796ead..f33d007a7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 2a1613fa1..3dcf027c2 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out index d24c09793..d448056f4 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt index 45fd6b479..c41d3b35f 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 676464 # Simulator instruction rate (inst/s) -host_mem_usage 149916 # Number of bytes of host memory used -host_seconds 285.95 # Real time elapsed on the host -host_tick_rate 676463 # Simulator tick rate (ticks/s) +host_inst_rate 673586 # Simulator instruction rate (inst/s) +host_mem_usage 150548 # Number of bytes of host memory used +host_seconds 287.17 # Real time elapsed on the host +host_tick_rate 336792536 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated -sim_seconds 0.000193 # Number of seconds simulated -sim_ticks 193435972 # Number of ticks simulated +sim_seconds 0.096718 # Number of seconds simulated +sim_ticks 96717986000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 193435973 # number of cpu cycles simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr index 94662b6e8..18e13818c 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x11e394 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout index 7c0e5ba5f..f878587c3 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 12 2007 16:53:49 -M5 started Mon Mar 12 17:37:07 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:48:51 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 193435972 because target called exit() +Exiting @ tick 96717986000 because target called exit() diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index 0e057cbbe..2a87cb78d 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out index 5f60c76d0..f79151c21 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 2fbdef851..0f4d2b473 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 471554 # Simulator instruction rate (inst/s) -host_mem_usage 155352 # Number of bytes of host memory used -host_seconds 410.21 # Real time elapsed on the host -host_tick_rate 766692 # Simulator tick rate (ticks/s) +host_inst_rate 500598 # Simulator instruction rate (inst/s) +host_mem_usage 156000 # Number of bytes of host memory used +host_seconds 386.41 # Real time elapsed on the host +host_tick_rate 699597163 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated -sim_seconds 0.000315 # Number of seconds simulated -sim_ticks 314505003 # Number of ticks simulated +sim_seconds 0.270332 # Number of seconds simulated +sim_ticks 270331639000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3705.925703 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2705.925703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1845551 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 6972000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1347551 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6474000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3995 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2995 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 14000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 13000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 3995 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 14000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2995 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 13000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3678.678637 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2678.678637 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13987.108656 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12987.108656 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3995045 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 15190000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2909045 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 14104000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3687.244949 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13991.161616 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5840596 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 22162000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4256596 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 20578000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3687.244949 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2687.244949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13991.161616 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 76708968 # number of overall hits -system.cpu.dcache.overall_miss_latency 5840596 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 22162000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_misses 1584 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4256596 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 20578000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1216.403972 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.473868 # Cycle average of tags in use system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3138.680633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2138.680633 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12584.365830 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11584.365830 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 38505334 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 154385000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 26237334 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 142117000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3138.680633 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12584.365830 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 38505334 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 154385000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 26237334 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 142117000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3138.680633 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2138.680633 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12584.365830 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 193423706 # number of overall hits -system.cpu.icache.overall_miss_latency 38505334 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 154385000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses system.cpu.icache.overall_misses 12268 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 26237334 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 142117000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10342 # number of replacements system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1567.271345 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.809550 # Cycle average of tags in use system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2847.598413 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1846.400619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14713541 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 67171000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9540352 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 56837000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) @@ -174,29 +174,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2847.598413 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14713541 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 67171000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9540352 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 56837000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2847.598413 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1846.400619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8708 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14713541 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 67171000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses system.cpu.l2cache.overall_misses 5167 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9540352 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 56837000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -213,12 +213,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3448.701925 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3507.169610 # Cycle average of tags in use system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 314505003 # number of cpu cycles simulated +system.cpu.numCycles 270331639000 # number of cpu cycles simulated system.cpu.num_insts 193435973 # Number of instructions executed system.cpu.num_refs 76732959 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr index 6e24f6d54..18e13818c 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -2,7 +2,6 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x11e394 length 0x10. warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index d50dfc3c4..316a2c0d3 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 16:12:35 -M5 started Thu Mar 29 16:13:01 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:53:38 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 314505003 because target called exit() +Exiting @ tick 270331639000 because target called exit() diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index a5e3f40d7..d0738b960 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -33,9 +33,14 @@ symbolfile= [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=100 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=8 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[14] side_b=system.membus.port[2] @@ -111,6 +116,7 @@ sys=system [system.iobus] type=Bus children=responder +block_size=64 bus_id=0 clock=2 responder_set=false @@ -137,6 +143,7 @@ pio=system.iobus.default [system.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=2 responder_set=false diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out index d7c3ccbd9..bc35fc4e7 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out @@ -69,6 +69,7 @@ bus_id=1 clock=2 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -103,10 +104,15 @@ zero=true [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=100 +nack_delay=8 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -361,6 +367,7 @@ bus_id=0 clock=2 width=64 responder_set=false +block_size=64 [system.iobus.responder] type=IsaFake diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt index 1e1ba049c..5229bd3a6 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 571923 # Simulator instruction rate (inst/s) -host_mem_usage 373992 # Number of bytes of host memory used -host_seconds 3905.40 # Real time elapsed on the host -host_tick_rate 571972 # Simulator tick rate (ticks/s) +host_inst_rate 584673 # Simulator instruction rate (inst/s) +host_mem_usage 374168 # Number of bytes of host memory used +host_seconds 3820.23 # Real time elapsed on the host +host_tick_rate 584723 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 2233583679 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr index d07f16195..cf3ec3bba 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr @@ -3,10132 +3,10 @@ Warning: rounding error > tolerance Warning: rounding error > tolerance 0.002000 rounded to 0 warn: No kernel set for full system simulation. Assuming you know what you're doing... +Listening for t1000 connection on port 3456 Listening for t1000 connection on port 3457 -Listening for t1000 connection on port 3458 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring write to SPARC ERROR regsiter warn: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. -warn: Attempted to set the CWP to 31 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout index 0639edaa5..ef048f157 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 12:26:45 -M5 started Fri Mar 30 12:26:47 2007 +M5 compiled May 15 2007 17:08:10 +M5 started Tue May 15 17:08:12 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 4d44e14fe..882c78529 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 686c3b2f6..701034053 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -167,7 +168,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 988584966..c07021f5a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 615 # Number of BTB hits -global.BPredUnit.BTBLookups 1663 # Number of BTB lookups -global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 439 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1180 # Number of conditional branches predicted -global.BPredUnit.lookups 2032 # Number of BP lookups -global.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. -host_inst_rate 15105 # Simulator instruction rate (inst/s) -host_mem_usage 154056 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host -host_tick_rate 3572881 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 13 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 524 # Number of BTB hits +global.BPredUnit.BTBLookups 1590 # Number of BTB lookups +global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted +global.BPredUnit.lookups 1843 # Number of BP lookups +global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target. +host_inst_rate 54565 # Simulator instruction rate (inst/s) +host_mem_usage 154084 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 44392410 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 127 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1144 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1331134 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 4588000 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 101 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 30311 +system.cpu.commit.COM:committed_per_cycle.samples 8514 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 27595 9103.96% - 1 1579 520.93% - 2 482 159.02% - 3 232 76.54% - 4 131 43.22% - 5 104 34.31% - 6 60 19.79% - 7 27 8.91% - 8 101 33.32% + 0 6195 7276.25% + 1 1158 1360.11% + 2 469 550.86% + 3 176 206.72% + 4 131 153.86% + 5 99 116.28% + 6 109 128.02% + 7 73 85.74% + 8 104 122.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 370 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4834 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3588 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 236.730215 # CPI: Cycles Per Instruction -system.cpu.cpi_total 236.730215 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 7256.076023 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7095.200000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1435 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1240789 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.106476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 171 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 71 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 709520 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.062267 # mshr miss rate for ReadReq accesses +system.cpu.cpi 1.635604 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.635604 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5928.571429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5385 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1342 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 788500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.090169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 538500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.067797 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8026.070225 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7200.452055 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 456 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2857281 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.438424 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 525633 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 4501.457726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1544000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 373500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.930636 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.468208 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2418 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7776.223909 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1891 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4098070 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.217949 # miss rate for demand accesses -system.cpu.dcache.demand_misses 527 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1235153 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071547 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2287 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1811 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2332500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208133 # miss rate for demand accesses +system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 912000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.075645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2418 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7776.223909 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7139.612717 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2287 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1891 # number of overall hits -system.cpu.dcache.overall_miss_latency 4098070 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.217949 # miss rate for overall accesses -system.cpu.dcache.overall_misses 527 # number of overall misses -system.cpu.dcache.overall_mshr_hits 354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1235153 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071547 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 1811 # number of overall hits +system.cpu.dcache.overall_miss_latency 2332500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208133 # miss rate for overall accesses +system.cpu.dcache.overall_misses 476 # number of overall misses +system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 912000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.075645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +121,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.478227 # Cycle average of tags in use -system.cpu.dcache.total_refs 1891 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 112.670676 # Cycle average of tags in use +system.cpu.dcache.total_refs 1811 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 17469 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 70 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 169 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11765 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10684 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2098 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 907 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2032 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1710 # Number of cache lines fetched -system.cpu.fetch.Cycles 3962 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12603 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.065089 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1710 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 919 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.403696 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 144 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10499 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1848 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 1843 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1471 # Number of cache lines fetched +system.cpu.fetch.Cycles 3451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11450 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.200391 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 765 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.244971 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 31219 +system.cpu.fetch.rateDist.samples 9197 system.cpu.fetch.rateDist.min_value 0 - 0 28979 9282.49% - 1 197 63.10% - 2 198 63.42% - 3 167 53.49% - 4 197 63.10% - 5 187 59.90% - 6 222 71.11% - 7 122 39.08% - 8 950 304.30% + 0 7219 7849.30% + 1 167 181.58% + 2 147 159.83% + 3 129 140.26% + 4 200 217.46% + 5 139 151.14% + 6 181 196.80% + 7 99 107.64% + 8 916 995.98% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1710 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5139.251163 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4349.151613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1280 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2209878 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.251462 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 430 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1348237 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.181287 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1471 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5375.757576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4524.038462 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1141 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1774000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.224337 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1411500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.212101 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.129032 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.657051 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1710 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5139.251163 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency -system.cpu.icache.demand_hits 1280 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2209878 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.251462 # miss rate for demand accesses -system.cpu.icache.demand_misses 430 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1348237 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.181287 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1471 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency +system.cpu.icache.demand_hits 1141 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1774000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.224337 # miss rate for demand accesses +system.cpu.icache.demand_misses 330 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1411500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.212101 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1710 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5139.251163 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4349.151613 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1471 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1280 # number of overall hits -system.cpu.icache.overall_miss_latency 2209878 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.251462 # miss rate for overall accesses -system.cpu.icache.overall_misses 430 # number of overall misses -system.cpu.icache.overall_mshr_hits 120 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1348237 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.181287 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses +system.cpu.icache.overall_hits 1141 # number of overall hits +system.cpu.icache.overall_miss_latency 1774000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.224337 # miss rate for overall accesses +system.cpu.icache.overall_misses 330 # number of overall misses +system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1411500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.212101 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,79 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 148.421347 # Cycle average of tags in use -system.cpu.icache.total_refs 1280 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.938349 # Cycle average of tags in use +system.cpu.icache.total_refs 1141 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1299916 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1267 # Number of branches executed -system.cpu.iew.EXEC:nop 48 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.270476 # Inst execution rate -system.cpu.iew.EXEC:refs 2748 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1031 # Number of stores executed +system.cpu.idleCycles 2475 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1148 # Number of branches executed +system.cpu.iew.EXEC:nop 40 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.837338 # Inst execution rate +system.cpu.iew.EXEC:refs 2524 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 977 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5354 # num instructions consuming a value -system.cpu.iew.WB:count 8160 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757378 # average fanout of values written-back +system.cpu.iew.WB:consumers 5205 # num instructions consuming a value +system.cpu.iew.WB:count 7402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.742747 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4055 # num instructions producing a value -system.cpu.iew.WB:rate 0.261379 # insts written-back per cycle -system.cpu.iew.WB:sent 8228 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 404 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 7230 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10469 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1717 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8444 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 3866 # num instructions producing a value +system.cpu.iew.WB:rate 0.804828 # insts written-back per cycle +system.cpu.iew.WB:sent 7467 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1876 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1144 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9245 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1547 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 280 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 907 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 682 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 81 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1165 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 60 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 279 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.004224 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.004224 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8743 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 897 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 332 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.611395 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5868 67.12% # Type of FU issued + (null) 2 0.03% # Type of FU issued + IntAlu 5322 66.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued + FloatAdd 2 0.03% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1809 20.69% # Type of FU issued - MemWrite 1061 12.14% # Type of FU issued + MemRead 1662 20.82% # Type of FU issued + MemWrite 992 12.43% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 87 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009951 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 1.15% # attempts to use FU when none available + IntAlu 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,43 +297,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 54 62.07% # attempts to use FU when none available - MemWrite 32 36.78% # attempts to use FU when none available + MemRead 71 66.98% # attempts to use FU when none available + MemWrite 35 33.02% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 31219 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9197 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 27042 8662.03% - 1 1845 590.99% - 2 1151 368.69% - 3 572 183.22% - 4 318 101.86% - 5 182 58.30% - 6 76 24.34% - 7 22 7.05% - 8 11 3.52% + 0 5952 6471.68% + 1 1107 1203.65% + 2 919 999.24% + 3 442 480.59% + 4 375 407.74% + 5 250 271.83% + 6 115 125.04% + 7 26 28.27% + 8 11 11.96% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.280054 # Inst issue rate -system.cpu.iq.iqInstsAdded 10397 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8743 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4378 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 481 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4807.594595 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2390.114345 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2312453 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.867783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 7981 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2045 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4639.751553 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2463.768116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2241000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 481 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1149645 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1190000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 481 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -342,32 +342,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4807.594595 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2312453 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2241000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 481 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1149645 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1190000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4807.594595 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2390.114345 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2312453 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2241000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 481 # number of overall misses +system.cpu.l2cache.overall_misses 483 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1149645 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1190000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 481 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,31 +380,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 481 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 250.999286 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 278.222582 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 31219 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 7810 # Number of cycles rename is blocking +system.cpu.numCycles 9197 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 10837 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 465 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 6 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 14384 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11306 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8499 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2010 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 907 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 491 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4448 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 9164 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 825 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IdleCycles 6383 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 12854 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 7485 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1746 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3434 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed +system.cpu.timesIdled 25 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr index 8053728f7..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr @@ -1,3 +1,2 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index ef47b0265..3ab3ef422 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:02 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:39 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1331134 because target called exit() +Exiting @ tick 4588000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 79673d775..bf00075ce 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -90,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -101,14 +60,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index 31870d5f3..117159126 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -30,6 +29,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,61 +48,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 96973fa46..4e1bd9447 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 684709 # Simulator instruction rate (inst/s) -host_mem_usage 148256 # Number of bytes of host memory used +host_inst_rate 576538 # Simulator instruction rate (inst/s) +host_mem_usage 148208 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 650634 # Simulator tick rate (ticks/s) +host_tick_rate 276546720 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 5641 # Number of ticks simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2820500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5642 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index c451577a3..6848303a8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:43 2006 +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:40 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic -Exiting @ tick 5641 because target called exit() +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 13004a42a..6daf0bd85 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -79,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -118,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -157,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -190,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -199,6 +154,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -213,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -224,14 +181,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 58b3f5296..7041702bf 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -30,6 +29,7 @@ executable=tests/test-progs/hello/bin/alpha/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,7 +48,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,56 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 68f6bcca4..ad908bf47 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 167195 # Simulator instruction rate (inst/s) -host_mem_usage 179768 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 51710933 # Simulator tick rate (ticks/s) +host_inst_rate 280990 # Simulator instruction rate (inst/s) +host_mem_usage 153668 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 642654954 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1767066 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13168000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3990.760870 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2990.760870 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 367150 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1288000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 275150 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1196000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3977.109589 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2977.109589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 290329 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1022000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 217329 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 949000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3984.721212 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 657479 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2310000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 492479 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2145000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3984.721212 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2984.721212 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 657479 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2310000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 492479 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2145000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 97.858233 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.640117 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3980.490975 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2980.490975 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13960.288809 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12960.288809 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1102596 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3867000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 825596 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3590000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3980.490975 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1102596 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3867000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 825596 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3590000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3980.490975 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2980.490975 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 1102596 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3867000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 825596 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3590000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 122.802112 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.241810 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2984.340136 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1983.340136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1316094 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5733000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 874653 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4851000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2984.340136 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1316094 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5733000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 874653 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2984.340136 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1983.340136 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1316094 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5733000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 874653 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 220.802916 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 232.802947 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1767066 # number of cpu cycles simulated +system.cpu.numCycles 13168000 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr index 87866a2a5..f33d007a7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr @@ -1 +1,2 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 61f79d88f..3fc11f801 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:44 2006 +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:40 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Exiting @ tick 1767066 because target called exit() +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 13168000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index bd6b9bcdc..40a8f1a84 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 58df46dcb..46dc2c36a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -167,7 +168,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index 1919ca3fe..c1b1b7625 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 187 # Number of BTB hits -global.BPredUnit.BTBLookups 653 # Number of BTB lookups -global.BPredUnit.RASInCorrect 41 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 217 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 426 # Number of conditional branches predicted -global.BPredUnit.lookups 832 # Number of BP lookups -global.BPredUnit.usedRAS 170 # Number of times the RAS was used to get a target. -host_inst_rate 19984 # Simulator instruction rate (inst/s) -host_mem_usage 153584 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 6228839 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 8 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 701 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 382 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 132 # Number of BTB hits +global.BPredUnit.BTBLookups 584 # Number of BTB lookups +global.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 208 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 376 # Number of conditional branches predicted +global.BPredUnit.lookups 738 # Number of BP lookups +global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target. +host_inst_rate 54176 # Simulator instruction rate (inst/s) +host_mem_usage 153592 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 46286693 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 357 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 746028 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 2053000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 52 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 29809 +system.cpu.commit.COM:committed_per_cycle.samples 3906 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 28885 9690.03% - 1 239 80.18% - 2 325 109.03% - 3 129 43.28% - 4 78 26.17% - 5 53 17.78% - 6 29 9.73% - 7 19 6.37% - 8 52 17.44% + 0 2949 7549.92% + 1 266 681.00% + 2 333 852.53% + 3 131 335.38% + 4 74 189.45% + 5 64 163.85% + 6 29 74.24% + 7 19 48.64% + 8 41 104.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 128 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1536 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 978 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 312.537914 # CPI: Cycles Per Instruction -system.cpu.cpi_total 312.537914 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 565 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 7055.843750 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7158.016393 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 677361 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.169912 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 436639 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.107965 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.cpi 1.721408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.721408 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5456.521739 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4737.288136 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 445 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.134241 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 69 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114786 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 59 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 7089.086420 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6946.208333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 574216 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 166709 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 5669.014085 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5020 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 223 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 402500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.241497 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 71 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.085034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 25 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.023529 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.952381 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 859 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7071.056497 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency -system.cpu.dcache.demand_hits 682 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1251577 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.206054 # miss rate for demand accesses -system.cpu.dcache.demand_misses 177 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 603348 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.098952 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 808 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency +system.cpu.dcache.demand_hits 668 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 779000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.173267 # miss rate for demand accesses +system.cpu.dcache.demand_misses 140 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 405000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.103960 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 84 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 859 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7071.056497 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7098.211765 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 808 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 682 # number of overall hits -system.cpu.dcache.overall_miss_latency 1251577 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.206054 # miss rate for overall accesses -system.cpu.dcache.overall_misses 177 # number of overall misses -system.cpu.dcache.overall_mshr_hits 92 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 603348 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.098952 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses +system.cpu.dcache.overall_hits 668 # number of overall hits +system.cpu.dcache.overall_miss_latency 779000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.173267 # miss rate for overall accesses +system.cpu.dcache.overall_misses 140 # number of overall misses +system.cpu.dcache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 405000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.103960 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 84 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,91 +119,90 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 84 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.650284 # Cycle average of tags in use -system.cpu.dcache.total_refs 682 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 51.851940 # Cycle average of tags in use +system.cpu.dcache.total_refs 668 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 23701 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 129 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4617 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5228 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 877 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 297 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 4 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 832 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 760 # Number of cache lines fetched -system.cpu.fetch.Cycles 1674 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 131 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5310 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.027635 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 760 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 357 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.176371 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 95 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 123 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4033 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 767 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 202 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 298 # Number of squashed instructions handled by decode +system.cpu.fetch.Branches 738 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 654 # Number of cache lines fetched +system.cpu.fetch.Cycles 1440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 120 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 4685 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 218 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.179606 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 654 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 272 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.140180 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 30107 +system.cpu.fetch.rateDist.samples 4109 system.cpu.fetch.rateDist.min_value 0 - 0 29196 9697.41% - 1 37 12.29% - 2 87 28.90% - 3 73 24.25% - 4 125 41.52% - 5 66 21.92% - 6 42 13.95% - 7 50 16.61% - 8 431 143.16% + 0 3325 8091.99% + 1 32 77.88% + 2 74 180.09% + 3 53 128.99% + 4 99 240.93% + 5 49 119.25% + 6 38 92.48% + 7 35 85.18% + 8 404 983.21% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 760 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4979.783333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4157.255435 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 520 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1195148 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.315789 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 240 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 764935 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.242105 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 184 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 654 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5296.019900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4553.763441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 453 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1064500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.307339 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 201 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 847000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.284404 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.826087 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.435484 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 760 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4979.783333 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency -system.cpu.icache.demand_hits 520 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1195148 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.315789 # miss rate for demand accesses -system.cpu.icache.demand_misses 240 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 764935 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.242105 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 184 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 654 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency +system.cpu.icache.demand_hits 453 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1064500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.307339 # miss rate for demand accesses +system.cpu.icache.demand_misses 201 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 847000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.284404 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 760 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4979.783333 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4157.255435 # average overall mshr miss latency +system.cpu.icache.overall_accesses 654 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 520 # number of overall hits -system.cpu.icache.overall_miss_latency 1195148 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.315789 # miss rate for overall accesses -system.cpu.icache.overall_misses 240 # number of overall misses -system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 764935 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.242105 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 184 # number of overall MSHR misses +system.cpu.icache.overall_hits 453 # number of overall hits +system.cpu.icache.overall_miss_latency 1064500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.307339 # miss rate for overall accesses +system.cpu.icache.overall_misses 201 # number of overall misses +system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 847000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.284404 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,61 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 184 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 91.559894 # Cycle average of tags in use -system.cpu.icache.total_refs 520 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 106.237740 # Cycle average of tags in use +system.cpu.icache.total_refs 453 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 715922 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 547 # Number of branches executed -system.cpu.iew.EXEC:nop 269 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.108081 # Inst execution rate -system.cpu.iew.EXEC:refs 940 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 340 # Number of stores executed +system.cpu.idleCycles 2992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 501 # Number of branches executed +system.cpu.iew.EXEC:nop 234 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.727184 # Inst execution rate +system.cpu.iew.EXEC:refs 878 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 333 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1841 # num instructions consuming a value -system.cpu.iew.WB:count 3178 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.788702 # average fanout of values written-back +system.cpu.iew.WB:consumers 1652 # num instructions consuming a value +system.cpu.iew.WB:count 2914 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.799637 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1452 # num instructions producing a value -system.cpu.iew.WB:rate 0.105557 # insts written-back per cycle -system.cpu.iew.WB:sent 3194 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 16588 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 701 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 62 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 382 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4113 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 600 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 110 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3254 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1321 # num instructions producing a value +system.cpu.iew.WB:rate 0.709175 # insts written-back per cycle +system.cpu.iew.WB:sent 2931 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 135 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 608 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 357 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 3571 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 545 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 87 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2988 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 297 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 202 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 29 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 22 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 286 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 88 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 96 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.003200 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.003200 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3364 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 193 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 63 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.580920 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.580920 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2398 71.28% # Type of FU issued + IntAlu 2178 70.83% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -279,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 618 18.37% # Type of FU issued - MemWrite 347 10.32% # Type of FU issued + MemRead 561 18.24% # Type of FU issued + MemWrite 335 10.89% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010107 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 2.94% # attempts to use FU when none available + IntAlu 2 5.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,43 +296,42 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11 32.35% # attempts to use FU when none available - MemWrite 22 64.71% # attempts to use FU when none available + MemRead 12 34.29% # attempts to use FU when none available + MemWrite 21 60.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 30107 +system.cpu.iq.ISSUE:issued_per_cycle.samples 4109 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 28628 9508.75% - 1 616 204.60% - 2 335 111.27% - 3 225 74.73% - 4 177 58.79% - 5 80 26.57% - 6 31 10.30% - 7 11 3.65% - 8 4 1.33% + 0 2849 6933.56% + 1 475 1156.00% + 2 270 657.09% + 3 217 528.11% + 4 159 386.96% + 5 86 209.30% + 6 34 82.75% + 7 13 31.64% + 8 6 14.60% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.111735 # Inst issue rate -system.cpu.iq.iqInstsAdded 3838 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3364 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1301 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 682 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 269 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4610.717472 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2315.289963 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1240283 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.748357 # Inst issue rate +system.cpu.iq.iqInstsAdded 3330 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3075 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 790 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 409 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 270 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4522.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2388.888889 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1221000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 269 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 622813 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 270 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 645000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 269 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 270 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -342,32 +340,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 269 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4610.717472 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1240283 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1221000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 269 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 622813 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 645000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 269 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 269 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4610.717472 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2315.289963 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1240283 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1221000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 269 # number of overall misses +system.cpu.l2cache.overall_misses 270 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 622813 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 645000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 269 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -380,30 +378,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 269 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 270 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 138.742329 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 158.236294 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 30107 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 16613 # Number of cycles rename is blocking +system.cpu.numCycles 4109 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5311 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 3116 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5020 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4436 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3192 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 802 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 297 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 23 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1424 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 7061 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 4416 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3886 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2777 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 696 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 202 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 6 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1009 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 89 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 9 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 55 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 7 # count of temporary serializing insts renamed +system.cpu.timesIdled 8 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index e582c15a8..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 25e5ec43b..587034bb2 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:05 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:41 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 746028 because target called exit() +Exiting @ tick 2053000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 41c8029a3..20dfddd0a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -90,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -101,14 +60,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index 88d1a9a45..acc734991 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -30,6 +29,7 @@ executable=tests/test-progs/hello/bin/alpha/tru64/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,61 +48,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 25dace389..e82d837af 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 480164 # Simulator instruction rate (inst/s) -host_mem_usage 147928 # Number of bytes of host memory used +host_inst_rate 484860 # Simulator instruction rate (inst/s) +host_mem_usage 147796 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 437596 # Simulator tick rate (ticks/s) +host_tick_rate 225459318 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 2577 # Number of ticks simulated +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 1288500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2578 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr index b3cdfe967..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr @@ -1,2 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 099a6d041..3b5348194 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:50 2006 +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic -Exiting @ tick 2577 because target called exit() +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1288500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 62041169c..1c1daa355 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -79,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -118,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -157,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -190,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -199,6 +154,7 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -213,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -224,14 +181,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 85dfbaa94..45a8521ac 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -30,6 +29,7 @@ executable=tests/test-progs/hello/bin/alpha/tru64/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -48,7 +48,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,56 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 010da4162..756244d02 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153015 # Simulator instruction rate (inst/s) -host_mem_usage 179088 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 56749783 # Simulator tick rate (ticks/s) +host_inst_rate 228404 # Simulator instruction rate (inst/s) +host_mem_usage 153176 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 552831639 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 980012 # Number of ticks simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 6472000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3988.472727 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2988.472727 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 219366 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 770000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 164366 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 715000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3991.518519 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2991.518519 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 107771 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 378000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 80771 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 351000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3989.475610 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 327137 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1148000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 245137 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1066000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3989.475610 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2989.475610 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.overall_miss_latency 327137 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1148000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 245137 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1066000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 45.884153 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 50.002941 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3986.705521 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2986.705521 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 649833 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2282000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 486833 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2119000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3986.705521 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 649833 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2282000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 486833 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2119000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3986.705521 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2986.705521 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2416 # number of overall hits -system.cpu.icache.overall_miss_latency 649833 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2282000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 486833 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2119000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 76.367476 # Cycle average of tags in use +system.cpu.icache.tagsinuse 86.067224 # Cycle average of tags in use system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2987.632653 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1986.632653 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 731970 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 3185000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 486725 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 2695000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2987.632653 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 731970 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3185000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 486725 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2987.632653 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1986.632653 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 731970 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 3185000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 486725 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 122.501625 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.108021 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 980012 # number of cpu cycles simulated +system.cpu.numCycles 6472000 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr index b3cdfe967..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr @@ -1,2 +1,3 @@ warn: Entering event queue @ 0. Starting simulation... +warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index cf7a58ef1..f5e3a6008 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:51 2006 +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing -Exiting @ tick 980012 because target called exit() +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 6472000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 59cadaa12..ea3ba751b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -1,50 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -55,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -64,7 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.physmem +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -90,8 +48,10 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 +responder_set=false width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port @@ -100,14 +60,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out index 064f467da..06a3d271d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -21,6 +19,8 @@ type=Bus bus_id=0 clock=1000 width=64 +responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -29,6 +29,7 @@ executable=tests/test-progs/hello/bin/mips/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -44,64 +45,14 @@ max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 progress_interval=0 -mem=system.physmem system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index 3b2a2730b..6a0c251b5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 52255 # Simulator instruction rate (inst/s) -host_mem_usage 148024 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 52038 # Simulator tick rate (ticks/s) +host_inst_rate 535701 # Simulator instruction rate (inst/s) +host_mem_usage 148368 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 257653061 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 5656 # Number of ticks simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2828000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5657 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index 600b178b3..7fb23e5a5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 9 2006 19:28:25 -M5 started Mon Oct 9 19:28:56 2006 +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic -Exiting @ tick 5656 because target called exit() +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 8e1bb0388..a5d4e6583 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -1,50 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -55,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -64,7 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -78,10 +35,8 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -118,10 +73,8 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -158,10 +111,8 @@ assoc=2 block_size=64 compressed_bus=false compression_latency=0 -do_copy=false hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -193,14 +144,17 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 +responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -215,8 +169,10 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 +responder_set=false width=64 port=system.physmem.port system.cpu.l2cache.mem_side @@ -225,14 +181,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out index d683d2355..3f8a51cf4 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -21,45 +19,8 @@ type=Bus bus_id=0 clock=1000 width=64 - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 +responder_set=false block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -do_copy=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.workload] type=LiveProcess @@ -68,6 +29,7 @@ executable=tests/test-progs/hello/bin/mips/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -83,11 +45,11 @@ max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 progress_interval=0 -mem=system.cpu.dcache system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -99,18 +61,56 @@ type=Bus bus_id=0 clock=1000 width=64 +responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -137,19 +137,17 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 prioritizeRequests=false -do_copy=false protocol=null trace_addr=0 hash_delay=1 @@ -176,55 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index ae23f7eec..41bb7c8b7 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 57798 # Simulator instruction rate (inst/s) -host_mem_usage 179040 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 17679602 # Simulator tick rate (ticks/s) +host_inst_rate 273338 # Simulator instruction rate (inst/s) +host_mem_usage 153844 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 633390216 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1738011 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13362000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3987.109756 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2987.109756 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 326943 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1148000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 244943 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1066000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3968.740000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2968.740000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 198437 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 700000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 148437 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 650000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3980.151515 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 525380 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1848000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 393380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1716000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3980.151515 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2980.151515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1922 # number of overall hits -system.cpu.dcache.overall_miss_latency 525380 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1848000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 393380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1716000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 82.396200 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 85.283494 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3978.069307 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2978.069307 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13986.798680 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12986.798680 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1205355 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 4238000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 902355 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3935000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3978.069307 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1205355 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 4238000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 902355 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3935000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3978.069307 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2978.069307 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 1205355 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 4238000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 902355 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3935000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.062649 # Cycle average of tags in use +system.cpu.icache.tagsinuse 136.309471 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2983.237875 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1982.237875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1291742 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 5629000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 858309 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4763000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2983.237875 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1291742 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5629000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 858309 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2983.237875 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1982.237875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1291742 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5629000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 858309 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 216.976175 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.872415 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1738011 # number of cpu cycles simulated +system.cpu.numCycles 13362000 # number of cpu cycles simulated system.cpu.num_insts 5657 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 8722547ad..6b688641a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,8 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 13 2006 18:43:33 -M5 started Fri Oct 13 18:44:16 2006 +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/MIPS_SE/m5.debug -d build/MIPS_SE/tests/debug/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing -Exiting @ tick 1738011 because target called exit() +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 13362000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 9da46d74f..0e142e6ce 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -1,50 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -55,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -64,7 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.physmem +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -76,6 +33,7 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -90,8 +48,10 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 +responder_set=false width=64 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port @@ -100,14 +60,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out index fc125a624..1666790d0 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -21,6 +19,8 @@ type=Bus bus_id=0 clock=1000 width=64 +responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -29,6 +29,7 @@ executable=tests/test-progs/hello/bin/sparc/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -44,64 +45,14 @@ max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 progress_interval=0 -mem=system.physmem system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 5c79f4d62..8e0baaf8b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 58121 # Simulator instruction rate (inst/s) -host_mem_usage 148396 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 57840 # Simulator tick rate (ticks/s) +host_inst_rate 439375 # Simulator instruction rate (inst/s) +host_mem_usage 149124 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 211870315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 4862 # Number of ticks simulated +sim_seconds 0.000002 # Number of seconds simulated +sim_ticks 2431000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 4863 # number of cpu cycles simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 1d76c6089..9e1770f92 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 27 2006 02:07:29 -M5 started Fri Oct 27 02:08:08 2006 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic -Exiting @ tick 4862 because target called exit() +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2431000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index da87d03a1..fdb2bc3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -1,50 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -55,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -64,7 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu.dcache +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -79,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -118,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -157,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -190,14 +144,17 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 +responder_set=false width=64 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side [system.cpu.workload] type=LiveProcess cmd=hello +cwd= egid=100 env= euid=100 @@ -212,8 +169,10 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 +responder_set=false width=64 port=system.physmem.port system.cpu.l2cache.mem_side @@ -222,14 +181,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out index 5210081b3..89910d3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -21,44 +19,8 @@ type=Bus bus_id=0 clock=1000 width=64 - -[system.cpu.dcache] -type=BaseCache -size=262144 -assoc=2 +responder_set=false block_size=64 -latency=1 -mshrs=10 -tgts_per_mshr=5 -write_buffers=8 -prioritizeRequests=false -protocol=null -trace_addr=0 -hash_delay=1 -repl=null -compressed_bus=false -store_compressed=false -adaptive_compression=false -compression_latency=0 -block_size=64 -max_miss_count=0 -addr_range=[0,18446744073709551615] -split=false -split_size=0 -lifo=false -two_queue=false -prefetch_miss=false -prefetch_access=false -prefetcher_size=100 -prefetch_past_page=false -prefetch_serial_squash=false -prefetch_latency=10 -prefetch_degree=1 -prefetch_policy=none -prefetch_cache_check_push=true -prefetch_use_cpu_id=true -prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.workload] type=LiveProcess @@ -67,6 +29,7 @@ executable=tests/test-progs/hello/bin/sparc/linux/hello input=cin output=cout env= +cwd= system=system uid=100 euid=100 @@ -82,11 +45,11 @@ max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 progress_interval=0 -mem=system.cpu.dcache system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -98,13 +61,52 @@ type=Bus bus_id=0 clock=1000 width=64 +responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -135,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -173,55 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index b0f73986b..839307810 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 158849 # Simulator instruction rate (inst/s) -host_mem_usage 179428 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 50697812 # Simulator tick rate (ticks/s) +host_inst_rate 239687 # Simulator instruction rate (inst/s) +host_mem_usage 154512 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 542234464 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1573001 # Number of ticks simulated +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11221000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3971.370370 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2971.370370 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13796.296296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12796.296296 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 214454 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 745000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 160454 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 691000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3981.559524 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2981.559524 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 334451 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1176000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 250451 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1092000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3977.572464 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 548905 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1921000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 410905 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1783000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3977.572464 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2977.572464 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1131 # number of overall hits -system.cpu.dcache.overall_miss_latency 548905 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1921000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 410905 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1783000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.997528 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.705022 # Cycle average of tags in use system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3977.960938 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.960938 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13914.062500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12914.062500 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1018358 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3562000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 762358 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3306000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3977.960938 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1018358 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3562000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 762358 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3306000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3977.960938 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2977.960938 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4608 # number of overall hits -system.cpu.icache.overall_miss_latency 1018358 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3562000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 762358 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3306000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 114.778311 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.172725 # Cycle average of tags in use system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2985.429668 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1984.429668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1167303 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5083000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 775912 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4301000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2985.429668 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1167303 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5083000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 775912 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4301000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2985.429668 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1984.429668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1167303 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5083000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 775912 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4301000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 195.424915 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.304892 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1573001 # number of cpu cycles simulated +system.cpu.numCycles 11221000 # number of cpu cycles simulated system.cpu.num_insts 4863 # Number of instructions executed system.cpu.num_refs 1269 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index b1da2e4ab..65bf4abca 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 27 2006 02:07:29 -M5 started Fri Oct 27 02:08:11 2006 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing -Exiting @ tick 1573001 because target called exit() +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 11221000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index e11ca74dd..5380fc831 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -379,6 +377,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index 0d9c5215b..c8129d10d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload0] type=LiveProcess @@ -183,7 +184,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 @@ -265,7 +266,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -296,14 +297,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -334,14 +334,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -372,7 +371,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -380,4 +378,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 684314d31..484bdcca9 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 827 # Number of BTB hits -global.BPredUnit.BTBLookups 3697 # Number of BTB lookups -global.BPredUnit.RASInCorrect 179 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1207 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2534 # Number of conditional branches predicted -global.BPredUnit.lookups 4455 # Number of BP lookups -global.BPredUnit.usedRAS 640 # Number of times the RAS was used to get a target. -host_inst_rate 15344 # Simulator instruction rate (inst/s) -host_mem_usage 154676 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host -host_tick_rate 2857242 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 24 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 4 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 5 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2132 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2142 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1150 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1138 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 674 # Number of BTB hits +global.BPredUnit.BTBLookups 3410 # Number of BTB lookups +global.BPredUnit.RASInCorrect 118 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1115 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2318 # Number of conditional branches predicted +global.BPredUnit.lookups 3964 # Number of BP lookups +global.BPredUnit.usedRAS 532 # Number of times the RAS was used to get a target. +host_inst_rate 56668 # Simulator instruction rate (inst/s) +host_mem_usage 154692 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 27618195 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1898 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1088 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1090 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2095164 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 5490000 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 123 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 165 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 165684 +system.cpu.commit.COM:committed_per_cycle.samples 10929 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 159919 9652.05% - 1 3333 201.17% - 2 1165 70.31% - 3 515 31.08% - 4 270 16.30% - 5 201 12.13% - 6 102 6.16% - 7 56 3.38% - 8 123 7.42% + 0 6410 5865.13% + 1 2019 1847.38% + 2 999 914.08% + 3 454 415.41% + 4 300 274.50% + 5 246 225.09% + 6 200 183.00% + 7 136 124.44% + 8 165 150.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -61,141 +61,133 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 947 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 874 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9432 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7769 # The number of squashed insts skipped by commit system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 372.606082 # CPI: Cycles Per Instruction -system.cpu.cpi_1 372.539829 # CPI: Cycles Per Instruction -system.cpu.cpi_total 186.286476 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3234 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3234 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10308.511696 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 10308.511696 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10789.975000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10789.975000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2892 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2892 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3525511 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 3525511 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.105751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.105751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 342 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 342 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 142 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 142 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2157995 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 2157995 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.061843 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.061843 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 200 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 200 # number of ReadReq MSHR misses +system.cpu.cpi_0 1.952516 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.952169 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976171 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 7072.992701 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6972.361809 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.092287 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067026 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8945.050491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 8945.050491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9931.897260 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 9931.897260 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 911 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 911 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6377821 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 6377821 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.439039 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.439039 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 713 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 713 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 567 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 567 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1450057 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1450057 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency_0 5352.409639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 5859.589041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.306650 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 855500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 855500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 994 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.991329 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.avg_refs 11.075362 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 994 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4858 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4858 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4593 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4593 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9387.044550 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 9387.044550 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10427.895954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 10427.895954 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3803 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3803 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3821 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3821 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9903332 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 9903332 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 4603500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 4603500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.217168 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.217168 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.168082 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 1055 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 1055 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 772 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 772 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 709 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 709 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 427 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 427 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3608052 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 3608052 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2243000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 2243000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.071223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.071223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075114 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 346 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 345 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4858 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4858 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4593 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4593 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9387.044550 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 9387.044550 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10427.895954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 10427.895954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3803 # number of overall hits -system.cpu.dcache.overall_hits_0 3803 # number of overall hits +system.cpu.dcache.overall_hits 3821 # number of overall hits +system.cpu.dcache.overall_hits_0 3821 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 9903332 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 9903332 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 4603500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 4603500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.217168 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.217168 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.168082 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 1055 # number of overall misses -system.cpu.dcache.overall_misses_0 1055 # number of overall misses +system.cpu.dcache.overall_misses 772 # number of overall misses +system.cpu.dcache.overall_misses_0 772 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 709 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 709 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 427 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 427 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3608052 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 3608052 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2243000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 2243000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.071223 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.071223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075114 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 346 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,153 +207,149 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 346 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 345 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 200.098842 # Cycle average of tags in use -system.cpu.dcache.total_refs 3803 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 221.724795 # Cycle average of tags in use +system.cpu.dcache.total_refs 3821 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 112235 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 273 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 396 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 24032 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 212833 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4096 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1856 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 672 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 181 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4455 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3542 # Number of cache lines fetched -system.cpu.fetch.Cycles 8000 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 26459 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1268 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.026888 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3542 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1467 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.159692 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 1857 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 251 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 21806 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 14535 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3658 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1498 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 351 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 145 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 3964 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2983 # Number of cache lines fetched +system.cpu.fetch.Cycles 6940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 24033 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1178 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.361053 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2983 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1206 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.188997 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 165688 +system.cpu.fetch.rateDist.samples 10979 system.cpu.fetch.rateDist.min_value 0 - 0 161234 9731.18% - 1 342 20.64% - 2 283 17.08% - 3 285 17.20% - 4 390 23.54% - 5 369 22.27% - 6 367 22.15% - 7 255 15.39% - 8 2163 130.55% + 0 7023 6396.76% + 1 285 259.59% + 2 224 204.03% + 3 248 225.89% + 4 335 305.13% + 5 281 255.94% + 6 301 274.16% + 7 251 228.62% + 8 2031 1849.90% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3542 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3542 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 7880.839306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 7880.839306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 7272.060897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7272.060897 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2677 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2677 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6816926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 6816926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.244212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.244212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 865 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 865 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 241 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 241 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4537766 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 4537766 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.176172 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.176172 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 624 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 624 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 5910.313901 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5152.173913 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.224271 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 669 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 669 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.208180 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 621 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.290064 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.726248 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3542 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3542 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2983 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2983 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 7880.839306 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 7880.839306 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 7272.060897 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 7272.060897 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2677 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2677 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2314 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2314 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6816926 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 6816926 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3954000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 3954000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.244212 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.244212 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.224271 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 865 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 865 # number of demand (read+write) misses +system.cpu.icache.demand_misses 669 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 669 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 241 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 241 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 48 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4537766 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 4537766 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3199500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 3199500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.176172 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.176172 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.208180 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 624 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 624 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 621 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3542 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3542 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2983 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2983 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 7880.839306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 7880.839306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 7272.060897 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 7272.060897 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2677 # number of overall hits -system.cpu.icache.overall_hits_0 2677 # number of overall hits +system.cpu.icache.overall_hits 2314 # number of overall hits +system.cpu.icache.overall_hits_0 2314 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 6816926 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 6816926 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3954000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 3954000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.244212 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.244212 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.224271 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 865 # number of overall misses -system.cpu.icache.overall_misses_0 865 # number of overall misses +system.cpu.icache.overall_misses 669 # number of overall misses +system.cpu.icache.overall_misses_0 669 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 241 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 241 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 48 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4537766 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 4537766 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3199500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 3199500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.176172 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.176172 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.208180 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 624 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 624 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 621 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -378,107 +366,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6 # number of replacements -system.cpu.icache.replacements_0 6 # number of replacements +system.cpu.icache.replacements 9 # number of replacements +system.cpu.icache.replacements_0 9 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 621 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 289.929418 # Cycle average of tags in use -system.cpu.icache.total_refs 2677 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 322.894952 # Cycle average of tags in use +system.cpu.icache.total_refs 2314 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 1929477 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2535 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1269 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1266 # Number of branches executed -system.cpu.iew.EXEC:nop 84 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 42 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 42 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.100864 # Inst execution rate -system.cpu.iew.EXEC:refs 5422 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2727 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2695 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1997 # Number of stores executed -system.cpu.iew.EXEC:stores_0 1003 # Number of stores executed -system.cpu.iew.EXEC:stores_1 994 # Number of stores executed +system.cpu.idleCycles 1998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2367 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1185 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1182 # Number of branches executed +system.cpu.iew.EXEC:nop 73 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 37 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 36 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.416158 # Inst execution rate +system.cpu.iew.EXEC:refs 4978 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2514 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2464 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1867 # Number of stores executed +system.cpu.iew.EXEC:stores_0 938 # Number of stores executed +system.cpu.iew.EXEC:stores_1 929 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10258 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5162 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5096 # num instructions consuming a value -system.cpu.iew.WB:count 16101 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 8089 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 8012 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.770326 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.768888 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.771782 # average fanout of values written-back +system.cpu.iew.WB:consumers 10219 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5113 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5106 # num instructions consuming a value +system.cpu.iew.WB:count 14974 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7532 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7442 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.526960 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.762957 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.764003 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7902 # num instructions producing a value -system.cpu.iew.WB:producers_0 3969 # num instructions producing a value -system.cpu.iew.WB:producers_1 3933 # num instructions producing a value -system.cpu.iew.WB:rate 0.097177 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.048821 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.048356 # insts written-back per cycle -system.cpu.iew.WB:sent 16249 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 8166 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 8083 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 84087 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4274 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 468 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2288 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 20693 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3425 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1724 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1701 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 741 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 16712 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7802 # num instructions producing a value +system.cpu.iew.WB:producers_0 3901 # num instructions producing a value +system.cpu.iew.WB:producers_1 3901 # num instructions producing a value +system.cpu.iew.WB:rate 1.363876 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.686037 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.677840 # insts written-back per cycle +system.cpu.iew.WB:sent 15105 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7590 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7515 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 941 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 7 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3823 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 501 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2178 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19078 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3111 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1576 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1535 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 864 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15548 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1856 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 131 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1498 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 70 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 42 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 60 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1153 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 338 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 946 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 276 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 65 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 38 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 59 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 54 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1163 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 326 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 119 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 791 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 240 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.002684 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.002684 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.005368 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8768 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 919 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 278 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 117 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 761 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 180 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.512160 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.512251 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024410 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8232 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5895 67.23% # Type of FU issued + IntAlu 5551 67.43% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +475,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1838 20.96% # Type of FU issued - MemWrite 1030 11.75% # Type of FU issued + MemRead 1704 20.70% # Type of FU issued + MemWrite 972 11.81% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8685 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8180 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5859 67.46% # Type of FU issued + IntAlu 5536 67.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +492,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1800 20.73% # Type of FU issued - MemWrite 1021 11.76% # Type of FU issued + MemRead 1681 20.55% # Type of FU issued + MemWrite 958 11.71% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 17453 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16412 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist (null) 4 0.02% # Type of FU issued - IntAlu 11754 67.35% # Type of FU issued + IntAlu 11087 67.55% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +509,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3638 20.84% # Type of FU issued - MemWrite 2051 11.75% # Type of FU issued + MemRead 3385 20.63% # Type of FU issued + MemWrite 1930 11.76% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 69 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 64 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007620 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.003953 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.003667 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 92 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010968 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.005606 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005362 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 0 0.00% # attempts to use FU when none available + IntAlu 16 8.89% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,133 +531,131 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 79 59.40% # attempts to use FU when none available - MemWrite 54 40.60% # attempts to use FU when none available + MemRead 97 53.89% # attempts to use FU when none available + MemWrite 67 37.22% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 165688 +system.cpu.iq.ISSUE:issued_per_cycle.samples 10979 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 156701 9457.59% - 1 4387 264.77% - 2 2473 149.26% - 3 1076 64.94% - 4 569 34.34% - 5 325 19.62% - 6 120 7.24% - 7 25 1.51% - 8 12 0.72% + 0 4788 4361.05% + 1 1816 1654.07% + 2 1657 1509.24% + 3 1039 946.35% + 4 774 704.98% + 5 501 456.33% + 6 289 263.23% + 7 90 81.97% + 8 25 22.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.105337 # Inst issue rate -system.cpu.iq.iqInstsAdded 20568 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 17453 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 41 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 214 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4870 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 7151.675620 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 7151.675620 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 3855.918388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3855.918388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 6922822 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 6922822 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 968 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 968 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3732529 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 3732529 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 968 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 968 # number of ReadReq MSHR misses +system.cpu.iq.ISSUE:rate 1.494854 # Inst issue rate +system.cpu.iq.iqInstsAdded 18963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16412 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 5220.374220 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2725.051975 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.998962 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998962 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 962 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.001040 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 963 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 963 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 7151.675620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 7151.675620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 3855.918388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3855.918388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6922822 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 6922822 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5022000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 5022000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.998962 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 968 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 968 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 962 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3732529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 3732529 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2621500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 2621500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.998962 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 968 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 968 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 962 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 963 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 963 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 7151.675620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 7151.675620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 3855.918388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3855.918388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_hits_0 0 # number of overall hits +system.cpu.l2cache.overall_hits 1 # number of overall hits +system.cpu.l2cache.overall_hits_0 1 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6922822 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 6922822 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5022000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 5022000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.998962 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 968 # number of overall misses -system.cpu.l2cache.overall_misses_0 968 # number of overall misses +system.cpu.l2cache.overall_misses 962 # number of overall misses +system.cpu.l2cache.overall_misses_0 962 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3732529 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 3732529 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2621500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 2621500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.998962 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 968 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 968 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 962 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -689,35 +675,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 968 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 962 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 491.189820 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 545.133409 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 165688 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 87802 # Number of cycles rename is blocking +system.cpu.numCycles 10979 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 614 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 24 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 213369 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2127 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 28570 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 22635 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 17117 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3694 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1856 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2143 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 9015 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 22337 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 51 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4330 # count of insts added to the skid buffer +system.cpu.rename.RENAME:IdleCycles 14840 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 684 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26359 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 20748 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15612 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3480 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1498 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 744 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7510 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 517 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2147 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.timesIdled 688 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr index 54505c240..d0a887867 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -1,5 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 -0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: Increasing stack size by one page. diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index b4ae56cae..ef617d5ef 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 13:12:55 -M5 started Fri Mar 30 13:13:07 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:42 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2095164 because target called exit() +Exiting @ tick 5490000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index f804a40fe..61102139c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -23,7 +23,7 @@ activity=0 backComSize=5 choiceCtrBits=2 choicePredictorSize=8192 -clock=1 +clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 commitToIEWDelay=1 @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out index d248f77bf..70564f749 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -167,7 +168,7 @@ FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUL [system.cpu] type=DerivO3CPU -clock=1 +clock=500 phase=0 numThreads=1 cpu_id=0 @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 7c0d31494..7859d5c2b 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 2990 # Number of BTB hits -global.BPredUnit.BTBLookups 7055 # Number of BTB lookups +global.BPredUnit.BTBHits 2726 # Number of BTB hits +global.BPredUnit.BTBLookups 7230 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2077 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 7846 # Number of conditional branches predicted -global.BPredUnit.lookups 7846 # Number of BP lookups +global.BPredUnit.condIncorrect 2062 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 7954 # Number of conditional branches predicted +global.BPredUnit.lookups 7954 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 15119 # Simulator instruction rate (inst/s) -host_mem_usage 154868 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host -host_tick_rate 1956796 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. +host_inst_rate 37089 # Simulator instruction rate (inst/s) +host_mem_usage 154932 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 53780846 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3250 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2817 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 3198 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2970 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1421211 # Number of ticks simulated +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 15931500 # Number of ticks simulated system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 172 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 146 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 221349 +system.cpu.commit.COM:committed_per_cycle.samples 28801 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 215844 9751.30% - 1 2970 134.18% - 2 1290 58.28% - 3 631 28.51% - 4 208 9.40% - 5 90 4.07% - 6 133 6.01% - 7 11 0.50% - 8 172 7.77% + 0 23411 8128.54% + 1 2862 993.72% + 2 1174 407.62% + 3 608 211.10% + 4 359 124.65% + 5 123 42.71% + 6 103 35.76% + 7 15 5.21% + 8 146 50.69% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,71 +43,71 @@ system.cpu.commit.COM:loads 1462 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2760 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2077 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 14263 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14297 # The number of squashed insts skipped by commit system.cpu.committedInsts 10976 # Number of Instructions Simulated system.cpu.committedInsts_total 10976 # Number of Instructions Simulated -system.cpu.cpi 129.483509 # CPI: Cycles Per Instruction -system.cpu.cpi_total 129.483509 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2737 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6585.044776 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6511.939394 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2603 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 882396 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.048959 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 429788 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.024114 # mshr miss rate for ReadReq accesses +system.cpu.cpi 2.903061 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.903061 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2743 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5392.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4696.969697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2659 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 453000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.030623 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 84 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 310000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.024061 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 7960.583924 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7136.918605 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 869 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3367327 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.327399 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 423 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 337 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 613775 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 5505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4802.325581 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1092 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1101000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.154799 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 200 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 114 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 413000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 22.881579 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 24.717105 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4029 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7629.664273 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 6865.546053 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3472 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4249723 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.138248 # miss rate for demand accesses -system.cpu.dcache.demand_misses 557 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 405 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1043563 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.037726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 4035 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5471.830986 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3751 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1554000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.070384 # miss rate for demand accesses +system.cpu.dcache.demand_misses 284 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.037670 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4029 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7629.664273 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 6865.546053 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 4035 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5471.830986 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3472 # number of overall hits -system.cpu.dcache.overall_miss_latency 4249723 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.138248 # miss rate for overall accesses -system.cpu.dcache.overall_misses 557 # number of overall misses -system.cpu.dcache.overall_mshr_hits 405 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1043563 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.037726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 3751 # number of overall hits +system.cpu.dcache.overall_miss_latency 1554000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.070384 # miss rate for overall accesses +system.cpu.dcache.overall_misses 284 # number of overall misses +system.cpu.dcache.overall_mshr_hits 132 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 723000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.037670 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -123,86 +123,86 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 90.938737 # Cycle average of tags in use -system.cpu.dcache.total_refs 3478 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 113.439038 # Cycle average of tags in use +system.cpu.dcache.total_refs 3757 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 192719 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 39774 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 20128 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 8238 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 3162 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 264 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 7846 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 5085 # Number of cache lines fetched -system.cpu.fetch.Cycles 14399 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 745 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 43304 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2134 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.034947 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 5085 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2990 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.192881 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 4602 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 38937 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 16098 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 7883 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 3063 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 218 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 7954 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4933 # Number of cache lines fetched +system.cpu.fetch.Cycles 14166 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 44421 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2121 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.249623 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 2726 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.394081 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 224511 +system.cpu.fetch.rateDist.samples 31864 system.cpu.fetch.rateDist.min_value 0 - 0 215198 9585.19% - 1 2258 100.57% - 2 627 27.93% - 3 958 42.67% - 4 553 24.63% - 5 816 36.35% - 6 951 42.36% - 7 280 12.47% - 8 2870 127.83% + 0 22632 7102.69% + 1 2187 686.35% + 2 562 176.37% + 3 869 272.72% + 4 521 163.51% + 5 770 241.65% + 6 886 278.06% + 7 243 76.26% + 8 3194 1002.39% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 5085 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 5148.266776 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4502.972752 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4474 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3145591 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.120157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 611 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 244 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1652591 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.072173 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 367 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 4933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5310.666667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4396.174863 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 4558 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1991500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.076019 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 375 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.074194 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12.325069 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12.453552 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5085 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 5148.266776 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4502.972752 # average overall mshr miss latency -system.cpu.icache.demand_hits 4474 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3145591 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.120157 # miss rate for demand accesses -system.cpu.icache.demand_misses 611 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 244 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1652591 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.072173 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 367 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 4933 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5310.666667 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency +system.cpu.icache.demand_hits 4558 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1991500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.076019 # miss rate for demand accesses +system.cpu.icache.demand_misses 375 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.074194 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5085 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 5148.266776 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4502.972752 # average overall mshr miss latency +system.cpu.icache.overall_accesses 4933 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5310.666667 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4474 # number of overall hits -system.cpu.icache.overall_miss_latency 3145591 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.120157 # miss rate for overall accesses -system.cpu.icache.overall_misses 611 # number of overall misses -system.cpu.icache.overall_mshr_hits 244 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1652591 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.072173 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 367 # number of overall MSHR misses +system.cpu.icache.overall_hits 4558 # number of overall hits +system.cpu.icache.overall_miss_latency 1991500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.076019 # miss rate for overall accesses +system.cpu.icache.overall_misses 375 # number of overall misses +system.cpu.icache.overall_mshr_hits 9 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.074194 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 366 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,61 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 363 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 172.869174 # Cycle average of tags in use -system.cpu.icache.total_refs 4474 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 233.760012 # Cycle average of tags in use +system.cpu.icache.total_refs 4558 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1196701 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3576 # Number of branches executed +system.cpu.idleCycles 499 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3548 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.092548 # Inst execution rate -system.cpu.iew.EXEC:refs 5257 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2386 # Number of stores executed +system.cpu.iew.EXEC:rate 0.670318 # Inst execution rate +system.cpu.iew.EXEC:refs 5385 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2502 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9737 # num instructions consuming a value -system.cpu.iew.WB:count 19769 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.790901 # average fanout of values written-back +system.cpu.iew.WB:consumers 10159 # num instructions consuming a value +system.cpu.iew.WB:count 20199 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790629 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7701 # num instructions producing a value -system.cpu.iew.WB:rate 0.088054 # insts written-back per cycle -system.cpu.iew.WB:sent 20061 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2593 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 476 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3250 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 617 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2705 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2817 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 25240 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2871 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1780 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 20778 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 8032 # num instructions producing a value +system.cpu.iew.WB:rate 0.633913 # insts written-back per cycle +system.cpu.iew.WB:sent 20448 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2568 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3198 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 610 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2750 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2970 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 25274 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2883 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 21359 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 3162 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 3063 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 39 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 52 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1788 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1519 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1631 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.007723 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.007723 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 22558 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 1736 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1672 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 52 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1610 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.344464 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.344464 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 22822 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 1831 8.12% # Type of FU issued - IntAlu 15054 66.73% # Type of FU issued + (null) 1826 8.00% # Type of FU issued + IntAlu 15247 66.81% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3091 13.70% # Type of FU issued - MemWrite 2582 11.45% # Type of FU issued + MemRead 3042 13.33% # Type of FU issued + MemWrite 2707 11.86% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007181 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 190 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 42 25.93% # attempts to use FU when none available + IntAlu 50 26.32% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 14 8.64% # attempts to use FU when none available - MemWrite 106 65.43% # attempts to use FU when none available + MemRead 25 13.16% # attempts to use FU when none available + MemWrite 115 60.53% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 224511 +system.cpu.iq.ISSUE:issued_per_cycle.samples 31864 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 215315 9590.40% - 1 4124 183.69% - 2 1297 57.77% - 3 1306 58.17% - 4 1190 53.00% - 5 707 31.49% - 6 433 19.29% - 7 83 3.70% - 8 56 2.49% + 0 22879 7180.20% + 1 3824 1200.10% + 2 1304 409.24% + 3 1251 392.61% + 4 1252 392.92% + 5 751 235.69% + 6 414 129.93% + 7 122 38.29% + 8 67 21.03% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.100476 # Inst issue rate -system.cpu.iq.iqInstsAdded 24623 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 22558 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 617 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 11469 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 174 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 290 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5834 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 513 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4754.779727 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2343.506823 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2439202 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.716231 # Inst issue rate +system.cpu.iq.iqInstsAdded 24664 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 22822 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 610 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 11119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 5685 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4458.171206 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2373.540856 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2291500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 513 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1202219 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 514 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1220000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 513 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 513 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4754.779727 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2343.506823 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 514 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4458.171206 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2439202 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2291500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 513 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 514 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1202219 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1220000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 513 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 514 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 513 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4754.779727 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2343.506823 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 514 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4458.171206 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2439202 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2291500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 513 # number of overall misses +system.cpu.l2cache.overall_misses 514 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1202219 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1220000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 513 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 514 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,32 +379,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 512 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 514 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 262.946375 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 345.564898 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 224511 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 960 # Number of cycles rename is blocking +system.cpu.numCycles 31864 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 20098 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 481 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 46931 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 31260 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 25831 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 7921 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 3162 # Number of cycles rename is squashing -system.cpu.rename.RENAME:SquashedInsts 8042 # Number of squashed instructions processed by rename -system.cpu.rename.RENAME:UnblockCycles 1212 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 15963 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 190573 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 638 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5594 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 629 # count of temporary serializing insts renamed -system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IdleCycles 16082 # Number of cycles rename is idle +system.cpu.rename.RENAME:RenameLookups 44650 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 29655 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 24195 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 7618 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 3063 # Number of cycles rename is squashing +system.cpu.rename.RENAME:SquashedInsts 8815 # Number of squashed instructions processed by rename +system.cpu.rename.RENAME:UnblockCycles 684 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 14327 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 3915 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 631 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4702 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 623 # count of temporary serializing insts renamed +system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr index 48affb0e2..7873672f2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr @@ -1,4 +1,3 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index 6cba2ba7e..0b6e54449 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 9 2007 03:06:26 -M5 started Mon Apr 9 03:06:54 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:06 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1421211 because target called exit() +Exiting @ tick 15931500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 06059c3eb..5493b952f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out index 7f9a83d25..c1a77ba0d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false width=1 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index 1ed7d50eb..468b3f0a1 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 65718 # Simulator instruction rate (inst/s) -host_mem_usage 179556 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 65601 # Simulator tick rate (ticks/s) +host_inst_rate 563720 # Simulator instruction rate (inst/s) +host_mem_usage 149048 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 276035132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 11000 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 5500000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 11001 # number of cpu cycles simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr index a3b9f045a..7873672f2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr @@ -1,4 +1,3 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index c89235e64..01c59e833 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 29 2007 15:29:35 -M5 started Thu Mar 29 15:39:35 2007 -M5 executing on zeep -command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Exiting @ tick 11000 because target called exit() +Exiting @ tick 5500000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 85d14933a..2e2789f26 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -12,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out index ec2d1886a..df1a9c852 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -47,7 +48,7 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index a4396b3da..33502bf5c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 39129 # Simulator instruction rate (inst/s) -host_mem_usage 153232 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -host_tick_rate 6030675 # Simulator tick rate (ticks/s) +host_inst_rate 346412 # Simulator instruction rate (inst/s) +host_mem_usage 154396 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 598818775 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1698003 # Number of ticks simulated +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 19264000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3977.759259 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2977.759259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 214799 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 756000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 160799 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 702000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3963.647727 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2963.647727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1204 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 348801 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1232000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.068111 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 88 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 260801 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1144000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.068111 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 88 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3969.014085 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2969.014085 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 2612 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 563600 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1988000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.051561 # miss rate for demand accesses system.cpu.dcache.demand_misses 142 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 421600 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1846000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.051561 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3969.014085 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2969.014085 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 2612 # number of overall hits -system.cpu.dcache.overall_miss_latency 563600 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1988000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.051561 # miss rate for overall accesses system.cpu.dcache.overall_misses 142 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 421600 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1846000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.051561 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 86.872921 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.809387 # Cycle average of tags in use system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 11002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3961.367491 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2961.367491 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13922.261484 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12922.261484 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 10719 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1121067 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3940000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.025723 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 838067 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3657000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.025723 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 11002 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3961.367491 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2961.367491 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13922.261484 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency system.cpu.icache.demand_hits 10719 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1121067 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3940000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.025723 # miss rate for demand accesses system.cpu.icache.demand_misses 283 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 838067 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3657000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.025723 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 11002 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3961.367491 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2961.367491 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13922.261484 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 10719 # number of overall hits -system.cpu.icache.overall_miss_latency 1121067 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3940000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.025723 # miss rate for overall accesses system.cpu.icache.overall_misses 283 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 838067 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3657000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.025723 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -140,18 +140,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 125.297191 # Cycle average of tags in use +system.cpu.icache.tagsinuse 163.879834 # Cycle average of tags in use system.cpu.icache.total_refs 10719 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 423 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2968.515366 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1967.515366 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1255682 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5499000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 423 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 832259 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4653000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -163,29 +163,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 423 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2968.515366 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1967.515366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1255682 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5499000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 832259 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 423 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2968.515366 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1967.515366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1255682 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5499000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 423 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 832259 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -202,12 +202,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 423 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 211.742547 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 266.922506 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1698003 # number of cpu cycles simulated +system.cpu.numCycles 19264000 # number of cpu cycles simulated system.cpu.num_insts 11001 # Number of instructions executed system.cpu.num_refs 2760 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr index fce46c90e..7873672f2 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr @@ -1,4 +1,3 @@ warn: More than two loadable segments in ELF object. warn: Ignoring segment @ 0x0 length 0x0. -0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index 100a1ebce..c2d31ed8f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 8 2007 05:25:15 -M5 started Sun Apr 8 22:54:12 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:07 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1698003 because target called exit() +Exiting @ tick 19264000 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index ce952d718..6e38281a1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -1,16 +1,12 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -25,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -55,21 +56,109 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -89,13 +178,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -103,7 +280,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -122,7 +299,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -144,27 +321,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -204,6 +421,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -213,7 +457,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -224,7 +468,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -239,7 +483,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -249,19 +493,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -306,7 +552,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -322,7 +568,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -338,7 +584,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -354,7 +600,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -370,7 +616,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -386,7 +632,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -402,7 +648,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -418,7 +664,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -434,7 +680,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -450,7 +696,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -466,7 +712,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -482,7 +728,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -498,7 +744,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -514,7 +760,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -530,7 +776,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -546,7 +792,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -562,7 +808,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -578,7 +824,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -594,7 +840,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -611,7 +857,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -619,13 +865,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -669,9 +917,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -682,7 +930,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -700,7 +948,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index 313620c59..324ede6b4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -14,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -30,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -46,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -58,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -81,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -99,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -124,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -132,6 +172,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -155,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -163,6 +287,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img @@ -176,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -191,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -206,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -221,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -236,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -251,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -259,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -291,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -311,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -326,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -334,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -349,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -364,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -379,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -394,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -409,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -424,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -439,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -454,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -472,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -513,12 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -527,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -546,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -561,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -569,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -584,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -635,18 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 4dbe8c13c..7765c2852 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,232 +1,632 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1026206 # Simulator instruction rate (inst/s) -host_mem_usage 240860 # Number of bytes of host memory used -host_seconds 63.27 # Real time elapsed on the host -host_tick_rate 58764450 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 64932819 # Number of instructions simulated -sim_seconds 1.859157 # Number of seconds simulated -sim_ticks 3718314928 # Number of ticks simulated -system.cpu0.dtb.accesses 544556 # DTB accesses -system.cpu0.dtb.acv 335 # DTB access violations -system.cpu0.dtb.hits 14841931 # DTB hits -system.cpu0.dtb.misses 7356 # DTB misses -system.cpu0.dtb.read_accesses 377530 # DTB read accesses -system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_hits 8970576 # DTB read hits -system.cpu0.dtb.read_misses 6581 # DTB read misses -system.cpu0.dtb.write_accesses 167026 # DTB write accesses -system.cpu0.dtb.write_acv 125 # DTB write access violations -system.cpu0.dtb.write_hits 5871355 # DTB write hits -system.cpu0.dtb.write_misses 775 # DTB write misses -system.cpu0.idle_fraction 0.984944 # Percentage of idle cycles -system.cpu0.itb.accesses 3586919 # ITB accesses -system.cpu0.itb.acv 184 # ITB acv -system.cpu0.itb.hits 3583450 # ITB hits -system.cpu0.itb.misses 3469 # ITB misses -system.cpu0.kern.callpal 182754 # number of callpals executed +host_inst_rate 607412 # Simulator instruction rate (inst/s) +host_mem_usage 245896 # Number of bytes of host memory used +host_seconds 103.93 # Real time elapsed on the host +host_tick_rate 17996726251 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63125943 # Number of instructions simulated +sim_seconds 1.870335 # Number of seconds simulated +sim_ticks 1870335097000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7464208 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.185481 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1699733 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5646723 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 286673 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.625609 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13110931 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.131573 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1986406 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15097337 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13110931 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.131573 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1986406 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1699733 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 122 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 21 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 14 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1359 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 725 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 282337 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks +system.cpu0.dcache.replacements 1978969 # number of replacements +system.cpu0.dcache.sampled_refs 1979481 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13115267 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 0 # number of writebacks +system.cpu0.dtb.accesses 698037 # DTB accesses +system.cpu0.dtb.acv 251 # DTB access violations +system.cpu0.dtb.hits 15082969 # DTB hits +system.cpu0.dtb.misses 7805 # DTB misses +system.cpu0.dtb.read_accesses 508987 # DTB read accesses +system.cpu0.dtb.read_acv 152 # DTB read access violations +system.cpu0.dtb.read_hits 9148390 # DTB read hits +system.cpu0.dtb.read_misses 7079 # DTB read misses +system.cpu0.dtb.write_accesses 189050 # DTB write accesses +system.cpu0.dtb.write_acv 99 # DTB write access violations +system.cpu0.dtb.write_hits 5934579 # DTB write hits +system.cpu0.dtb.write_misses 726 # DTB write misses +system.cpu0.icache.ReadReq_accesses 57190172 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56305300 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 884872 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 63.637052 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57190172 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_hits 56305300 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses +system.cpu0.icache.demand_misses 884872 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57190172 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56305300 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses +system.cpu0.icache.overall_misses 884872 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 884872 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 25821 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 78 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 6 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 884276 # number of replacements +system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use +system.cpu0.icache.total_refs 56305300 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles +system.cpu0.itb.accesses 3858835 # ITB accesses +system.cpu0.itb.acv 127 # ITB acv +system.cpu0.itb.hits 3855350 # ITB hits +system.cpu0.itb.misses 3485 # ITB misses +system.cpu0.kern.callpal 183272 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 115 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3791 2.07% 2.14% # number of callpals executed -system.cpu0.kern.callpal_tbi 49 0.03% 2.17% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.17% # number of callpals executed -system.cpu0.kern.callpal_swpipl 167832 91.83% 94.01% # number of callpals executed -system.cpu0.kern.callpal_rdps 5780 3.16% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168017 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_wrusp 2 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_rdusp 9 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal_rti 4696 2.57% 99.75% # number of callpals executed -system.cpu0.kern.callpal_callsys 344 0.19% 99.93% # number of callpals executed -system.cpu0.kern.callpal_imb 122 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 196249 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6184 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174678 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70736 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 245 0.14% 40.64% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1896 1.09% 41.72% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101793 58.27% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 140889 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69374 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 245 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1896 1.35% 50.76% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.hwrei 197101 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174850 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101695 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69366 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3718314513 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3683820285 99.07% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 40474 0.00% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 163056 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 2026 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 34288672 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.806564 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1870334889500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125118000 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17106668000 0.91% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.681442 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1192 -system.cpu0.kern.mode_good_user 1193 +system.cpu0.kern.ipl_used_31 0.684606 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1155 +system.cpu0.kern.mode_good_user 1156 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7143 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1193 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1156 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.286108 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.166877 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.162906 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3716671550 99.96% 99.96% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 1642961 0.04% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869377889500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3792 # number of times the context was actually changed -system.cpu0.kern.syscall 199 # number of syscalls executed -system.cpu0.kern.syscall_2 8 4.02% 4.02% # number of syscalls executed -system.cpu0.kern.syscall_3 17 8.54% 12.56% # number of syscalls executed -system.cpu0.kern.syscall_4 4 2.01% 14.57% # number of syscalls executed -system.cpu0.kern.syscall_6 29 14.57% 29.15% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.50% 29.65% # number of syscalls executed -system.cpu0.kern.syscall_17 4 2.01% 31.66% # number of syscalls executed -system.cpu0.kern.syscall_19 10 5.03% 36.68% # number of syscalls executed -system.cpu0.kern.syscall_20 6 3.02% 39.70% # number of syscalls executed -system.cpu0.kern.syscall_23 1 0.50% 40.20% # number of syscalls executed -system.cpu0.kern.syscall_24 3 1.51% 41.71% # number of syscalls executed -system.cpu0.kern.syscall_33 6 3.02% 44.72% # number of syscalls executed -system.cpu0.kern.syscall_41 2 1.01% 45.73% # number of syscalls executed -system.cpu0.kern.syscall_45 31 15.58% 61.31% # number of syscalls executed -system.cpu0.kern.syscall_47 3 1.51% 62.81% # number of syscalls executed -system.cpu0.kern.syscall_48 10 5.03% 67.84% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.52% 72.36% # number of syscalls executed -system.cpu0.kern.syscall_59 6 3.02% 75.38% # number of syscalls executed -system.cpu0.kern.syscall_71 20 10.05% 85.43% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.51% 86.93% # number of syscalls executed -system.cpu0.kern.syscall_74 5 2.51% 89.45% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.50% 89.95% # number of syscalls executed -system.cpu0.kern.syscall_90 3 1.51% 91.46% # number of syscalls executed -system.cpu0.kern.syscall_92 8 4.02% 95.48% # number of syscalls executed -system.cpu0.kern.syscall_97 2 1.01% 96.48% # number of syscalls executed -system.cpu0.kern.syscall_98 2 1.01% 97.49% # number of syscalls executed -system.cpu0.kern.syscall_132 1 0.50% 97.99% # number of syscalls executed -system.cpu0.kern.syscall_144 2 1.01% 98.99% # number of syscalls executed -system.cpu0.kern.syscall_147 2 1.01% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015056 # Percentage of non-idle cycles -system.cpu0.numCycles 55984201 # number of cpu cycles simulated -system.cpu0.num_insts 55980548 # Number of instructions executed -system.cpu0.num_refs 15081320 # Number of memory references -system.cpu1.dtb.accesses 761000 # DTB accesses -system.cpu1.dtb.acv 32 # DTB access violations -system.cpu1.dtb.hits 2658022 # DTB hits -system.cpu1.dtb.misses 4173 # DTB misses -system.cpu1.dtb.read_accesses 523552 # DTB read accesses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 1679180 # DTB read hits -system.cpu1.dtb.read_misses 3798 # DTB read misses -system.cpu1.dtb.write_accesses 237448 # DTB write accesses -system.cpu1.dtb.write_acv 32 # DTB write access violations -system.cpu1.dtb.write_hits 978842 # DTB write hits -system.cpu1.dtb.write_misses 375 # DTB write misses -system.cpu1.idle_fraction 0.997592 # Percentage of idle cycles -system.cpu1.itb.accesses 2420426 # ITB accesses -system.cpu1.itb.acv 0 # ITB acv -system.cpu1.itb.hits 2418839 # ITB hits -system.cpu1.itb.misses 1587 # ITB misses -system.cpu1.kern.callpal 34411 # number of callpals executed +system.cpu0.kern.swap_context 3762 # number of times the context was actually changed +system.cpu0.kern.syscall 226 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed +system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed +system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed +system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed +system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed +system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed +system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed +system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed +system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed +system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed +system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed +system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed +system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed +system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed +system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.numCycles 57193784 # number of cpu cycles simulated +system.cpu0.num_insts 57190172 # Number of instructions executed +system.cpu0.num_refs 15322419 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1167383 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 1124444 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.036782 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 42939 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 749650 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 723062 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.035467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26588 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1917033 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1847506 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.036268 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 69527 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1917033 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1847506 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.036268 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 69527 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 42939 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 61769 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 39 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1538 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2755 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 24475 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 641 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1472 # write misses to shared blocks +system.cpu1.dcache.replacements 62341 # number of replacements +system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851266669500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 0 # number of writebacks +system.cpu1.dtb.accesses 323622 # DTB accesses +system.cpu1.dtb.acv 116 # DTB access violations +system.cpu1.dtb.hits 1914885 # DTB hits +system.cpu1.dtb.misses 3692 # DTB misses +system.cpu1.dtb.read_accesses 220342 # DTB read accesses +system.cpu1.dtb.read_acv 58 # DTB read access violations +system.cpu1.dtb.read_hits 1163439 # DTB read hits +system.cpu1.dtb.read_misses 3277 # DTB read misses +system.cpu1.dtb.write_accesses 103280 # DTB write accesses +system.cpu1.dtb.write_acv 58 # DTB write access violations +system.cpu1.dtb.write_hits 751446 # DTB write hits +system.cpu1.dtb.write_misses 415 # DTB write misses +system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses +system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5832135 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses +system.cpu1.icache.overall_misses 103636 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 103636 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 17328 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 25 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 103097 # number of replacements +system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 427.126314 # Cycle average of tags in use +system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868932665500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.itb.accesses 1469938 # ITB accesses +system.cpu1.itb.acv 57 # ITB acv +system.cpu1.itb.hits 1468399 # ITB hits +system.cpu1.itb.misses 1539 # ITB misses +system.cpu1.kern.callpal 32131 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 468 1.36% 1.39% # number of callpals executed -system.cpu1.kern.callpal_tbi 5 0.01% 1.41% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.43% # number of callpals executed -system.cpu1.kern.callpal_swpipl 28036 81.47% 82.90% # number of callpals executed -system.cpu1.kern.callpal_rdps 3042 8.84% 91.74% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 91.74% # number of callpals executed -system.cpu1.kern.callpal_wrusp 5 0.01% 91.76% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 91.77% # number of callpals executed -system.cpu1.kern.callpal_rti 2586 7.52% 99.28% # number of callpals executed -system.cpu1.kern.callpal_callsys 187 0.54% 99.83% # number of callpals executed -system.cpu1.kern.callpal_imb 59 0.17% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed +system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed +system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed +system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed +system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed +system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 42215 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2214 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 32633 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 11168 34.22% 34.22% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1895 5.81% 40.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 115 0.35% 40.38% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 19455 59.62% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 24201 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 11153 46.08% 46.08% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1895 7.83% 53.92% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 115 0.48% 54.39% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 11038 45.61% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3717892668 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3695802544 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 162970 0.00% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 29122 0.00% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21898032 0.59% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.741611 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.998657 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1870124001500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859122583000 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.567361 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 602 -system.cpu1.kern.mode_good_user 563 -system.cpu1.kern.mode_good_idle 39 -system.cpu1.kern.mode_switch_kernel 1011 # number of protection mode switches -system.cpu1.kern.mode_switch_user 563 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2045 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.332689 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.595450 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 612 +system.cpu1.kern.mode_good_user 580 +system.cpu1.kern.mode_good_idle 32 +system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches +system.cpu1.kern.mode_switch_user 580 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.019071 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 4872726 0.13% 0.13% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1950903 0.05% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3710606044 99.82% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 469 # number of times the context was actually changed -system.cpu1.kern.syscall 130 # number of syscalls executed -system.cpu1.kern.syscall_3 13 10.00% 10.00% # number of syscalls executed -system.cpu1.kern.syscall_6 14 10.77% 20.77% # number of syscalls executed -system.cpu1.kern.syscall_15 1 0.77% 21.54% # number of syscalls executed -system.cpu1.kern.syscall_17 11 8.46% 30.00% # number of syscalls executed -system.cpu1.kern.syscall_23 3 2.31% 32.31% # number of syscalls executed -system.cpu1.kern.syscall_24 3 2.31% 34.62% # number of syscalls executed -system.cpu1.kern.syscall_33 5 3.85% 38.46% # number of syscalls executed -system.cpu1.kern.syscall_45 24 18.46% 56.92% # number of syscalls executed -system.cpu1.kern.syscall_47 3 2.31% 59.23% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.77% 60.00% # number of syscalls executed -system.cpu1.kern.syscall_58 1 0.77% 60.77% # number of syscalls executed -system.cpu1.kern.syscall_59 1 0.77% 61.54% # number of syscalls executed -system.cpu1.kern.syscall_71 34 26.15% 87.69% # number of syscalls executed -system.cpu1.kern.syscall_74 11 8.46% 96.15% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.54% 97.69% # number of syscalls executed -system.cpu1.kern.syscall_132 3 2.31% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.002408 # Percentage of non-idle cycles -system.cpu1.numCycles 8953858 # number of cpu cycles simulated -system.cpu1.num_insts 8952271 # Number of instructions executed -system.cpu1.num_refs 2670182 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 1373909500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002152500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 471 # number of times the context was actually changed +system.cpu1.kern.syscall 100 # number of syscalls executed +system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed +system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed +system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed +system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed +system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed +system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed +system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed +system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed +system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed +system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed +system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed +system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed +system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed +system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed +system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed +system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed +system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles +system.cpu1.numCycles 5937367 # number of cpu cycles simulated +system.cpu1.num_insts 5935771 # Number of instructions executed +system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306245 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 181107 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.408621 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1782852 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.345539 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941303 # number of ReadReq misses +system.l2c.Writeback_accesses 427632 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427632 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.242866 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2724155 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 1782852 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.345539 # miss rate for demand accesses +system.l2c.demand_misses 941303 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3151787 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 2210484 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.298657 # miss rate for overall accesses +system.l2c.overall_misses 941303 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 1000779 # number of replacements +system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.575355 # Cycle average of tags in use +system.l2c.total_refs 2391252 # Total number of references to valid blocks. +system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 9a6301977..563ca3160 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,8 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 195723: Trying to launch CPU number 1! +warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 1cecd3a25..6afe2cfa0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:06:16 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Exiting @ tick 3718314928 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:06:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1870335097000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 8cb8b6cbd..791200f9a 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -1,16 +1,12 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -25,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -55,13 +56,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -69,7 +158,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -88,7 +177,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -110,27 +199,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -170,6 +299,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -179,7 +335,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -190,7 +346,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -205,7 +361,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -215,19 +371,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -272,7 +430,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -288,7 +446,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -304,7 +462,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -320,7 +478,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -336,7 +494,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -352,7 +510,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -368,7 +526,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -384,7 +542,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -400,7 +558,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -416,7 +574,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -432,7 +590,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -448,7 +606,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -464,7 +622,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -480,7 +638,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -496,7 +654,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -512,7 +670,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -528,7 +686,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -544,7 +702,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -560,7 +718,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -577,7 +735,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -585,13 +743,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -635,9 +795,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -648,7 +808,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -666,7 +826,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index ab56c5d90..94cc53f32 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -14,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -30,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -46,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -58,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -81,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -99,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage @@ -114,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -129,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -144,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -159,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -174,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -189,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -197,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -244,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -260,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -280,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -295,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -303,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -318,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -333,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -348,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -363,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -378,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -393,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -408,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -423,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -441,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -482,12 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -496,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -515,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -530,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -538,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -553,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -604,18 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index a10779a99..aaa6c0c86 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,137 +1,366 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1452138 # Simulator instruction rate (inst/s) -host_mem_usage 239532 # Number of bytes of host memory used -host_seconds 42.57 # Real time elapsed on the host -host_tick_rate 85380734 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61811715 # Number of instructions simulated -sim_seconds 1.817169 # Number of seconds simulated -sim_ticks 3634338452 # Number of ticks simulated -system.cpu.dtb.accesses 1304494 # DTB accesses +host_inst_rate 577751 # Simulator instruction rate (inst/s) +host_mem_usage 244724 # Number of bytes of host memory used +host_seconds 103.86 # Real time elapsed on the host +host_tick_rate 17603359253 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60007317 # Number of instructions simulated +sim_seconds 1.828355 # Number of seconds simulated +sim_ticks 1828355481500 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7984499 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1738834 # number of ReadReq misses +system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.866570 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_hits 14029592 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2043188 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14029592 # number of overall hits +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2043188 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1738834 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2042663 # number of replacements +system.cpu.dcache.sampled_refs 2043175 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029604 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16556949 # DTB hits -system.cpu.dtb.misses 11425 # DTB misses -system.cpu.dtb.read_accesses 900425 # DTB read accesses +system.cpu.dtb.hits 16053818 # DTB hits +system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 10041919 # DTB read hits -system.cpu.dtb.read_misses 10280 # DTB read misses -system.cpu.dtb.write_accesses 404069 # DTB write accesses +system.cpu.dtb.read_hits 9703850 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6515030 # DTB write hits -system.cpu.dtb.write_misses 1145 # DTB write misses -system.cpu.idle_fraction 0.982991 # Percentage of idle cycles -system.cpu.itb.accesses 5655354 # ITB accesses +system.cpu.dtb.write_hits 6349968 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses +system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59087263 # number of overall hits +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses +system.cpu.icache.overall_misses 920054 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 919427 # number of replacements +system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use +system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0.983588 # Percentage of idle cycles +system.cpu.itb.accesses 4979217 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 5650364 # ITB hits -system.cpu.itb.misses 4990 # ITB misses -system.cpu.kern.callpal 193847 # number of callpals executed +system.cpu.itb.hits 4974211 # ITB hits +system.cpu.itb.misses 5006 # ITB misses +system.cpu.kern.callpal 192139 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4203 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 176756 91.18% 93.38% # number of callpals executed -system.cpu.kern.callpal_rdps 6881 3.55% 96.93% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.94% # number of callpals executed -system.cpu.kern.callpal_rti 5211 2.69% 99.63% # number of callpals executed -system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed +system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed +system.cpu.kern.callpal_rti 5202 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212913 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6275 # number of quiesce instructions executed -system.cpu.kern.ipl_count 184066 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75351 40.94% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 245 0.13% 41.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1853 1.01% 42.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106617 57.92% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 150066 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73984 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 245 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1853 1.23% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73984 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3634338037 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3599646965 99.05% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 40474 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 159358 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 34491240 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.815284 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981858 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed +system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1828355274000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087543000 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.693923 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1937 -system.cpu.kern.mode_good_user 1757 -system.cpu.kern.mode_good_idle 180 -system.cpu.kern.mode_switch_kernel 5978 # number of protection mode switches -system.cpu.kern.mode_switch_user 1757 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2102 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.393819 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.324021 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1908 +system.cpu.kern.mode_good_user 1737 +system.cpu.kern.mode_good_idle 171 +system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches +system.cpu.kern.mode_switch_user 1737 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.085633 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 54841721 1.51% 1.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3591234 0.10% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3575905080 98.39% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4204 # number of times the context was actually changed -system.cpu.kern.syscall 329 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.43% 2.43% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.12% 11.55% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.22% 12.77% # number of syscalls executed -system.cpu.kern.syscall_6 43 13.07% 25.84% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.30% 26.14% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.30% 26.44% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.56% 31.00% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.04% 34.04% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.82% 35.87% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.22% 37.08% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.82% 38.91% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.34% 42.25% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.86% # number of syscalls executed -system.cpu.kern.syscall_45 55 16.72% 59.57% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.82% 61.40% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.04% 64.44% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.04% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.30% 67.78% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.13% 69.91% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.41% 86.32% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.91% 87.23% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.86% 92.10% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.30% 92.40% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.91% 93.31% # number of syscalls executed -system.cpu.kern.syscall_92 10 3.04% 96.35% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.96% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.57% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056177500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.017009 # Percentage of non-idle cycles -system.cpu.numCycles 61816889 # number of cpu cycles simulated -system.cpu.num_insts 61811715 # Number of instructions executed -system.cpu.num_refs 16805478 # Number of memory references +system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles +system.cpu.numCycles 60012507 # number of cpu cycles simulated +system.cpu.num_insts 60007317 # Number of instructions executed +system.cpu.num_refs 16302129 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658871 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1717827 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941044 # number of ReadReq misses +system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.205900 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2658871 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 1717827 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses +system.l2c.demand_misses 941044 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3087756 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 2146712 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses +system.l2c.overall_misses 941044 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992432 # number of replacements +system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use +system.l2c.total_refs 2333445 # Total number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 69304a604..072cb6c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,6 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index 631453025..e47b6f226 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:05:33 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Exiting @ tick 3634338452 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:06:07 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1828355481500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 856856ae8..7bcdbdb71 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -1,16 +1,12 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -25,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -53,21 +54,109 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -85,13 +174,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -99,7 +276,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -118,7 +295,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -140,27 +317,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -200,6 +417,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -209,7 +453,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -220,7 +464,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -235,7 +479,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -245,19 +489,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -302,7 +548,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -318,7 +564,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -334,7 +580,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -350,7 +596,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -366,7 +612,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -382,7 +628,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -398,7 +644,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -414,7 +660,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -430,7 +676,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -446,7 +692,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -462,7 +708,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -478,7 +724,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -494,7 +740,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -510,7 +756,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -526,7 +772,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -542,7 +788,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -558,7 +804,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -574,7 +820,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -590,7 +836,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -607,7 +853,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -615,13 +861,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -665,9 +913,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -678,7 +926,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -696,7 +944,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index a4dd003e4..68698cf83 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -14,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing kernel=/dist/m5/system/binaries/vmlinux @@ -30,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -46,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -58,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -81,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -99,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -124,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -132,6 +172,90 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -155,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -163,6 +287,90 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img @@ -176,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -191,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -206,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -221,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -236,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -251,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -259,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -291,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -311,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -326,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -334,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -349,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -364,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -379,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -394,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -409,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -424,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -439,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -454,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -472,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -513,12 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -527,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -546,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -561,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -569,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -584,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -635,18 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index d6bc028f1..83bb77f93 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,196 +1,578 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 359240 # Simulator instruction rate (inst/s) -host_mem_usage 240844 # Number of bytes of host memory used -host_seconds 186.42 # Real time elapsed on the host -host_tick_rate 21297758 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 66968427 # Number of instructions simulated -sim_seconds 1.985132 # Number of seconds simulated -sim_ticks 3970264174 # Number of ticks simulated -system.cpu0.dtb.accesses 1003481 # DTB accesses +host_inst_rate 213082 # Simulator instruction rate (inst/s) +host_mem_usage 203724 # Number of bytes of host memory used +host_seconds 296.83 # Real time elapsed on the host +host_tick_rate 6573231278 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63248814 # Number of instructions simulated +sim_seconds 1.951129 # Number of seconds simulated +sim_ticks 1951129131000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9299202 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 13073.177688 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12073.152824 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7589849 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 22346675500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.183817 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1709353 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 20637280000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.183817 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1709353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable 6873 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu0.dcache.ReadResp_mshr_uncacheable_latency 841915000 # number of ReadResp MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_accesses 6016348 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 12644.438594 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 11630.972878 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 5727689 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 3649931000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.047979 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 288659 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 3357385000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.047979 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 288659 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable 9698 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu0.dcache.WriteResp_mshr_uncacheable_latency 1186164500 # number of WriteResp MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.687909 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15315550 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13317538 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 25996606500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.130456 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1998012 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 23994665000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.130456 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1998012 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15315550 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13317538 # number of overall hits +system.cpu0.dcache.overall_miss_latency 25996606500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.130456 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1998012 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 23994665000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.130456 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1998012 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 16571 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1709421 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 908 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 3762 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 72 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2297 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 235 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 207 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 15 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 7 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1074 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 726 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 284810 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2533 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1354 # write misses to shared blocks +system.cpu0.dcache.replacements 1991354 # number of replacements +system.cpu0.dcache.sampled_refs 1991866 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 503.775443 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13321418 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 57953000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 401606 # number of writebacks +system.cpu0.dtb.accesses 719860 # DTB accesses system.cpu0.dtb.acv 289 # DTB access violations -system.cpu0.dtb.hits 13332650 # DTB hits -system.cpu0.dtb.misses 8437 # DTB misses -system.cpu0.dtb.read_accesses 695694 # DTB read accesses +system.cpu0.dtb.hits 15299767 # DTB hits +system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.read_accesses 524201 # DTB read accesses system.cpu0.dtb.read_acv 174 # DTB read access violations -system.cpu0.dtb.read_hits 8285777 # DTB read hits -system.cpu0.dtb.read_misses 7640 # DTB read misses -system.cpu0.dtb.write_accesses 307787 # DTB write accesses +system.cpu0.dtb.read_hits 9282693 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses +system.cpu0.dtb.write_accesses 195659 # DTB write accesses system.cpu0.dtb.write_acv 115 # DTB write access violations -system.cpu0.dtb.write_hits 5046873 # DTB write hits -system.cpu0.dtb.write_misses 797 # DTB write misses -system.cpu0.idle_fraction 0.928155 # Percentage of idle cycles -system.cpu0.itb.accesses 4220935 # ITB accesses +system.cpu0.dtb.write_hits 6017074 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses +system.cpu0.icache.ReadReq_accesses 57872551 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 12029.752588 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11029.000057 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 56957639 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 11006165000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.015809 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 914912 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10090564500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.015809 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 914912 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 62.632934 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57872551 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.demand_hits 56957639 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 11006165000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015809 # miss rate for demand accesses +system.cpu0.icache.demand_misses 914912 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 10090564500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.015809 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 914912 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57872551 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56957639 # number of overall hits +system.cpu0.icache.overall_miss_latency 11006165000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015809 # miss rate for overall accesses +system.cpu0.icache.overall_misses 914912 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 10090564500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.015809 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 914912 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 915158 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 4652 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 8768 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 121 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 908876 # number of replacements +system.cpu0.icache.sampled_refs 909388 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 508.806183 # Cycle average of tags in use +system.cpu0.icache.total_refs 56957639 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 34906249000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.943968 # Percentage of idle cycles +system.cpu0.itb.accesses 3944641 # ITB accesses system.cpu0.itb.acv 143 # ITB acv -system.cpu0.itb.hits 4217111 # ITB hits -system.cpu0.itb.misses 3824 # ITB misses -system.cpu0.kern.callpal 144637 # number of callpals executed +system.cpu0.itb.hits 3940800 # ITB hits +system.cpu0.itb.misses 3841 # ITB misses +system.cpu0.kern.callpal 187118 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 571 0.39% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2907 2.01% 2.41% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.44% # number of callpals executed -system.cpu0.kern.callpal_swpipl 129633 89.63% 92.07% # number of callpals executed -system.cpu0.kern.callpal_rdps 6650 4.60% 96.67% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 96.67% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_rti 4286 2.96% 99.64% # number of callpals executed -system.cpu0.kern.callpal_callsys 372 0.26% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 149 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 96 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3865 2.07% 2.12% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.15% # number of callpals executed +system.cpu0.kern.callpal_swpipl 171254 91.52% 93.67% # number of callpals executed +system.cpu0.kern.callpal_rdps 6635 3.55% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rti 4694 2.51% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 159963 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6648 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 136551 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 54497 39.91% 39.91% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 143 0.10% 40.01% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 2005 1.47% 41.48% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 483 0.35% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 79423 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 110306 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 54079 49.03% 49.03% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 143 0.13% 49.16% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 2005 1.82% 50.97% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 483 0.44% 51.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 53596 48.59% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3970262390 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3836377682 96.63% 96.63% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 133000 0.00% 96.63% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1870128 0.05% 96.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1206048 0.03% 96.71% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 130675532 3.29% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.807801 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.992330 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 201983 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6162 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178054 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72322 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1968 1.11% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 103627 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144005 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 70953 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1968 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 70947 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1951128432000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1894864204500 97.12% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 72482500 0.00% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 564462000 0.03% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 4114000 0.00% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 55623169000 2.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981071 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.674817 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1253 -system.cpu0.kern.mode_good_user 1254 +system.cpu0.kern.ipl_used_31 0.684638 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1230 +system.cpu0.kern.mode_good_user 1231 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6799 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1254 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7215 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1231 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.311313 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.184292 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170478 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3956507378 99.65% 99.65% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 13755004 0.35% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1947973402000 99.84% 99.84% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3155028000 0.16% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2908 # number of times the context was actually changed -system.cpu0.kern.syscall 227 # number of syscalls executed -system.cpu0.kern.syscall_2 6 2.64% 2.64% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.37% 11.01% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.32% 12.33% # number of syscalls executed -system.cpu0.kern.syscall_6 31 13.66% 25.99% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.44% 26.43% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.44% 26.87% # number of syscalls executed -system.cpu0.kern.syscall_17 10 4.41% 31.28% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.64% 33.92% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.76% 35.68% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.88% 36.56% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.76% 38.33% # number of syscalls executed -system.cpu0.kern.syscall_33 8 3.52% 41.85% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.88% 42.73% # number of syscalls executed -system.cpu0.kern.syscall_45 40 17.62% 60.35% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.76% 62.11% # number of syscalls executed -system.cpu0.kern.syscall_48 7 3.08% 65.20% # number of syscalls executed -system.cpu0.kern.syscall_54 9 3.96% 69.16% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.44% 69.60% # number of syscalls executed -system.cpu0.kern.syscall_59 5 2.20% 71.81% # number of syscalls executed -system.cpu0.kern.syscall_71 32 14.10% 85.90% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.32% 87.22% # number of syscalls executed -system.cpu0.kern.syscall_74 9 3.96% 91.19% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.44% 91.63% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.88% 92.51% # number of syscalls executed -system.cpu0.kern.syscall_92 8 3.52% 96.04% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.88% 96.92% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.88% 97.80% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.88% 98.68% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.44% 99.12% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.071845 # Percentage of non-idle cycles -system.cpu0.numCycles 3970264174 # number of cpu cycles simulated -system.cpu0.num_insts 52311968 # Number of instructions executed -system.cpu0.num_refs 13564877 # Number of memory references -system.cpu1.dtb.accesses 302962 # DTB accesses +system.cpu0.kern.swap_context 3866 # number of times the context was actually changed +system.cpu0.kern.syscall 224 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed +system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed +system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed +system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed +system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed +system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed +system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed +system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed +system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed +system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed +system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed +system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed +system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed +system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed +system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.056032 # Percentage of non-idle cycles +system.cpu0.numCycles 1951129131000 # number of cpu cycles simulated +system.cpu0.num_insts 57872550 # Number of instructions executed +system.cpu0.num_refs 15541096 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1052558 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 11119.734481 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10119.576119 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 1014670 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 421304500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035996 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 37888 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 383410500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035996 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 37888 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable 120 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu1.dcache.ReadResp_mshr_uncacheable_latency 14641500 # number of ReadResp MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_accesses 677186 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 11920.138166 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 10843.231096 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 653157 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 286429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.035484 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 24029 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 260552000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.035484 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 24029 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable 2496 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu1.dcache.WriteResp_mshr_uncacheable_latency 304596500 # number of WriteResp MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.876823 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1729744 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1667827 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 707733500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.035795 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 61917 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 643962500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.035795 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 61917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1729744 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1667827 # number of overall hits +system.cpu1.dcache.overall_miss_latency 707733500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.035795 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 61917 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 643962500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.035795 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 61917 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 2616 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 37951 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 906 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 1965 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 254 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 65869 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 191 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 198 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 48 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 42 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1132 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2716 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 22206 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 601 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1247 # write misses to shared blocks +system.cpu1.dcache.replacements 55360 # number of replacements +system.cpu1.dcache.sampled_refs 55749 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 388.749341 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1665603 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1935095598000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 27663 # number of writebacks +system.cpu1.dtb.accesses 302878 # DTB accesses system.cpu1.dtb.acv 84 # DTB access violations -system.cpu1.dtb.hits 4640482 # DTB hits -system.cpu1.dtb.misses 3107 # DTB misses -system.cpu1.dtb.read_accesses 205912 # DTB read accesses +system.cpu1.dtb.hits 1728432 # DTB hits +system.cpu1.dtb.misses 3106 # DTB misses +system.cpu1.dtb.read_accesses 205838 # DTB read accesses system.cpu1.dtb.read_acv 36 # DTB read access violations -system.cpu1.dtb.read_hits 2668410 # DTB read hits -system.cpu1.dtb.read_misses 2747 # DTB read misses -system.cpu1.dtb.write_accesses 97050 # DTB write accesses +system.cpu1.dtb.read_hits 1049360 # DTB read hits +system.cpu1.dtb.read_misses 2750 # DTB read misses +system.cpu1.dtb.write_accesses 97040 # DTB write accesses system.cpu1.dtb.write_acv 48 # DTB write access violations -system.cpu1.dtb.write_hits 1972072 # DTB write hits -system.cpu1.dtb.write_misses 360 # DTB write misses -system.cpu1.idle_fraction 0.974914 # Percentage of idle cycles -system.cpu1.itb.accesses 1965758 # ITB accesses +system.cpu1.dtb.write_hits 679072 # DTB write hits +system.cpu1.dtb.write_misses 356 # DTB write misses +system.cpu1.icache.ReadReq_accesses 5376264 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 12045.939531 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11045.466957 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5281041 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1147050500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.017712 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 95223 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1051782500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.017712 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 95223 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 57.662729 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5376264 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5281041 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1147050500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017712 # miss rate for demand accesses +system.cpu1.icache.demand_misses 95223 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 1051782500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.017712 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 95223 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5376264 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5281041 # number of overall hits +system.cpu1.icache.overall_miss_latency 1147050500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017712 # miss rate for overall accesses +system.cpu1.icache.overall_misses 95223 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 1051782500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.017712 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 95223 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 97341 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 39627 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 214588 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 26 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 91073 # number of replacements +system.cpu1.icache.sampled_refs 91585 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 420.500398 # Cycle average of tags in use +system.cpu1.icache.total_refs 5281041 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1947911714000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.995322 # Percentage of idle cycles +system.cpu1.itb.accesses 1399877 # ITB accesses system.cpu1.itb.acv 41 # ITB acv -system.cpu1.itb.hits 1964511 # ITB hits -system.cpu1.itb.misses 1247 # ITB misses -system.cpu1.kern.callpal 80671 # number of callpals executed +system.cpu1.itb.hits 1398631 # ITB hits +system.cpu1.itb.misses 1246 # ITB misses +system.cpu1.kern.callpal 29847 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 483 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2277 2.82% 3.43% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 3.45% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71267 88.34% 91.79% # number of callpals executed -system.cpu1.kern.callpal_rdps 2378 2.95% 94.74% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 94.74% # number of callpals executed -system.cpu1.kern.callpal_wrusp 3 0.00% 94.74% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.00% 94.74% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 94.75% # number of callpals executed -system.cpu1.kern.callpal_rti 4044 5.01% 99.76% # number of callpals executed -system.cpu1.kern.callpal_callsys 161 0.20% 99.96% # number of callpals executed -system.cpu1.kern.callpal_imb 31 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_swpctx 375 1.26% 1.29% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.03% 1.32% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24461 81.95% 83.30% # number of callpals executed +system.cpu1.kern.callpal_rdps 2201 7.37% 90.67% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 90.68% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 90.70% # number of callpals executed +system.cpu1.kern.callpal_rti 2582 8.65% 99.35% # number of callpals executed +system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 87720 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2808 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 77880 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30262 38.86% 38.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1997 2.56% 41.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 571 0.73% 42.15% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45050 57.85% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 60603 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29303 48.35% 48.35% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1997 3.30% 51.65% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 571 0.94% 52.59% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 28732 47.41% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3968772136 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3846937158 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1867822 0.05% 96.98% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 1457952 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118509204 2.99% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.778159 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.968310 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 36385 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2332 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 29103 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9344 32.11% 32.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1963 6.75% 38.85% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 96 0.33% 39.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 17700 60.82% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20635 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9336 45.24% 45.24% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1963 9.51% 54.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 96 0.47% 55.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9240 44.78% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1950372731000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1911409272000 98.00% 98.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 494740000 0.03% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 52316000 0.00% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 38416403000 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999144 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.637780 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1014 -system.cpu1.kern.mode_good_user 519 -system.cpu1.kern.mode_good_idle 495 -system.cpu1.kern.mode_switch_kernel 2345 # number of protection mode switches -system.cpu1.kern.mode_switch_user 519 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 3028 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.344196 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.432409 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.522034 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 538 +system.cpu1.kern.mode_good_user 517 +system.cpu1.kern.mode_good_idle 21 +system.cpu1.kern.mode_switch_kernel 884 # number of protection mode switches +system.cpu1.kern.mode_switch_user 517 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2075 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.618718 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.608597 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.163474 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 63257834 1.59% 1.59% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 5106070 0.13% 1.72% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3899443084 98.28% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2278 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good_idle 0.010120 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 3563216000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1513259000 0.08% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1945257297000 99.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 376 # number of times the context was actually changed system.cpu1.kern.syscall 102 # number of syscalls executed system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed @@ -213,28 +595,113 @@ system.cpu1.kern.syscall_90 1 0.98% 95.10% # nu system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.025086 # Percentage of non-idle cycles -system.cpu1.numCycles 3968772376 # number of cpu cycles simulated -system.cpu1.num_insts 14656459 # Number of instructions executed -system.cpu1.num_refs 4670067 # Number of memory references +system.cpu1.not_idle_fraction 0.004678 # Percentage of non-idle cycles +system.cpu1.numCycles 1950372761000 # number of cpu cycles simulated +system.cpu1.num_insts 5376264 # Number of instructions executed +system.cpu1.num_refs 1738417 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306499 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 12998.029396 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 10997.988681 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 183694 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1596223000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.400670 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 122805 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1350608000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.400670 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 122805 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2751323 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 12999.901707 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 10999.990968 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1810263 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12233687500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.342039 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941060 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 10351530500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.342035 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 941049 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6993 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 779629500 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 12194 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1356619000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429269 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429256 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.000030 # miss rate for Writeback accesses +system.l2c.Writeback_misses 13 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.000030 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 13 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.277768 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2751323 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 12999.901707 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.demand_hits 1810263 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12233687500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.342039 # miss rate for demand accesses +system.l2c.demand_misses 941060 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10351530500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.342035 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 941049 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3180592 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 12999.722126 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2239519 # number of overall hits +system.l2c.overall_miss_latency 12233687500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.295880 # miss rate for overall accesses +system.l2c.overall_misses 941073 # number of overall misses +system.l2c.overall_mshr_hits 11 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10351530500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.295872 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 941049 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 19187 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 998318 # number of replacements +system.l2c.sampled_refs 1063854 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65469.787238 # Cycle average of tags in use +system.l2c.total_refs 2423213 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3064127000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 79556 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 5b02d9b91..dc84ff88b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,8 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for system connection on port 3457 +0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7002 warn: Entering event queue @ 0. Starting simulation... -warn: 1082476: Trying to launch CPU number 1! +warn: 423901000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 9c25032e4..a3bd937f6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:09:33 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Exiting @ tick 3970264174 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:07:53 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1951129131000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 6f48977b0..ded525737 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -1,16 +1,12 @@ [root] type=Root children=system -checkpoint= -clock=2000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -25,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -53,13 +54,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -67,7 +156,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -86,7 +175,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -108,27 +197,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -168,6 +297,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -177,7 +333,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -188,7 +344,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -203,7 +359,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -213,19 +369,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -270,7 +428,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -286,7 +444,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -302,7 +460,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -318,7 +476,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -334,7 +492,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -350,7 +508,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -366,7 +524,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -382,7 +540,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -398,7 +556,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -414,7 +572,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -430,7 +588,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -446,7 +604,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -462,7 +620,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -478,7 +636,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -494,7 +652,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -510,7 +668,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -526,7 +684,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -542,7 +700,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -558,7 +716,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -575,7 +733,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -583,13 +741,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -633,9 +793,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -646,7 +806,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -664,7 +824,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index a99b59ae7..b51eb234e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=2000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -14,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing kernel=/dist/m5/system/binaries/vmlinux @@ -30,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -46,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -58,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -81,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -99,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage @@ -114,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -129,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -144,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -159,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -174,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -189,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -197,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -244,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -260,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -280,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -295,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -303,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -318,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -333,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -348,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -363,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -378,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -393,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -408,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -423,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -441,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -482,12 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -496,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -515,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -530,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -538,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -553,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -604,18 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 75746eadf..d9f42b16b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,137 +1,408 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 469266 # Simulator instruction rate (inst/s) -host_mem_usage 238376 # Number of bytes of host memory used -host_seconds 131.89 # Real time elapsed on the host -host_tick_rate 29380471 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 61893104 # Number of instructions simulated -sim_seconds 1.937550 # Number of seconds simulated -sim_ticks 3875100962 # Number of ticks simulated -system.cpu.dtb.accesses 1304554 # DTB accesses +host_inst_rate 212380 # Simulator instruction rate (inst/s) +host_mem_usage 201984 # Number of bytes of host memory used +host_seconds 282.69 # Real time elapsed on the host +host_tick_rate 6746442466 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60037406 # Number of instructions simulated +sim_seconds 1.907146 # Number of seconds simulated +sim_ticks 1907146437000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9726331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13065.219101 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12065.192690 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7984648 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 22755470000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.179069 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1741683 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 21013741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.179069 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1741683 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu.dcache.ReadResp_mshr_uncacheable_latency 824099000 # number of ReadResp MSHR uncacheable cycles +system.cpu.dcache.WriteReq_accesses 6350552 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 12768.106941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11768.067509 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6046235 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3885552000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.047920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304317 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3581223000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.047920 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 304317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu.dcache.WriteResp_mshr_uncacheable_latency 1154484000 # number of WriteResp MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.857760 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16076883 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.demand_hits 14030883 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26641022000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127263 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2046000 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 24594964000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.127263 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2046000 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16076883 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14030883 # number of overall hits +system.cpu.dcache.overall_miss_latency 26641022000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127263 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2046000 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 24594964000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.127263 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2046000 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1741683 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 9 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 4 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 92 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304305 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2045476 # number of replacements +system.cpu.dcache.sampled_refs 2045988 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.987904 # Cycle average of tags in use +system.cpu.dcache.total_refs 14030895 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 57945000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 429989 # number of writebacks +system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16571487 # DTB hits -system.cpu.dtb.misses 11447 # DTB misses -system.cpu.dtb.read_accesses 900486 # DTB read accesses +system.cpu.dtb.hits 16057425 # DTB hits +system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 10051940 # DTB read hits -system.cpu.dtb.read_misses 10303 # DTB read misses -system.cpu.dtb.write_accesses 404068 # DTB write accesses +system.cpu.dtb.read_hits 9706740 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6519547 # DTB write hits -system.cpu.dtb.write_misses 1144 # DTB write misses -system.cpu.idle_fraction 0.918919 # Percentage of idle cycles -system.cpu.itb.accesses 5664253 # ITB accesses +system.cpu.dtb.write_hits 6350685 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 60037407 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12029.456206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11028.713640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 59110217 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11153591500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.015444 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 927190 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10225713000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.015444 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 927190 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 63.763003 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60037407 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.demand_hits 59110217 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11153591500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015444 # miss rate for demand accesses +system.cpu.icache.demand_misses 927190 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10225713000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.015444 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 927190 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60037407 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59110217 # number of overall hits +system.cpu.icache.overall_miss_latency 11153591500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015444 # miss rate for overall accesses +system.cpu.icache.overall_misses 927190 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10225713000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.015444 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 927190 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 927190 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 644 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1040 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 146 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 2 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 926519 # number of replacements +system.cpu.icache.sampled_refs 927030 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 508.761542 # Cycle average of tags in use +system.cpu.icache.total_refs 59110217 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 34634685000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0.940784 # Percentage of idle cycles +system.cpu.itb.accesses 4977586 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 5659250 # ITB hits -system.cpu.itb.misses 5003 # ITB misses -system.cpu.kern.callpal 195265 # number of callpals executed +system.cpu.itb.hits 4972580 # ITB hits +system.cpu.itb.misses 5006 # ITB misses +system.cpu.kern.callpal 192752 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4161 2.13% 2.13% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.16% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.16% # number of callpals executed -system.cpu.kern.callpal_swpipl 178117 91.22% 93.38% # number of callpals executed -system.cpu.kern.callpal_rdps 6978 3.57% 96.96% # number of callpals executed +system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 175824 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal_rdps 6824 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal_rti 5213 2.67% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 531 0.27% 99.91% # number of callpals executed +system.cpu.kern.callpal_rti 5148 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 214368 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6180 # number of quiesce instructions executed -system.cpu.kern.ipl_count 185431 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75630 40.79% 40.79% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 143 0.08% 40.86% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1957 1.06% 41.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 107701 58.08% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 150626 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 74263 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 143 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1957 1.30% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 74263 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3875099178 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3747191842 96.70% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 122728 0.00% 96.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 915876 0.02% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126868732 3.27% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.812302 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981925 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211836 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183027 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74862 40.90% 40.90% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1923 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106111 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149044 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73495 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1923 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73495 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1907145727000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1851261210000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 73754500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 531976500 0.03% 97.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 55278786000 2.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981740 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.689529 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1926 -system.cpu.kern.mode_good_user 1765 -system.cpu.kern.mode_good_idle 161 -system.cpu.kern.mode_switch_kernel 5968 # number of protection mode switches -system.cpu.kern.mode_switch_user 1765 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2072 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.392861 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322721 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.692624 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1910 +system.cpu.kern.mode_good_user 1740 +system.cpu.kern.mode_good_idle 170 +system.cpu.kern.mode_switch_kernel 5894 # number of protection mode switches +system.cpu.kern.mode_switch_user 1740 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.405165 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.324058 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.077703 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 118484404 3.06% 3.06% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 18744972 0.48% 3.54% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3737869794 96.46% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4162 # number of times the context was actually changed -system.cpu.kern.syscall 329 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.43% 2.43% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.12% 11.55% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.22% 12.77% # number of syscalls executed -system.cpu.kern.syscall_6 43 13.07% 25.84% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.30% 26.14% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.30% 26.44% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.56% 31.00% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.04% 34.04% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.82% 35.87% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.22% 37.08% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.82% 38.91% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.34% 42.25% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.86% # number of syscalls executed -system.cpu.kern.syscall_45 55 16.72% 59.57% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.82% 61.40% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.04% 64.44% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.04% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.30% 67.78% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.13% 69.91% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.41% 86.32% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.91% 87.23% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.86% 92.10% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.30% 92.40% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.91% 93.31% # number of syscalls executed -system.cpu.kern.syscall_92 10 3.04% 96.35% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.96% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.57% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.mode_switch_good_idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 42657550000 2.24% 2.24% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4648649000 0.24% 2.48% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1859839526000 97.52% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.syscall 326 # number of syscalls executed +system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed +system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed +system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed +system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed +system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed +system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed +system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed +system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed +system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed +system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed +system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed +system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed +system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed +system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed +system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed +system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed +system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed +system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed +system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed +system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed +system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed +system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed +system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed +system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed +system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed +system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed +system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed +system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.081081 # Percentage of non-idle cycles -system.cpu.numCycles 3875100962 # number of cpu cycles simulated -system.cpu.num_insts 61893104 # Number of instructions executed -system.cpu.num_refs 16819569 # Number of memory references +system.cpu.not_idle_fraction 0.059216 # Percentage of non-idle cycles +system.cpu.numCycles 1907146437000 # number of cpu cycles simulated +system.cpu.num_insts 60037406 # Number of instructions executed +system.cpu.num_refs 16305563 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2702336 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 302 # Number of full page size DMA writes. -system.disk0.dma_write_txs 408 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304305 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 13000.153945 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 11000.153945 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 187380 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1520043000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.384236 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116925 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1286193000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.384236 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 116925 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2668854 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 13000.065889 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 11000.065889 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1727874 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12232802000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.352578 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 940980 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 10350842000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.352578 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 940980 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 750102000 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1050666000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429989 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429989 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.216875 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2668854 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.demand_hits 1727874 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12232802000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.352578 # miss rate for demand accesses +system.l2c.demand_misses 940980 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10350842000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.352578 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 940980 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3098843 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2157863 # number of overall hits +system.l2c.overall_miss_latency 12232802000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.303655 # miss rate for overall accesses +system.l2c.overall_misses 940980 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10350842000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.303655 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 940980 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992369 # number of replacements +system.l2c.sampled_refs 1057905 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65468.856552 # Cycle average of tags in use +system.l2c.total_refs 2345243 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3045832000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 74072 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 69304a604..072cb6c8c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,6 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 -0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 +Listening for system connection on port 3456 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 206c366c1..b8196fe27 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:07:20 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Exiting @ tick 3875100962 because m5_exit instruction encountered +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:07:53 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 1907146437000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 71c721b07..0431dd3db 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=AtomicSimpleCPU children=workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 simulate_stalls=false system=system @@ -82,6 +39,7 @@ system=system [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -93,14 +51,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 95a0614c9..73c363bc4 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=EioProcess @@ -40,61 +39,11 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false width=1 function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 50d3a76c7..7380e419f 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1281059 # Simulator instruction rate (inst/s) -host_mem_usage 147756 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -host_tick_rate 1279755 # Simulator tick rate (ticks/s) +host_inst_rate 819297 # Simulator instruction rate (inst/s) +host_mem_usage 147636 # Number of bytes of host memory used +host_seconds 0.61 # Real time elapsed on the host +host_tick_rate 409362131 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 499999 # Number of ticks simulated +sim_seconds 0.000250 # Number of seconds simulated +sim_ticks 249999500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 500000 # number of cpu cycles simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 18a78c936..c8bcb5723 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,8 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:57 2006 +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:43 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic -Exiting @ tick 499999 because a thread reached the max instruction count +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 249999500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 2be814794..c05a66f9d 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -1,51 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[debug] -break_cycles= - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -56,7 +12,7 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache icache l2cache toL2Bus workload -clock=1 +clock=500 cpu_id=0 defer_registration=false function_trace=false @@ -65,6 +21,7 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 +phase=0 progress_interval=0 system=system workload=system.cpu.workload @@ -79,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -118,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -157,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -190,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -205,6 +160,7 @@ system=system [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -216,14 +172,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index bd0dbfad0..570ef7de8 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -1,15 +1,13 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -22,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=EioProcess @@ -40,7 +39,8 @@ progress_interval=0 system=system cpu_id=0 workload=system.cpu.workload -clock=1 +clock=500 +phase=0 defer_registration=false // width not specified function_trace=false @@ -53,13 +53,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -90,14 +91,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -128,14 +128,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -166,56 +165,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[debug] -break_cycles= - -[statsreset] -reset_cycle=0 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index d8d06877e..be87d3617 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 542626 # Simulator instruction rate (inst/s) -host_mem_usage 178896 # Number of bytes of host memory used -host_seconds 0.92 # Real time elapsed on the host -host_tick_rate 4319791 # Simulator tick rate (ticks/s) +host_inst_rate 392036 # Simulator instruction rate (inst/s) +host_mem_usage 153128 # Number of bytes of host memory used +host_seconds 1.28 # Real time elapsed on the host +host_tick_rate 542334315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 3982316 # Number of ticks simulated +sim_seconds 0.000692 # Number of seconds simulated +sim_ticks 691915000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3670.641270 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2670.641270 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1156252 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4410000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 841252 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4095000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3907.374101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2907.374101 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 543125 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1946000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 404125 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1807000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3743.121145 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1699377 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 6356000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1245377 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5902000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3743.121145 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180321 # number of overall hits -system.cpu.dcache.overall_miss_latency 1699377 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 6356000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1245377 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5902000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 227.376906 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 290.922203 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3977.722084 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.722084 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1603022 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 5642000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 1200022 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 5239000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3977.722084 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1603022 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 5642000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1200022 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 5239000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3977.722084 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits -system.cpu.icache.overall_miss_latency 1603022 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 5642000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1200022 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 5239000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 221.721362 # Cycle average of tags in use +system.cpu.icache.tagsinuse 267.665433 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2853.441074 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1852.441074 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2445399 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 11141000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1587542 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 9427000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2853.441074 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2445399 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 11141000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1587542 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9427000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2853.441074 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2445399 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 11141000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1587542 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9427000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 449.313470 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 558.588875 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 3982316 # number of cpu cycles simulated +system.cpu.numCycles 691915000 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 787ea041d..83f216de6 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 3 2006 17:10:27 -M5 started Fri Nov 3 17:10:58 2006 +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:44 2007 M5 executing on zizzer.eecs.umich.edu -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing -Exiting @ tick 3982316 because a thread reached the max instruction count +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 691915000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 05eb91461..bf66a6947 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -1,48 +1,7 @@ [root] type=Root children=system -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 - -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - -[serialize] -count=10 -cycle=0 -dir=cpt.%012d -period=0 - -[stats] -descriptions=true -dump_cycle=0 -dump_period=0 -dump_reset=false -ignore_events= -mysql_db= -mysql_host= -mysql_password= -mysql_user= -project_name=test -simulation_name=test -simulation_sample=0 -text_compat=true -text_file=m5stats.txt +dummy=0 [system] type=System @@ -75,8 +34,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -136,8 +94,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -197,8 +154,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -258,8 +214,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -319,8 +274,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -380,8 +334,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -441,8 +394,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -502,8 +454,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -555,8 +506,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=10 +latency=10000 lifo=false max_miss_count=0 mshrs=92 @@ -588,6 +538,7 @@ mem_side=system.membus.port[0] [system.membus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=false @@ -604,18 +555,10 @@ port=system.membus.port[1] [system.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=false width=16 port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out index b8ae04bc0..53f718c0d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [system.physmem] type=PhysicalMemory @@ -23,13 +20,14 @@ bus_id=0 clock=2 width=16 responder_set=false +block_size=64 [system.l2c] type=BaseCache size=65536 assoc=8 block_size=64 -latency=10 +latency=10000 mshrs=92 tgts_per_mshr=16 write_buffers=8 @@ -60,7 +58,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu6] type=MemTest @@ -85,7 +82,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -116,7 +113,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu4] type=MemTest @@ -141,7 +137,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -172,7 +168,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu5] type=MemTest @@ -197,7 +192,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -228,7 +223,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu2] type=MemTest @@ -253,7 +247,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -284,7 +278,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu3] type=MemTest @@ -309,7 +302,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -340,7 +333,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu0] type=MemTest @@ -365,7 +357,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -396,7 +388,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu1] type=MemTest @@ -421,7 +412,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -452,7 +443,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.funcmem] type=PhysicalMemory @@ -484,7 +474,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -515,7 +505,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.toL2Bus] type=Bus @@ -523,52 +512,5 @@ bus_id=0 clock=2 width=16 responder_set=false - -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 +block_size=64 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index a65b235b0..2617dd49e 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 435124 # Number of bytes of host memory used -host_seconds 28.46 # Real time elapsed on the host -host_tick_rate 202211 # Simulator tick rate (ticks/s) +host_mem_usage 1265676 # Number of bytes of host memory used +host_seconds 390.60 # Real time elapsed on the host +host_tick_rate 215953 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5755736 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 45048 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 959.688548 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 884.132516 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_hits 7543 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 35993119 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.832556 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37505 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 33159390 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.832556 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37505 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable 9815 # number of ReadReq MSHR uncacheable +sim_seconds 0.000084 # Number of seconds simulated +sim_ticks 84350509 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44421 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 14010.391786 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 12986.475734 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7291 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 520205847 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.835866 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37130 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 482187844 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.835866 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37130 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable 9916 # number of ReadReq MSHR uncacheable system.cpu0.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 17521633 # number of ReadResp MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24308 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 862.246942 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 778.821396 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_hits 1173 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 19948083 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.951744 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23135 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 18018033 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.951744 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23135 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable 5428 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 255520881 # number of ReadResp MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 23898 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 12904.605270 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 11399.917485 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_hits 1090 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 294328237 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.954389 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 22808 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 260009318 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.954389 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 22808 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable 5184 # number of WriteReq MSHR uncacheable system.cpu0.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 10755873 # number of WriteResp MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 81.366905 # average number of cycles each access was blocked +system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 154702333 # number of WriteResp MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1194.948852 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.417208 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 69811 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.407238 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69093 # number of cycles access was blocked system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 5680305 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 82562601 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 69356 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 922.513226 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8716 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 55941202 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.874330 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60640 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68319 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 13589.610664 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8381 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 814534084 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.877325 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 59938 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 51177423 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.874330 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60640 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 742197162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.877325 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 59938 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 69356 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 922.513226 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency +system.cpu0.l1c.overall_accesses 68319 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 13589.610664 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8716 # number of overall hits -system.cpu0.l1c.overall_miss_latency 55941202 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.874330 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60640 # number of overall misses +system.cpu0.l1c.overall_hits 8381 # number of overall hits +system.cpu0.l1c.overall_miss_latency 814534084 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.877325 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 59938 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 51177423 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.874330 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60640 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_miss_latency 742197162 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.877325 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 59938 # number of overall MSHR misses system.cpu0.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_misses 15243 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses 15100 # number of overall MSHR uncacheable misses system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -78,103 +78,103 @@ system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu0.l1c.protocol.read_invalid 109554 # read misses to invalid blocks +system.cpu0.l1c.protocol.read_invalid 1761660 # read misses to invalid blocks system.cpu0.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu0.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu0.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu0.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu0.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu0.l1c.protocol.snoop_read_exclusive 2807 # read snoops on exclusive blocks -system.cpu0.l1c.protocol.snoop_read_modified 12380 # read snoops on modified blocks -system.cpu0.l1c.protocol.snoop_read_owned 7157 # read snoops on owned blocks -system.cpu0.l1c.protocol.snoop_read_shared 22767 # read snoops on shared blocks -system.cpu0.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks -system.cpu0.l1c.protocol.snoop_readex_modified 6851 # readEx snoops on modified blocks -system.cpu0.l1c.protocol.snoop_readex_owned 3877 # readEx snoops on owned blocks -system.cpu0.l1c.protocol.snoop_readex_shared 12465 # readEx snoops on shared blocks -system.cpu0.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks -system.cpu0.l1c.protocol.snoop_upgrade_shared 2994 # upgradee snoops on shared blocks +system.cpu0.l1c.protocol.snoop_read_exclusive 2836 # read snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_read_modified 12378 # read snoops on modified blocks +system.cpu0.l1c.protocol.snoop_read_owned 7300 # read snoops on owned blocks +system.cpu0.l1c.protocol.snoop_read_shared 1749577 # read snoops on shared blocks +system.cpu0.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_readex_modified 6692 # readEx snoops on modified blocks +system.cpu0.l1c.protocol.snoop_readex_owned 4009 # readEx snoops on owned blocks +system.cpu0.l1c.protocol.snoop_readex_shared 12550 # readEx snoops on shared blocks +system.cpu0.l1c.protocol.snoop_upgrade_owned 790 # upgrade snoops on owned blocks +system.cpu0.l1c.protocol.snoop_upgrade_shared 3004 # upgradee snoops on shared blocks system.cpu0.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu0.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu0.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu0.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu0.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu0.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu0.l1c.protocol.write_invalid 60706 # write misses to invalid blocks -system.cpu0.l1c.protocol.write_owned 1361 # write misses to owned blocks -system.cpu0.l1c.protocol.write_shared 4416 # write misses to shared blocks -system.cpu0.l1c.replacements 27529 # number of replacements -system.cpu0.l1c.sampled_refs 27883 # Sample count of references to valid blocks. +system.cpu0.l1c.protocol.write_invalid 940728 # write misses to invalid blocks +system.cpu0.l1c.protocol.write_owned 1344 # write misses to owned blocks +system.cpu0.l1c.protocol.write_shared 4484 # write misses to shared blocks +system.cpu0.l1c.replacements 27160 # number of replacements +system.cpu0.l1c.sampled_refs 27495 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 342.460043 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11633 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 342.709273 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11197 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 10915 # number of writebacks +system.cpu0.l1c.writebacks 10716 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99586 # number of read accesses completed -system.cpu0.num_writes 53803 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44416 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 969.343786 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 893.327484 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_hits 7486 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 35797866 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.831457 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 36930 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 32990584 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831457 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 36930 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable 9894 # number of ReadReq MSHR uncacheable +system.cpu0.num_reads 98012 # number of read accesses completed +system.cpu0.num_writes 53207 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44893 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 13909.754864 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 12900.185775 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7579 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 519028593 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.831176 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37314 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 481357532 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831176 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37314 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable 9811 # number of ReadReq MSHR uncacheable system.cpu1.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 17663360 # number of ReadResp MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24084 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 871.179293 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 786.258930 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_hits 1155 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 19975270 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.952043 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 22929 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 18028131 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.952043 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 22929 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable 5271 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 251708747 # number of ReadResp MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24614 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 12788.679753 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 11344.205121 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_hits 1257 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 298705193 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.948932 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23357 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 264966599 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.948932 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23357 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable 5453 # number of WriteReq MSHR uncacheable system.cpu1.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 10523322 # number of WriteResp MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 82.260179 # average number of cycles each access was blocked +system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 163813954 # number of WriteResp MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1183.149435 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.414867 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 68941 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.414323 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69763 # number of cycles access was blocked system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 5671099 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 82540054 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 68500 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 931.741860 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8641 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 55773136 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.873854 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 59859 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 69507 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 13478.165615 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8836 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 817733786 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.872876 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60671 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 51018715 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.873854 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 59859 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 746324131 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.872876 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60671 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 68500 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 931.741860 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency +system.cpu1.l1c.overall_accesses 69507 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 13478.165615 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8641 # number of overall hits -system.cpu1.l1c.overall_miss_latency 55773136 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.873854 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 59859 # number of overall misses +system.cpu1.l1c.overall_hits 8836 # number of overall hits +system.cpu1.l1c.overall_miss_latency 817733786 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.872876 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60671 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 51018715 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.873854 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 59859 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_miss_latency 746324131 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.872876 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60671 # number of overall MSHR misses system.cpu1.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_misses 15165 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses 15264 # number of overall MSHR uncacheable misses system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -185,103 +185,103 @@ system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu1.l1c.protocol.read_invalid 114228 # read misses to invalid blocks +system.cpu1.l1c.protocol.read_invalid 1717891 # read misses to invalid blocks system.cpu1.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu1.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu1.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu1.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu1.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu1.l1c.protocol.snoop_read_exclusive 2718 # read snoops on exclusive blocks -system.cpu1.l1c.protocol.snoop_read_modified 12396 # read snoops on modified blocks -system.cpu1.l1c.protocol.snoop_read_owned 7348 # read snoops on owned blocks -system.cpu1.l1c.protocol.snoop_read_shared 23222 # read snoops on shared blocks -system.cpu1.l1c.protocol.snoop_readex_exclusive 1497 # readEx snoops on exclusive blocks -system.cpu1.l1c.protocol.snoop_readex_modified 6706 # readEx snoops on modified blocks -system.cpu1.l1c.protocol.snoop_readex_owned 3865 # readEx snoops on owned blocks -system.cpu1.l1c.protocol.snoop_readex_shared 12512 # readEx snoops on shared blocks -system.cpu1.l1c.protocol.snoop_upgrade_owned 852 # upgrade snoops on owned blocks -system.cpu1.l1c.protocol.snoop_upgrade_shared 2973 # upgradee snoops on shared blocks +system.cpu1.l1c.protocol.snoop_read_exclusive 2925 # read snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_read_modified 12701 # read snoops on modified blocks +system.cpu1.l1c.protocol.snoop_read_owned 7436 # read snoops on owned blocks +system.cpu1.l1c.protocol.snoop_read_shared 1669937 # read snoops on shared blocks +system.cpu1.l1c.protocol.snoop_readex_exclusive 1611 # readEx snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_readex_modified 6726 # readEx snoops on modified blocks +system.cpu1.l1c.protocol.snoop_readex_owned 3965 # readEx snoops on owned blocks +system.cpu1.l1c.protocol.snoop_readex_shared 12596 # readEx snoops on shared blocks +system.cpu1.l1c.protocol.snoop_upgrade_owned 860 # upgrade snoops on owned blocks +system.cpu1.l1c.protocol.snoop_upgrade_shared 2979 # upgradee snoops on shared blocks system.cpu1.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu1.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu1.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu1.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu1.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu1.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu1.l1c.protocol.write_invalid 61595 # write misses to invalid blocks -system.cpu1.l1c.protocol.write_owned 1320 # write misses to owned blocks -system.cpu1.l1c.protocol.write_shared 4183 # write misses to shared blocks -system.cpu1.l1c.replacements 27139 # number of replacements -system.cpu1.l1c.sampled_refs 27498 # Sample count of references to valid blocks. +system.cpu1.l1c.protocol.write_invalid 914774 # write misses to invalid blocks +system.cpu1.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu1.l1c.protocol.write_shared 4382 # write misses to shared blocks +system.cpu1.l1c.replacements 27806 # number of replacements +system.cpu1.l1c.sampled_refs 28164 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 341.113569 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11408 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 345.545872 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11669 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10884 # number of writebacks +system.cpu1.l1c.writebacks 11204 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98821 # number of read accesses completed -system.cpu1.num_writes 53366 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 45016 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 956.031371 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 880.781951 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_hits 7529 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 35838748 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.832748 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37487 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 33017873 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832748 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable 9887 # number of ReadReq MSHR uncacheable +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 54335 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44489 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 14018.031231 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 12993.788573 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7507 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 518414831 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.831262 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 36982 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 480536289 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.831262 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 36982 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable system.cpu2.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 17582637 # number of ReadResp MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24456 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 859.707355 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 777.777296 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_hits 1165 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 20023444 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.952363 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23291 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 18115211 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.952363 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23291 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable 5362 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 253484666 # number of ReadResp MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24340 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 12765.385606 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 11318.971789 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_hits 1122 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 296386723 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.953903 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23218 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 262803887 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.953903 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23218 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable 5480 # number of WriteReq MSHR uncacheable system.cpu2.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 10583136 # number of WriteResp MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 81.152375 # average number of cycles each access was blocked +system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 165110755 # number of WriteResp MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1190.317505 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.404365 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 69867 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.414721 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69202 # number of cycles access was blocked system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 5669873 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 82372352 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 69472 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 919.118628 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8694 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 55862192 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.874856 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60778 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68829 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 13534.909535 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8629 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 814801554 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.874631 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60200 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 51133084 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.874856 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60778 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 743340176 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.874631 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60200 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 69472 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 919.118628 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency +system.cpu2.l1c.overall_accesses 68829 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 13534.909535 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8694 # number of overall hits -system.cpu2.l1c.overall_miss_latency 55862192 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.874856 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60778 # number of overall misses +system.cpu2.l1c.overall_hits 8629 # number of overall hits +system.cpu2.l1c.overall_miss_latency 814801554 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.874631 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60200 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 51133084 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.874856 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60778 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_miss_latency 743340176 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.874631 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60200 # number of overall MSHR misses system.cpu2.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_misses 15249 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses 15341 # number of overall MSHR uncacheable misses system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -292,103 +292,103 @@ system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu2.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu2.l1c.protocol.read_invalid 111528 # read misses to invalid blocks +system.cpu2.l1c.protocol.read_invalid 1818161 # read misses to invalid blocks system.cpu2.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu2.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu2.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu2.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu2.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu2.l1c.protocol.snoop_read_exclusive 2757 # read snoops on exclusive blocks -system.cpu2.l1c.protocol.snoop_read_modified 12587 # read snoops on modified blocks -system.cpu2.l1c.protocol.snoop_read_owned 7252 # read snoops on owned blocks -system.cpu2.l1c.protocol.snoop_read_shared 22967 # read snoops on shared blocks -system.cpu2.l1c.protocol.snoop_readex_exclusive 1579 # readEx snoops on exclusive blocks -system.cpu2.l1c.protocol.snoop_readex_modified 6680 # readEx snoops on modified blocks -system.cpu2.l1c.protocol.snoop_readex_owned 3891 # readEx snoops on owned blocks -system.cpu2.l1c.protocol.snoop_readex_shared 12468 # readEx snoops on shared blocks -system.cpu2.l1c.protocol.snoop_upgrade_owned 850 # upgrade snoops on owned blocks -system.cpu2.l1c.protocol.snoop_upgrade_shared 2951 # upgradee snoops on shared blocks +system.cpu2.l1c.protocol.snoop_read_exclusive 2846 # read snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_read_modified 12505 # read snoops on modified blocks +system.cpu2.l1c.protocol.snoop_read_owned 7354 # read snoops on owned blocks +system.cpu2.l1c.protocol.snoop_read_shared 1719896 # read snoops on shared blocks +system.cpu2.l1c.protocol.snoop_readex_exclusive 1512 # readEx snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_readex_modified 6836 # readEx snoops on modified blocks +system.cpu2.l1c.protocol.snoop_readex_owned 4066 # readEx snoops on owned blocks +system.cpu2.l1c.protocol.snoop_readex_shared 12494 # readEx snoops on shared blocks +system.cpu2.l1c.protocol.snoop_upgrade_owned 828 # upgrade snoops on owned blocks +system.cpu2.l1c.protocol.snoop_upgrade_shared 2975 # upgradee snoops on shared blocks system.cpu2.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu2.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu2.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu2.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu2.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu2.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu2.l1c.protocol.write_invalid 57618 # write misses to invalid blocks -system.cpu2.l1c.protocol.write_owned 1263 # write misses to owned blocks -system.cpu2.l1c.protocol.write_shared 4251 # write misses to shared blocks -system.cpu2.l1c.replacements 28062 # number of replacements -system.cpu2.l1c.sampled_refs 28405 # Sample count of references to valid blocks. +system.cpu2.l1c.protocol.write_invalid 1061132 # write misses to invalid blocks +system.cpu2.l1c.protocol.write_owned 1410 # write misses to owned blocks +system.cpu2.l1c.protocol.write_shared 4436 # write misses to shared blocks +system.cpu2.l1c.replacements 27337 # number of replacements +system.cpu2.l1c.sampled_refs 27674 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 344.040679 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11486 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 343.290844 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11477 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 11295 # number of writebacks +system.cpu2.l1c.writebacks 10872 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 54133 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44504 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 968.772953 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 892.914985 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_hits 7428 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 35918226 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.833094 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37076 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 33105716 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833094 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37076 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable 9876 # number of ReadReq MSHR uncacheable +system.cpu2.num_reads 98887 # number of read accesses completed +system.cpu2.num_writes 53640 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44566 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 14066.553951 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 13052.525235 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7375 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 523149208 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.834515 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37191 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 485436466 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.834515 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable system.cpu3.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 17594905 # number of ReadResp MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24087 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 868.499565 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 784.537397 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_hits 1117 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 19949435 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.953626 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 22970 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 18020824 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.953626 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 22970 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable 5355 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 252799971 # number of ReadResp MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24030 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 12807.474484 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 11345.837164 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_hits 1142 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 293137476 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.952476 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 22888 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 259683521 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.952476 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 22888 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable 5294 # number of WriteReq MSHR uncacheable system.cpu3.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 10637792 # number of WriteResp MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 82.097897 # average number of cycles each access was blocked +system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 159218905 # number of WriteResp MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1193.729049 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.411489 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69124 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.411345 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69160 # number of cycles access was blocked system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 5674935 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 82558301 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 68591 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 930.414366 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8545 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 55867661 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.875421 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60046 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68596 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 13586.888663 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8517 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 816286684 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.875838 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60079 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 51126540 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.875421 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60046 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 745119987 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.875838 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60079 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 68591 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 930.414366 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency +system.cpu3.l1c.overall_accesses 68596 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 13586.888663 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8545 # number of overall hits -system.cpu3.l1c.overall_miss_latency 55867661 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.875421 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60046 # number of overall misses +system.cpu3.l1c.overall_hits 8517 # number of overall hits +system.cpu3.l1c.overall_miss_latency 816286684 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.875838 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60079 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 51126540 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.875421 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60046 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_miss_latency 745119987 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.875838 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60079 # number of overall MSHR misses system.cpu3.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_misses 15231 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses 15114 # number of overall MSHR uncacheable misses system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -399,103 +399,103 @@ system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu3.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu3.l1c.protocol.read_invalid 110901 # read misses to invalid blocks +system.cpu3.l1c.protocol.read_invalid 1894373 # read misses to invalid blocks system.cpu3.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu3.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu3.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu3.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu3.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu3.l1c.protocol.snoop_read_exclusive 2843 # read snoops on exclusive blocks -system.cpu3.l1c.protocol.snoop_read_modified 12490 # read snoops on modified blocks -system.cpu3.l1c.protocol.snoop_read_owned 7235 # read snoops on owned blocks -system.cpu3.l1c.protocol.snoop_read_shared 23011 # read snoops on shared blocks -system.cpu3.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks -system.cpu3.l1c.protocol.snoop_readex_modified 6732 # readEx snoops on modified blocks -system.cpu3.l1c.protocol.snoop_readex_owned 3954 # readEx snoops on owned blocks -system.cpu3.l1c.protocol.snoop_readex_shared 12354 # readEx snoops on shared blocks -system.cpu3.l1c.protocol.snoop_upgrade_owned 858 # upgrade snoops on owned blocks -system.cpu3.l1c.protocol.snoop_upgrade_shared 3087 # upgradee snoops on shared blocks +system.cpu3.l1c.protocol.snoop_read_exclusive 2902 # read snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_read_modified 12291 # read snoops on modified blocks +system.cpu3.l1c.protocol.snoop_read_owned 7221 # read snoops on owned blocks +system.cpu3.l1c.protocol.snoop_read_shared 1743434 # read snoops on shared blocks +system.cpu3.l1c.protocol.snoop_readex_exclusive 1553 # readEx snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_readex_modified 6822 # readEx snoops on modified blocks +system.cpu3.l1c.protocol.snoop_readex_owned 3914 # readEx snoops on owned blocks +system.cpu3.l1c.protocol.snoop_readex_shared 12477 # readEx snoops on shared blocks +system.cpu3.l1c.protocol.snoop_upgrade_owned 867 # upgrade snoops on owned blocks +system.cpu3.l1c.protocol.snoop_upgrade_shared 3008 # upgradee snoops on shared blocks system.cpu3.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu3.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu3.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu3.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu3.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu3.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu3.l1c.protocol.write_invalid 59061 # write misses to invalid blocks -system.cpu3.l1c.protocol.write_owned 1261 # write misses to owned blocks -system.cpu3.l1c.protocol.write_shared 4235 # write misses to shared blocks -system.cpu3.l1c.replacements 27216 # number of replacements -system.cpu3.l1c.sampled_refs 27556 # Sample count of references to valid blocks. +system.cpu3.l1c.protocol.write_invalid 1046634 # write misses to invalid blocks +system.cpu3.l1c.protocol.write_owned 1364 # write misses to owned blocks +system.cpu3.l1c.protocol.write_shared 4484 # write misses to shared blocks +system.cpu3.l1c.replacements 27286 # number of replacements +system.cpu3.l1c.sampled_refs 27624 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 341.602377 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11339 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 342.290575 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11363 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10831 # number of writebacks +system.cpu3.l1c.writebacks 10681 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98893 # number of read accesses completed -system.cpu3.num_writes 53654 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44272 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 976.655364 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 901.292278 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_hits 7468 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 35944824 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.831316 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 36804 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 33171161 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831316 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 36804 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable 9822 # number of ReadReq MSHR uncacheable +system.cpu3.num_reads 99322 # number of read accesses completed +system.cpu3.num_writes 53280 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 13943.186039 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 12937.718615 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7581 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 521335726 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.831425 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37390 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 483741299 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831425 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37390 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable 9931 # number of ReadReq MSHR uncacheable system.cpu4.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 17532387 # number of ReadResp MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 23994 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 874.063859 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 788.017488 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_hits 1178 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 19942641 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.950904 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 22816 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 17979407 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.950904 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 22816 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable 5315 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 254015216 # number of ReadResp MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24134 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 12764.573629 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 11273.971841 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_hits 1086 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 294197893 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.955001 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23048 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 259842503 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.955001 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23048 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable 5390 # number of WriteReq MSHR uncacheable system.cpu4.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 10563676 # number of WriteResp MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 82.703233 # average number of cycles each access was blocked +system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 161643344 # number of WriteResp MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1186.636056 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.416368 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 68707 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.410931 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69637 # number of cycles access was blocked system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 5682291 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 82633775 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68266 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 937.394582 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8646 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 55887465 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.873348 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 59620 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 69105 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 13493.722807 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8667 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 815533619 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.874582 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60438 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 51150568 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.873348 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 59620 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 743583802 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.874582 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60438 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 68266 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 937.394582 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency +system.cpu4.l1c.overall_accesses 69105 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 13493.722807 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8646 # number of overall hits -system.cpu4.l1c.overall_miss_latency 55887465 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.873348 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 59620 # number of overall misses +system.cpu4.l1c.overall_hits 8667 # number of overall hits +system.cpu4.l1c.overall_miss_latency 815533619 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.874582 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60438 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 51150568 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.873348 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 59620 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_miss_latency 743583802 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.874582 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60438 # number of overall MSHR misses system.cpu4.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_misses 15137 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses 15321 # number of overall MSHR uncacheable misses system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -506,103 +506,103 @@ system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu4.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu4.l1c.protocol.read_invalid 113154 # read misses to invalid blocks +system.cpu4.l1c.protocol.read_invalid 1830675 # read misses to invalid blocks system.cpu4.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu4.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu4.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu4.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu4.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu4.l1c.protocol.snoop_read_exclusive 2804 # read snoops on exclusive blocks -system.cpu4.l1c.protocol.snoop_read_modified 12453 # read snoops on modified blocks -system.cpu4.l1c.protocol.snoop_read_owned 7418 # read snoops on owned blocks -system.cpu4.l1c.protocol.snoop_read_shared 23136 # read snoops on shared blocks -system.cpu4.l1c.protocol.snoop_readex_exclusive 1528 # readEx snoops on exclusive blocks -system.cpu4.l1c.protocol.snoop_readex_modified 6607 # readEx snoops on modified blocks -system.cpu4.l1c.protocol.snoop_readex_owned 3922 # readEx snoops on owned blocks -system.cpu4.l1c.protocol.snoop_readex_shared 12524 # readEx snoops on shared blocks -system.cpu4.l1c.protocol.snoop_upgrade_owned 843 # upgrade snoops on owned blocks -system.cpu4.l1c.protocol.snoop_upgrade_shared 2904 # upgradee snoops on shared blocks +system.cpu4.l1c.protocol.snoop_read_exclusive 2847 # read snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_read_modified 12499 # read snoops on modified blocks +system.cpu4.l1c.protocol.snoop_read_owned 7458 # read snoops on owned blocks +system.cpu4.l1c.protocol.snoop_read_shared 1765770 # read snoops on shared blocks +system.cpu4.l1c.protocol.snoop_readex_exclusive 1560 # readEx snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_readex_modified 6711 # readEx snoops on modified blocks +system.cpu4.l1c.protocol.snoop_readex_owned 3919 # readEx snoops on owned blocks +system.cpu4.l1c.protocol.snoop_readex_shared 12526 # readEx snoops on shared blocks +system.cpu4.l1c.protocol.snoop_upgrade_owned 902 # upgrade snoops on owned blocks +system.cpu4.l1c.protocol.snoop_upgrade_shared 3023 # upgradee snoops on shared blocks system.cpu4.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu4.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu4.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu4.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu4.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu4.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu4.l1c.protocol.write_invalid 59622 # write misses to invalid blocks -system.cpu4.l1c.protocol.write_owned 1265 # write misses to owned blocks -system.cpu4.l1c.protocol.write_shared 4187 # write misses to shared blocks -system.cpu4.l1c.replacements 27000 # number of replacements -system.cpu4.l1c.sampled_refs 27346 # Sample count of references to valid blocks. +system.cpu4.l1c.protocol.write_invalid 854606 # write misses to invalid blocks +system.cpu4.l1c.protocol.write_owned 1318 # write misses to owned blocks +system.cpu4.l1c.protocol.write_shared 4519 # write misses to shared blocks +system.cpu4.l1c.replacements 27664 # number of replacements +system.cpu4.l1c.sampled_refs 28012 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 342.121323 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11386 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 344.185288 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11511 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10847 # number of writebacks +system.cpu4.l1c.writebacks 10935 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98882 # number of read accesses completed -system.cpu4.num_writes 53288 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44218 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 975.652027 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 898.818359 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_hits 7310 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 36009365 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.834683 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 36908 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 33173588 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.834683 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 36908 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable 9866 # number of ReadReq MSHR uncacheable +system.cpu4.num_reads 99841 # number of read accesses completed +system.cpu4.num_writes 54005 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 45075 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 13980.675167 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 12974.186518 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7588 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 524093570 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.831658 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37487 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 486363330 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831658 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable 9769 # number of ReadReq MSHR uncacheable system.cpu5.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 17625443 # number of ReadResp MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 23923 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 873.308611 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 788.173188 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_hits 1150 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 19887857 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.951929 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 22773 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 17949068 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.951929 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 22773 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable 5207 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 252483534 # number of ReadResp MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24120 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 12733.111936 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 11249.826210 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_hits 1098 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 293141703 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.954478 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23022 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 258993499 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.954478 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23022 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable 5232 # number of WriteReq MSHR uncacheable system.cpu5.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 10374807 # number of WriteResp MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 82.590363 # average number of cycles each access was blocked +system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 155064988 # number of WriteResp MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1188.349008 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.413664 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 68944 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.414917 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 5694110 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 82634225 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 68141 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 936.599956 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8460 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 55897222 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.875846 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 59681 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 69195 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 13506.011883 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8686 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 817235273 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.874471 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60509 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 51122656 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.875846 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 59681 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 745356829 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.874471 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60509 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 68141 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 936.599956 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency +system.cpu5.l1c.overall_accesses 69195 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 13506.011883 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8460 # number of overall hits -system.cpu5.l1c.overall_miss_latency 55897222 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.875846 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 59681 # number of overall misses +system.cpu5.l1c.overall_hits 8686 # number of overall hits +system.cpu5.l1c.overall_miss_latency 817235273 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.874471 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60509 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 51122656 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.875846 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 59681 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_miss_latency 745356829 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.874471 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60509 # number of overall MSHR misses system.cpu5.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_misses 15073 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses 15001 # number of overall MSHR uncacheable misses system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -613,103 +613,103 @@ system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu5.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu5.l1c.protocol.read_invalid 114279 # read misses to invalid blocks +system.cpu5.l1c.protocol.read_invalid 1718821 # read misses to invalid blocks system.cpu5.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu5.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu5.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu5.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu5.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu5.l1c.protocol.snoop_read_exclusive 2860 # read snoops on exclusive blocks -system.cpu5.l1c.protocol.snoop_read_modified 12253 # read snoops on modified blocks -system.cpu5.l1c.protocol.snoop_read_owned 7231 # read snoops on owned blocks -system.cpu5.l1c.protocol.snoop_read_shared 23182 # read snoops on shared blocks -system.cpu5.l1c.protocol.snoop_readex_exclusive 1499 # readEx snoops on exclusive blocks -system.cpu5.l1c.protocol.snoop_readex_modified 6757 # readEx snoops on modified blocks -system.cpu5.l1c.protocol.snoop_readex_owned 3896 # readEx snoops on owned blocks -system.cpu5.l1c.protocol.snoop_readex_shared 12461 # readEx snoops on shared blocks -system.cpu5.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks -system.cpu5.l1c.protocol.snoop_upgrade_shared 3020 # upgradee snoops on shared blocks +system.cpu5.l1c.protocol.snoop_read_exclusive 2926 # read snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_read_modified 12465 # read snoops on modified blocks +system.cpu5.l1c.protocol.snoop_read_owned 7201 # read snoops on owned blocks +system.cpu5.l1c.protocol.snoop_read_shared 1810557 # read snoops on shared blocks +system.cpu5.l1c.protocol.snoop_readex_exclusive 1622 # readEx snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_readex_modified 6690 # readEx snoops on modified blocks +system.cpu5.l1c.protocol.snoop_readex_owned 3947 # readEx snoops on owned blocks +system.cpu5.l1c.protocol.snoop_readex_shared 12574 # readEx snoops on shared blocks +system.cpu5.l1c.protocol.snoop_upgrade_owned 818 # upgrade snoops on owned blocks +system.cpu5.l1c.protocol.snoop_upgrade_shared 3092 # upgradee snoops on shared blocks system.cpu5.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu5.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu5.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu5.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu5.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu5.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu5.l1c.protocol.write_invalid 60969 # write misses to invalid blocks -system.cpu5.l1c.protocol.write_owned 1349 # write misses to owned blocks -system.cpu5.l1c.protocol.write_shared 4191 # write misses to shared blocks -system.cpu5.l1c.replacements 26828 # number of replacements -system.cpu5.l1c.sampled_refs 27196 # Sample count of references to valid blocks. +system.cpu5.l1c.protocol.write_invalid 914561 # write misses to invalid blocks +system.cpu5.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu5.l1c.protocol.write_shared 4534 # write misses to shared blocks +system.cpu5.l1c.replacements 27551 # number of replacements +system.cpu5.l1c.sampled_refs 27914 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 340.865502 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11250 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 344.440637 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11582 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10567 # number of writebacks +system.cpu5.l1c.writebacks 10931 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 97882 # number of read accesses completed -system.cpu5.num_writes 52965 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 967.006541 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 890.563660 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_hits 7514 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 36221164 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.832915 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37457 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 33357843 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37457 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable 9684 # number of ReadReq MSHR uncacheable +system.cpu5.num_reads 99674 # number of read accesses completed +system.cpu5.num_writes 53393 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44595 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 14001.082353 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 12995.526917 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7462 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 519902191 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.832672 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37133 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 482562901 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832672 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37133 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable system.cpu6.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 17275344 # number of ReadResp MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 23996 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 873.777515 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 790.631514 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_hits 1181 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 19935234 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.950783 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 22815 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 18038258 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.950783 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 22815 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable 5345 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 251671127 # number of ReadResp MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24364 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 12854.640783 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 11385.598176 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_hits 1222 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 297482097 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.949844 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23142 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 263485513 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.949844 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23142 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable 5447 # number of WriteReq MSHR uncacheable system.cpu6.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 10602140 # number of WriteResp MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 82.071085 # average number of cycles each access was blocked +system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 163399316 # number of WriteResp MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1189.328084 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.412251 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 69157 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.411043 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 69345 # number of cycles access was blocked system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 5675790 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 82473956 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 68967 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 931.716187 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8695 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 56156398 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.873925 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60272 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68959 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 13560.917263 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8684 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 817384288 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.874070 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60275 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 51396101 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.873925 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60272 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 746048414 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.874070 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60275 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 68967 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 931.716187 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency +system.cpu6.l1c.overall_accesses 68959 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 13560.917263 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8695 # number of overall hits -system.cpu6.l1c.overall_miss_latency 56156398 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.873925 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60272 # number of overall misses +system.cpu6.l1c.overall_hits 8684 # number of overall hits +system.cpu6.l1c.overall_miss_latency 817384288 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.874070 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60275 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 51396101 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.873925 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60272 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_miss_latency 746048414 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.874070 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60275 # number of overall MSHR misses system.cpu6.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_misses 15029 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses 15267 # number of overall MSHR uncacheable misses system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -720,103 +720,103 @@ system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu6.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu6.l1c.protocol.read_invalid 114488 # read misses to invalid blocks +system.cpu6.l1c.protocol.read_invalid 1894590 # read misses to invalid blocks system.cpu6.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu6.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu6.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu6.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu6.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu6.l1c.protocol.snoop_read_exclusive 2876 # read snoops on exclusive blocks -system.cpu6.l1c.protocol.snoop_read_modified 12371 # read snoops on modified blocks -system.cpu6.l1c.protocol.snoop_read_owned 7223 # read snoops on owned blocks -system.cpu6.l1c.protocol.snoop_read_shared 23305 # read snoops on shared blocks -system.cpu6.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks -system.cpu6.l1c.protocol.snoop_readex_modified 6693 # readEx snoops on modified blocks -system.cpu6.l1c.protocol.snoop_readex_owned 3909 # readEx snoops on owned blocks -system.cpu6.l1c.protocol.snoop_readex_shared 12446 # readEx snoops on shared blocks -system.cpu6.l1c.protocol.snoop_upgrade_owned 833 # upgrade snoops on owned blocks -system.cpu6.l1c.protocol.snoop_upgrade_shared 2948 # upgradee snoops on shared blocks +system.cpu6.l1c.protocol.snoop_read_exclusive 2887 # read snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_read_modified 12551 # read snoops on modified blocks +system.cpu6.l1c.protocol.snoop_read_owned 7188 # read snoops on owned blocks +system.cpu6.l1c.protocol.snoop_read_shared 1703425 # read snoops on shared blocks +system.cpu6.l1c.protocol.snoop_readex_exclusive 1550 # readEx snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_readex_modified 6733 # readEx snoops on modified blocks +system.cpu6.l1c.protocol.snoop_readex_owned 3926 # readEx snoops on owned blocks +system.cpu6.l1c.protocol.snoop_readex_shared 12456 # readEx snoops on shared blocks +system.cpu6.l1c.protocol.snoop_upgrade_owned 800 # upgrade snoops on owned blocks +system.cpu6.l1c.protocol.snoop_upgrade_shared 3156 # upgradee snoops on shared blocks system.cpu6.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu6.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu6.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu6.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu6.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu6.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu6.l1c.protocol.write_invalid 58413 # write misses to invalid blocks -system.cpu6.l1c.protocol.write_owned 1374 # write misses to owned blocks -system.cpu6.l1c.protocol.write_shared 4109 # write misses to shared blocks -system.cpu6.l1c.replacements 27477 # number of replacements -system.cpu6.l1c.sampled_refs 27835 # Sample count of references to valid blocks. +system.cpu6.l1c.protocol.write_invalid 987928 # write misses to invalid blocks +system.cpu6.l1c.protocol.write_owned 1405 # write misses to owned blocks +system.cpu6.l1c.protocol.write_shared 4406 # write misses to shared blocks +system.cpu6.l1c.replacements 27613 # number of replacements +system.cpu6.l1c.sampled_refs 27946 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 342.134742 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11475 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 344.860122 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11487 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 10759 # number of writebacks +system.cpu6.l1c.writebacks 11073 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99303 # number of read accesses completed -system.cpu6.num_writes 53385 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44438 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 975.306986 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 899.340271 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_hits 7394 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 36129272 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.833611 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37044 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 33315161 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833611 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37044 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable +system.cpu6.num_reads 98723 # number of read accesses completed +system.cpu6.num_writes 53876 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44990 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 13952.283047 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 12937.789329 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7505 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 523001330 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.833185 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37485 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 484973033 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833185 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37485 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable 10001 # number of ReadReq MSHR uncacheable system.cpu7.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 17576395 # number of ReadResp MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 23999 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 861.568979 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 776.580264 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_hits 1137 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 19697190 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.952623 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 22862 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 17754178 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.952623 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 22862 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable 5386 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 257188342 # number of ReadResp MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 12615.682417 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 11155.458639 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_hits 1163 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 289151441 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.951709 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 22920 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 255683112 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.951709 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 22920 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable 5323 # number of WriteReq MSHR uncacheable system.cpu7.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 10720857 # number of WriteResp MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 82.167211 # average number of cycles each access was blocked +system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 159397105 # number of WriteResp MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1185.864523 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.419292 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 68907 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.413879 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69665 # number of cycles access was blocked system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 5661896 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 82613252 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 68437 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 931.901012 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8531 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 55826462 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.875345 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 59906 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 69073 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 13445.124923 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8668 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 812152771 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.874510 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60405 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 51069339 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.875345 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 59906 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 740656145 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.874510 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60405 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 68437 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 931.901012 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency +system.cpu7.l1c.overall_accesses 69073 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 13445.124923 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8531 # number of overall hits -system.cpu7.l1c.overall_miss_latency 55826462 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.875345 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 59906 # number of overall misses +system.cpu7.l1c.overall_hits 8668 # number of overall hits +system.cpu7.l1c.overall_miss_latency 812152771 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.874510 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60405 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 51069339 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.875345 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 59906 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_miss_latency 740656145 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.874510 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60405 # number of overall MSHR misses system.cpu7.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_misses 15247 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses 15324 # number of overall MSHR uncacheable misses system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -827,111 +827,111 @@ system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu7.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu7.l1c.protocol.read_invalid 115064 # read misses to invalid blocks +system.cpu7.l1c.protocol.read_invalid 1929884 # read misses to invalid blocks system.cpu7.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu7.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu7.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu7.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu7.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu7.l1c.protocol.snoop_read_exclusive 2793 # read snoops on exclusive blocks -system.cpu7.l1c.protocol.snoop_read_modified 12588 # read snoops on modified blocks -system.cpu7.l1c.protocol.snoop_read_owned 7412 # read snoops on owned blocks -system.cpu7.l1c.protocol.snoop_read_shared 23048 # read snoops on shared blocks -system.cpu7.l1c.protocol.snoop_readex_exclusive 1548 # readEx snoops on exclusive blocks -system.cpu7.l1c.protocol.snoop_readex_modified 6593 # readEx snoops on modified blocks -system.cpu7.l1c.protocol.snoop_readex_owned 3944 # readEx snoops on owned blocks -system.cpu7.l1c.protocol.snoop_readex_shared 12404 # readEx snoops on shared blocks -system.cpu7.l1c.protocol.snoop_upgrade_owned 919 # upgrade snoops on owned blocks -system.cpu7.l1c.protocol.snoop_upgrade_shared 2959 # upgradee snoops on shared blocks +system.cpu7.l1c.protocol.snoop_read_exclusive 2904 # read snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_read_modified 12387 # read snoops on modified blocks +system.cpu7.l1c.protocol.snoop_read_owned 7174 # read snoops on owned blocks +system.cpu7.l1c.protocol.snoop_read_shared 1782059 # read snoops on shared blocks +system.cpu7.l1c.protocol.snoop_readex_exclusive 1587 # readEx snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_readex_modified 6687 # readEx snoops on modified blocks +system.cpu7.l1c.protocol.snoop_readex_owned 3842 # readEx snoops on owned blocks +system.cpu7.l1c.protocol.snoop_readex_shared 12759 # readEx snoops on shared blocks +system.cpu7.l1c.protocol.snoop_upgrade_owned 792 # upgrade snoops on owned blocks +system.cpu7.l1c.protocol.snoop_upgrade_shared 3085 # upgradee snoops on shared blocks system.cpu7.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu7.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu7.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu7.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu7.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu7.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu7.l1c.protocol.write_invalid 58173 # write misses to invalid blocks -system.cpu7.l1c.protocol.write_owned 1351 # write misses to owned blocks -system.cpu7.l1c.protocol.write_shared 4494 # write misses to shared blocks -system.cpu7.l1c.replacements 27080 # number of replacements -system.cpu7.l1c.sampled_refs 27420 # Sample count of references to valid blocks. +system.cpu7.l1c.protocol.write_invalid 930930 # write misses to invalid blocks +system.cpu7.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu7.l1c.protocol.write_shared 4465 # write misses to shared blocks +system.cpu7.l1c.replacements 27486 # number of replacements +system.cpu7.l1c.sampled_refs 27827 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 342.061742 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11497 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 344.310963 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11517 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10789 # number of writebacks +system.cpu7.l1c.writebacks 10979 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98350 # number of read accesses completed -system.cpu7.num_writes 53282 # number of write accesses completed -system.l2c.ReadExReq_accesses 75399 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 89.483714 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 6.467886 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits 39632 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 3200564 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 0.474370 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 35767 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 231311 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.474317 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 35763 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 138997 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 89.683271 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 6.196645 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 72568 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 5957570 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.477917 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 66429 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 411544 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.477809 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 66414 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable +system.cpu7.num_reads 99734 # number of read accesses completed +system.cpu7.num_writes 53652 # number of write accesses completed +system.l2c.ReadExReq_accesses 75160 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 10115.633652 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 6085.503709 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 39620 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 359509620 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.472858 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 35540 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 220 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 214939991 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.469931 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 35320 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 138762 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 10150.344064 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 6129.500996 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 72597 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 671597515 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.476824 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 66165 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 406 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 403069856 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.473898 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 65759 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 78927 # number of ReadReq MSHR uncacheable system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles -system.l2c.WriteReqNoAck|Writeback_accesses 86614 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.l2c.WriteReqNoAck|Writeback_hits 18299 # number of WriteReqNoAck|Writeback hits -system.l2c.WriteReqNoAck|Writeback_miss_rate 0.788729 # miss rate for WriteReqNoAck|Writeback accesses -system.l2c.WriteReqNoAck|Writeback_misses 68315 # number of WriteReqNoAck|Writeback misses -system.l2c.WriteReqNoAck|Writeback_mshr_miss_rate 0.788729 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.l2c.WriteReqNoAck|Writeback_mshr_misses 68315 # number of WriteReqNoAck|Writeback MSHR misses -system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable +system.l2c.ReadResp_mshr_uncacheable_latency 484683934 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 42802 # number of WriteReq MSHR uncacheable system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.WriteResp_mshr_uncacheable_latency 248118294 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 86706 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 18948 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.781468 # miss rate for Writeback accesses +system.l2c.Writeback_misses 67758 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.781468 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 67758 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs 3278 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.277186 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.avg_refs 1.297661 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 3 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 9834 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 138997 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 89.683271 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency -system.l2c.demand_hits 72568 # number of demand (read+write) hits -system.l2c.demand_miss_latency 5957570 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.477917 # miss rate for demand accesses -system.l2c.demand_misses 66429 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 411544 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.477809 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 66414 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 138762 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 10150.344064 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency +system.l2c.demand_hits 72597 # number of demand (read+write) hits +system.l2c.demand_miss_latency 671597515 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.476824 # miss rate for demand accesses +system.l2c.demand_misses 66165 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 406 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 403069856 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.473898 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 65759 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 225611 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 44.213991 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency +system.l2c.overall_accesses 225468 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 5014.803394 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.l2c.overall_hits 90867 # number of overall hits -system.l2c.overall_miss_latency 5957570 # number of overall miss cycles -system.l2c.overall_miss_rate 0.597240 # miss rate for overall accesses -system.l2c.overall_misses 134744 # number of overall misses -system.l2c.overall_mshr_hits 15 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 411544 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.294374 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 66414 # number of overall MSHR misses +system.l2c.overall_hits 91545 # number of overall hits +system.l2c.overall_miss_latency 671597515 # number of overall miss cycles +system.l2c.overall_miss_rate 0.593978 # miss rate for overall accesses +system.l2c.overall_misses 133923 # number of overall misses +system.l2c.overall_mshr_hits 406 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 403069856 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.291656 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 65759 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 121364 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses 121729 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -941,12 +941,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 101153 # number of replacements -system.l2c.sampled_refs 102177 # Sample count of references to valid blocks. +system.l2c.replacements 100054 # number of replacements +system.l2c.sampled_refs 101078 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1022.647312 # Cycle average of tags in use -system.l2c.total_refs 130499 # Total number of references to valid blocks. -system.l2c.warmup_cycle 31838 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 15786 # number of writebacks +system.l2c.tagsinuse 1023.099242 # Cycle average of tags in use +system.l2c.total_refs 131165 # Total number of references to valid blocks. +system.l2c.warmup_cycle 296156 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 16243 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr index 16580296b..d45294bbb 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -1,74 +1,74 @@ warn: Entering event queue @ 0. Starting simulation... -system.cpu2: completed 10000 read accesses @573559 -system.cpu1: completed 10000 read accesses @574452 -system.cpu4: completed 10000 read accesses @578704 -system.cpu6: completed 10000 read accesses @579414 -system.cpu0: completed 10000 read accesses @588706 -system.cpu5: completed 10000 read accesses @590846 -system.cpu7: completed 10000 read accesses @592958 -system.cpu3: completed 10000 read accesses @604807 -system.cpu2: completed 20000 read accesses @1142209 -system.cpu1: completed 20000 read accesses @1143294 -system.cpu6: completed 20000 read accesses @1150506 -system.cpu4: completed 20000 read accesses @1152288 -system.cpu0: completed 20000 read accesses @1160537 -system.cpu3: completed 20000 read accesses @1175338 -system.cpu5: completed 20000 read accesses @1175648 -system.cpu7: completed 20000 read accesses @1180960 -system.cpu6: completed 30000 read accesses @1716218 -system.cpu3: completed 30000 read accesses @1728281 -system.cpu1: completed 30000 read accesses @1735983 -system.cpu0: completed 30000 read accesses @1736422 -system.cpu2: completed 30000 read accesses @1739692 -system.cpu4: completed 30000 read accesses @1746362 -system.cpu5: completed 30000 read accesses @1766199 -system.cpu7: completed 30000 read accesses @1783424 -system.cpu6: completed 40000 read accesses @2281651 -system.cpu0: completed 40000 read accesses @2300760 -system.cpu3: completed 40000 read accesses @2312993 -system.cpu2: completed 40000 read accesses @2314026 -system.cpu4: completed 40000 read accesses @2332178 -system.cpu1: completed 40000 read accesses @2336380 -system.cpu5: completed 40000 read accesses @2349370 -system.cpu7: completed 40000 read accesses @2365352 -system.cpu6: completed 50000 read accesses @2863317 -system.cpu0: completed 50000 read accesses @2878182 -system.cpu2: completed 50000 read accesses @2884989 -system.cpu3: completed 50000 read accesses @2897940 -system.cpu4: completed 50000 read accesses @2918842 -system.cpu1: completed 50000 read accesses @2929102 -system.cpu5: completed 50000 read accesses @2938269 -system.cpu7: completed 50000 read accesses @2944872 -system.cpu6: completed 60000 read accesses @3435715 -system.cpu2: completed 60000 read accesses @3454809 -system.cpu0: completed 60000 read accesses @3462986 -system.cpu3: completed 60000 read accesses @3485243 -system.cpu4: completed 60000 read accesses @3498361 -system.cpu1: completed 60000 read accesses @3501000 -system.cpu5: completed 60000 read accesses @3516984 -system.cpu7: completed 60000 read accesses @3517323 -system.cpu6: completed 70000 read accesses @4032530 -system.cpu0: completed 70000 read accesses @4041457 -system.cpu2: completed 70000 read accesses @4043695 -system.cpu7: completed 70000 read accesses @4070977 -system.cpu1: completed 70000 read accesses @4075964 -system.cpu4: completed 70000 read accesses @4076518 -system.cpu3: completed 70000 read accesses @4082470 -system.cpu5: completed 70000 read accesses @4104778 -system.cpu0: completed 80000 read accesses @4610101 -system.cpu2: completed 80000 read accesses @4622528 -system.cpu6: completed 80000 read accesses @4627690 -system.cpu1: completed 80000 read accesses @4654033 -system.cpu4: completed 80000 read accesses @4661016 -system.cpu3: completed 80000 read accesses @4662752 -system.cpu7: completed 80000 read accesses @4668924 -system.cpu5: completed 80000 read accesses @4689767 -system.cpu2: completed 90000 read accesses @5186824 -system.cpu0: completed 90000 read accesses @5189006 -system.cpu6: completed 90000 read accesses @5214829 -system.cpu1: completed 90000 read accesses @5229787 -system.cpu3: completed 90000 read accesses @5235400 -system.cpu4: completed 90000 read accesses @5240445 -system.cpu7: completed 90000 read accesses @5254426 -system.cpu5: completed 90000 read accesses @5292462 -system.cpu2: completed 100000 read accesses @5755736 +system.cpu7: completed 10000 read accesses @8253930 +system.cpu1: completed 10000 read accesses @8325085 +system.cpu6: completed 10000 read accesses @8427313 +system.cpu4: completed 10000 read accesses @8438233 +system.cpu2: completed 10000 read accesses @8458126 +system.cpu5: completed 10000 read accesses @8549800 +system.cpu3: completed 10000 read accesses @8559995 +system.cpu0: completed 10000 read accesses @8593654 +system.cpu7: completed 20000 read accesses @16744182 +system.cpu1: completed 20000 read accesses @16774744 +system.cpu4: completed 20000 read accesses @16786220 +system.cpu3: completed 20000 read accesses @16787358 +system.cpu5: completed 20000 read accesses @16795808 +system.cpu6: completed 20000 read accesses @16836913 +system.cpu2: completed 20000 read accesses @17031052 +system.cpu0: completed 20000 read accesses @17126654 +system.cpu5: completed 30000 read accesses @24892576 +system.cpu6: completed 30000 read accesses @24903300 +system.cpu3: completed 30000 read accesses @24935860 +system.cpu4: completed 30000 read accesses @25020642 +system.cpu1: completed 30000 read accesses @25031726 +system.cpu7: completed 30000 read accesses @25112091 +system.cpu2: completed 30000 read accesses @25235960 +system.cpu0: completed 30000 read accesses @25505209 +system.cpu5: completed 40000 read accesses @33191203 +system.cpu6: completed 40000 read accesses @33273684 +system.cpu4: completed 40000 read accesses @33345526 +system.cpu3: completed 40000 read accesses @33406412 +system.cpu7: completed 40000 read accesses @33509130 +system.cpu1: completed 40000 read accesses @33509218 +system.cpu2: completed 40000 read accesses @33664822 +system.cpu0: completed 40000 read accesses @33869626 +system.cpu5: completed 50000 read accesses @41488848 +system.cpu4: completed 50000 read accesses @41582702 +system.cpu7: completed 50000 read accesses @41828988 +system.cpu3: completed 50000 read accesses @41829496 +system.cpu1: completed 50000 read accesses @41849534 +system.cpu6: completed 50000 read accesses @41982608 +system.cpu2: completed 50000 read accesses @42197798 +system.cpu0: completed 50000 read accesses @42443468 +system.cpu5: completed 60000 read accesses @49751344 +system.cpu4: completed 60000 read accesses @49783100 +system.cpu1: completed 60000 read accesses @49918062 +system.cpu7: completed 60000 read accesses @49929008 +system.cpu3: completed 60000 read accesses @50173996 +system.cpu6: completed 60000 read accesses @50351766 +system.cpu2: completed 60000 read accesses @50352657 +system.cpu0: completed 60000 read accesses @50789771 +system.cpu4: completed 70000 read accesses @58352386 +system.cpu5: completed 70000 read accesses @58394758 +system.cpu7: completed 70000 read accesses @58570698 +system.cpu1: completed 70000 read accesses @58764169 +system.cpu3: completed 70000 read accesses @58764648 +system.cpu2: completed 70000 read accesses @58921714 +system.cpu6: completed 70000 read accesses @58929984 +system.cpu0: completed 70000 read accesses @59567320 +system.cpu1: completed 80000 read accesses @67092786 +system.cpu5: completed 80000 read accesses @67153667 +system.cpu4: completed 80000 read accesses @67153760 +system.cpu7: completed 80000 read accesses @67207042 +system.cpu3: completed 80000 read accesses @67238507 +system.cpu2: completed 80000 read accesses @67633112 +system.cpu6: completed 80000 read accesses @67664637 +system.cpu0: completed 80000 read accesses @68437288 +system.cpu1: completed 90000 read accesses @75679048 +system.cpu4: completed 90000 read accesses @75680280 +system.cpu7: completed 90000 read accesses @75751053 +system.cpu5: completed 90000 read accesses @75781514 +system.cpu3: completed 90000 read accesses @75844118 +system.cpu2: completed 90000 read accesses @76346671 +system.cpu6: completed 90000 read accesses @76491728 +system.cpu0: completed 90000 read accesses @77376872 +system.cpu1: completed 100000 read accesses @84350509 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 3d3289d71..fb8e47d20 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 6 2007 20:30:01 -M5 started Tue Feb 6 21:04:07 2007 -M5 executing on vm1 +M5 compiled May 14 2007 16:35:50 +M5 started Tue May 15 12:18:46 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional @@ -15,4 +15,5 @@ warning: overwriting port funcmem.functional value cpu3.functional with cpu4.fun warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional -Exiting @ tick 5755736 because Maximum number of loads reached! +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 84350509 because Maximum number of loads reached! diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 2750dd3c0..57b643510 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -1,11 +1,7 @@ [root] type=Root children=drivesys etherdump etherlink testsys -checkpoint= -clock=1000000000000 -max_tick=0 -output_file=cout -progress_interval=0 +dummy=0 [drivesys] type=LinuxAlphaSystem @@ -18,16 +14,21 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/tmp/newmem/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 [drivesys.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=drivesys.iobus.port[0] side_b=drivesys.membus.port[0] @@ -110,6 +111,7 @@ sys=drivesys [drivesys.iobus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=true @@ -120,6 +122,7 @@ port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pi [drivesys.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=1000 responder_set=false @@ -214,8 +217,10 @@ dma_read_delay=0 dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 -hardware_address=00:90:00:00:00:02 +hardware_address=00:90:00:00:00:01 intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 @@ -588,6 +593,8 @@ children=configdata config_latency=20000 configdata=drivesys.tsunami.ide.configdata disks=drivesys.disk0 drivesys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 @@ -697,16 +704,21 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 [testsys.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=testsys.iobus.port[0] side_b=testsys.membus.port[0] @@ -789,6 +801,7 @@ sys=testsys [testsys.iobus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=true @@ -799,6 +812,7 @@ port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio t [testsys.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=1000 responder_set=false @@ -895,6 +909,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:02 intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 @@ -1267,6 +1283,8 @@ children=configdata config_latency=20000 configdata=testsys.tsunami.ide.configdata disks=testsys.disk0 testsys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out index c422f07ac..613664aec 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -1,9 +1,6 @@ [root] type=Root -clock=1000000000000 -max_tick=0 -progress_interval=0 -output_file=cout +dummy=0 [testsys.physmem] type=PhysicalMemory @@ -21,7 +18,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/tmp/newmem/configs/boot/netperf-stream-client.rcS symbolfile= init_param=0 system_type=34 @@ -33,6 +30,7 @@ bus_id=1 clock=1000 width=64 responder_set=false +block_size=64 [testsys.intrctrl] type=IntrControl @@ -60,10 +58,15 @@ system=testsys [testsys.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [testsys.disk0.image.child] type=RawDiskImage @@ -482,6 +485,8 @@ BAR5Size=0 type=NSGigE system=testsys platform=testsys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=testsys.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -604,6 +609,8 @@ BAR5Size=0 type=IdeController system=testsys platform=testsys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=testsys.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -618,6 +625,7 @@ bus_id=0 clock=1000 width=64 responder_set=true +block_size=64 [drivesys.physmem] type=PhysicalMemory @@ -635,7 +643,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/tmp/newmem/configs/boot/netperf-server.rcS symbolfile= init_param=0 system_type=34 @@ -689,6 +697,8 @@ BAR5Size=0 type=NSGigE system=drivesys platform=drivesys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=drivesys.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -709,7 +719,7 @@ tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true -hardware_address=00:90:00:00:00:02 +hardware_address=00:90:00:00:00:01 rx_thread=false tx_thread=false rss=false @@ -739,6 +749,7 @@ bus_id=1 clock=1000 width=64 responder_set=false +block_size=64 [drivesys.membus.responder] type=IsaFake @@ -757,10 +768,15 @@ system=drivesys [drivesys.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [drivesys.disk0.image.child] type=RawDiskImage @@ -1232,6 +1248,8 @@ BAR5Size=0 type=IdeController system=drivesys platform=drivesys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=drivesys.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -1246,4 +1264,5 @@ bus_id=0 clock=1000 width=64 responder_set=true +block_size=64 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 585dfef42..1a834ab03 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -2,15 +2,15 @@ ---------- Begin Simulation Statistics ---------- drivesys.cpu.dtb.accesses 401302 # DTB accesses drivesys.cpu.dtb.acv 40 # DTB access violations -drivesys.cpu.dtb.hits 624298 # DTB hits +drivesys.cpu.dtb.hits 624235 # DTB hits drivesys.cpu.dtb.misses 569 # DTB misses drivesys.cpu.dtb.read_accesses 268057 # DTB read accesses drivesys.cpu.dtb.read_acv 30 # DTB read access violations -drivesys.cpu.dtb.read_hits 393538 # DTB read hits +drivesys.cpu.dtb.read_hits 393500 # DTB read hits drivesys.cpu.dtb.read_misses 487 # DTB read misses drivesys.cpu.dtb.write_accesses 133245 # DTB write accesses drivesys.cpu.dtb.write_acv 10 # DTB write access violations -drivesys.cpu.dtb.write_hits 230760 # DTB write hits +drivesys.cpu.dtb.write_hits 230735 # DTB write hits drivesys.cpu.dtb.write_misses 82 # DTB write misses drivesys.cpu.idle_fraction 1.000000 # Percentage of idle cycles drivesys.cpu.itb.accesses 1337980 # ITB accesses @@ -39,12 +39,11 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199572064521 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199571744558 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks 199572412849 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199572093137 100.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_31 300713 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_used 0.618707 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl @@ -55,13 +54,13 @@ drivesys.cpu.kern.mode_good_idle 3 drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches -drivesys.cpu.kern.mode_switch_good 0.440882 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good 1.645945 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks_kernel 263475 0.24% 0.24% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 106485080 98.57% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 1278343 1.16% 1.40% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 108485080 98.60% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed drivesys.cpu.kern.syscall 22 # number of syscalls executed drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed @@ -77,9 +76,9 @@ drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # nu drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles -drivesys.cpu.numCycles 1959205 # number of cpu cycles simulated -drivesys.cpu.num_insts 1958989 # Number of instructions executed -drivesys.cpu.num_refs 626286 # Number of memory references +drivesys.cpu.numCycles 1958954 # number of cpu cycles simulated +drivesys.cpu.num_insts 1958738 # Number of instructions executed +drivesys.cpu.num_refs 626223 # Number of memory references drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -101,9 +100,9 @@ drivesys.tsunami.ethernet.coalescedTotal 1 # av drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -drivesys.tsunami.ethernet.descDMAReads 5 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 4 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 120 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped drivesys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU @@ -131,7 +130,7 @@ drivesys.tsunami.ethernet.totalRxOk 0 # to drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -drivesys.tsunami.ethernet.totalTxIdle 5 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 4 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s) drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted @@ -140,78 +139,77 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 65873683 # Simulator instruction rate (inst/s) -host_mem_usage 463096 # Number of bytes of host memory used -host_seconds 4.19 # Real time elapsed on the host -host_tick_rate 47718011872 # Simulator tick rate (ticks/s) +host_inst_rate 36401739 # Simulator instruction rate (inst/s) +host_mem_usage 388436 # Number of bytes of host memory used +host_seconds 7.51 # Real time elapsed on the host +host_tick_rate 26633033203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 276082930 # Number of instructions simulated +sim_insts 273348482 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses testsys.cpu.dtb.acv 161 # DTB access violations -testsys.cpu.dtb.hits 1163399 # DTB hits +testsys.cpu.dtb.hits 1163322 # DTB hits testsys.cpu.dtb.misses 3815 # DTB misses testsys.cpu.dtb.read_accesses 225414 # DTB read accesses testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_hits 658556 # DTB read hits +testsys.cpu.dtb.read_hits 658456 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.write_accesses 109988 # DTB write accesses testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_hits 504843 # DTB write hits +testsys.cpu.dtb.write_hits 504866 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles -testsys.cpu.itb.accesses 1249804 # ITB accesses +testsys.cpu.itb.accesses 1249851 # ITB accesses testsys.cpu.itb.acv 69 # ITB acv -testsys.cpu.itb.hits 1248307 # ITB hits +testsys.cpu.itb.hits 1248354 # ITB hits testsys.cpu.itb.misses 1497 # ITB misses -testsys.cpu.kern.callpal 13124 # number of callpals executed -testsys.cpu.kern.callpal_swpctx 440 3.35% 3.35% # number of callpals executed -testsys.cpu.kern.callpal_tbi 20 0.15% 3.51% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11075 84.39% 87.89% # number of callpals executed -testsys.cpu.kern.callpal_rdps 359 2.74% 90.63% # number of callpals executed -testsys.cpu.kern.callpal_wrusp 3 0.02% 90.65% # number of callpals executed +testsys.cpu.kern.callpal 13125 # number of callpals executed +testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed +testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11077 84.40% 87.89% # number of callpals executed +testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed +testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed -testsys.cpu.kern.callpal_rti 1040 7.92% 98.60% # number of callpals executed +testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 19054 # number of hwrei instructions executed -testsys.cpu.kern.inst.quiesce 377 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12503 # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_21 183 1.46% 41.94% # number of times we switched to this ipl +testsys.cpu.kern.inst.hwrei 19056 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed +testsys.cpu.kern.ipl_count 12507 # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_0 5061 40.47% 40.47% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_21 184 1.47% 41.94% # number of times we switched to this ipl testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7054 56.42% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_good 10498 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_count_31 7057 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_21 183 1.74% 49.90% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199569923816 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199569308246 100.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_21 30857 0.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks 199570420798 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199569805534 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 567083 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used 0.839638 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_ticks_31 566608 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.mode_good_kernel 654 -testsys.cpu.kern.mode_good_user 649 +testsys.cpu.kern.ipl_used_31 0.716310 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good_kernel 655 +testsys.cpu.kern.mode_good_user 650 testsys.cpu.kern.mode_good_idle 5 testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches -testsys.cpu.kern.mode_switch_good 0.614085 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel 0.594545 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_user 650 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 380 # number of protection mode switches +testsys.cpu.kern.mode_switch_good 1.608612 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.595455 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1821166 2.16% 2.16% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 81403516 96.58% 100.00% # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 440 # number of times the context was actually changed +testsys.cpu.kern.mode_switch_good_idle 0.013158 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 1822940 2.12% 2.12% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065616 1.24% 3.36% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 83000460 96.64% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.cpu.kern.syscall 83 # number of syscalls executed testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed @@ -235,9 +233,9 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 3566149 # number of cpu cycles simulated -testsys.cpu.num_insts 3564583 # Number of instructions executed -testsys.cpu.num_refs 1173698 # Number of memory references +testsys.cpu.numCycles 3566060 # number of cpu cycles simulated +testsys.cpu.num_insts 3564494 # Number of instructions executed +testsys.cpu.num_refs 1173605 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -259,9 +257,9 @@ testsys.tsunami.ethernet.coalescedTotal 1 # av testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -testsys.tsunami.ethernet.descDMAReads 8 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 192 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped testsys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU @@ -289,7 +287,7 @@ testsys.tsunami.ethernet.totalRxOk 0 # to testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -testsys.tsunami.ethernet.totalTxIdle 8 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 6 # total number of TxIdle written to ISR testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s) testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted @@ -357,10 +355,10 @@ drivesys.tsunami.ethernet.coalescedRxIdle <err: div-0> # a drivesys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post drivesys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -drivesys.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.coalescedTxDesc no value # average number of TxDesc's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxOk no value # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -383,12 +381,12 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 145844125726 # Simulator instruction rate (inst/s) -host_mem_usage 463096 # Number of bytes of host memory used +host_inst_rate 79025291125 # Simulator instruction rate (inst/s) +host_mem_usage 388436 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 385283333 # Simulator tick rate (ticks/s) +host_tick_rate 211511841 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 276082930 # Number of instructions simulated +sim_insts 273348482 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses @@ -446,10 +444,10 @@ testsys.tsunami.ethernet.coalescedRxIdle <err: div-0> # av testsys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post testsys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -testsys.tsunami.ethernet.coalescedTotal no value # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.coalescedTxDesc no value # average number of TxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.coalescedTxOk no value # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr index 0be24123b..045c1ddf7 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr @@ -1,8 +1,6 @@ - 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3456 - 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Listening for console connection on port 3457 -0: testsys.remote_gdb.listener: listening for remote gdb #0 on port 7000 -0: drivesys.remote_gdb.listener: listening for remote gdb #1 on port 7001 +Listening for testsys connection on port 3456 +Listening for drivesys connection on port 3458 +0: testsys.remote_gdb.listener: listening for remote gdb on port 7000 +0: drivesys.remote_gdb.listener: listening for remote gdb on port 7003 warn: Entering event queue @ 0. Starting simulation... warn: Obsolete M5 instruction ivlb encountered. diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index e529ca1ae..4f93fd528 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,10 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 25 2007 15:05:30 -M5 started Thu Jan 25 15:12:40 2007 -M5 executing on zeep -command line: /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/m5.opt -d /n/zeep/y/binkertn/build/rtc/build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -Resetting stats at cycle 4093398828093! -Resetting stats at cycle 4293399617561! -Exiting @ tick 4293400403539 because checkpoint +M5 compiled May 15 2007 19:06:05 +M5 started Tue May 15 19:12:37 2007 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 4300235844056 because checkpoint |