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author | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-16 05:49:31 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-16 05:49:31 -0400 |
commit | a63ba6c7b7fe6620478c0d8d7812661c6a36d55a (patch) | |
tree | 4a0a18fc30f5402dab1833a7166d4f231f4d57e6 /tests | |
parent | 1efe42fa97ed03662666cafee1b9dec9dfe524e9 (diff) | |
download | gem5-a63ba6c7b7fe6620478c0d8d7812661c6a36d55a.tar.xz |
stats: Small bump of trailing stats
Somehow these seem to have been missed.
Diffstat (limited to 'tests')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 14 | ||||
-rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 12 |
2 files changed, 13 insertions, 13 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 9ab6b9d66..5b52389f0 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.125902 # Nu sim_ticks 5125902116500 # Number of ticks simulated final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125787 # Simulator instruction rate (inst/s) -host_op_rate 248644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1580293827 # Simulator tick rate (ticks/s) -host_mem_usage 793336 # Number of bytes of host memory used -host_seconds 3243.64 # Real time elapsed on the host +host_inst_rate 254798 # Simulator instruction rate (inst/s) +host_op_rate 503662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3201100243 # Simulator tick rate (ticks/s) +host_mem_usage 749084 # Number of bytes of host memory used +host_seconds 1601.29 # Real time elapsed on the host sim_insts 408006726 # Number of instructions simulated sim_ops 806511598 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -773,8 +773,8 @@ system.cpu.iew.iewIQFullEvents 416093 # Nu system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 536897 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1052437 # Number of branch mispredicts detected at execute +system.cpu.iew.predictedNotTakenIncorrect 536896 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1052436 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 1477345 # Number of squashed instructions skipped in execute diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index b27ae5a40..b4b37847e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.407884 # Nu sim_ticks 407883784500 # Number of ticks simulated final_tick 407883784500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65117 # Simulator instruction rate (inst/s) -host_op_rate 80168 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41458433 # Simulator tick rate (ticks/s) -host_mem_usage 2600432 # Number of bytes of host memory used -host_seconds 9838.38 # Real time elapsed on the host +host_inst_rate 135225 # Simulator instruction rate (inst/s) +host_op_rate 166480 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 86093843 # Simulator tick rate (ticks/s) +host_mem_usage 2533572 # Number of bytes of host memory used +host_seconds 4737.67 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -420,7 +420,7 @@ system.cpu.numCycles 815767570 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 84062545 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200075862 # Number of instructions fetch has processed +system.cpu.fetch.Insts 1200075863 # Number of instructions fetch has processed system.cpu.fetch.Branches 233961455 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 133292629 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 716015819 # Number of cycles fetch has run and was not squashing or blocked |