config: Move the memory instantiation outside FSConfig

This patch moves the instantiation of the memory controller outside
FSConfig and instead relies on the mem_ranges to pass the information
to the caller (e.g. fs.py or one of the regression scripts). The main
motivation for this change is to expose the structural composition of
the memory system and allow more tuning and configuration without
adding a large number of options to the makeSystem functions.

The patch updates the relevant example scripts to maintain the current
functionality. As the order that ports are connected to the memory bus
changes (in certain regresisons), some bus stats are shuffled
around. For example, what used to be layer 0 is now layer 1.

Going forward, options will be added to support the addition of
multi-channel memory controllers.

33 files changed, 76 insertions, 16 deletions

diff --git a/tests/configs/alpha_generic.py b/tests/configs/alpha_generic.py
index f7a4166be..a4ebba54d 100644
--- a/tests/configs/alpha_generic.py
+++ b/tests/configs/alpha_generic.py
@@ -59,7 +59,7 @@ class LinuxAlphaSystemBuilder(object):
         pass
 
     def create_system(self):
-        system = FSConfig.makeLinuxAlphaSystem(self.mem_mode, DDR3_1600_x64)
+        system = FSConfig.makeLinuxAlphaSystem(self.mem_mode)
         self.init_system(system)
         return system
 
diff --git a/tests/configs/arm_generic.py b/tests/configs/arm_generic.py
index 0cf170a9b..ada49ba97 100644
--- a/tests/configs/arm_generic.py
+++ b/tests/configs/arm_generic.py
@@ -60,9 +60,7 @@ class LinuxArmSystemBuilder(object):
 
     def create_system(self):
         system = FSConfig.makeArmSystem(self.mem_mode,
-                                        self.machine_type,
-                                        DDR3_1600_x64,
-                                        None, False)
+                                        self.machine_type, None, False)
 
         # We typically want the simulator to panic if the kernel
         # panics or oopses. This prevents the simulator from running
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index 16620c4dd..d93be0d1b 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -221,6 +221,14 @@ class BaseFSSystem(BaseSystem):
     def init_system(self, system):
         BaseSystem.init_system(self, system)
 
+        # create the memory controllers and connect them, stick with
+        # the physmem name to avoid bumping all the reference stats
+        system.physmem = [self.mem_class(range = r,
+                                         conf_table_reported = True)
+                          for r in system.mem_ranges]
+        for i in xrange(len(system.physmem)):
+            system.physmem[i].port = system.membus.master
+
         # create the iocache, which by default runs at the system clock
         system.iocache = IOCache(addr_ranges=system.mem_ranges)
         system.iocache.cpu_side = system.iobus.master
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 3261ba3ff..a0500458a 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -91,6 +91,8 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
 for cpu in cpus:
     cpu.clk_domain = system.cpu_clk_domain
 
+system.mem_ranges = AddrRange('256MB')
+
 Ruby.create_system(options, system)
 
 # Create a separate clock domain for Ruby
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index 6020478a0..ed21a9f38 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -39,4 +39,5 @@ from m5.objects import *
 from x86_generic import *
 
 root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=DerivO3CPU).create_root()
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index ce6aa0616..94a06ed6f 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -39,4 +39,5 @@ from m5.objects import *
 from x86_generic import *
 
 root = LinuxX86FSSystemUniprocessor(mem_mode='atomic',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=AtomicSimpleCPU).create_root()
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index e0ef72db9..7fd9c0b5f 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -55,7 +55,7 @@ options.num_cpus = 2
 
 #the system
 mdesc = SysConfig(disk = 'linux-x86.img')
-system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
+system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
                                      mdesc=mdesc, Ruby=True)
 
 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
@@ -84,5 +84,11 @@ for (i, cpu) in enumerate(system.cpu):
     # Set access_phys_mem to True for ruby port
     system.ruby._cpu_ruby_ports[i].access_phys_mem = True
 
+system.physmem = [DDR3_1600_x64(range = r,
+                                conf_table_reported = True)
+                  for r in system.mem_ranges]
+for i in xrange(len(system.physmem)):
+    system.physmem[i].port = system.piobus.master
+
 root = Root(full_system = True, system = system)
 m5.ticks.setGlobalFrequency('1THz')
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index e8d73a249..45fff460e 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -39,5 +39,6 @@ from m5.objects import *
 from x86_generic import *
 
 root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=TimingSimpleCPU).create_root()
 
diff --git a/tests/configs/pc-switcheroo-full.py b/tests/configs/pc-switcheroo-full.py
index c94987638..ccae0cc76 100644
--- a/tests/configs/pc-switcheroo-full.py
+++ b/tests/configs/pc-switcheroo-full.py
@@ -42,6 +42,7 @@ from x86_generic import *
 import switcheroo
 
 root = LinuxX86FSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
     ).create_root()
 
diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py
index 3f252bf2c..6c930e759 100644
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -39,5 +39,6 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=DerivO3CPU,
                                     checker=True).create_root()
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 56e6aee73..b686acced 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -38,5 +38,7 @@
 from m5.objects import *
 from arm_generic import *
 
-root = LinuxArmFSSystem(mem_mode='timing', cpu_class=DerivO3CPU,
+root = LinuxArmFSSystem(mem_mode='timing',
+                        mem_class=DDR3_1600_x64,
+                        cpu_class=DerivO3CPU,
                         num_cpus=2).create_root()
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index 99f8ea3dc..b8580a3a2 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -39,4 +39,5 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=DerivO3CPU).create_root()
diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index 64ddf0595..0d6b11cf6 100644
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -38,5 +38,7 @@
 from m5.objects import *
 from arm_generic import *
 
-root = LinuxArmFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
+root = LinuxArmFSSystem(mem_mode='atomic',
+                        mem_class=DDR3_1600_x64,
+                        cpu_class=AtomicSimpleCPU,
                         num_cpus=2).create_root()
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 866a13395..a440de291 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -39,5 +39,6 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='atomic',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=AtomicSimpleCPU).create_root()
 
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index 86efd4c1a..1744f4af0 100644
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -38,5 +38,7 @@
 from m5.objects import *
 from arm_generic import *
 
-root = LinuxArmFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
+root = LinuxArmFSSystem(mem_mode='timing',
+                        mem_class=DDR3_1600_x64,
+                        cpu_class=TimingSimpleCPU,
                         num_cpus=2).create_root()
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 9ff8b33e0..f73823d30 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -39,4 +39,5 @@ from m5.objects import *
 from arm_generic import *
 
 root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+                                    mem_class=DDR3_1600_x64,
                                     cpu_class=TimingSimpleCPU).create_root()
diff --git a/tests/configs/realview-switcheroo-atomic.py b/tests/configs/realview-switcheroo-atomic.py
index 880162527..bab11ebe6 100644
--- a/tests/configs/realview-switcheroo-atomic.py
+++ b/tests/configs/realview-switcheroo-atomic.py
@@ -40,6 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(AtomicSimpleCPU, AtomicSimpleCPU)
     ).create_root()
 
diff --git a/tests/configs/realview-switcheroo-full.py b/tests/configs/realview-switcheroo-full.py
index 091357114..3467eb4c9 100644
--- a/tests/configs/realview-switcheroo-full.py
+++ b/tests/configs/realview-switcheroo-full.py
@@ -40,6 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
     ).create_root()
 
diff --git a/tests/configs/realview-switcheroo-o3.py b/tests/configs/realview-switcheroo-o3.py
index 6079402e2..864e0cfd4 100644
--- a/tests/configs/realview-switcheroo-o3.py
+++ b/tests/configs/realview-switcheroo-o3.py
@@ -40,6 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(DerivO3CPU, DerivO3CPU)
     ).create_root()
 
diff --git a/tests/configs/realview-switcheroo-timing.py b/tests/configs/realview-switcheroo-timing.py
index 2329de6b0..ff09b7f26 100644
--- a/tests/configs/realview-switcheroo-timing.py
+++ b/tests/configs/realview-switcheroo-timing.py
@@ -40,6 +40,7 @@ from arm_generic import *
 import switcheroo
 
 root = LinuxArmFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(TimingSimpleCPU, TimingSimpleCPU)
     ).create_root()
 
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 1553e29f4..d2809f2a2 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -80,6 +80,8 @@ tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
 system = System(tester = tester, physmem = SimpleMemory(null = True),
                 clk_domain = SrcClockDomain(clock = options.sys_clock))
 
+system.mem_ranges = AddrRange('256MB')
+
 Ruby.create_system(options, system)
 
 # Create a separate clock domain for Ruby
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 27d56a31d..ce155c23c 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -74,6 +74,8 @@ system = System(cpu = cpu, physmem = SimpleMemory(null = True),
 # CPUs frequency
 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
 
+system.mem_ranges = AddrRange('256MB')
+
 Ruby.create_system(options, system)
 
 # Create a separate clock for Ruby
diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index c0744a6a2..64c3dc408 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -31,7 +31,7 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 import FSConfig
 
-system = FSConfig.makeSparcSystem('atomic', SimpleMemory)
+system = FSConfig.makeSparcSystem('atomic')
 system.clk_domain = SrcClockDomain(clock = '1GHz')
 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz')
 cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
@@ -40,6 +40,14 @@ system.cpu = cpu
 cpu.createInterruptController()
 cpu.connectAllPorts(system.membus)
 
+# create the memory controllers and connect them, stick with
+# the physmem name to avoid bumping all the reference stats
+system.physmem = [SimpleMemory(range = r,
+                               conf_table_reported = True)
+                  for r in system.mem_ranges]
+for i in xrange(len(system.physmem)):
+    system.physmem[i].port = system.membus.master
+
 root = Root(full_system=True, system=system)
 
 m5.ticks.setGlobalFrequency('2GHz')
diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index 102c5a8d2..9f052527f 100644
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -39,4 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
+                                      mem_class=DDR3_1600_x64,
                                       cpu_class=InOrderCPU).create_root()
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index d7964b4d8..b50cda557 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -38,5 +38,7 @@
 from m5.objects import *
 from alpha_generic import *
 
-root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=DerivO3CPU,
+root = LinuxAlphaFSSystem(mem_mode='timing',
+                          mem_class=DDR3_1600_x64,
+                          cpu_class=DerivO3CPU,
                           num_cpus=2).create_root()
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index 2c782e2cc..dbbc75e1c 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -39,4 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
+                                      mem_class=DDR3_1600_x64,
                                       cpu_class=DerivO3CPU).create_root()
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 36dc8133b..9f827d9d9 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -38,5 +38,7 @@
 from m5.objects import *
 from alpha_generic import *
 
-root = LinuxAlphaFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
+root = LinuxAlphaFSSystem(mem_mode='atomic',
+                          mem_class=DDR3_1600_x64,
+                          cpu_class=AtomicSimpleCPU,
                           num_cpus=2).create_root()
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index be8e93a18..8c486204c 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -39,4 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='atomic',
+                                      mem_class=DDR3_1600_x64,
                                       cpu_class=AtomicSimpleCPU).create_root()
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 2ca280f06..5b8a99ca6 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -38,5 +38,7 @@
 from m5.objects import *
 from alpha_generic import *
 
-root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
+root = LinuxAlphaFSSystem(mem_mode='timing',
+                          mem_class=DDR3_1600_x64,
+                          cpu_class=TimingSimpleCPU,
                           num_cpus=2).create_root()
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 27cb679b8..082f79d1e 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -39,4 +39,5 @@ from m5.objects import *
 from alpha_generic import *
 
 root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
+                                      mem_class=DDR3_1600_x64,
                                       cpu_class=TimingSimpleCPU).create_root()
diff --git a/tests/configs/tsunami-switcheroo-full.py b/tests/configs/tsunami-switcheroo-full.py
index d2be0ebfa..121e669b4 100644
--- a/tests/configs/tsunami-switcheroo-full.py
+++ b/tests/configs/tsunami-switcheroo-full.py
@@ -40,6 +40,7 @@ from alpha_generic import *
 import switcheroo
 
 root = LinuxAlphaFSSwitcheroo(
+    mem_class=DDR3_1600_x64,
     cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU)
     ).create_root()
 
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index 22c6686ae..b69e35517 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -32,8 +32,8 @@ m5.util.addToPath('../configs/common')
 from FSConfig import *
 from Benchmarks import *
 
-test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
-                                 SysConfig('netperf-stream-client.rcS'))
+test_sys = makeLinuxAlphaSystem('atomic',
+                                SysConfig('netperf-stream-client.rcS'))
 
 # Create the system clock domain
 test_sys.clk_domain = SrcClockDomain(clock = '1GHz')
@@ -57,7 +57,10 @@ test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
 test_sys.iobridge.slave = test_sys.iobus.master
 test_sys.iobridge.master = test_sys.membus.slave
 
-drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
+test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0])
+test_sys.physmem.port = test_sys.membus.master
+
+drive_sys = makeLinuxAlphaSystem('atomic',
                                  SysConfig('netperf-server.rcS'))
 # Create the system clock domain
 drive_sys.clk_domain = SrcClockDomain(clock = '1GHz')
@@ -77,6 +80,9 @@ drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
 drive_sys.iobridge.slave = drive_sys.iobus.master
 drive_sys.iobridge.master = drive_sys.membus.slave
 
+drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0])
+drive_sys.physmem.port = drive_sys.membus.master
+
 root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
 
 maxtick = 199999999
diff --git a/tests/configs/x86_generic.py b/tests/configs/x86_generic.py
index be28ba687..d30087df1 100644
--- a/tests/configs/x86_generic.py
+++ b/tests/configs/x86_generic.py
@@ -58,7 +58,6 @@ class LinuxX86SystemBuilder(object):
     def create_system(self):
         mdesc = SysConfig(disk = 'linux-x86.img')
         system = FSConfig.makeLinuxX86System(self.mem_mode,
-                                             DDR3_1600_x64,
                                              numCPUs=self.num_cpus,
                                              mdesc=mdesc)
         system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')