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authorAndreas Hansson <andreas.hansson@arm.com>2013-01-07 13:05:38 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2013-01-07 13:05:38 -0500
commite65de3f5ca1d1a91265d09b1950a2d69c620631b (patch)
tree032c2483fde6e6c79e79495862f7ee5dd490ffd9 /tests
parent15a979c6be704a4bb083b64148d1a25d7fc4e682 (diff)
downloadgem5-e65de3f5ca1d1a91265d09b1950a2d69c620631b.tar.xz
config: Do not use hardcoded physmem in fs script
This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge. The change is needed to allow interleaved memory controllers in the system.
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/base_config.py2
-rw-r--r--tests/configs/twosys-tsunami-simple-atomic.py4
2 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index 3efbe46fb..945bcb495 100644
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -147,7 +147,7 @@ class BaseFSSystem(BaseSystem):
BaseSystem.init_system(self, system)
#create the iocache
- system.iocache = IOCache(clock='1GHz', addr_ranges=[system.physmem.range])
+ system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges)
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index 71b139787..dbfcaaafe 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -42,7 +42,7 @@ test_sys.cpu.clock = '2GHz'
# In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses
# from masters on the IO bus to the memory bus
-test_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')])
+test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
@@ -53,7 +53,7 @@ drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
drive_sys.cpu.clock = '4GHz'
-drive_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')])
+drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave