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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-15 11:53:35 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-15 11:53:35 -0500 |
| commit | 147095cb0886a962620e60b6950a68931fbd734a (patch) | |
| tree | b81211a4e2441c897149b4823506a60f49966a79 /tests | |
| parent | 69ef57fd0f226af90faf46ac877343b5493df693 (diff) | |
| download | gem5-147095cb0886a962620e60b6950a68931fbd734a.tar.xz | |
Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
Prefetch requests issued from the L2 or below wouldn't check if valid data is
present higher in the system. If a prefetch into the L2 occured at the same
time as writeback from a higher-level cache the dirty data could be replaced
in by unmodified data in memory.
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions