diff options
| author | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2009-04-22 10:25:17 -0700 |
| commit | 567cab685965e4e627ac1541a9fdacb93fd6e5fe (patch) | |
| tree | d79f8cfd677dfc314ccb48630b77785412a9f1bd /tests | |
| parent | ca3d82b38ab92114f5056a35bacf0dceb8b6d4a6 (diff) | |
| download | gem5-567cab685965e4e627ac1541a9fdacb93fd6e5fe.tar.xz | |
stats: update reference outputs now that compatibility is gone
Because of the initialization bug, it wasn't consistent anyway.
Diffstat (limited to 'tests')
94 files changed, 4390 insertions, 4421 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 9ba264ef1..34e6ec7b4 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:09:58 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:30 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 090a41f44..c6d7a6e70 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 211142 # Simulator instruction rate (inst/s) -host_mem_usage 204372 # Number of bytes of host memory used -host_seconds 2678.54 # Real time elapsed on the host -host_tick_rate 62376647 # Simulator tick rate (ticks/s) +host_inst_rate 310118 # Simulator instruction rate (inst/s) +host_mem_usage 206072 # Number of bytes of host memory used +host_seconds 1823.67 # Real time elapsed on the host +host_tick_rate 91616419 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.167078 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 1692219 # Nu system.cpu.commit.COM:branches 62547159 # Number of branches committed system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 322711250 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 108088758 3349.40% - 1 100475751 3113.49% - 2 37367184 1157.91% - 3 9733028 301.60% - 4 10676883 330.85% - 5 22147835 686.31% - 6 13251874 410.64% - 7 3269687 101.32% - 8 17700250 548.49% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 322711250 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 108088758 33.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 100475751 31.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 37367184 11.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 9733028 3.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 10676883 3.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 22147835 6.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 13251874 4.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 3269687 1.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 17700250 5.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 322711250 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.865001 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.301723 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed system.cpu.commit.COM:loads 115049510 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -71,13 +73,13 @@ system.cpu.dcache.WriteReq_mshr_hits 1992407 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6922.723577 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21318.181818 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 123 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 851495 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 234500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency @@ -96,7 +98,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 149415339 # number of overall hits system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses @@ -149,21 +151,23 @@ system.cpu.fetch.branchRate 0.227555 # Nu system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 332581112 -system.cpu.fetch.rateDist.min_value 0 - 0 201466223 6057.66% - 1 10360747 311.53% - 2 15882081 477.54% - 3 14599006 438.96% - 4 12362950 371.73% - 5 14822134 445.67% - 6 6008311 180.66% - 7 3307530 99.45% - 8 53772130 1616.81% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 332581112 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 201466223 60.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 10360747 3.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 15882081 4.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 14599006 4.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 12362950 3.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 14822134 4.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 6008311 1.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 3307530 0.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53772130 16.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 332581112 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.101334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.065263 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency @@ -175,13 +179,13 @@ system.cpu.icache.ReadReq_mshr_hits 267 # nu system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency @@ -200,7 +204,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 66013237 # number of overall hits system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses @@ -263,58 +267,54 @@ system.cpu.iew.predictedNotTakenIncorrect 540315 # N system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 605718112 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 438834840 72.45% # Type of FU issued - IntMult 6546 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 29 0.00% # Type of FU issued - FloatCmp 5 0.00% # Type of FU issued - FloatCvt 5 0.00% # Type of FU issued - FloatMult 4 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 124855453 20.61% # Type of FU issued - MemWrite 42021230 6.94% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 438834840 72.45% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6546 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 124855453 20.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 42021230 6.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 605718112 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 5390831 74.54% # attempts to use FU when none available - IntMult 67 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 1490139 20.60% # attempts to use FU when none available - MemWrite 351286 4.86% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34% -system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 332581112 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5390831 74.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 67 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1490139 20.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 351286 4.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 332581112 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued @@ -369,13 +369,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5083.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 78 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 396500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency @@ -394,7 +394,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 181383 # number of overall hits system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout index 3f5339a48..6de92788c 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:10:28 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:42 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index c10711f5d..dfa3f12e0 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1860782 # Simulator instruction rate (inst/s) -host_mem_usage 203344 # Number of bytes of host memory used -host_seconds 323.44 # Real time elapsed on the host -host_tick_rate 2405379783 # Simulator tick rate (ticks/s) +host_inst_rate 2876228 # Simulator instruction rate (inst/s) +host_mem_usage 205052 # Number of bytes of host memory used +host_seconds 209.25 # Real time elapsed on the host +host_tick_rate 3718015194 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.778004 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 328891 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153435240 # number of overall hits system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 795 # nu system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 757057.991195 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601861103 # number of overall hits system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses @@ -187,13 +187,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -212,7 +212,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 167236 # number of overall hits system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 42dccffd2..04375240b 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:17:54 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:21:10 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 7ce31fb30..a99c3f466 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 110757 # Simulator instruction rate (inst/s) -host_mem_usage 206360 # Number of bytes of host memory used -host_seconds 12690.99 # Real time elapsed on the host -host_tick_rate 86885218 # Simulator tick rate (ticks/s) +host_inst_rate 148321 # Simulator instruction rate (inst/s) +host_mem_usage 208096 # Number of bytes of host memory used +host_seconds 9476.87 # Real time elapsed on the host +host_tick_rate 116352721 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405618365 # Number of instructions simulated sim_seconds 1.102659 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 0 # Nu system.cpu.commit.COM:branches 86248929 # Number of branches committed system.cpu.commit.COM:bw_lim_events 8096109 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1964055004 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 1088074201 5539.94% - 1 575643784 2930.89% - 2 120435541 613.20% - 3 120975798 615.95% - 4 27955067 142.33% - 5 8084166 41.16% - 6 10447088 53.19% - 7 4343250 22.11% - 8 8096109 41.22% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 1964055004 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 1088074201 55.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 575643784 29.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 120435541 6.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 120975798 6.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 27955067 1.42% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 8084166 0.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 10447088 0.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 4343250 0.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 8096109 0.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1964055004 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.758399 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.188214 # Number of insts commited each cycle system.cpu.commit.COM:count 1489537508 # Number of instructions committed system.cpu.commit.COM:loads 402517243 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed @@ -79,13 +81,13 @@ system.cpu.dcache.WriteReq_mshr_hits 1870625 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 12696288000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1119.158447 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 30916.284897 # average overall miss latency @@ -104,7 +106,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 30916.284897 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 589980331 # number of overall hits system.cpu.dcache.overall_miss_latency 97022505500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses @@ -138,21 +140,23 @@ system.cpu.fetch.branchRate 0.115384 # Nu system.cpu.fetch.icacheStallCycles 354588619 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 2203814981 -system.cpu.fetch.rateDist.min_value 0 - 0 1359102894 6167.05% - 1 256500547 1163.89% - 2 81150170 368.23% - 3 38425919 174.36% - 4 85384463 387.44% - 5 41200023 186.95% - 6 32567288 147.78% - 7 20688755 93.88% - 8 288794922 1310.43% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 2203814981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 1359102894 61.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 256500547 11.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 81150170 3.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 38425919 1.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 85384463 3.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 41200023 1.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 32567288 1.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 20688755 0.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 288794922 13.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 2203814981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.693518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.831719 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 354588619 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency @@ -164,13 +168,13 @@ system.cpu.icache.ReadReq_mshr_hits 748 # nu system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 257319.660377 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 354588619 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency @@ -189,7 +193,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 354588619 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 354586492 # number of overall hits system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses @@ -252,58 +256,54 @@ system.cpu.iew.predictedNotTakenIncorrect 1481544 # N system.cpu.iew.predictedTakenIncorrect 90333500 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1989307661 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 1186637129 59.65% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2990803 0.15% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 571681967 28.74% # Type of FU issued - MemWrite 227997762 11.46% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186637129 59.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2990803 0.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 571681967 28.74% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 227997762 11.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 1989307661 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 4014627 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 142220 3.54% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 232755 5.80% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 3328922 82.92% # attempts to use FU when none available - MemWrite 310730 7.74% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 2203814981 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083881876 49.18% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425801 26.61% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714420 13.55% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995038 7.49% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215803 2.14% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943143 0.68% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716019 0.30% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 790183 0.04% -system.cpu.iq.ISSUE:issued_per_cycle::8 132698 0.01% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 2203814981 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 142220 3.54% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 232755 5.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3328922 82.92% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 310730 7.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 2203814981 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083881876 49.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425801 26.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714420 13.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995038 7.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215803 2.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943143 0.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716019 0.30% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 790183 0.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 132698 0.01% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 2203814981 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate system.cpu.iq.iqInstsAdded 2506731488 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 1989307661 # Number of instructions issued @@ -342,13 +342,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 348749 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 348749 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 4.234507 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34273.636870 # average overall miss latency @@ -367,7 +367,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34273.636870 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 214678 # number of overall hits system.cpu.l2cache.overall_miss_latency 10764492500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.593992 # miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout index 87c6b0d93..224bbd08c 100755 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:13:21 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:25:44 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 2bdd6d4c0..72665606e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1263053 # Simulator instruction rate (inst/s) -host_mem_usage 205412 # Number of bytes of host memory used -host_seconds 1179.30 # Real time elapsed on the host -host_tick_rate 1760361196 # Simulator tick rate (ticks/s) +host_inst_rate 2042056 # Simulator instruction rate (inst/s) +host_mem_usage 207148 # Number of bytes of host memory used +host_seconds 729.42 # Real time elapsed on the host +host_tick_rate 2846083906 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489523295 # Number of instructions simulated sim_seconds 2.076001 # Number of seconds simulated @@ -38,13 +38,13 @@ system.cpu.dcache.WriteReq_misses 319595 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency @@ -63,7 +63,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568846579 # number of overall hits system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses @@ -91,13 +91,13 @@ system.cpu.icache.ReadReq_misses 1107 # nu system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency @@ -116,7 +116,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1485111905 # number of overall hits system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses @@ -165,13 +165,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -190,7 +190,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 160849 # number of overall hits system.cpu.l2cache.overall_miss_latency 15260908000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.645963 # miss rate for overall accesses diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 852b3d501..450751534 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:10:33 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:55 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:33:03 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 88ced5522..7585c05e4 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1809758 # Simulator instruction rate (inst/s) -host_mem_usage 205688 # Number of bytes of host memory used -host_seconds 894.80 # Real time elapsed on the host -host_tick_rate 2028277640 # Simulator tick rate (ticks/s) +host_inst_rate 1739159 # Simulator instruction rate (inst/s) +host_mem_usage 207648 # Number of bytes of host memory used +host_seconds 931.12 # Real time elapsed on the host +host_tick_rate 1949153444 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1619365954 # Number of instructions simulated sim_seconds 1.814897 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 312146 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 16543738000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001659 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 312146 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 1364.014744 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 607228174 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 42400.023531 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 607228174 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 42400.023531 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 39400.023531 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 606718219 # number of overall hits system.cpu.dcache.overall_miss_latency 21622104000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000840 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 722 # nu system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 1643373.934903 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1186516703 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 1186516703 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1186515981 # number of overall hits system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 65104 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 308934 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 308934 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.437895 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 445573 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 445573 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 165128 # number of overall hits system.cpu.l2cache.overall_miss_latency 14583140000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.629403 # miss rate for overall accesses diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 41fbd38b3..f57e2c6eb 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 17:45:48 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:52:26 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:24 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:26 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index fe62d358c..00639600d 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 130489 # Simulator instruction rate (inst/s) -host_mem_usage 295320 # Number of bytes of host memory used -host_seconds 430.62 # Real time elapsed on the host -host_tick_rate 4430183157 # Simulator tick rate (ticks/s) +host_inst_rate 194901 # Simulator instruction rate (inst/s) +host_mem_usage 296848 # Number of bytes of host memory used +host_seconds 288.30 # Real time elapsed on the host +host_tick_rate 6617017260 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56190549 # Number of instructions simulated sim_seconds 1.907705 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu0.BPredUnit.usedRAS 690374 # Nu system.cpu0.commit.COM:branches 5979895 # Number of branches committed system.cpu0.commit.COM:bw_lim_events 670392 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle.samples 69432713 -system.cpu0.commit.COM:committed_per_cycle.min_value 0 - 0 52133999 7508.56% - 1 7662367 1103.57% - 2 4443977 640.04% - 3 2023862 291.49% - 4 1473823 212.27% - 5 453845 65.36% - 6 276436 39.81% - 7 294012 42.34% - 8 670392 96.55% -system.cpu0.commit.COM:committed_per_cycle.max_value 8 -system.cpu0.commit.COM:committed_per_cycle.end_dist - +system.cpu0.commit.COM:committed_per_cycle::samples 69432713 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0-1 52133999 75.09% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1-2 7662367 11.04% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2-3 4443977 6.40% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3-4 2023862 2.91% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4-5 1473823 2.12% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5-6 453845 0.65% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6-7 276436 0.40% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7-8 294012 0.42% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 670392 0.97% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::total 69432713 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.574171 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.330726 # Number of insts commited each cycle system.cpu0.commit.COM:count 39866260 # Number of instructions committed system.cpu0.commit.COM:loads 6404474 # Number of loads committed system.cpu0.commit.COM:membars 151021 # Number of memory barriers committed @@ -94,13 +96,13 @@ system.cpu0.dcache.WriteReq_mshr_miss_latency 15269947736 system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066495 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 283141 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050789497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9307.081114 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets 16250 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9307.081114 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 16250 # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 9.224233 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 116343 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 2 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 1082813738 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 32500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 116343 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 1082813738 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 32500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 10672732 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 41596.652338 # average overall miss latency @@ -173,21 +175,23 @@ system.cpu0.fetch.branchRate 0.100032 # Nu system.cpu0.fetch.icacheStallCycles 6456937 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.predictedBranches 5666568 # Number of branches that fetch has predicted taken system.cpu0.fetch.rate 0.515416 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist.samples 70526783 -system.cpu0.fetch.rateDist.min_value 0 - 0 60303519 8550.44% - 1 761816 108.02% - 2 1433855 203.31% - 3 636077 90.19% - 4 2329701 330.33% - 5 474692 67.31% - 6 552515 78.34% - 7 815434 115.62% - 8 3219174 456.45% -system.cpu0.fetch.rateDist.max_value 8 -system.cpu0.fetch.rateDist.end_dist - +system.cpu0.fetch.rateDist::samples 70526783 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0-1 60303519 85.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1-2 761816 1.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2-3 1433855 2.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3-4 636077 0.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4-5 2329701 3.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5-6 474692 0.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6-7 552515 0.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7-8 815434 1.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3219174 4.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 70526783 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.737401 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.023896 # Number of instructions fetched each cycle (Total) system.cpu0.icache.ReadReq_accesses 6456937 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_avg_miss_latency 15194.125887 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.650508 # average ReadReq mshr miss latency @@ -199,13 +203,13 @@ system.cpu0.icache.ReadReq_mshr_hits 29877 # nu system.cpu0.icache.ReadReq_mshr_miss_latency 7526063499 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.096077 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 620366 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs 11808.794118 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11808.794118 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 9.361634 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 34 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 401499 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 401499 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 6456937 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 15194.125887 # average overall miss latency @@ -224,7 +228,7 @@ system.cpu0.icache.no_allocate_misses 0 # Nu system.cpu0.icache.overall_accesses 6456937 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 15194.125887 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 12131.650508 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 5806694 # number of overall hits system.cpu0.icache.overall_miss_latency 9879873999 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.100705 # miss rate for overall accesses @@ -287,58 +291,54 @@ system.cpu0.iew.predictedNotTakenIncorrect 255799 # system.cpu0.iew.predictedTakenIncorrect 313044 # Number of branches that were predicted taken incorrectly system.cpu0.ipc 0.373240 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.373240 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0 40987369 # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0.start_dist - No_OpClass 3326 0.01% # Type of FU issued - IntAlu 28267868 68.97% # Type of FU issued - IntMult 42211 0.10% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 12076 0.03% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 1657 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 7398159 18.05% # Type of FU issued - MemWrite 4612021 11.25% # Type of FU issued - IprAccess 650051 1.59% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0.end_dist +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3326 0.01% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 28267868 68.97% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 42211 0.10% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 12076 0.03% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1657 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 7398159 18.05% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 4612021 11.25% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 650051 1.59% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::total 40987369 # Type of FU issued system.cpu0.iq.ISSUE:fu_busy_cnt 290458 # FU busy when requested system.cpu0.iq.ISSUE:fu_busy_rate 0.007087 # FU busy rate (busy events/executed inst) -system.cpu0.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 33502 11.53% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 185621 63.91% # attempts to use FU when none available - MemWrite 71335 24.56% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full.end_dist -system.cpu0.iq.ISSUE:issued_per_cycle::samples 70526783 -system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 49764700 70.56% -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 10507721 14.90% -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4625277 6.56% -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2839073 4.03% -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1729944 2.45% -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 663617 0.94% -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 315224 0.45% -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 67146 0.10% -system.cpu0.iq.ISSUE:issued_per_cycle::8 14081 0.02% -system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu0.iq.ISSUE:issued_per_cycle::total 70526783 -system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.581160 -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.133092 +system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 33502 11.53% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 185621 63.91% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 71335 24.56% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:issued_per_cycle::samples 70526783 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 49764700 70.56% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 10507721 14.90% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4625277 6.56% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2839073 4.03% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1729944 2.45% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 663617 0.94% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 315224 0.45% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 67146 0.10% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 14081 0.02% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::total 70526783 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.581160 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.133092 # Number of insts issued each cycle system.cpu0.iq.ISSUE:rate 0.406210 # Inst issue rate system.cpu0.iq.iqInstsAdded 42280479 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqInstsIssued 40987369 # Number of instructions issued @@ -363,94 +363,94 @@ system.cpu0.itb.write_accesses 0 # DT system.cpu0.itb.write_acv 0 # DTB write access violations system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.kern.callpal 129578 # number of callpals executed -system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 96 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2410 1.86% 1.94% # number of callpals executed -system.cpu0.kern.callpal_tbi 51 0.04% 1.98% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.01% 1.98% # number of callpals executed -system.cpu0.kern.callpal_swpipl 116005 89.53% 91.51% # number of callpals executed -system.cpu0.kern.callpal_rdps 6357 4.91% 96.41% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.41% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 96.42% # number of callpals executed -system.cpu0.kern.callpal_rdusp 9 0.01% 96.42% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.42% # number of callpals executed -system.cpu0.kern.callpal_rti 4116 3.18% 99.60% # number of callpals executed -system.cpu0.kern.callpal_callsys 381 0.29% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 136 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal::cserve 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wripir 96 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2410 1.86% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.04% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% # number of callpals executed +system.cpu0.kern.callpal::swpipl 116005 89.53% # number of callpals executed +system.cpu0.kern.callpal::rdps 6357 4.91% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4116 3.18% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.29% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.10% # number of callpals executed +system.cpu0.kern.callpal::total 129578 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.hwrei 144417 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 4856 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 122308 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 47763 39.05% 39.05% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 239 0.20% 39.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1931 1.58% 40.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 17 0.01% 40.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 72358 59.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 96397 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 47113 48.87% 48.87% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1931 2.00% 51.13% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 47097 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1907288793500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1871606920000 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 101495000 0.01% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 398001000 0.02% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 9331000 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 35173046500 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.986391 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.650889 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1283 -system.cpu0.kern.mode_good_user 1283 -system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 5894 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1283 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.217679 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1905143965500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 2121516000 0.11% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.ipl_count::0 47763 39.05% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 239 0.20% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1931 1.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 17 0.01% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 72358 59.16% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 122308 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 47113 48.87% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 239 0.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1931 2.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 17 0.02% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 47097 48.86% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 96397 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1871606920000 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 101495000 0.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398001000 0.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 9331000 0.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 35173046500 1.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907288793500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.986391 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.650889 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1283 +system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::idle 0 +system.cpu0.kern.mode_switch::kernel 5894 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.217679 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1905143965500 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2121516000 0.11% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 0 0.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2411 # number of times the context was actually changed -system.cpu0.kern.syscall 222 # number of syscalls executed -system.cpu0.kern.syscall_2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall_4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall_6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall_17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall_19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall_20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall_23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall_24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall_33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall_45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall_47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall_48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall_54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall_59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall_71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall_74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall_90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall_92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall_132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall_144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::2 8 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.memDep0.conflictingLoads 2050556 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 1832562 # Number of conflicting stores. system.cpu0.memDep0.insertedLoads 7553743 # Number of loads inserted to the mem dependence unit. @@ -485,21 +485,23 @@ system.cpu1.BPredUnit.usedRAS 417428 # Nu system.cpu1.commit.COM:branches 2947825 # Number of branches committed system.cpu1.commit.COM:bw_lim_events 401526 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle.samples 37477420 -system.cpu1.commit.COM:committed_per_cycle.min_value 0 - 0 29419430 7849.91% - 1 3577485 954.57% - 2 1728132 461.11% - 3 1049887 280.14% - 4 708572 189.07% - 5 265966 70.97% - 6 180885 48.27% - 7 145537 38.83% - 8 401526 107.14% -system.cpu1.commit.COM:committed_per_cycle.max_value 8 -system.cpu1.commit.COM:committed_per_cycle.end_dist - +system.cpu1.commit.COM:committed_per_cycle::samples 37477420 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0-1 29419430 78.50% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1-2 3577485 9.55% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2-3 1728132 4.61% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3-4 1049887 2.80% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4-5 708572 1.89% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5-6 265966 0.71% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6-7 180885 0.48% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7-8 145537 0.39% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 401526 1.07% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::total 37477420 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.524684 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.336555 # Number of insts commited each cycle system.cpu1.commit.COM:count 19663805 # Number of instructions committed system.cpu1.commit.COM:loads 3551077 # Number of loads committed system.cpu1.commit.COM:membars 87378 # Number of memory barriers committed @@ -560,13 +562,13 @@ system.cpu1.dcache.WriteReq_mshr_miss_latency 7735954636 system.cpu1.dcache.WriteReq_mshr_miss_rate 0.063808 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 142604 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526038500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles_no_mshrs 13994.026145 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets 5000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13994.026145 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 8.879077 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 31364 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 438908636 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 5000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 31364 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 438908636 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 5824280 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 33113.418856 # average overall miss latency @@ -639,21 +641,23 @@ system.cpu1.fetch.branchRate 0.129267 # Nu system.cpu1.fetch.icacheStallCycles 3089103 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.predictedBranches 2688799 # Number of branches that fetch has predicted taken system.cpu1.fetch.rate 0.626137 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist.samples 38118943 -system.cpu1.fetch.rateDist.min_value 0 - 0 33077920 8677.55% - 1 338218 88.73% - 2 684572 179.59% - 3 401329 105.28% - 4 792382 207.87% - 5 254420 66.74% - 6 341251 89.52% - 7 404733 106.18% - 8 1824118 478.53% -system.cpu1.fetch.rateDist.max_value 8 -system.cpu1.fetch.rateDist.end_dist - +system.cpu1.fetch.rateDist::samples 38118943 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0-1 33077920 86.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1-2 338218 0.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2-3 684572 1.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3-4 401329 1.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4-5 792382 2.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5-6 254420 0.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6-7 341251 0.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7-8 404733 1.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1824118 4.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 38118943 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.703759 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.021088 # Number of instructions fetched each cycle (Total) system.cpu1.icache.ReadReq_accesses 3089103 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_avg_miss_latency 14554.957905 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.745633 # average ReadReq mshr miss latency @@ -665,13 +669,13 @@ system.cpu1.icache.ReadReq_mshr_hits 20962 # nu system.cpu1.icache.ReadReq_mshr_miss_latency 5189282500 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate 0.144757 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 447169 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs 11057.692308 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11057.692308 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 5.861938 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 26 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 287500 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 287500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 3089103 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 14554.957905 # average overall miss latency @@ -690,7 +694,7 @@ system.cpu1.icache.no_allocate_misses 0 # Nu system.cpu1.icache.overall_accesses 3089103 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 14554.957905 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11604.745633 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 2620972 # number of overall hits system.cpu1.icache.overall_miss_latency 6813626999 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.151543 # miss rate for overall accesses @@ -753,58 +757,54 @@ system.cpu1.iew.predictedNotTakenIncorrect 160561 # system.cpu1.iew.predictedTakenIncorrect 178400 # Number of branches that were predicted taken incorrectly system.cpu1.ipc 0.432490 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.432490 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0 20562807 # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0.start_dist - No_OpClass 3984 0.02% # Type of FU issued - IntAlu 13476075 65.54% # Type of FU issued - IntMult 28965 0.14% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 13702 0.07% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 1986 0.01% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 4173782 20.30% # Type of FU issued - MemWrite 2443072 11.88% # Type of FU issued - IprAccess 421241 2.05% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0.end_dist +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3984 0.02% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 13476075 65.54% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 28965 0.14% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 13702 0.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1986 0.01% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 4173782 20.30% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 2443072 11.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 421241 2.05% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::total 20562807 # Type of FU issued system.cpu1.iq.ISSUE:fu_busy_cnt 221150 # FU busy when requested system.cpu1.iq.ISSUE:fu_busy_rate 0.010755 # FU busy rate (busy events/executed inst) -system.cpu1.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 16139 7.30% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 131899 59.64% # attempts to use FU when none available - MemWrite 73112 33.06% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full.end_dist -system.cpu1.iq.ISSUE:issued_per_cycle::samples 38118943 -system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 28405834 74.52% -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4664798 12.24% -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1989487 5.22% -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1362185 3.57% -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 979454 2.57% -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 465472 1.22% -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 186874 0.49% -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 52652 0.14% -system.cpu1.iq.ISSUE:issued_per_cycle::8 12187 0.03% -system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu1.iq.ISSUE:issued_per_cycle::total 38118943 -system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.539438 -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.158785 +system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 16139 7.30% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 131899 59.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 73112 33.06% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:issued_per_cycle::samples 38118943 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 28405834 74.52% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4664798 12.24% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1989487 5.22% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1362185 3.57% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 979454 2.57% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 465472 1.22% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 186874 0.49% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 52652 0.14% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 12187 0.03% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::total 38118943 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.539438 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.158785 # Number of insts issued each cycle system.cpu1.iq.ISSUE:rate 0.479940 # Inst issue rate system.cpu1.iq.iqInstsAdded 21283926 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqInstsIssued 20562807 # Number of instructions issued @@ -829,73 +829,73 @@ system.cpu1.itb.write_accesses 0 # DT system.cpu1.itb.write_acv 0 # DTB write access violations system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.kern.callpal 87355 # number of callpals executed -system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 17 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal_swpctx 1838 2.10% 2.13% # number of callpals executed -system.cpu1.kern.callpal_tbi 3 0.00% 2.13% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal_swpipl 79684 91.22% 93.36% # number of callpals executed -system.cpu1.kern.callpal_rdps 2408 2.76% 96.11% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 96.11% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal_rti 3206 3.67% 99.79% # number of callpals executed -system.cpu1.kern.callpal_callsys 136 0.16% 99.95% # number of callpals executed -system.cpu1.kern.callpal_imb 44 0.05% 100.00% # number of callpals executed -system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.callpal::cserve 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 17 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1838 2.10% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% # number of callpals executed +system.cpu1.kern.callpal::swpipl 79684 91.22% # number of callpals executed +system.cpu1.kern.callpal::rdps 2408 2.76% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% # number of callpals executed +system.cpu1.kern.callpal::rti 3206 3.67% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.16% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.05% # number of callpals executed +system.cpu1.kern.callpal::rdunique 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::total 87355 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.hwrei 93966 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 3806 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 84915 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 34143 40.21% 40.21% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1928 2.27% 42.48% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 96 0.11% 42.59% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 48748 57.41% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 68760 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 33416 48.60% 48.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 33320 48.46% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1907704531000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1871986905500 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 352078000 0.02% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 40004500 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 35325543000 1.85% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.978707 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.683515 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 521 -system.cpu1.kern.mode_good_user 463 -system.cpu1.kern.mode_good_idle 58 -system.cpu1.kern.mode_switch_kernel 2305 # number of protection mode switches -system.cpu1.kern.mode_switch_user 463 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2035 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.254532 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.226030 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.028501 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 46750182500 2.45% 2.45% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1015923000 0.05% 2.50% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1859938417500 97.50% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.ipl_count::0 34143 40.21% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1928 2.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 96 0.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 48748 57.41% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 84915 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 33416 48.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1928 2.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 96 0.14% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 33320 48.46% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 68760 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871986905500 98.13% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 352078000 0.02% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 40004500 0.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 35325543000 1.85% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907704531000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978707 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.683515 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 521 +system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.mode_good::idle 58 +system.cpu1.kern.mode_switch::kernel 2305 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2035 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.226030 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::idle 0.028501 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.254532 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 46750182500 2.45% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1015923000 0.05% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1859938417500 97.50% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1839 # number of times the context was actually changed -system.cpu1.kern.syscall 104 # number of syscalls executed -system.cpu1.kern.syscall_3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall_6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall_15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall_17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall_23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall_24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall_33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall_45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall_47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall_59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall_71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall_74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall_132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::3 11 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.memDep0.conflictingLoads 906343 # Number of conflicting loads. system.cpu1.memDep0.conflictingStores 817120 # Number of conflicting stores. system.cpu1.memDep0.insertedLoads 4247431 # Number of loads inserted to the mem dependence unit. @@ -949,13 +949,13 @@ system.iocache.WriteReq_misses 41552 # nu system.iocache.WriteReq_mshr_miss_latency 3566847774 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6165.982406 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6165.982406 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10458 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64483844 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64483844 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41727 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency 137749.749658 # average overall miss latency @@ -974,7 +974,7 @@ system.iocache.no_allocate_misses 0 # Nu system.iocache.overall_accesses 41727 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency 137749.749658 # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits system.iocache.overall_miss_latency 5747883804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses @@ -1027,13 +1027,13 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency inf system.l2c.WriteReq_mshr_uncacheable_latency 1423763998 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses 455578 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 455578 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 4.834791 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 2522281 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 52179.674113 # average overall miss latency @@ -1070,15 +1070,15 @@ system.l2c.tagsinuse 31163.178813 # Cy system.l2c.total_refs 2096699 # Total number of references to valid blocks. system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 124293 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index fffbf9b56..9bbf14964 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 17:45:48 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:46:13 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:24 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:26 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 1a13ce67c..a3d576207 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 142678 # Simulator instruction rate (inst/s) -host_mem_usage 293540 # Number of bytes of host memory used -host_seconds 372.10 # Real time elapsed on the host -host_tick_rate 5018472256 # Simulator tick rate (ticks/s) +host_inst_rate 194380 # Simulator instruction rate (inst/s) +host_mem_usage 294816 # Number of bytes of host memory used +host_seconds 273.13 # Real time elapsed on the host +host_tick_rate 6837009197 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 53090223 # Number of instructions simulated sim_seconds 1.867363 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 1034705 # Nu system.cpu.commit.COM:branches 8461925 # Number of branches committed system.cpu.commit.COM:bw_lim_events 978098 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 100629475 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 76387036 7590.92% - 1 10760374 1069.31% - 2 5981089 594.37% - 3 2990150 297.14% - 4 2079430 206.64% - 5 662647 65.85% - 6 398739 39.62% - 7 391912 38.95% - 8 978098 97.20% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 100629475 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 76387036 75.91% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 10760374 10.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 5981089 5.94% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 2990150 2.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2079430 2.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 662647 0.66% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 398739 0.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 391912 0.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 978098 0.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 100629475 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.559325 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.322901 # Number of insts commited each cycle system.cpu.commit.COM:count 56284559 # Number of instructions committed system.cpu.commit.COM:loads 9308572 # Number of loads committed system.cpu.commit.COM:membars 228000 # Number of memory barriers committed @@ -94,13 +96,13 @@ system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 system.cpu.dcache.WriteReq_mshr_miss_rate 0.064467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles_no_mshrs 10022.289139 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 16500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10022.289139 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16500 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 8.827872 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 137083 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 1373885462 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 66000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137083 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1373885462 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 66000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 15499631 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 38794.252006 # average overall miss latency @@ -173,21 +175,23 @@ system.cpu.fetch.branchRate 0.106306 # Nu system.cpu.fetch.icacheStallCycles 8997144 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 7967591 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.542091 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 102272708 -system.cpu.fetch.rateDist.min_value 0 - 0 87829962 8587.82% - 1 1051726 102.84% - 2 2021481 197.66% - 3 968950 94.74% - 4 2998384 293.18% - 5 688876 67.36% - 6 831559 81.31% - 7 1217734 119.07% - 8 4664036 456.04% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 102272708 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 87829962 85.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1051726 1.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 2021481 1.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 968950 0.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 2998384 2.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 688876 0.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 831559 0.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1217734 1.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4664036 4.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 102272708 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.726149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.019798 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 8997144 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 14906.743449 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency @@ -199,13 +203,13 @@ system.cpu.icache.ReadReq_mshr_hits 51877 # nu system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.110664 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs 11545.454545 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 11545.454545 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 7.985800 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 55 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 635000 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 635000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 8997144 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 14906.743449 # average overall miss latency @@ -224,7 +228,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 8997144 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 14906.743449 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 7949609 # number of overall hits system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.116430 # miss rate for overall accesses @@ -287,58 +291,54 @@ system.cpu.iew.predictedNotTakenIncorrect 381050 # N system.cpu.iew.predictedTakenIncorrect 476475 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.387526 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.387526 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 58124772 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 7284 0.01% # Type of FU issued - IntAlu 39611417 68.15% # Type of FU issued - IntMult 62110 0.11% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 25607 0.04% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 3636 0.01% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 10788116 18.56% # Type of FU issued - MemWrite 6673339 11.48% # Type of FU issued - IprAccess 953263 1.64% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7284 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39611417 68.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62110 0.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10788116 18.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6673339 11.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 953263 1.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 58124772 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 433051 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.007450 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 50716 11.71% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 279321 64.50% # attempts to use FU when none available - MemWrite 103014 23.79% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10% -system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 102272708 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 50716 11.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 279321 64.50% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 103014 23.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 102272708 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.424275 # Inst issue rate system.cpu.iq.iqInstsAdded 60155940 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 58124772 # Number of instructions issued @@ -363,90 +363,90 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.kern.callpal 192652 # number of callpals executed -system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal_swpipl 175681 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.callpal::cserve 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrmces 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrfen 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrvptptr 1 0.00% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% # number of callpals executed +system.cpu.kern.callpal::swpipl 175681 91.19% # number of callpals executed +system.cpu.kern.callpal::rdps 6794 3.53% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrusp 7 0.00% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% # number of callpals executed +system.cpu.kern.callpal::rti 5221 2.71% # number of callpals executed +system.cpu.kern.callpal::callsys 515 0.27% # number of callpals executed +system.cpu.kern.callpal::imb 181 0.09% # number of callpals executed +system.cpu.kern.callpal::total 192652 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.hwrei 211811 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183030 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74956 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105947 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149305 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1867362103000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1824761131000 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 102621000 0.01% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 392338000 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 42106013000 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981763 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.694583 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1910 -system.cpu.kern.mode_good_user 1740 -system.cpu.kern.mode_good_idle 170 -system.cpu.kern.mode_switch_kernel 5972 # number of protection mode switches -system.cpu.kern.mode_switch_user 1740 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.400971 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319826 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 31331138500 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 3191204500 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1832839752000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.ipl_count::0 74956 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 237 0.13% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1890 1.03% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105947 57.89% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183030 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73589 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 237 0.16% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1890 1.27% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73589 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149305 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1824761131000 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 102621000 0.01% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 392338000 0.02% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42106013000 2.25% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1867362103000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981763 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694583 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch::kernel 5972 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.319826 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.400971 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 31331138500 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3191204500 0.17% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832839752000 98.15% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.kern.syscall 326 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed +system.cpu.kern.syscall::2 8 2.45% # number of syscalls executed +system.cpu.kern.syscall::3 30 9.20% # number of syscalls executed +system.cpu.kern.syscall::4 4 1.23% # number of syscalls executed +system.cpu.kern.syscall::6 42 12.88% # number of syscalls executed +system.cpu.kern.syscall::12 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::15 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::17 15 4.60% # number of syscalls executed +system.cpu.kern.syscall::19 10 3.07% # number of syscalls executed +system.cpu.kern.syscall::20 6 1.84% # number of syscalls executed +system.cpu.kern.syscall::23 4 1.23% # number of syscalls executed +system.cpu.kern.syscall::24 6 1.84% # number of syscalls executed +system.cpu.kern.syscall::33 11 3.37% # number of syscalls executed +system.cpu.kern.syscall::41 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::45 54 16.56% # number of syscalls executed +system.cpu.kern.syscall::47 6 1.84% # number of syscalls executed +system.cpu.kern.syscall::48 10 3.07% # number of syscalls executed +system.cpu.kern.syscall::54 10 3.07% # number of syscalls executed +system.cpu.kern.syscall::58 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::59 7 2.15% # number of syscalls executed +system.cpu.kern.syscall::71 54 16.56% # number of syscalls executed +system.cpu.kern.syscall::73 3 0.92% # number of syscalls executed +system.cpu.kern.syscall::74 16 4.91% # number of syscalls executed +system.cpu.kern.syscall::87 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::90 3 0.92% # number of syscalls executed +system.cpu.kern.syscall::92 9 2.76% # number of syscalls executed +system.cpu.kern.syscall::97 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::98 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::132 4 1.23% # number of syscalls executed +system.cpu.kern.syscall::144 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::147 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::total 326 # number of syscalls executed system.cpu.memDep0.conflictingLoads 3077147 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2881540 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 11048107 # Number of loads inserted to the mem dependence unit. @@ -500,13 +500,13 @@ system.iocache.WriteReq_misses 41552 # nu system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6161.136802 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6161.136802 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10475 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64537908 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64537908 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency 137700.822145 # average overall miss latency @@ -525,7 +525,7 @@ system.iocache.no_allocate_misses 0 # Nu system.iocache.overall_accesses 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency 137700.822145 # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses @@ -578,13 +578,13 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency inf system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses 430447 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 430447 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 4.597861 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 2398325 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 52201.631966 # average overall miss latency @@ -621,15 +621,15 @@ system.l2c.tagsinuse 30690.397149 # Cy system.l2c.total_refs 1966597 # Total number of references to valid blocks. system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 119094 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout index 2fa26b5da..431d9905a 100755 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:10:11 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:30:43 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt index aab215cd0..803a77546 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1286984 # Simulator instruction rate (inst/s) -host_mem_usage 337604 # Number of bytes of host memory used -host_seconds 189.46 # Real time elapsed on the host -host_tick_rate 1934075040 # Simulator tick rate (ticks/s) +host_inst_rate 1809872 # Simulator instruction rate (inst/s) +host_mem_usage 339332 # Number of bytes of host memory used +host_seconds 134.73 # Real time elapsed on the host +host_tick_rate 2719868473 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243835278 # Number of instructions simulated sim_seconds 0.366435 # Number of seconds simulated @@ -38,13 +38,13 @@ system.cpu.dcache.WriteReq_misses 94963 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency @@ -63,7 +63,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 104134565 # number of overall hits system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses @@ -91,13 +91,13 @@ system.cpu.icache.ReadReq_misses 882 # nu system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency @@ -116,7 +116,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 244420630 # number of overall hits system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses @@ -165,13 +165,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 94877 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 94877 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -190,7 +190,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 892653 # number of overall hits system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index f69f1702d..d2184b8d7 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:25:28 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:55 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:35:54 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index b30863c58..fe50ece29 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1561663 # Simulator instruction rate (inst/s) -host_mem_usage 340216 # Number of bytes of host memory used -host_seconds 172.69 # Real time elapsed on the host -host_tick_rate 2209830759 # Simulator tick rate (ticks/s) +host_inst_rate 1578716 # Simulator instruction rate (inst/s) +host_mem_usage 342176 # Number of bytes of host memory used +host_seconds 170.83 # Real time elapsed on the host +host_tick_rate 2233960314 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269686785 # Number of instructions simulated sim_seconds 0.381621 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 229177 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 58.501856 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 120039828 # number of overall hits system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 808 # nu system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 269424.955446 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 217696172 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 217696172 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 217695364 # number of overall hits system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 125325 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 229129 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 229129 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 13.678118 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 2054848 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000.160754 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 2054848 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000.160754 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1862007 # number of overall hits system.cpu.l2cache.overall_miss_latency 10027763000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.093847 # miss rate for overall accesses diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 2e4d3d070..fb61c1f63 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:28:21 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:55 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:37:54 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 1dc17b8c3..190dc2ac9 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1120182 # Simulator instruction rate (inst/s) -host_mem_usage 209372 # Number of bytes of host memory used -host_seconds 1335.04 # Real time elapsed on the host -host_tick_rate 1290116936 # Simulator tick rate (ticks/s) +host_inst_rate 1774247 # Simulator instruction rate (inst/s) +host_mem_usage 211336 # Number of bytes of host memory used +host_seconds 842.88 # Real time elapsed on the host +host_tick_rate 2043406156 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1495482368 # Number of instructions simulated sim_seconds 1.722353 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 1466148 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 77705715500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009829 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1466148 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 210.782575 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 533262382 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 38773.620317 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 533262382 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 38773.620317 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35773.619690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 530069421 # number of overall hits system.cpu.dcache.overall_miss_latency 123802657500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005988 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 2814 # nu system.cpu.icache.ReadReq_mshr_miss_latency 127806000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 2814 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 379653.254797 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1068347073 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 48417.910448 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 1068347073 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 48417.910448 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 45417.910448 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1068344259 # number of overall hits system.cpu.icache.overall_miss_latency 136248000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 674990 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 1463913 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 1463913 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 3.428066 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 2520785 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000.009499 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 2520785 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000.009499 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1310104 # number of overall hits system.cpu.l2cache.overall_miss_latency 62955423500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.480279 # miss rate for overall accesses diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 856b2af50..1aca9720a 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:15:52 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:54 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 2a30c3ff4..282f33cac 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 243057 # Simulator instruction rate (inst/s) -host_mem_usage 211796 # Number of bytes of host memory used -host_seconds 1545.21 # Real time elapsed on the host -host_tick_rate 87364560 # Simulator tick rate (ticks/s) +host_inst_rate 246720 # Simulator instruction rate (inst/s) +host_mem_usage 213512 # Number of bytes of host memory used +host_seconds 1522.27 # Real time elapsed on the host +host_tick_rate 88680917 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated sim_seconds 0.134997 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 12344504 # Nu system.cpu.commit.COM:branches 44587532 # Number of branches committed system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 254545673 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 123085210 4835.49% - 1 50466868 1982.63% - 2 18758377 736.94% - 3 19955031 783.95% - 4 11844121 465.30% - 5 8478667 333.09% - 6 5819307 228.62% - 7 2974518 116.86% - 8 13163574 517.14% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 254545673 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 123085210 48.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 50466868 19.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 18758377 7.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 19955031 7.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 11844121 4.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 8478667 3.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 5819307 2.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 2974518 1.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 13163574 5.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 254545673 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.566181 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.242361 # Number of insts commited each cycle system.cpu.commit.COM:count 398664594 # Number of instructions committed system.cpu.commit.COM:loads 100651995 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -71,13 +73,13 @@ system.cpu.dcache.WriteReq_mshr_hits 14704 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3249.700000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 32497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency @@ -96,7 +98,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 169002312 # number of overall hits system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses @@ -149,21 +151,23 @@ system.cpu.fetch.branchRate 0.230412 # Nu system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 269852647 -system.cpu.fetch.rateDist.min_value 0 - 0 164102333 6081.18% - 1 12367121 458.29% - 2 12410556 459.90% - 3 6615129 245.14% - 4 15923029 590.06% - 5 8709903 322.77% - 6 6580254 243.85% - 7 4007808 148.52% - 8 39136514 1450.29% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 269852647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 164102333 60.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 12367121 4.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 12410556 4.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 6615129 2.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 15923029 5.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 8709903 3.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 6580254 2.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 4007808 1.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39136514 14.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 269852647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.019263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.001909 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency @@ -175,13 +179,13 @@ system.cpu.icache.ReadReq_mshr_hits 945 # nu system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency @@ -200,7 +204,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 63861348 # number of overall hits system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses @@ -263,58 +267,54 @@ system.cpu.iew.predictedNotTakenIncorrect 847804 # N system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 429600196 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 33581 0.01% # Type of FU issued - IntAlu 166319014 38.71% # Type of FU issued - IntMult 2152935 0.50% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 35077566 8.17% # Type of FU issued - FloatCmp 7830879 1.82% # Type of FU issued - FloatCvt 2898460 0.67% # Type of FU issued - FloatMult 16788316 3.91% # Type of FU issued - FloatDiv 1569716 0.37% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 113503270 26.42% # Type of FU issued - MemWrite 83426459 19.42% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 166319014 38.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 2152935 0.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 35077566 8.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7830879 1.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2898460 0.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 16788316 3.91% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1569716 0.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 113503270 26.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 83426459 19.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 429600196 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 40640 0.39% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 76056 0.73% # attempts to use FU when none available - FloatCmp 13381 0.13% # attempts to use FU when none available - FloatCvt 12891 0.12% # attempts to use FU when none available - FloatMult 1723474 16.48% # attempts to use FU when none available - FloatDiv 1473560 14.09% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 5907144 56.49% # attempts to use FU when none available - MemWrite 1209900 11.57% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 269852647 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 99465935 36.86% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 57766030 21.41% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 39984554 14.82% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 29664959 10.99% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 23966120 8.88% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 10452563 3.87% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 5712016 2.12% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 2252970 0.83% -system.cpu.iq.ISSUE:issued_per_cycle::8 587500 0.22% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 269852647 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.591981 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720906 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 40640 0.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 76056 0.73% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 13381 0.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 12891 0.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 1723474 16.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 1473560 14.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 5907144 56.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 1209900 11.57% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 269852647 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 99465935 36.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 57766030 21.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 39984554 14.82% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 29664959 10.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 23966120 8.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 10452563 3.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 5712016 2.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 2252970 0.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 587500 0.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 269852647 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.591981 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720906 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued @@ -369,13 +369,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 3000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 6000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency @@ -394,7 +394,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 655 # number of overall hits system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout index 421c424a0..c7ba9a351 100755 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:04 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:06:21 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 1883943d5..5933cded2 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1575428 # Simulator instruction rate (inst/s) -host_mem_usage 210936 # Number of bytes of host memory used -host_seconds 253.05 # Real time elapsed on the host -host_tick_rate 2242037981 # Simulator tick rate (ticks/s) +host_inst_rate 2382679 # Simulator instruction rate (inst/s) +host_mem_usage 212620 # Number of bytes of host memory used +host_seconds 167.32 # Real time elapsed on the host +host_tick_rate 3390857898 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567352 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 3314 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 168270956 # number of overall hits system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 3673 # nu system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 398660993 # number of overall hits system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses @@ -187,13 +187,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -212,7 +212,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 585 # number of overall hits system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 064222d23..6f66e500e 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:44:16 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:07:12 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 6e24feffe..24cb425d3 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 191030 # Simulator instruction rate (inst/s) -host_mem_usage 211708 # Number of bytes of host memory used -host_seconds 9543.22 # Real time elapsed on the host -host_tick_rate 73891181 # Simulator tick rate (ticks/s) +host_inst_rate 234613 # Simulator instruction rate (inst/s) +host_mem_usage 213416 # Number of bytes of host memory used +host_seconds 7770.43 # Real time elapsed on the host +host_tick_rate 90749074 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.705159 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 49888256 # Nu system.cpu.commit.COM:branches 266706457 # Number of branches committed system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1310002801 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 603585597 4607.51% - 1 273587005 2088.45% - 2 174037133 1328.52% - 3 65399708 499.23% - 4 48333001 368.95% - 5 34003110 259.57% - 6 18481318 141.08% - 7 23715685 181.04% - 8 68860244 525.65% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 1310002801 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 603585597 46.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 273587005 20.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 174037133 13.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 65399708 4.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 48333001 3.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 34003110 2.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 18481318 1.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 23715685 1.81% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 68860244 5.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1310002801 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.533575 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.199105 # Number of insts commited each cycle system.cpu.commit.COM:count 2008987604 # Number of instructions committed system.cpu.commit.COM:loads 511595302 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -71,13 +73,13 @@ system.cpu.dcache.WriteReq_mshr_hits 484574 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 5124.928571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 18000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5124.928571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18000 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 28 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 143498 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 18000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 143498 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 18000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency @@ -96,7 +98,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 674038251 # number of overall hits system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses @@ -149,21 +151,23 @@ system.cpu.fetch.branchRate 0.247763 # Nu system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1410161885 -system.cpu.fetch.rateDist.min_value 0 - 0 830588040 5890.02% - 1 53463106 379.13% - 2 39766072 282.00% - 3 63538024 450.57% - 4 121390719 860.83% - 5 35256321 250.02% - 6 38761682 274.87% - 7 6988644 49.56% - 8 220409277 1563.01% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 1410161885 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 830588040 58.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 53463106 3.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 39766072 2.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 63538024 4.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 121390719 8.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 35256321 2.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 38761682 2.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 6988644 0.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 220409277 15.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1410161885 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.148845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.029305 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency @@ -175,13 +179,13 @@ system.cpu.icache.ReadReq_mshr_hits 881 # nu system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency @@ -200,7 +204,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 348437250 # number of overall hits system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses @@ -263,58 +267,54 @@ system.cpu.iew.predictedNotTakenIncorrect 816990 # N system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2089507805 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 2752 0.00% # Type of FU issued - IntAlu 1204412678 57.64% # Type of FU issued - IntMult 17591 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 27851349 1.33% # Type of FU issued - FloatCmp 8254694 0.40% # Type of FU issued - FloatCvt 7204646 0.34% # Type of FU issued - FloatMult 4 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 557993260 26.70% # Type of FU issued - MemWrite 283770831 13.58% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1204412678 57.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 17591 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851349 1.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254694 0.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.34% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 557993260 26.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 283770831 13.58% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 2089507805 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 8291 0.02% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 28032977 75.57% # attempts to use FU when none available - MemWrite 9052278 24.40% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 1410161885 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 537278436 38.10% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 285217724 20.23% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 273546804 19.40% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 154810620 10.98% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 63341841 4.49% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 51438515 3.65% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 32491109 2.30% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 9036668 0.64% -system.cpu.iq.ISSUE:issued_per_cycle::8 3000168 0.21% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 1410161885 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.481750 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637343 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 8291 0.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 28032977 75.57% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 9052278 24.40% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 1410161885 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 537278436 38.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 285217724 20.23% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 273546804 19.40% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 154810620 10.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 63341841 4.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 51438515 3.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 32491109 2.30% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 9036668 0.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 3000168 0.21% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 1410161885 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.481750 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637343 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued @@ -369,13 +369,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 8187.500000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8187.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 8 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 65500 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 65500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency @@ -394,7 +394,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 28934 # number of overall hits system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 816f64d63..81c2e87d9 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:12 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:09:09 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 27fe7637a..93430ba50 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1413347 # Simulator instruction rate (inst/s) -host_mem_usage 210092 # Number of bytes of host memory used -host_seconds 1421.44 # Real time elapsed on the host -host_tick_rate 1980352310 # Simulator tick rate (ticks/s) +host_inst_rate 2471520 # Simulator instruction rate (inst/s) +host_mem_usage 211800 # Number of bytes of host memory used +host_seconds 812.86 # Real time elapsed on the host +host_tick_rate 3463041314 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.814951 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 74787 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 720331943 # number of overall hits system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 10596 # nu system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2009410475 # number of overall hits system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses @@ -187,13 +187,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.023744 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -212,7 +212,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 29320 # number of overall hits system.cpu.l2cache.overall_miss_latency 78593840000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index 689b74dbf..bbbd6fcec 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:52:32 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:09:12 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 99db99027..f8c066dab 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 274491 # Simulator instruction rate (inst/s) -host_mem_usage 215172 # Number of bytes of host memory used -host_seconds 289.96 # Real time elapsed on the host -host_tick_rate 93580527 # Simulator tick rate (ticks/s) +host_inst_rate 261277 # Simulator instruction rate (inst/s) +host_mem_usage 216964 # Number of bytes of host memory used +host_seconds 304.63 # Real time elapsed on the host +host_tick_rate 89075669 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.027135 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 1941929 # Nu system.cpu.commit.COM:branches 13754477 # Number of branches committed system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 51751169 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 22506446 4348.97% - 1 11357579 2194.65% - 2 5114502 988.29% - 3 3560855 688.07% - 4 2552504 493.23% - 5 1532717 296.17% - 6 1008933 194.96% - 7 796739 153.96% - 8 3320894 641.70% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 51751169 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 22506446 43.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 11357579 21.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 5114502 9.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 3560855 6.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2552504 4.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 1532717 2.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 1008933 1.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 796739 1.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 3320894 6.42% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 51751169 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.707028 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.326549 # Number of insts commited each cycle system.cpu.commit.COM:count 88340672 # Number of instructions committed system.cpu.commit.COM:loads 20379399 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -71,13 +73,13 @@ system.cpu.dcache.WriteReq_mshr_hits 900532 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3166.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 18998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency @@ -96,7 +98,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 33838925 # number of overall hits system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses @@ -149,21 +151,23 @@ system.cpu.fetch.branchRate 0.299421 # Nu system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 53041270 -system.cpu.fetch.rateDist.min_value 0 - 0 33206277 6260.46% - 1 1871594 352.86% - 2 1529415 288.34% - 3 1809626 341.17% - 4 3985239 751.35% - 5 1867239 352.04% - 6 695846 131.19% - 7 1111736 209.60% - 8 6964298 1313.00% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 53041270 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 33206277 62.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1871594 3.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1529415 2.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 1809626 3.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 3985239 7.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1867239 3.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 695846 1.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1111736 2.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6964298 13.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 53041270 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.947692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.940902 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency @@ -175,13 +179,13 @@ system.cpu.icache.ReadReq_mshr_hits 2770 # nu system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency @@ -200,7 +204,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 13297366 # number of overall hits system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses @@ -263,58 +267,54 @@ system.cpu.iew.predictedNotTakenIncorrect 106828 # N system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 85346345 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 47898565 56.12% # Type of FU issued - IntMult 42953 0.05% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 121655 0.14% # Type of FU issued - FloatCmp 88 0.00% # Type of FU issued - FloatCvt 122104 0.14% # Type of FU issued - FloatMult 53 0.00% # Type of FU issued - FloatDiv 38535 0.05% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 21753622 25.49% # Type of FU issued - MemWrite 15368770 18.01% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 47898565 56.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 42953 0.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 121655 0.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 88 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122104 0.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 53 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38535 0.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 21753622 25.49% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 15368770 18.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 85346345 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 97100 9.91% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 470602 48.04% # attempts to use FU when none available - MemWrite 411938 42.05% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 53041270 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86% -system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 53041270 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.609055 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.711333 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 97100 9.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 470602 48.04% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 411938 42.05% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 53041270 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 53041270 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.609055 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.711333 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued @@ -369,13 +369,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency @@ -394,7 +394,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 102894 # number of overall hits system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout index b076edccd..0cf74eb02 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:43:17 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:10:15 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index cd99a1a3e..cc2716377 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1524580 # Simulator instruction rate (inst/s) -host_mem_usage 213492 # Number of bytes of host memory used -host_seconds 57.94 # Real time elapsed on the host -host_tick_rate 2332726052 # Simulator tick rate (ticks/s) +host_inst_rate 2287584 # Simulator instruction rate (inst/s) +host_mem_usage 215192 # Number of bytes of host memory used +host_seconds 38.62 # Real time elapsed on the host +host_tick_rate 3500174868 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.135169 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 149793 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 50768.948371 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34679456 # number of overall hits system.cpu.dcache.overall_miss_latency 10689859000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 76436 # nu system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88361638 # number of overall hits system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses @@ -187,13 +187,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.630830 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -212,7 +212,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 93905 # number of overall hits system.cpu.l2cache.overall_miss_latency 9717500000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.665557 # miss rate for overall accesses diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout index 95fbb7b97..ccf7882ed 100755 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:15:57 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:31:17 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 067472342..9bb41084a 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1167251 # Simulator instruction rate (inst/s) -host_mem_usage 214304 # Number of bytes of host memory used -host_seconds 116.63 # Real time elapsed on the host -host_tick_rate 1743737825 # Simulator tick rate (ticks/s) +host_inst_rate 1881110 # Simulator instruction rate (inst/s) +host_mem_usage 216040 # Number of bytes of host memory used +host_seconds 72.37 # Real time elapsed on the host +host_tick_rate 2810156861 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136139203 # Number of instructions simulated sim_seconds 0.203377 # Number of seconds simulated @@ -38,13 +38,13 @@ system.cpu.dcache.WriteReq_misses 109405 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency @@ -63,7 +63,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57940701 # number of overall hits system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses @@ -91,13 +91,13 @@ system.cpu.icache.ReadReq_misses 187024 # nu system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency @@ -116,7 +116,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 134366560 # number of overall hits system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses @@ -165,13 +165,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 107279 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 1.433874 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -190,7 +190,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 192777 # number of overall hits system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index a3fed9503..d46e4c412 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:57:40 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:10:17 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index f9cc5dfc4..8a66d53b4 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 165473 # Simulator instruction rate (inst/s) -host_mem_usage 204148 # Number of bytes of host memory used -host_seconds 10491.39 # Real time elapsed on the host -host_tick_rate 70754150 # Simulator tick rate (ticks/s) +host_inst_rate 225916 # Simulator instruction rate (inst/s) +host_mem_usage 205860 # Number of bytes of host memory used +host_seconds 7684.48 # Real time elapsed on the host +host_tick_rate 96598522 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.742309 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 23750300 # Nu system.cpu.commit.COM:branches 214632552 # Number of branches committed system.cpu.commit.COM:bw_lim_events 62782585 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 1379215339 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 736540831 5340.29% - 1 260049504 1885.49% - 2 126970462 920.60% - 3 77723426 563.53% - 4 51327439 372.15% - 5 27759546 201.27% - 6 26179568 189.81% - 7 9881978 71.65% - 8 62782585 455.21% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 1379215339 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 736540831 53.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 260049504 18.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 126970462 9.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 77723426 5.64% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 51327439 3.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 27759546 2.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 26179568 1.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 9881978 0.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 62782585 4.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1379215339 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.319431 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.090314 # Number of insts commited each cycle system.cpu.commit.COM:count 1819780126 # Number of instructions committed system.cpu.commit.COM:loads 445666361 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -79,13 +81,13 @@ system.cpu.dcache.WriteReq_mshr_hits 3182477 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 83541376693 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2248527 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6337.465393 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 31613.485382 # average number of cycles each access was blocked system.cpu.dcache.avg_refs 73.053349 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 156253 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65330 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 990247980 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2065309000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 683988466 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 22764.945466 # average overall miss latency @@ -104,7 +106,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 683988466 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 22764.945466 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 17378.935401 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 668251814 # number of overall hits system.cpu.dcache.overall_miss_latency 358244024594 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses @@ -157,21 +159,23 @@ system.cpu.fetch.branchRate 0.232721 # Nu system.cpu.fetch.icacheStallCycles 355180518 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 336596037 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 1472299541 -system.cpu.fetch.rateDist.min_value 0 - 0 907273323 6162.29% - 1 47886355 325.25% - 2 34613456 235.10% - 3 52095475 353.84% - 4 125971058 855.61% - 5 69335096 470.93% - 6 50458684 342.72% - 7 40993758 278.43% - 8 143672336 975.84% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 1472299541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 907273323 61.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 47886355 3.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 34613456 2.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 52095475 3.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 125971058 8.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 69335096 4.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 50458684 3.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 40993758 2.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 143672336 9.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1472299541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.944609 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.837831 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 355180518 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency @@ -183,13 +187,13 @@ system.cpu.icache.ReadReq_mshr_hits 332 # nu system.cpu.icache.ReadReq_mshr_miss_latency 31989000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 393768.607539 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 355180518 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency @@ -208,7 +212,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 355180518 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 355179284 # number of overall hits system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses @@ -271,58 +275,54 @@ system.cpu.iew.predictedNotTakenIncorrect 703796 # N system.cpu.iew.predictedTakenIncorrect 20638338 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 2315844900 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 1532920254 66.19% # Type of FU issued - IntMult 99 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 234 0.00% # Type of FU issued - FloatCmp 20 0.00% # Type of FU issued - FloatCvt 143 0.00% # Type of FU issued - FloatMult 16 0.00% # Type of FU issued - FloatDiv 24 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 577889733 24.95% # Type of FU issued - MemWrite 205034377 8.85% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1532920254 66.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 99 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 234 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 20 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 143 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 577889733 24.95% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 205034377 8.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 2315844900 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 2738956 19.03% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 9224843 64.09% # attempts to use FU when none available - MemWrite 2429770 16.88% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 1472299541 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 577695763 39.24% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543756 18.44% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 242868170 16.50% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713874 9.49% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 122021082 8.29% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 69652698 4.73% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 39670196 2.69% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 8017828 0.54% -system.cpu.iq.ISSUE:issued_per_cycle::8 1116174 0.08% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 1472299541 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.572944 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.737325 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 2738956 19.03% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 9224843 64.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 2429770 16.88% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 1472299541 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 577695763 39.24% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 271543756 18.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 242868170 16.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 139713874 9.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 122021082 8.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 69652698 4.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39670196 2.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 8017828 0.54% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 1116174 0.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 1472299541 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.572944 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.737325 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate system.cpu.iq.iqInstsAdded 2492922509 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2315844900 # Number of instructions issued @@ -377,13 +377,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 363811 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2245449 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2245449 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11899.405570 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 2.417950 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 39818 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 473810531 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9160773 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency @@ -402,7 +402,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 9160773 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5387454 # number of overall hits system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout index 3314840b7..154e8b6b0 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:41:08 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:13:47 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 5f4f3edad..106a8a8a6 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1697488 # Simulator instruction rate (inst/s) -host_mem_usage 203260 # Number of bytes of host memory used -host_seconds 1072.04 # Real time elapsed on the host -host_tick_rate 2544665146 # Simulator tick rate (ticks/s) +host_inst_rate 2540644 # Simulator instruction rate (inst/s) +host_mem_usage 204972 # Number of bytes of host memory used +host_seconds 716.27 # Real time elapsed on the host +host_tick_rate 3808619272 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.727991 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 2247802 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 595853949 # number of overall hits system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 802 # nu system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1826377708 # number of overall hits system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses @@ -187,13 +187,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -212,7 +212,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5348043 # number of overall hits system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index aa3bb16f1..b190e5ac3 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:50:36 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:55 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:42:41 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index f81f1eda7..103b5bcb4 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1080301 # Simulator instruction rate (inst/s) -host_mem_usage 205584 # Number of bytes of host memory used -host_seconds 4307.30 # Real time elapsed on the host -host_tick_rate 1390213645 # Simulator tick rate (ticks/s) +host_inst_rate 1577505 # Simulator instruction rate (inst/s) +host_mem_usage 207544 # Number of bytes of host memory used +host_seconds 2949.71 # Real time elapsed on the host +host_tick_rate 2030054219 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4653176270 # Number of instructions simulated sim_seconds 5.988064 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 2247102 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 119096034000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005124 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 2247102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 183.099497 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1677713078 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 32368.922185 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 1677713078 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32368.922185 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 29368.922185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1668242528 # number of overall hits system.cpu.dcache.overall_miss_latency 306551496000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 675 # nu system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 5945529.207407 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 4013232890 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 4013232890 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4013232215 # number of overall hits system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 357472 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244013 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2244013 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 2.381201 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9113753 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 9113753 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5328546 # number of overall hits system.cpu.l2cache.overall_miss_latency 196830764000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.415329 # miss rate for overall accesses diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index e5f5aca9e..851652629 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:02:55 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:14:17 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index af7bb24bb..844d1a099 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 199037 # Simulator instruction rate (inst/s) -host_mem_usage 209432 # Number of bytes of host memory used -host_seconds 422.94 # Real time elapsed on the host -host_tick_rate 96512612 # Simulator tick rate (ticks/s) +host_inst_rate 205698 # Simulator instruction rate (inst/s) +host_mem_usage 211132 # Number of bytes of host memory used +host_seconds 409.24 # Real time elapsed on the host +host_tick_rate 99742770 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.040819 # Number of seconds simulated @@ -19,21 +19,23 @@ system.cpu.BPredUnit.usedRAS 1719783 # Nu system.cpu.commit.COM:branches 10240685 # Number of branches committed system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 73457197 -system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 36278942 4938.79% - 1 18156304 2471.68% - 2 7455517 1014.95% - 3 3880419 528.26% - 4 2046448 278.59% - 5 1301140 177.13% - 6 721823 98.26% - 7 760802 103.57% - 8 2855802 388.77% -system.cpu.commit.COM:committed_per_cycle.max_value 8 -system.cpu.commit.COM:committed_per_cycle.end_dist - +system.cpu.commit.COM:committed_per_cycle::samples 73457197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 36278942 49.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 18156304 24.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 7455517 10.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 3880419 5.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2046448 2.79% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 1301140 1.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 721823 0.98% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 760802 1.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2855802 3.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 73457197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.251110 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.949680 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed system.cpu.commit.COM:loads 20034413 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -71,13 +73,13 @@ system.cpu.dcache.WriteReq_mshr_hits 6453 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2649.700000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 26497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency @@ -96,7 +98,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 29894354 # number of overall hits system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses @@ -149,21 +151,23 @@ system.cpu.fetch.branchRate 0.238476 # Nu system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle -system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 81528343 -system.cpu.fetch.rateDist.min_value 0 - 0 50560378 6201.57% - 1 3114212 381.98% - 2 2012618 246.86% - 3 3505366 429.96% - 4 4590613 563.07% - 5 1506961 184.84% - 6 2028359 248.79% - 7 1846743 226.52% - 8 12363093 1516.42% -system.cpu.fetch.rateDist.max_value 8 -system.cpu.fetch.rateDist.end_dist - +system.cpu.fetch.rateDist::samples 81528343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 50560378 62.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 3114212 3.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 2012618 2.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 3505366 4.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 4590613 5.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1506961 1.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 2028359 2.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1846743 2.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12363093 15.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 81528343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.055174 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.061669 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency @@ -175,13 +179,13 @@ system.cpu.icache.ReadReq_mshr_hits 982 # nu system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency @@ -200,7 +204,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 19218965 # number of overall hits system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses @@ -263,58 +267,54 @@ system.cpu.iew.predictedNotTakenIncorrect 218646 # N system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 7 0.00% # Type of FU issued - IntAlu 64430040 61.93% # Type of FU issued - IntMult 475055 0.46% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2782164 2.67% # Type of FU issued - FloatCmp 115645 0.11% # Type of FU issued - FloatCvt 2377276 2.29% # Type of FU issued - FloatMult 305748 0.29% # Type of FU issued - FloatDiv 755245 0.73% # Type of FU issued - FloatSqrt 323 0.00% # Type of FU issued - MemRead 25462424 24.48% # Type of FU issued - MemWrite 7324714 7.04% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 64430040 61.93% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 475055 0.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2782164 2.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 115645 0.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2377276 2.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 305748 0.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755245 0.73% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 25462424 24.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7324714 7.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 104028641 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 274346 14.19% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 31 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 6547 0.34% # attempts to use FU when none available - FloatMult 2333 0.12% # attempts to use FU when none available - FloatDiv 832912 43.09% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 743147 38.44% # attempts to use FU when none available - MemWrite 73812 3.82% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 81528343 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 35305774 43.30% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 18904885 23.19% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 11574997 14.20% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 6762756 8.29% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 5075415 6.23% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2394533 2.94% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1208963 1.48% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 250769 0.31% -system.cpu.iq.ISSUE:issued_per_cycle::8 50251 0.06% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 81528343 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.275981 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540298 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 274346 14.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 31 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 6547 0.34% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 2333 0.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 832912 43.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 743147 38.44% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 73812 3.82% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 81528343 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 35305774 43.30% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 18904885 23.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 11574997 14.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 6762756 8.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 5075415 6.23% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2394533 2.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1208963 1.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 250769 0.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 50251 0.06% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 81528343 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.275981 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540298 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued @@ -369,13 +369,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 3000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency @@ -394,7 +394,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 7186 # number of overall hits system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout index 977b57eee..723d89b16 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:51:59 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:16:45 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 369af5305..557fc7bf7 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2784324 # Simulator instruction rate (inst/s) -host_mem_usage 208188 # Number of bytes of host memory used -host_seconds 33.01 # Real time elapsed on the host -host_tick_rate 3597581254 # Simulator tick rate (ticks/s) +host_inst_rate 2678753 # Simulator instruction rate (inst/s) +host_mem_usage 209892 # Number of bytes of host memory used +host_seconds 34.31 # Real time elapsed on the host +host_tick_rate 3461170696 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118747 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 1859 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26494967 # number of overall hits system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 8510 # nu system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 91894580 # number of overall hits system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses @@ -187,13 +187,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -212,7 +212,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 5942 # number of overall hits system.cpu.l2cache.overall_miss_latency 249132000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.446380 # miss rate for overall accesses diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout index ac7620094..4ba32ea3a 100755 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:07:46 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:32:30 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt index c019fdbed..ce58f98ef 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1335116 # Simulator instruction rate (inst/s) -host_mem_usage 209936 # Number of bytes of host memory used -host_seconds 144.89 # Real time elapsed on the host -host_tick_rate 1867472873 # Simulator tick rate (ticks/s) +host_inst_rate 1857648 # Simulator instruction rate (inst/s) +host_mem_usage 211672 # Number of bytes of host memory used +host_seconds 104.13 # Real time elapsed on the host +host_tick_rate 2598354088 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193444769 # Number of instructions simulated sim_seconds 0.270578 # Number of seconds simulated @@ -38,13 +38,13 @@ system.cpu.dcache.WriteReq_misses 1101 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency @@ -63,7 +63,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 76709909 # number of overall hits system.cpu.dcache.overall_miss_latency 89544000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses @@ -91,13 +91,13 @@ system.cpu.icache.ReadReq_misses 12288 # nu system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency @@ -116,7 +116,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 193433261 # number of overall hits system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses @@ -165,13 +165,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 2.134332 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 13864 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -190,7 +190,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8691 # number of overall hits system.cpu.l2cache.overall_miss_latency 268996000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.373125 # miss rate for overall accesses diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index c109ece93..ddb53fb83 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,11 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:54:37 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:55 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:46:04 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index 558f7df88..f9e29c4be 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1114702 # Simulator instruction rate (inst/s) -host_mem_usage 212960 # Number of bytes of host memory used -host_seconds 196.10 # Real time elapsed on the host -host_tick_rate 1279666495 # Simulator tick rate (ticks/s) +host_inst_rate 1679742 # Simulator instruction rate (inst/s) +host_mem_usage 214928 # Number of bytes of host memory used +host_seconds 130.14 # Real time elapsed on the host +host_tick_rate 1928325538 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 218595312 # Number of instructions simulated sim_seconds 0.250946 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 1601 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 77163409 # number of overall hits system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 4694 # nu system.cpu.icache.ReadReq_mshr_miss_latency 170919000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 4694 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 36959.880912 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 173494375 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 39412.334896 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 173494375 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 39412.334896 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 36412.228377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 173489681 # number of overall hits system.cpu.icache.overall_miss_latency 185001500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.591895 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 6588 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52001.373336 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 6588 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52001.373336 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1855 # number of overall hits system.cpu.l2cache.overall_miss_latency 246122500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.718427 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index a47274398..e252a511f 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:57:23 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:20 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index d9c15b30b..da7fb5f85 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 118345 # Simulator instruction rate (inst/s) -host_mem_usage 200916 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 230331062 # Simulator tick rate (ticks/s) +host_inst_rate 98931 # Simulator instruction rate (inst/s) +host_mem_usage 202620 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 192504745 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -71,13 +71,13 @@ system.cpu.dcache.WriteReq_mshr_hits 293 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency @@ -96,7 +96,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 2104 # number of overall hits system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses @@ -177,13 +177,13 @@ system.cpu.icache.ReadReq_mshr_hits 117 # nu system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency @@ -202,7 +202,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1378 # number of overall hits system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses @@ -265,58 +265,54 @@ system.cpu.iew.predictedNotTakenIncorrect 290 # N system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 9345 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 2 0.02% # Type of FU issued - IntAlu 6254 66.92% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 1986 21.25% # Type of FU issued - MemWrite 1100 11.77% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6254 66.92% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1986 21.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1100 11.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 9345 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 14 13.33% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 56 53.33% # attempts to use FU when none available - MemWrite 35 33.33% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% -system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 13314 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 14 13.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 56 53.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 35 33.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 13314 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued @@ -369,13 +365,13 @@ system.cpu.l2cache.UpgradeReq_misses 14 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency @@ -394,7 +390,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout index 15dc4382a..9f3354a73 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:52:32 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:21 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt index 1153fe460..fcff4ad2a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 457919 # Simulator instruction rate (inst/s) -host_mem_usage 200100 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 2381009446 # Simulator tick rate (ticks/s) +host_inst_rate 244055 # Simulator instruction rate (inst/s) +host_mem_usage 201804 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 1274748085 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000034 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 87 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1868 # number of overall hits system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 279 # nu system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6136 # number of overall hits system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses @@ -185,13 +185,13 @@ system.cpu.l2cache.UpgradeReq_misses 14 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -210,7 +210,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 63832f049..ac3d159cd 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:11 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:21 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 98d731942..2fa8bf1eb 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 48067 # Simulator instruction rate (inst/s) -host_mem_usage 199912 # Number of bytes of host memory used +host_inst_rate 51063 # Simulator instruction rate (inst/s) +host_mem_usage 201612 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 143884460 # Simulator tick rate (ticks/s) +host_tick_rate 152859058 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -19,23 +19,23 @@ system.cpu.BPredUnit.usedRAS 165 # Nu system.cpu.commit.COM:branches 396 # Number of branches committed system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6197 -system.cpu.commit.COM:committed_per_cycle::min_value 0 -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::0-1 5240 84.56% -system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% -system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% -system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% -system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% -system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% -system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% -system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% -system.cpu.commit.COM:committed_per_cycle::8 38 0.61% -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::total 6197 -system.cpu.commit.COM:committed_per_cycle::max_value 8 -system.cpu.commit.COM:committed_per_cycle::mean 0.415685 -system.cpu.commit.COM:committed_per_cycle::stdev 1.207973 +system.cpu.commit.COM:committed_per_cycle::samples 6197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 5240 84.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 38 0.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 6197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.415685 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.207973 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -71,13 +71,13 @@ system.cpu.dcache.WriteReq_mshr_hits 70 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency @@ -96,7 +96,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 674 # number of overall hits system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses @@ -177,13 +177,13 @@ system.cpu.icache.ReadReq_mshr_hits 54 # nu system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency @@ -202,7 +202,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 512 # number of overall hits system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses @@ -265,58 +265,54 @@ system.cpu.iew.predictedNotTakenIncorrect 97 # N system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 2506 71.31% # Type of FU issued - IntMult 1 0.03% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 639 18.18% # Type of FU issued - MemWrite 368 10.47% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2506 71.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 639 18.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 368 10.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 3514 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 2.94% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11 32.35% # attempts to use FU when none available - MemWrite 22 64.71% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% -system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 6528 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.94% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 11 32.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 22 64.71% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 6528 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued @@ -368,13 +364,13 @@ system.cpu.l2cache.UpgradeReq_misses 14 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency @@ -393,7 +389,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout index 82648883e..103381b7c 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:59:01 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:22 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt index d6291acb4..72ee5d06d 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 164528 # Simulator instruction rate (inst/s) -host_mem_usage 199264 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1091811726 # Simulator tick rate (ticks/s) +host_inst_rate 89461 # Simulator instruction rate (inst/s) +host_mem_usage 200972 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 597928210 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 38 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 616 # number of overall hits system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 163 # nu system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2423 # number of overall hits system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses @@ -184,13 +184,13 @@ system.cpu.l2cache.UpgradeReq_misses 11 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -209,7 +209,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 4849c504d..f62e2f8fb 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:01:16 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:01:42 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:36 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:19:48 +M5 executing on maize command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index abebc01ef..5137cef3d 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 62820 # Simulator instruction rate (inst/s) -host_mem_usage 202152 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 173066613 # Simulator tick rate (ticks/s) +host_inst_rate 69701 # Simulator instruction rate (inst/s) +host_mem_usage 203728 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 191895105 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5024 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -71,13 +71,13 @@ system.cpu.dcache.WriteReq_mshr_hits 226 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 2310000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 20.970370 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 3210 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 29612.709832 # average overall miss latency @@ -96,7 +96,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 3210 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 29612.709832 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36060 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 2793 # number of overall hits system.cpu.dcache.overall_miss_latency 12348500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.129907 # miss rate for overall accesses @@ -169,13 +169,13 @@ system.cpu.icache.ReadReq_mshr_hits 101 # nu system.cpu.icache.ReadReq_mshr_miss_latency 11522000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.152636 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 5.245455 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2162 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 35500 # average overall miss latency @@ -194,7 +194,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 2162 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 35500 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1731 # number of overall hits system.cpu.icache.overall_miss_latency 15300500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.199352 # miss rate for overall accesses @@ -257,58 +257,54 @@ system.cpu.iew.predictedNotTakenIncorrect 276 # N system.cpu.iew.predictedTakenIncorrect 385 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.180954 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.180954 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8620 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 4988 57.87% # Type of FU issued - IntMult 5 0.06% # Type of FU issued - IntDiv 2 0.02% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 2560 29.70% # Type of FU issued - MemWrite 1063 12.33% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 4988 57.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2560 29.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1063 12.33% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 8620 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.018794 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 10 6.17% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 98 60.49% # attempts to use FU when none available - MemWrite 54 33.33% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 15217 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 11370 74.72% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1673 10.99% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 787 5.17% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 717 4.71% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 332 2.18% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 198 1.30% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.60% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.22% -system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 15217 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566472 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217507 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 10 6.17% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 98 60.49% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 15217 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 11370 74.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1673 10.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 787 5.17% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 717 4.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 332 2.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 198 1.30% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 15217 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566472 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217507 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.310474 # Inst issue rate system.cpu.iq.iqInstsAdded 9773 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 8620 # Number of instructions issued @@ -353,13 +349,13 @@ system.cpu.l2cache.UpgradeReq_misses 15 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 467500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.010076 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 465 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34350.325380 # average overall miss latency @@ -378,7 +374,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 465 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34350.325380 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31159.436009 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits system.cpu.l2cache.overall_miss_latency 15835500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.991398 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout index f10279373..7d691a50e 100755 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:01:16 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:01:42 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:36 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:19:48 +M5 executing on maize command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt index caa6f8c7b..8e4a1aeed 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 35646 # Simulator instruction rate (inst/s) -host_mem_usage 201368 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -host_tick_rate 203367436 # Simulator tick rate (ticks/s) +host_inst_rate 198393 # Simulator instruction rate (inst/s) +host_mem_usage 202876 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 1123305762 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000032 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 64 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1908 # number of overall hits system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses @@ -90,13 +90,13 @@ system.cpu.icache.ReadReq_misses 303 # nu system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency @@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses @@ -171,13 +171,13 @@ system.cpu.l2cache.UpgradeReq_misses 14 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.005420 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -196,7 +196,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout index 156edd943..788a84f52 100755 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:14:35 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:32:52 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt index 185c6fd8b..2f90cc999 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 333292 # Simulator instruction rate (inst/s) -host_mem_usage 201348 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1783998034 # Simulator tick rate (ticks/s) +host_inst_rate 165633 # Simulator instruction rate (inst/s) +host_mem_usage 203084 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 893371492 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5340 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 96 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1239 # number of overall hits system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 257 # nu system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5127 # number of overall hits system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses @@ -153,13 +153,13 @@ system.cpu.l2cache.UpgradeReq_misses 15 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -178,7 +178,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index b776401d1..869d0cef1 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:57:54 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:55 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:48:15 +M5 executing on maize command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index fa5ab8e26..b46b73886 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 426927 # Simulator instruction rate (inst/s) -host_mem_usage 201388 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1322141682 # Simulator tick rate (ticks/s) +host_inst_rate 183914 # Simulator instruction rate (inst/s) +host_mem_usage 203340 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 573138759 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9494 # Number of instructions simulated sim_seconds 0.000030 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 98 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 13.939850 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1987 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 1987 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1835 # number of overall hits system.cpu.dcache.overall_miss_latency 8512000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.076497 # miss rate for overall accesses @@ -81,13 +81,13 @@ system.cpu.icache.ReadReq_misses 228 # nu system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.033106 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 29.206140 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 6887 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency @@ -106,7 +106,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 6887 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6659 # number of overall hits system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.033106 # miss rate for overall accesses @@ -153,13 +153,13 @@ system.cpu.l2cache.UpgradeReq_misses 19 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.003817 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 361 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -178,7 +178,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 361 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_miss_latency 18720000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997230 # miss rate for overall accesses diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index a796d7912..7545f2cff 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:11 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:23 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 06def78dc..3a5ef660d 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 75551 # Simulator instruction rate (inst/s) -host_mem_usage 201440 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 84168035 # Simulator tick rate (ticks/s) +host_inst_rate 105048 # Simulator instruction rate (inst/s) +host_mem_usage 203136 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 116961296 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -16,13 +16,13 @@ system.cpu.BPredUnit.condIncorrect 1595 # Nu system.cpu.BPredUnit.condPredicted 3153 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 5548 # Number of BP lookups system.cpu.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 2102 # Number of branches committed -system.cpu.commit.COM:branches_0 1051 # Number of branches committed -system.cpu.commit.COM:branches_1 1051 # Number of branches committed +system.cpu.commit.COM:branches::0 1051 # Number of branches committed +system.cpu.commit.COM:branches::1 1051 # Number of branches committed +system.cpu.commit.COM:branches::total 2102 # Number of branches committed system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached -system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle::samples 22838 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle @@ -40,168 +40,168 @@ system.cpu.commit.COM:committed_per_cycle::total 22838 system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::mean 0.560776 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 1.272228 # Number of insts commited each cycle -system.cpu.commit.COM:count 12807 # Number of instructions committed -system.cpu.commit.COM:count_0 6403 # Number of instructions committed -system.cpu.commit.COM:count_1 6404 # Number of instructions committed -system.cpu.commit.COM:loads 2370 # Number of loads committed -system.cpu.commit.COM:loads_0 1185 # Number of loads committed -system.cpu.commit.COM:loads_1 1185 # Number of loads committed -system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed -system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 4100 # Number of memory references committed -system.cpu.commit.COM:refs_0 2050 # Number of memory references committed -system.cpu.commit.COM:refs_1 2050 # Number of memory references committed -system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed -system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed +system.cpu.commit.COM:count::0 6403 # Number of instructions committed +system.cpu.commit.COM:count::1 6404 # Number of instructions committed +system.cpu.commit.COM:count::total 12807 # Number of instructions committed +system.cpu.commit.COM:loads::0 1185 # Number of loads committed +system.cpu.commit.COM:loads::1 1185 # Number of loads committed +system.cpu.commit.COM:loads::total 2370 # Number of loads committed +system.cpu.commit.COM:membars::0 0 # Number of memory barriers committed +system.cpu.commit.COM:membars::1 0 # Number of memory barriers committed +system.cpu.commit.COM:membars::total 0 # Number of memory barriers committed +system.cpu.commit.COM:refs::0 2050 # Number of memory references committed +system.cpu.commit.COM:refs::1 2050 # Number of memory references committed +system.cpu.commit.COM:refs::total 4100 # Number of memory references committed +system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 6386 # Number of Instructions Simulated -system.cpu.committedInsts_1 6387 # Number of Instructions Simulated +system.cpu.committedInsts::0 6386 # Number of Instructions Simulated +system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi_0 4.463514 # CPI: Cycles Per Instruction -system.cpu.cpi_1 4.462815 # CPI: Cycles Per Instruction +system.cpu.cpi::0 4.463514 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.462815 # CPI: Cycles Per Instruction system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3925 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 35473.913043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 36849.514563 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 3580 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.087898 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 345 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.052484 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 206 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 206 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 33703.947368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 36103.448276 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 25615000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 25615000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.439306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 760 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 6282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100578 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_accesses::0 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3925 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 35473.913043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36849.514563 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits::0 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3580 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::0 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12238500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.087898 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 345 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::0 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7591000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.052484 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::0 206 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 206 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 33703.947368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36103.448276 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits::0 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 970 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::0 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.439306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 760 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::0 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 5655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 34256.561086 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 4550 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 37853500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 37853500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.195402 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 1105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 725 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 725 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 13873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.067197 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 380 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 380 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses::0 5655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5655 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 34256.561086 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 4550 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4550 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::0 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.195402 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 1105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1105 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::0 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::0 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.067197 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::0 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 5655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 34256.561086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 36507.894737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4550 # number of overall hits -system.cpu.dcache.overall_hits_0 4550 # number of overall hits -system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 37853500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 37853500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.195402 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 1105 # number of overall misses -system.cpu.dcache.overall_misses_0 1105 # number of overall misses -system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 725 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 725 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13873000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 13873000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.067197 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 380 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 380 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.replacements_0 0 # number of replacements -system.cpu.dcache.replacements_1 0 # number of replacements +system.cpu.dcache.overall_accesses::0 5655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5655 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 34256.561086 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits::0 4550 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 4550 # number of overall hits +system.cpu.dcache.overall_miss_latency::0 37853500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 37853500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.195402 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 1105 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 1105 # number of overall misses +system.cpu.dcache.overall_mshr_hits::0 725 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 725 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::0 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.067197 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::0 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements::0 0 # number of replacements +system.cpu.dcache.replacements::1 0 # number of replacements +system.cpu.dcache.replacements::total 0 # number of replacements system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.writebacks_0 0 # number of writebacks -system.cpu.dcache.writebacks_1 0 # number of writebacks +system.cpu.dcache.writebacks::0 0 # number of writebacks +system.cpu.dcache.writebacks::1 0 # number of writebacks +system.cpu.dcache.writebacks::total 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 5063 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch @@ -254,166 +254,166 @@ system.cpu.fetch.rateDist::total 22904 # Nu system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.351249 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.742840 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 4113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 35793.697979 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 35516.155089 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 3272 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.204474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 841 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.150498 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.ReadReq_accesses::0 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4113 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 35793.697979 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35516.155089 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3272 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::0 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30102500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.204474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 841 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 841 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits::0 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency::0 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21984500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.150498 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::0 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 619 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 4113 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 35793.697979 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 3272 # number of demand (read+write) hits -system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 30102500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 30102500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.204474 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 841 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 841 # number of demand (read+write) misses -system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 222 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 222 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 21984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.150498 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses::0 4113 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4113 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 35793.697979 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.icache.demand_hits::0 3272 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3272 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::0 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.204474 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 841 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 841 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits::0 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency::0 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.150498 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 619 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 4113 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 35793.697979 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 35516.155089 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3272 # number of overall hits -system.cpu.icache.overall_hits_0 3272 # number of overall hits -system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 30102500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 30102500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.204474 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 841 # number of overall misses -system.cpu.icache.overall_misses_0 841 # number of overall misses -system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 222 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 222 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 21984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.150498 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 6 # number of replacements -system.cpu.icache.replacements_0 6 # number of replacements -system.cpu.icache.replacements_1 0 # number of replacements +system.cpu.icache.overall_accesses::0 4113 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4113 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 35793.697979 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits::0 3272 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 3272 # number of overall hits +system.cpu.icache.overall_miss_latency::0 30102500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30102500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.204474 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 841 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 841 # number of overall misses +system.cpu.icache.overall_mshr_hits::0 222 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 222 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency::0 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.150498 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements::0 6 # number of replacements +system.cpu.icache.replacements::1 0 # number of replacements +system.cpu.icache.replacements::total 6 # number of replacements system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use system.cpu.icache.total_refs 3272 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.writebacks_0 0 # number of writebacks -system.cpu.icache.writebacks_1 0 # number of writebacks +system.cpu.icache.writebacks::0 0 # number of writebacks +system.cpu.icache.writebacks::1 0 # number of writebacks +system.cpu.icache.writebacks::total 0 # number of writebacks system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3160 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1573 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1587 # Number of branches executed -system.cpu.iew.EXEC:nop 135 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 70 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 65 # number of nop insts executed +system.cpu.iew.EXEC:branches::0 1573 # Number of branches executed +system.cpu.iew.EXEC:branches::1 1587 # Number of branches executed +system.cpu.iew.EXEC:branches::total 3160 # Number of branches executed +system.cpu.iew.EXEC:nop::0 70 # number of nop insts executed +system.cpu.iew.EXEC:nop::1 65 # number of nop insts executed +system.cpu.iew.EXEC:nop::total 135 # number of nop insts executed system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate -system.cpu.iew.EXEC:refs 6321 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 3132 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 3189 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2175 # Number of stores executed -system.cpu.iew.EXEC:stores_0 1090 # Number of stores executed -system.cpu.iew.EXEC:stores_1 1085 # Number of stores executed -system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed -system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 11901 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5984 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5917 # num instructions consuming a value -system.cpu.iew.WB:count 18426 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 9221 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 9205 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.552811 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.776404 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.776407 # average fanout of values written-back -system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 9240 # num instructions producing a value -system.cpu.iew.WB:producers_0 4646 # num instructions producing a value -system.cpu.iew.WB:producers_1 4594 # num instructions producing a value -system.cpu.iew.WB:rate 0.646436 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.323498 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.322937 # insts written-back per cycle -system.cpu.iew.WB:sent 18664 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 9324 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 9340 # cumulative count of insts sent to commit +system.cpu.iew.EXEC:refs::0 3132 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::1 3189 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::total 6321 # number of memory reference insts executed +system.cpu.iew.EXEC:stores::0 1090 # Number of stores executed +system.cpu.iew.EXEC:stores::1 1085 # Number of stores executed +system.cpu.iew.EXEC:stores::total 2175 # Number of stores executed +system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed +system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed +system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed +system.cpu.iew.WB:consumers::0 5984 # num instructions consuming a value +system.cpu.iew.WB:consumers::1 5917 # num instructions consuming a value +system.cpu.iew.WB:consumers::total 11901 # num instructions consuming a value +system.cpu.iew.WB:count::0 9221 # cumulative count of insts written-back +system.cpu.iew.WB:count::1 9205 # cumulative count of insts written-back +system.cpu.iew.WB:count::total 18426 # cumulative count of insts written-back +system.cpu.iew.WB:fanout::0 0.776404 # average fanout of values written-back +system.cpu.iew.WB:fanout::1 0.776407 # average fanout of values written-back +system.cpu.iew.WB:fanout::total 1.552811 # average fanout of values written-back +system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers::0 4646 # num instructions producing a value +system.cpu.iew.WB:producers::1 4594 # num instructions producing a value +system.cpu.iew.WB:producers::total 9240 # num instructions producing a value +system.cpu.iew.WB:rate::0 0.323498 # insts written-back per cycle +system.cpu.iew.WB:rate::1 0.322937 # insts written-back per cycle +system.cpu.iew.WB:rate::total 0.646436 # insts written-back per cycle +system.cpu.iew.WB:sent::0 9324 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::1 9340 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::total 18664 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions @@ -421,9 +421,9 @@ system.cpu.iew.iewDispNonSpecInsts 44 # Nu system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 4146 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 2042 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 2104 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::0 2042 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2104 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4146 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall @@ -454,99 +454,91 @@ system.cpu.iew.lsq.thread.1.squashedStores 438 # system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.224039 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.224074 # IPC: Instructions Per Cycle +system.cpu.ipc::0 0.224039 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.224074 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 10179 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 2 0.02% # Type of FU issued - IntAlu 6830 67.10% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 2173 21.35% # Type of FU issued - MemWrite 1171 11.50% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 10211 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1.start_dist - No_OpClass 2 0.02% # Type of FU issued - IntAlu 6842 67.01% # Type of FU issued - IntMult 1 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 2230 21.84% # Type of FU issued - MemWrite 1134 11.11% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 20390 # Type of FU issued -system.cpu.iq.ISSUE:FU_type.start_dist - No_OpClass 4 0.02% # Type of FU issued - IntAlu 13672 67.05% # Type of FU issued - IntMult 2 0.01% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 4 0.02% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 4403 21.59% # Type of FU issued - MemWrite 2305 11.30% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 172 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 87 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 85 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.008436 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004267 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.004169 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 13 7.56% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 96 55.81% # attempts to use FU when none available - MemWrite 63 36.63% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% -system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 22904 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6830 67.10% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2173 21.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1171 11.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 10179 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntAlu 6842 67.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemRead 2230 21.84% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemWrite 1134 11.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::total 10211 # Type of FU issued +system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntAlu 13672 67.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemRead 4403 21.59% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemWrite 2305 11.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::total 20390 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt::0 87 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::total 172 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::1 0.004169 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::total 0.008436 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 13 7.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 96 55.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 63 36.63% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 22904 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued @@ -571,151 +563,151 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses_0 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 34643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 31589.041096 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses_0 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4612000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 4612000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses_0 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 34555.285541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 31414.337789 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.997576 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 823 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 823 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses_0 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 34482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 31357.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 965500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 965500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses_0 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 878000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 878000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses_0 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs 6750 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_accesses::0 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31589.041096 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::0 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::0 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 825 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34555.285541 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31414.337789 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits::0 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::0 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::0 0.997576 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::0 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25854000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997576 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::0 823 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses::0 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34482.142857 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31357.142857 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency::0 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses::0 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 28 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 4 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 27000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 34568.627451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 33497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 33497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997940 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 30466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 30466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_accesses::0 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::0 34568.627451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.demand_hits::0 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::0 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::0 0.997940 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.l2cache.demand_misses::0 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::0 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::0 0.997940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::0 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 34568.627451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 31440.660475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_hits_0 2 # number of overall hits -system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 33497000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 33497000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997940 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 969 # number of overall misses -system.cpu.l2cache.overall_misses_0 969 # number of overall misses -system.cpu.l2cache.overall_misses_1 0 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 30466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 30466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.replacements_0 0 # number of replacements -system.cpu.l2cache.replacements_1 0 # number of replacements +system.cpu.l2cache.overall_accesses::0 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::0 34568.627451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits::0 2 # number of overall hits +system.cpu.l2cache.overall_hits::1 0 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.overall_miss_latency::0 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::0 0.997940 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.l2cache.overall_misses::0 969 # number of overall misses +system.cpu.l2cache.overall_misses::1 0 # number of overall misses +system.cpu.l2cache.overall_misses::total 969 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::0 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::0 0.997940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::0 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.replacements::0 0 # number of replacements +system.cpu.l2cache.replacements::1 0 # number of replacements +system.cpu.l2cache.replacements::total 0 # number of replacements system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.writebacks_0 0 # number of writebacks -system.cpu.l2cache.writebacks_1 0 # number of writebacks +system.cpu.l2cache.writebacks::0 0 # number of writebacks +system.cpu.l2cache.writebacks::1 0 # number of writebacks +system.cpu.l2cache.writebacks::total 0 # number of writebacks system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 34998e971..4f7aebff8 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:05:07 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:32:52 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 3e04b78ab..a3713da81 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 47616 # Simulator instruction rate (inst/s) -host_mem_usage 201812 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 91393866 # Simulator tick rate (ticks/s) +host_inst_rate 75091 # Simulator instruction rate (inst/s) +host_mem_usage 203556 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host +host_tick_rate 144061639 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated @@ -73,13 +73,13 @@ system.cpu.dcache.WriteReq_mshr_hits 341 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency @@ -98,7 +98,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 4728 # number of overall hits system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses @@ -160,13 +160,13 @@ system.cpu.icache.ReadReq_mshr_hits 176 # nu system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency @@ -185,7 +185,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 6821 # number of overall hits system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses @@ -248,58 +248,54 @@ system.cpu.iew.predictedNotTakenIncorrect 758 # N system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 21395 73.22% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 4720 16.15% # Type of FU issued - MemWrite 3105 10.63% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 21395 73.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 4720 16.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 3105 10.63% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 29220 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 40 23.12% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 20 11.56% # attempts to use FU when none available - MemWrite 113 65.32% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full.end_dist -system.cpu.iq.ISSUE:issued_per_cycle::samples 47090 -system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::0-1 34112 72.44% -system.cpu.iq.ISSUE:issued_per_cycle::1-2 5516 11.71% -system.cpu.iq.ISSUE:issued_per_cycle::2-3 3070 6.52% -system.cpu.iq.ISSUE:issued_per_cycle::3-4 2146 4.56% -system.cpu.iq.ISSUE:issued_per_cycle::4-5 997 2.12% -system.cpu.iq.ISSUE:issued_per_cycle::5-6 653 1.39% -system.cpu.iq.ISSUE:issued_per_cycle::6-7 342 0.73% -system.cpu.iq.ISSUE:issued_per_cycle::7-8 211 0.45% -system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% -system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu.iq.ISSUE:issued_per_cycle::total 47090 -system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.620514 -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.275912 +system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 40 23.12% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 20 11.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 113 65.32% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:issued_per_cycle::samples 47090 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 34112 72.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 5516 11.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 3070 6.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 2146 4.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 997 2.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 653 1.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 342 0.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 211 0.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 47090 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.620514 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.275912 # Number of insts issued each cycle system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued @@ -336,13 +332,13 @@ system.cpu.l2cache.UpgradeReq_misses 19 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency @@ -361,7 +357,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index 4ea7967d3..76cbb3c5f 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:15:57 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:32:53 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 43fac0d7a..5c475dff1 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 347867 # Simulator instruction rate (inst/s) -host_mem_usage 201056 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 973883913 # Simulator tick rate (ticks/s) +host_inst_rate 286976 # Simulator instruction rate (inst/s) +host_mem_usage 202788 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 804151064 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000043 # Number of seconds simulated @@ -30,13 +30,13 @@ system.cpu.dcache.WriteReq_misses 102 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency @@ -55,7 +55,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 3513 # number of overall hits system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses @@ -83,13 +83,13 @@ system.cpu.icache.ReadReq_misses 280 # nu system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency @@ -108,7 +108,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 14941 # number of overall hits system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses @@ -155,13 +155,13 @@ system.cpu.l2cache.UpgradeReq_misses 17 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -180,7 +180,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 1c7915c5e..d4eeca11f 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 17:45:48 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:54:58 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:24 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:27 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 7757176f7..ee7ad5474 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2919011 # Simulator instruction rate (inst/s) -host_mem_usage 293452 # Number of bytes of host memory used -host_seconds 21.64 # Real time elapsed on the host -host_tick_rate 86446798213 # Simulator tick rate (ticks/s) +host_inst_rate 4288852 # Simulator instruction rate (inst/s) +host_mem_usage 294988 # Number of bytes of host memory used +host_seconds 14.73 # Real time elapsed on the host +host_tick_rate 127013871331 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -24,17 +24,17 @@ system.cpu0.dcache.WriteReq_accesses 5748261 # nu system.cpu0.dcache.WriteReq_hits 5374453 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_rate 0.065030 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 373808 # number of WriteReq misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 14729930 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.demand_hits 12672559 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_rate 0.139673 # miss rate for demand accesses @@ -48,8 +48,8 @@ system.cpu0.dcache.mshr_cap_events 0 # nu system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.overall_accesses 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.overall_hits 12672559 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.139673 # miss rate for overall accesses @@ -87,17 +87,17 @@ system.cpu0.icache.ReadReq_accesses 57230132 # nu system.cpu0.icache.ReadReq_hits 56345132 # number of ReadReq hits system.cpu0.icache.ReadReq_miss_rate 0.015464 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses 885000 # number of ReadReq misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 57230132 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.icache.demand_hits 56345132 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.015464 # miss rate for demand accesses @@ -111,8 +111,8 @@ system.cpu0.icache.mshr_cap_events 0 # nu system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.overall_accesses 57230132 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 56345132 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.015464 # miss rate for overall accesses @@ -147,95 +147,95 @@ system.cpu0.itb.write_accesses 0 # DT system.cpu0.itb.write_acv 0 # DTB write access violations system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.kern.callpal 183291 # number of callpals executed -system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3762 2.05% 2.11% # number of callpals executed -system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168035 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed -system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::cserve 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wripir 110 0.06% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3762 2.05% # number of callpals executed +system.cpu0.kern.callpal::tbi 38 0.02% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% # number of callpals executed +system.cpu0.kern.callpal::swpipl 168035 91.68% # number of callpals executed +system.cpu0.kern.callpal::rdps 6150 3.36% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4673 2.55% # number of callpals executed +system.cpu0.kern.callpal::callsys 357 0.19% # number of callpals executed +system.cpu0.kern.callpal::imb 142 0.08% # number of callpals executed +system.cpu0.kern.callpal::total 183291 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174868 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 71004 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101705 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 141425 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.980748 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684617 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1157 -system.cpu0.kern.mode_good_user 1158 -system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7091 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.163165 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.ipl_count::0 71004 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 243 0.14% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1908 1.09% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 8 0.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 101705 58.16% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69637 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 243 0.17% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1908 1.35% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 8 0.01% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 69629 49.23% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 20110000 0.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 82044000 0.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 949500 0.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 17242445000 0.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1157 +system.cpu0.kern.mode_good::user 1158 +system.cpu0.kern.mode_good::idle 0 +system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 957009000 0.05% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 0 0.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3763 # number of times the context was actually changed -system.cpu0.kern.syscall 226 # number of syscalls executed -system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed -system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed -system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed -system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed -system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed -system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed -system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed -system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed -system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed -system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed -system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed -system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed -system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed -system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed -system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::2 6 2.65% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.41% # number of syscalls executed +system.cpu0.kern.syscall::4 2 0.88% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.16% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.44% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.98% # number of syscalls executed +system.cpu0.kern.syscall::19 8 3.54% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.65% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.88% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.77% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.10% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.88% # number of syscalls executed +system.cpu0.kern.syscall::45 37 16.37% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.77% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.54% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.42% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% # number of syscalls executed +system.cpu0.kern.syscall::59 4 1.77% # number of syscalls executed +system.cpu0.kern.syscall::71 30 13.27% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.33% # number of syscalls executed +system.cpu0.kern.syscall::74 8 3.54% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.88% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.98% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.88% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.88% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.88% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.88% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.88% # number of syscalls executed +system.cpu0.kern.syscall::total 226 # number of syscalls executed system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles system.cpu0.numCycles 3740670933 # number of cpu cycles simulated system.cpu0.num_insts 57222076 # Number of instructions executed @@ -256,17 +256,17 @@ system.cpu1.dcache.WriteReq_accesses 733305 # nu system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses @@ -280,8 +280,8 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.overall_hits 1812118 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses @@ -319,17 +319,17 @@ system.cpu1.icache.ReadReq_accesses 5935766 # nu system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses @@ -343,8 +343,8 @@ system.cpu1.icache.mshr_cap_events 0 # nu system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 5832136 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses @@ -379,78 +379,78 @@ system.cpu1.itb.write_accesses 0 # DT system.cpu1.itb.write_acv 0 # DTB write access violations system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.kern.callpal 32131 # number of callpals executed -system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed -system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed -system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed -system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed -system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed -system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed -system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.callpal::cserve 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 8 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 470 1.46% # number of callpals executed +system.cpu1.kern.callpal::tbi 15 0.05% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26238 81.66% # number of callpals executed +system.cpu1.kern.callpal::rdps 2576 8.02% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% # number of callpals executed +system.cpu1.kern.callpal::rti 2607 8.11% # number of callpals executed +system.cpu1.kern.callpal::callsys 158 0.49% # number of callpals executed +system.cpu1.kern.callpal::imb 38 0.12% # number of callpals executed +system.cpu1.kern.callpal::rdunique 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::total 32131 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 612 -system.cpu1.kern.mode_good_user 580 -system.cpu1.kern.mode_good_idle 32 -system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches -system.cpu1.kern.mode_switch_user 580 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.ipl_count::0 10328 33.46% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1907 6.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 110 0.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18518 60.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10318 45.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1907 8.46% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 110 0.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10208 45.28% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 82001000 0.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 14064500 0.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 10905353000 0.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 612 +system.cpu1.kern.mode_good::user 580 +system.cpu1.kern.mode_good::idle 32 +system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches +system.cpu1.kern.mode_switch::user 580 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 508289000 0.03% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% # number of ticks spent at the given mode system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.kern.syscall 100 # number of syscalls executed -system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed -system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed -system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed -system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed -system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed -system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed -system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed -system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed -system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed -system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed -system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed -system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed -system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed -system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed -system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed -system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed -system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::2 2 2.00% # number of syscalls executed +system.cpu1.kern.syscall::3 11 11.00% # number of syscalls executed +system.cpu1.kern.syscall::4 2 2.00% # number of syscalls executed +system.cpu1.kern.syscall::6 10 10.00% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.00% # number of syscalls executed +system.cpu1.kern.syscall::19 2 2.00% # number of syscalls executed +system.cpu1.kern.syscall::23 2 2.00% # number of syscalls executed +system.cpu1.kern.syscall::24 2 2.00% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.00% # number of syscalls executed +system.cpu1.kern.syscall::45 17 17.00% # number of syscalls executed +system.cpu1.kern.syscall::47 2 2.00% # number of syscalls executed +system.cpu1.kern.syscall::48 2 2.00% # number of syscalls executed +system.cpu1.kern.syscall::59 3 3.00% # number of syscalls executed +system.cpu1.kern.syscall::71 24 24.00% # number of syscalls executed +system.cpu1.kern.syscall::74 8 8.00% # number of syscalls executed +system.cpu1.kern.syscall::90 1 1.00% # number of syscalls executed +system.cpu1.kern.syscall::132 2 2.00% # number of syscalls executed +system.cpu1.kern.syscall::total 100 # number of syscalls executed system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles system.cpu1.numCycles 3740248881 # number of cpu cycles simulated system.cpu1.num_insts 5931958 # Number of instructions executed @@ -473,17 +473,17 @@ system.iocache.ReadReq_misses 175 # nu system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41727 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency 0 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses @@ -497,8 +497,8 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41727 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency 0 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits system.iocache.overall_miss_latency 0 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses @@ -528,17 +528,17 @@ system.l2c.UpgradeReq_miss_rate 1 # mi system.l2c.UpgradeReq_misses 125007 # number of UpgradeReq misses system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 427641 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 1.788900 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 3030514 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.demand_hits 1759731 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate 0.419329 # miss rate for demand accesses @@ -552,8 +552,8 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.overall_accesses 3030514 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits 1759731 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles system.l2c.overall_miss_rate 0.419329 # miss rate for overall accesses @@ -571,15 +571,15 @@ system.l2c.tagsinuse 30526.475636 # Cy system.l2c.total_refs 1952499 # Total number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 123882 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 6085e3c17..b85207b5e 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 17:45:48 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:54:37 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:24 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:27 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 2f7905f66..a536081c4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2944628 # Simulator instruction rate (inst/s) -host_mem_usage 292076 # Number of bytes of host memory used -host_seconds 20.39 # Real time elapsed on the host -host_tick_rate 89719993414 # Simulator tick rate (ticks/s) +host_inst_rate 4025289 # Simulator instruction rate (inst/s) +host_mem_usage 293608 # Number of bytes of host memory used +host_seconds 14.92 # Real time elapsed on the host +host_tick_rate 122645865621 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -24,17 +24,17 @@ system.cpu.dcache.WriteReq_accesses 6152574 # nu system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 15682061 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.demand_hits 13560932 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.135258 # miss rate for demand accesses @@ -48,8 +48,8 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 13560932 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.135258 # miss rate for overall accesses @@ -87,17 +87,17 @@ system.cpu.icache.ReadReq_accesses 60050143 # nu system.cpu.icache.ReadReq_hits 59129922 # number of ReadReq hits system.cpu.icache.ReadReq_miss_rate 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 920221 # number of ReadReq misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 60050143 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.demand_hits 59129922 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.015324 # miss rate for demand accesses @@ -111,8 +111,8 @@ system.cpu.icache.mshr_cap_events 0 # nu system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 59129922 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.015324 # miss rate for overall accesses @@ -147,90 +147,90 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.kern.callpal 192180 # number of callpals executed -system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175249 91.19% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6771 3.52% 96.92% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal_rti 5203 2.71% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.callpal::cserve 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrmces 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrfen 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrvptptr 1 0.00% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% # number of callpals executed +system.cpu.kern.callpal::swpipl 175249 91.19% # number of callpals executed +system.cpu.kern.callpal::rdps 6771 3.52% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrusp 7 0.00% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% # number of callpals executed +system.cpu.kern.callpal::rti 5203 2.71% # number of callpals executed +system.cpu.kern.callpal::callsys 515 0.27% # number of callpals executed +system.cpu.kern.callpal::imb 181 0.09% # number of callpals executed +system.cpu.kern.callpal::total 192180 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182562 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 74830 40.99% 40.99% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105623 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1829332050500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981732 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695521 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1909 -system.cpu.kern.mode_good_user 1738 -system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch_user 1738 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402439 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320894 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.ipl_count::0 74830 40.99% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 243 0.13% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1866 1.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105623 57.86% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73463 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 243 0.16% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1866 1.25% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73463 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1811927407500 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 20110000 0.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 80238000 0.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17304295000 0.95% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::idle 171 +system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26834202500 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465074000 0.08% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801032773000 98.45% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.kern.syscall 326 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed +system.cpu.kern.syscall::2 8 2.45% # number of syscalls executed +system.cpu.kern.syscall::3 30 9.20% # number of syscalls executed +system.cpu.kern.syscall::4 4 1.23% # number of syscalls executed +system.cpu.kern.syscall::6 42 12.88% # number of syscalls executed +system.cpu.kern.syscall::12 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::15 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::17 15 4.60% # number of syscalls executed +system.cpu.kern.syscall::19 10 3.07% # number of syscalls executed +system.cpu.kern.syscall::20 6 1.84% # number of syscalls executed +system.cpu.kern.syscall::23 4 1.23% # number of syscalls executed +system.cpu.kern.syscall::24 6 1.84% # number of syscalls executed +system.cpu.kern.syscall::33 11 3.37% # number of syscalls executed +system.cpu.kern.syscall::41 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::45 54 16.56% # number of syscalls executed +system.cpu.kern.syscall::47 6 1.84% # number of syscalls executed +system.cpu.kern.syscall::48 10 3.07% # number of syscalls executed +system.cpu.kern.syscall::54 10 3.07% # number of syscalls executed +system.cpu.kern.syscall::58 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::59 7 2.15% # number of syscalls executed +system.cpu.kern.syscall::71 54 16.56% # number of syscalls executed +system.cpu.kern.syscall::73 3 0.92% # number of syscalls executed +system.cpu.kern.syscall::74 16 4.91% # number of syscalls executed +system.cpu.kern.syscall::87 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::90 3 0.92% # number of syscalls executed +system.cpu.kern.syscall::92 9 2.76% # number of syscalls executed +system.cpu.kern.syscall::97 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::98 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::132 4 1.23% # number of syscalls executed +system.cpu.kern.syscall::144 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::147 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::total 326 # number of syscalls executed system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles system.cpu.numCycles 3658664408 # number of cpu cycles simulated system.cpu.num_insts 60038305 # Number of instructions executed @@ -253,17 +253,17 @@ system.iocache.ReadReq_misses 174 # nu system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses 41552 # number of WriteReq misses -system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41726 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency 0 # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.demand_hits 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate 1 # miss rate for demand accesses @@ -277,8 +277,8 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.overall_accesses 41726 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency 0 # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits system.iocache.overall_miss_latency 0 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses @@ -308,17 +308,17 @@ system.l2c.UpgradeReq_miss_rate 1 # mi system.l2c.UpgradeReq_misses 124945 # number of UpgradeReq misses system.l2c.Writeback_accesses 428893 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 428893 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.demand_hits 1696652 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses @@ -332,8 +332,8 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits 1696652 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses @@ -351,15 +351,15 @@ system.l2c.tagsinuse 30228.585605 # Cy system.l2c.total_refs 1867269 # Total number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. system.l2c.writebacks 119147 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 28d9dc74d..25b3fda7c 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 17:45:48 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:56:00 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:24 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:27 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 6292a0ccf..93714e8e1 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1283961 # Simulator instruction rate (inst/s) -host_mem_usage 290228 # Number of bytes of host memory used -host_seconds 46.28 # Real time elapsed on the host -host_tick_rate 42613693899 # Simulator tick rate (ticks/s) +host_inst_rate 2079010 # Simulator instruction rate (inst/s) +host_mem_usage 291764 # Number of bytes of host memory used +host_seconds 28.58 # Real time elapsed on the host +host_tick_rate 69000495741 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59420593 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated @@ -52,13 +52,13 @@ system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064858 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 9.990826 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 14335823 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 33770.954076 # average overall miss latency @@ -121,13 +121,13 @@ system.cpu0.icache.ReadReq_misses 916324 # nu system.cpu0.icache.ReadReq_mshr_miss_latency 10703476000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.016917 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 916324 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 58.118732 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 54164416 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 14681.637172 # average overall miss latency @@ -146,7 +146,7 @@ system.cpu0.icache.no_allocate_misses 0 # Nu system.cpu0.icache.overall_accesses 54164416 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 14681.637172 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 53248092 # number of overall hits system.cpu0.icache.overall_miss_latency 13453136500 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.016917 # miss rate for overall accesses @@ -181,95 +181,95 @@ system.cpu0.itb.write_accesses 0 # DT system.cpu0.itb.write_acv 0 # DTB write access violations system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.kern.callpal 188012 # number of callpals executed -system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3868 2.06% 2.11% # number of callpals executed -system.cpu0.kern.callpal_tbi 44 0.02% 2.13% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.13% # number of callpals executed -system.cpu0.kern.callpal_swpipl 172068 91.52% 93.65% # number of callpals executed -system.cpu0.kern.callpal_rdps 6698 3.56% 97.22% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed -system.cpu0.kern.callpal_rti 4713 2.51% 99.73% # number of callpals executed -system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::cserve 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wripir 91 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3868 2.06% # number of callpals executed +system.cpu0.kern.callpal::tbi 44 0.02% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% # number of callpals executed +system.cpu0.kern.callpal::swpipl 172068 91.52% # number of callpals executed +system.cpu0.kern.callpal::rdps 6698 3.56% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4713 2.51% # number of callpals executed +system.cpu0.kern.callpal::callsys 356 0.19% # number of callpals executed +system.cpu0.kern.callpal::imb 149 0.08% # number of callpals executed +system.cpu0.kern.callpal::total 188012 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.hwrei 202896 # number of hwrei instructions executed system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 178906 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 72641 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.07% 40.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 1987 1.11% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 6 0.00% 41.79% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 104141 58.21% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 144662 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 71272 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 71266 49.26% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 1972134703000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 1908230091000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 96186500 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 576952000 0.03% 96.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 5442500 0.00% 96.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 63226031000 3.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used_0 0.981154 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684322 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1231 -system.cpu0.kern.mode_good_user 1232 -system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7237 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1232 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.170098 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 1968330503000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3804198000 0.19% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.ipl_count::0 72641 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1987 1.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 104141 58.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 178906 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71272 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1987 1.37% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71266 49.26% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144662 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1908230091000 96.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96186500 0.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 576952000 0.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5442500 0.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 63226031000 3.21% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1972134703000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981154 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684322 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1231 +system.cpu0.kern.mode_good::user 1232 +system.cpu0.kern.mode_good::idle 0 +system.cpu0.kern.mode_switch::kernel 7237 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1232 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170098 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1968330503000 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3804198000 0.19% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 0 0.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3869 # number of times the context was actually changed -system.cpu0.kern.syscall 224 # number of syscalls executed -system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed -system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed -system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed -system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed -system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed -system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed -system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed -system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed -system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed -system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::2 6 2.68% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.48% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.34% # number of syscalls executed +system.cpu0.kern.syscall::6 30 13.39% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.46% # number of syscalls executed +system.cpu0.kern.syscall::19 6 2.68% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.79% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.89% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.79% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.57% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% # number of syscalls executed +system.cpu0.kern.syscall::45 39 17.41% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.79% # number of syscalls executed +system.cpu0.kern.syscall::48 7 3.12% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.02% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.23% # number of syscalls executed +system.cpu0.kern.syscall::71 32 14.29% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.34% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.02% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.89% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.12% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.89% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.45% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% # number of syscalls executed +system.cpu0.kern.syscall::total 224 # number of syscalls executed system.cpu0.not_idle_fraction 0.066840 # Percentage of non-idle cycles system.cpu0.numCycles 3944270922 # number of cpu cycles simulated system.cpu0.num_insts 54155641 # Number of instructions executed @@ -318,13 +318,13 @@ system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040541 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 30.141759 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 1670551 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 32269.608001 # average overall miss latency @@ -387,13 +387,13 @@ system.cpu1.icache.ReadReq_misses 87436 # nu system.cpu1.icache.ReadReq_mshr_miss_latency 1015724000 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate 0.016597 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 87436 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 59.270387 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 5268142 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 14617.211446 # average overall miss latency @@ -412,7 +412,7 @@ system.cpu1.icache.no_allocate_misses 0 # Nu system.cpu1.icache.overall_accesses 5268142 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 14617.211446 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 5180706 # number of overall hits system.cpu1.icache.overall_miss_latency 1278070500 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.016597 # miss rate for overall accesses @@ -447,82 +447,82 @@ system.cpu1.itb.write_accesses 0 # DT system.cpu1.itb.write_acv 0 # DTB write access violations system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.kern.callpal 29503 # number of callpals executed -system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 365 1.24% 1.27% # number of callpals executed -system.cpu1.kern.callpal_tbi 10 0.03% 1.30% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.02% 1.33% # number of callpals executed -system.cpu1.kern.callpal_swpipl 24144 81.84% 83.16% # number of callpals executed -system.cpu1.kern.callpal_rdps 2172 7.36% 90.52% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 90.53% # number of callpals executed -system.cpu1.kern.callpal_wrusp 3 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 90.54% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 90.55% # number of callpals executed -system.cpu1.kern.callpal_rti 2594 8.79% 99.35% # number of callpals executed -system.cpu1.kern.callpal_callsys 161 0.55% 99.89% # number of callpals executed -system.cpu1.kern.callpal_imb 31 0.11% 100.00% # number of callpals executed -system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed +system.cpu1.kern.callpal::cserve 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 365 1.24% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24144 81.84% # number of callpals executed +system.cpu1.kern.callpal::rdps 2172 7.36% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% # number of callpals executed +system.cpu1.kern.callpal::rti 2594 8.79% # number of callpals executed +system.cpu1.kern.callpal::callsys 161 0.55% # number of callpals executed +system.cpu1.kern.callpal::imb 31 0.11% # number of callpals executed +system.cpu1.kern.callpal::rdunique 1 0.00% # number of callpals executed +system.cpu1.kern.callpal::total 29503 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.hwrei 36053 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2351 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 28810 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9173 31.84% 31.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1980 6.87% 38.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 91 0.32% 39.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 17566 60.97% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 20310 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9165 45.13% 45.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 9074 44.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 1971683837000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 1927968787500 97.78% 97.78% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 511194500 0.03% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 58584000 0.00% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 43145271000 2.19% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used_0 0.999128 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.516566 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 532 -system.cpu1.kern.mode_good_user 516 -system.cpu1.kern.mode_good_idle 16 -system.cpu1.kern.mode_switch_kernel 880 # number of protection mode switches -system.cpu1.kern.mode_switch_user 516 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2081 # number of protection mode switches -system.cpu1.kern.mode_switch_good 1.612234 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.604545 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.007689 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 4596640000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1703543000 0.09% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 1964670722000 99.68% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.ipl_count::0 9173 31.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1980 6.87% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 91 0.32% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17566 60.97% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28810 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9165 45.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1980 9.75% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 91 0.45% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9074 44.68% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20310 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1927968787500 97.78% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 511194500 0.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 58584000 0.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 43145271000 2.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1971683837000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999128 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.516566 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 532 +system.cpu1.kern.mode_good::user 516 +system.cpu1.kern.mode_good::idle 16 +system.cpu1.kern.mode_switch::kernel 880 # number of protection mode switches +system.cpu1.kern.mode_switch::user 516 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2081 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.604545 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::idle 0.007689 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.612234 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4596640000 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1703543000 0.09% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1964670722000 99.68% # number of ticks spent at the given mode system.cpu1.kern.swap_context 366 # number of times the context was actually changed -system.cpu1.kern.syscall 102 # number of syscalls executed -system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed -system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed -system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed -system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed -system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed -system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed -system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed -system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed -system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed -system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed -system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed -system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed -system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed -system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed -system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed -system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed -system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed -system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed -system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::2 2 1.96% # number of syscalls executed +system.cpu1.kern.syscall::3 11 10.78% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.98% # number of syscalls executed +system.cpu1.kern.syscall::6 12 11.76% # number of syscalls executed +system.cpu1.kern.syscall::17 5 4.90% # number of syscalls executed +system.cpu1.kern.syscall::19 4 3.92% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.96% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.96% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.96% # number of syscalls executed +system.cpu1.kern.syscall::33 3 2.94% # number of syscalls executed +system.cpu1.kern.syscall::45 15 14.71% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.96% # number of syscalls executed +system.cpu1.kern.syscall::48 3 2.94% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.98% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.96% # number of syscalls executed +system.cpu1.kern.syscall::71 22 21.57% # number of syscalls executed +system.cpu1.kern.syscall::74 7 6.86% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.98% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.96% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.96% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.98% # number of syscalls executed +system.cpu1.kern.syscall::total 102 # number of syscalls executed system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles system.cpu1.numCycles 3943367734 # number of cpu cycles simulated system.cpu1.num_insts 5264952 # Number of instructions executed @@ -557,13 +557,13 @@ system.iocache.WriteReq_misses 41552 # nu system.iocache.WriteReq_mshr_miss_latency 3569262880 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6169.706090 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6169.706090 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10459 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64528956 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64528956 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41730 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency 137805.458998 # average overall miss latency @@ -582,7 +582,7 @@ system.iocache.no_allocate_misses 0 # Nu system.iocache.overall_accesses 41730 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency 137805.458998 # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits system.iocache.overall_miss_latency 5750621804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses @@ -635,13 +635,13 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency inf system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses 430351 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 430351 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 4.554189 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 2397119 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 52009.472790 # average overall miss latency @@ -678,15 +678,15 @@ system.l2c.tagsinuse 30859.505450 # Cy system.l2c.total_refs 1961635 # Total number of references to valid blocks. system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 123162 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index b6e01de39..1cd35589d 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 17:45:48 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:55:21 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:24 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:27 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 589cc1a34..9f5363b35 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1437585 # Simulator instruction rate (inst/s) -host_mem_usage 288848 # Number of bytes of host memory used -host_seconds 39.10 # Real time elapsed on the host -host_tick_rate 49367876331 # Simulator tick rate (ticks/s) +host_inst_rate 2080568 # Simulator instruction rate (inst/s) +host_mem_usage 290384 # Number of bytes of host memory used +host_seconds 27.01 # Real time elapsed on the host +host_tick_rate 71448233358 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56205703 # Number of instructions simulated sim_seconds 1.930165 # Number of seconds simulated @@ -52,13 +52,13 @@ system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 system.cpu.dcache.WriteReq_mshr_miss_rate 0.065070 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 15048990 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 33777.675695 # average overall miss latency @@ -121,13 +121,13 @@ system.cpu.icache.ReadReq_misses 931101 # nu system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.016562 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 59.387754 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 56217537 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 14711.221983 # average overall miss latency @@ -146,7 +146,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 56217537 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 14711.221983 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 55286436 # number of overall hits system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.016562 # miss rate for overall accesses @@ -181,90 +181,90 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.kern.callpal 193221 # number of callpals executed -system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4171 2.16% 2.16% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.19% # number of callpals executed -system.cpu.kern.callpal_swpipl 176257 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal_rdps 6844 3.54% 96.95% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rti 5169 2.68% 99.64% # number of callpals executed -system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed +system.cpu.kern.callpal::cserve 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrmces 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrfen 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrvptptr 1 0.00% # number of callpals executed +system.cpu.kern.callpal::swpctx 4171 2.16% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% # number of callpals executed +system.cpu.kern.callpal::wrent 7 0.00% # number of callpals executed +system.cpu.kern.callpal::swpipl 176257 91.22% # number of callpals executed +system.cpu.kern.callpal::rdps 6844 3.54% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% # number of callpals executed +system.cpu.kern.callpal::wrusp 7 0.00% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% # number of callpals executed +system.cpu.kern.callpal::rti 5169 2.68% # number of callpals executed +system.cpu.kern.callpal::callsys 515 0.27% # number of callpals executed +system.cpu.kern.callpal::imb 181 0.09% # number of callpals executed +system.cpu.kern.callpal::total 193221 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.hwrei 212325 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183502 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75001 40.87% 40.87% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 131 0.07% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1944 1.06% 42.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106426 58.00% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149343 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 1930163835000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 96331500 0.00% 96.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 565310500 0.03% 96.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used_0 0.981774 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691880 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1911 -system.cpu.kern.mode_good_user 1744 -system.cpu.kern.mode_good_idle 167 -system.cpu.kern.mode_switch_kernel 5917 # number of protection mode switches -system.cpu.kern.mode_switch_user 1744 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2089 # number of protection mode switches -system.cpu.kern.mode_switch_good 1.402910 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.322968 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.079943 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5539986000 0.29% 2.80% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode +system.cpu.kern.ipl_count::0 75001 40.87% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1944 1.06% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106426 58.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183502 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73634 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1944 1.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73634 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149343 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1866810523000 96.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 96331500 0.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 565310500 0.03% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 62691670000 3.25% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1930163835000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981774 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.691880 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1744 +system.cpu.kern.mode_good::idle 167 +system.cpu.kern.mode_switch::kernel 5917 # number of protection mode switches +system.cpu.kern.mode_switch::user 1744 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.322968 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.402910 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 48447088000 2.51% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5539986000 0.29% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1876176759000 97.20% # number of ticks spent at the given mode system.cpu.kern.swap_context 4172 # number of times the context was actually changed -system.cpu.kern.syscall 326 # number of syscalls executed -system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed +system.cpu.kern.syscall::2 8 2.45% # number of syscalls executed +system.cpu.kern.syscall::3 30 9.20% # number of syscalls executed +system.cpu.kern.syscall::4 4 1.23% # number of syscalls executed +system.cpu.kern.syscall::6 42 12.88% # number of syscalls executed +system.cpu.kern.syscall::12 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::15 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::17 15 4.60% # number of syscalls executed +system.cpu.kern.syscall::19 10 3.07% # number of syscalls executed +system.cpu.kern.syscall::20 6 1.84% # number of syscalls executed +system.cpu.kern.syscall::23 4 1.23% # number of syscalls executed +system.cpu.kern.syscall::24 6 1.84% # number of syscalls executed +system.cpu.kern.syscall::33 11 3.37% # number of syscalls executed +system.cpu.kern.syscall::41 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::45 54 16.56% # number of syscalls executed +system.cpu.kern.syscall::47 6 1.84% # number of syscalls executed +system.cpu.kern.syscall::48 10 3.07% # number of syscalls executed +system.cpu.kern.syscall::54 10 3.07% # number of syscalls executed +system.cpu.kern.syscall::58 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::59 7 2.15% # number of syscalls executed +system.cpu.kern.syscall::71 54 16.56% # number of syscalls executed +system.cpu.kern.syscall::73 3 0.92% # number of syscalls executed +system.cpu.kern.syscall::74 16 4.91% # number of syscalls executed +system.cpu.kern.syscall::87 1 0.31% # number of syscalls executed +system.cpu.kern.syscall::90 3 0.92% # number of syscalls executed +system.cpu.kern.syscall::92 9 2.76% # number of syscalls executed +system.cpu.kern.syscall::97 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::98 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::132 4 1.23% # number of syscalls executed +system.cpu.kern.syscall::144 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::147 2 0.61% # number of syscalls executed +system.cpu.kern.syscall::total 326 # number of syscalls executed system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles system.cpu.numCycles 3860329186 # number of cpu cycles simulated system.cpu.num_insts 56205703 # Number of instructions executed @@ -299,13 +299,13 @@ system.iocache.WriteReq_misses 41552 # nu system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles_no_mshrs 6163.674943 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6163.674943 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked_no_mshrs 10472 # number of cycles access was blocked -system.iocache.blocked_no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles_no_mshrs 64546004 # number of cycles access was blocked -system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10472 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64546004 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency 137782.763427 # average overall miss latency @@ -324,7 +324,7 @@ system.iocache.no_allocate_misses 0 # Nu system.iocache.overall_accesses 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency 137782.763427 # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits 0 # number of overall hits system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles system.iocache.overall_miss_rate 1 # miss rate for overall accesses @@ -376,13 +376,13 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency inf system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses 430459 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 430459 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 4.436562 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 2323200 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 52009.864773 # average overall miss latency @@ -419,15 +419,15 @@ system.l2c.tagsinuse 30591.543942 # Cy system.l2c.total_refs 1889545 # Total number of references to valid blocks. system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit. system.l2c.writebacks 119060 # number of writebacks -system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post -system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post -system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout index ad2ad5770..b68290cbf 100755 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:59:01 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 74765736f..2894da70d 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1514764 # Simulator instruction rate (inst/s) -host_mem_usage 199328 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host -host_tick_rate 2232178480 # Simulator tick rate (ticks/s) +host_inst_rate 2302773 # Simulator instruction rate (inst/s) +host_mem_usage 201032 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 3391978546 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000737 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu.dcache.WriteReq_misses 311 # nu system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180149 # number of overall hits system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu.icache.ReadReq_misses 403 # nu system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks. -system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499617 # number of overall hits system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses @@ -184,13 +184,13 @@ system.cpu.l2cache.UpgradeReq_misses 172 # nu system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency @@ -209,7 +209,7 @@ system.cpu.l2cache.no_allocate_misses 0 # Nu system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout index 7c058e100..6828937b6 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:02 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:24 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index 2a786c1d0..75b87a853 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2806031 # Simulator instruction rate (inst/s) -host_mem_usage 1124224 # Number of bytes of host memory used -host_seconds 0.71 # Real time elapsed on the host -host_tick_rate 350627795 # Simulator tick rate (ticks/s) +host_inst_rate 4530821 # Simulator instruction rate (inst/s) +host_mem_usage 1125932 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host +host_tick_rate 566039081 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2000004 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated @@ -16,17 +16,17 @@ system.cpu0.dcache.WriteReq_accesses 56340 # nu system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses @@ -40,8 +40,8 @@ system.cpu0.dcache.mshr_cap_events 0 # nu system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.overall_hits 180140 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses @@ -79,17 +79,17 @@ system.cpu0.icache.ReadReq_accesses 500019 # nu system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses @@ -103,8 +103,8 @@ system.cpu0.icache.mshr_cap_events 0 # nu system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 499556 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses @@ -152,17 +152,17 @@ system.cpu1.dcache.WriteReq_accesses 56340 # nu system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses @@ -176,8 +176,8 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.overall_hits 180140 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses @@ -215,17 +215,17 @@ system.cpu1.icache.ReadReq_accesses 500019 # nu system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses @@ -239,8 +239,8 @@ system.cpu1.icache.mshr_cap_events 0 # nu system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 499556 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses @@ -288,17 +288,17 @@ system.cpu2.dcache.WriteReq_accesses 56340 # nu system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses @@ -312,8 +312,8 @@ system.cpu2.dcache.mshr_cap_events 0 # nu system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.overall_hits 180140 # number of overall hits system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses @@ -351,17 +351,17 @@ system.cpu2.icache.ReadReq_accesses 500019 # nu system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses @@ -375,8 +375,8 @@ system.cpu2.icache.mshr_cap_events 0 # nu system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.icache.overall_hits 499556 # number of overall hits system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses @@ -424,17 +424,17 @@ system.cpu3.dcache.WriteReq_accesses 56340 # nu system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses -system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses @@ -448,8 +448,8 @@ system.cpu3.dcache.mshr_cap_events 0 # nu system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.dcache.overall_hits 180140 # number of overall hits system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses @@ -487,17 +487,17 @@ system.cpu3.icache.ReadReq_accesses 500019 # nu system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses @@ -511,8 +511,8 @@ system.cpu3.icache.mshr_cap_events 0 # nu system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.icache.overall_hits 499556 # number of overall hits system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses @@ -564,17 +564,17 @@ system.l2c.UpgradeReq_miss_rate 1 # mi system.l2c.UpgradeReq_misses 688 # number of UpgradeReq misses system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 116 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 3704 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.demand_hits 276 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate 0.925486 # miss rate for demand accesses @@ -588,8 +588,8 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.overall_accesses 3704 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits 276 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout index 4f024f577..8902435b9 100755 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 16:39:10 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:25 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index cb27727f8..2214f40ec 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1377736 # Simulator instruction rate (inst/s) -host_mem_usage 206716 # Number of bytes of host memory used -host_seconds 1.45 # Real time elapsed on the host -host_tick_rate 508569870 # Simulator tick rate (ticks/s) +host_inst_rate 2185563 # Simulator instruction rate (inst/s) +host_mem_usage 208428 # Number of bytes of host memory used +host_seconds 0.92 # Real time elapsed on the host +host_tick_rate 806662952 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1999941 # Number of instructions simulated sim_seconds 0.000738 # Number of seconds simulated @@ -28,13 +28,13 @@ system.cpu0.dcache.WriteReq_misses 311 # nu system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 389.434125 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 180771 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 55480.314961 # average overall miss latency @@ -53,7 +53,7 @@ system.cpu0.dcache.no_allocate_misses 0 # Nu system.cpu0.dcache.overall_accesses 180771 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 55480.314961 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 52480.314961 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.overall_hits 180136 # number of overall hits system.cpu0.dcache.overall_miss_latency 35230000 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses @@ -97,13 +97,13 @@ system.cpu0.icache.ReadReq_misses 463 # nu system.cpu0.icache.ReadReq_mshr_miss_latency 22096000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 1078.913607 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 500000 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 50723.542117 # average overall miss latency @@ -122,7 +122,7 @@ system.cpu0.icache.no_allocate_misses 0 # Nu system.cpu0.icache.overall_accesses 500000 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 50723.542117 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 47723.542117 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 499537 # number of overall hits system.cpu0.icache.overall_miss_latency 23485000 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses @@ -182,13 +182,13 @@ system.cpu1.dcache.WriteReq_misses 311 # nu system.cpu1.dcache.WriteReq_mshr_miss_latency 16496000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 389.427646 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 180768 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 55464.566929 # average overall miss latency @@ -207,7 +207,7 @@ system.cpu1.dcache.no_allocate_misses 0 # Nu system.cpu1.dcache.overall_accesses 180768 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 55464.566929 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 52464.566929 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.overall_hits 180133 # number of overall hits system.cpu1.dcache.overall_miss_latency 35220000 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses @@ -251,13 +251,13 @@ system.cpu1.icache.ReadReq_misses 463 # nu system.cpu1.icache.ReadReq_mshr_miss_latency 22115000 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 1078.900648 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 499994 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 50764.578834 # average overall miss latency @@ -276,7 +276,7 @@ system.cpu1.icache.no_allocate_misses 0 # Nu system.cpu1.icache.overall_accesses 499994 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 499531 # number of overall hits system.cpu1.icache.overall_miss_latency 23504000 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses @@ -336,13 +336,13 @@ system.cpu2.dcache.WriteReq_misses 311 # nu system.cpu2.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles system.cpu2.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses system.cpu2.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency @@ -361,7 +361,7 @@ system.cpu2.dcache.no_allocate_misses 0 # Nu system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.overall_hits 180140 # number of overall hits system.cpu2.dcache.overall_miss_latency 35212000 # number of overall miss cycles system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses @@ -405,13 +405,13 @@ system.cpu2.icache.ReadReq_misses 463 # nu system.cpu2.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.avg_refs 1078.956803 # Average number of references to valid blocks. -system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.demand_accesses 500020 # number of demand (read+write) accesses system.cpu2.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency @@ -430,7 +430,7 @@ system.cpu2.icache.no_allocate_misses 0 # Nu system.cpu2.icache.overall_accesses 500020 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.icache.overall_hits 499557 # number of overall hits system.cpu2.icache.overall_miss_latency 23479000 # number of overall miss cycles system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses @@ -490,13 +490,13 @@ system.cpu3.dcache.WriteReq_misses 311 # nu system.cpu3.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles system.cpu3.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses -system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_refs 389.436285 # Average number of references to valid blocks. -system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.demand_accesses 180772 # number of demand (read+write) accesses system.cpu3.dcache.demand_avg_miss_latency 55478.740157 # average overall miss latency @@ -515,7 +515,7 @@ system.cpu3.dcache.no_allocate_misses 0 # Nu system.cpu3.dcache.overall_accesses 180772 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 55478.740157 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency 52478.740157 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.dcache.overall_hits 180137 # number of overall hits system.cpu3.dcache.overall_miss_latency 35229000 # number of overall miss cycles system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses @@ -559,13 +559,13 @@ system.cpu3.icache.ReadReq_misses 463 # nu system.cpu3.icache.ReadReq_mshr_miss_latency 22093000 # number of ReadReq MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.avg_refs 1078.920086 # Average number of references to valid blocks. -system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.demand_accesses 500003 # number of demand (read+write) accesses system.cpu3.icache.demand_avg_miss_latency 50717.062635 # average overall miss latency @@ -584,7 +584,7 @@ system.cpu3.icache.no_allocate_misses 0 # Nu system.cpu3.icache.overall_accesses 500003 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 50717.062635 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency 47717.062635 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.icache.overall_hits 499540 # number of overall hits system.cpu3.icache.overall_miss_latency 23482000 # number of overall miss cycles system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses @@ -654,13 +654,13 @@ system.l2c.UpgradeReq_mshr_miss_rate 1 # ms system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses 116 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 116 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 0.120000 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 3704 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 52008.168028 # average overall miss latency @@ -679,7 +679,7 @@ system.l2c.no_allocate_misses 0 # Nu system.l2c.overall_accesses 3704 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 52008.168028 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits 276 # number of overall hits system.l2c.overall_miss_latency 178284000 # number of overall miss cycles system.l2c.overall_miss_rate 0.925486 # miss rate for overall accesses diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 3245c7a36..6fafed395 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:04:58 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:32:54 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index df75bec2d..570c98e31 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 52497 # Simulator instruction rate (inst/s) -host_mem_usage 211604 # Number of bytes of host memory used -host_seconds 8.36 # Real time elapsed on the host -host_tick_rate 26370227 # Simulator tick rate (ticks/s) +host_inst_rate 72753 # Simulator instruction rate (inst/s) +host_mem_usage 213332 # Number of bytes of host memory used +host_seconds 6.03 # Real time elapsed on the host +host_tick_rate 36544582 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 438923 # Number of instructions simulated sim_seconds 0.000220 # Number of seconds simulated @@ -82,13 +82,13 @@ system.cpu0.dcache.WriteReq_mshr_hits 18 # nu system.cpu0.dcache.WriteReq_mshr_miss_latency 1565500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 735.966667 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 40537 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 20113.149847 # average overall miss latency @@ -107,7 +107,7 @@ system.cpu0.dcache.no_allocate_misses 0 # Nu system.cpu0.dcache.overall_accesses 40537 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 20113.149847 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 15416.666667 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.overall_hits 40210 # number of overall hits system.cpu0.dcache.overall_miss_latency 6577000 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.008067 # miss rate for overall accesses @@ -141,21 +141,23 @@ system.cpu0.fetch.branchRate 0.198634 # Nu system.cpu0.fetch.icacheStallCycles 83600 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.predictedBranches 54549 # Number of branches that fetch has predicted taken system.cpu0.fetch.rate 1.028021 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist.samples 399788 -system.cpu0.fetch.rateDist.min_value 0 - 0 239369 5987.40% - 1 86666 2167.80% - 2 18970 474.50% - 3 18363 459.32% - 4 2993 74.86% - 5 13233 331.00% - 6 1665 41.65% - 7 2406 60.18% - 8 16123 403.29% -system.cpu0.fetch.rateDist.max_value 8 -system.cpu0.fetch.rateDist.end_dist - +system.cpu0.fetch.rateDist::samples 399788 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0-1 239369 59.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1-2 86666 21.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2-3 18970 4.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3-4 18363 4.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4-5 2993 0.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5-6 13233 3.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6-7 1665 0.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7-8 2406 0.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 16123 4.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 399788 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.034668 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.929402 # Number of instructions fetched each cycle (Total) system.cpu0.icache.ReadReq_accesses 83600 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_avg_miss_latency 14035.763411 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11552.755906 # average ReadReq mshr miss latency @@ -167,13 +169,13 @@ system.cpu0.icache.ReadReq_mshr_hits 92 # nu system.cpu0.icache.ReadReq_mshr_miss_latency 7336000 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.007596 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 635 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 130.508661 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 83600 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 14035.763411 # average overall miss latency @@ -192,7 +194,7 @@ system.cpu0.icache.no_allocate_misses 0 # Nu system.cpu0.icache.overall_accesses 83600 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 14035.763411 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 11552.755906 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 82873 # number of overall hits system.cpu0.icache.overall_miss_latency 10204000 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.008696 # miss rate for overall accesses @@ -255,58 +257,54 @@ system.cpu0.iew.predictedNotTakenIncorrect 856 # system.cpu0.iew.predictedTakenIncorrect 30841 # Number of branches that were predicted taken incorrectly system.cpu0.ipc 0.260942 # IPC: Instructions Per Cycle system.cpu0.ipc_total 0.260942 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0 202881 # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 142871 70.42% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 46166 22.76% # Type of FU issued - MemWrite 13844 6.82% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0.end_dist +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 142871 70.42% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 46166 22.76% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 13844 6.82% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::total 202881 # Type of FU issued system.cpu0.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested system.cpu0.iq.ISSUE:fu_busy_rate 0.000853 # FU busy rate (busy events/executed inst) -system.cpu0.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 23 13.29% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11 6.36% # attempts to use FU when none available - MemWrite 139 80.35% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full.end_dist -system.cpu0.iq.ISSUE:issued_per_cycle::samples 399788 -system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 279763 69.98% -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 72065 18.03% -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 24983 6.25% -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 14756 3.69% -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 5406 1.35% -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 2153 0.54% -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 473 0.12% -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 157 0.04% -system.cpu0.iq.ISSUE:issued_per_cycle::8 32 0.01% -system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu0.iq.ISSUE:issued_per_cycle::total 399788 -system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.507471 -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.960639 +system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 23 13.29% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 11 6.36% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 139 80.35% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:issued_per_cycle::samples 399788 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 279763 69.98% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 72065 18.03% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 24983 6.25% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 14756 3.69% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 5406 1.35% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 2153 0.54% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 473 0.12% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 157 0.04% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 32 0.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::total 399788 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.507471 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.960639 # Number of insts issued each cycle system.cpu0.iq.ISSUE:rate 0.504211 # Inst issue rate system.cpu0.iq.iqInstsAdded 204299 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqInstsIssued 202881 # Number of instructions issued @@ -410,13 +408,13 @@ system.cpu1.dcache.WriteReq_mshr_hits 17 # nu system.cpu1.dcache.WriteReq_mshr_miss_latency 1732000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_rate 0.009707 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 109 # number of WriteReq MSHR misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 709.516129 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 40428 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 20280.063291 # average overall miss latency @@ -435,7 +433,7 @@ system.cpu1.dcache.no_allocate_misses 0 # Nu system.cpu1.dcache.overall_accesses 40428 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 20280.063291 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 15870.909091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.overall_hits 40112 # number of overall hits system.cpu1.dcache.overall_miss_latency 6408500 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate 0.007816 # miss rate for overall accesses @@ -469,21 +467,23 @@ system.cpu1.fetch.branchRate 0.217162 # Nu system.cpu1.fetch.icacheStallCycles 83559 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.predictedBranches 53615 # Number of branches that fetch has predicted taken system.cpu1.fetch.rate 1.065163 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist.samples 399545 -system.cpu1.fetch.rateDist.min_value 0 - 0 239335 5990.19% - 1 86108 2155.15% - 2 18621 466.06% - 3 13625 341.01% - 4 2965 74.21% - 5 17436 436.40% - 6 2130 53.31% - 7 2391 59.84% - 8 16934 423.83% -system.cpu1.fetch.rateDist.max_value 8 -system.cpu1.fetch.rateDist.end_dist - +system.cpu1.fetch.rateDist::samples 399545 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0-1 239335 59.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1-2 86108 21.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2-3 18621 4.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3-4 13625 3.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4-5 2965 0.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5-6 17436 4.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6-7 2130 0.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7-8 2391 0.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 16934 4.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 399545 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.071854 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.991830 # Number of instructions fetched each cycle (Total) system.cpu1.icache.ReadReq_accesses 83559 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_avg_miss_latency 13800.273598 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11301.412873 # average ReadReq mshr miss latency @@ -495,13 +495,13 @@ system.cpu1.icache.ReadReq_mshr_hits 94 # nu system.cpu1.icache.ReadReq_mshr_miss_latency 7199000 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate 0.007623 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 637 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 130.028257 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 83559 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 13800.273598 # average overall miss latency @@ -520,7 +520,7 @@ system.cpu1.icache.no_allocate_misses 0 # Nu system.cpu1.icache.overall_accesses 83559 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 13800.273598 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11301.412873 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 82828 # number of overall hits system.cpu1.icache.overall_miss_latency 10088000 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.008748 # miss rate for overall accesses @@ -583,58 +583,54 @@ system.cpu1.iew.predictedNotTakenIncorrect 844 # system.cpu1.iew.predictedTakenIncorrect 30716 # Number of branches that were predicted taken incorrectly system.cpu1.ipc 0.260482 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.260482 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0 202698 # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 142808 70.45% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 46141 22.76% # Type of FU issued - MemWrite 13749 6.78% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0.end_dist +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 142808 70.45% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 46141 22.76% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 13749 6.78% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::total 202698 # Type of FU issued system.cpu1.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested system.cpu1.iq.ISSUE:fu_busy_rate 0.000853 # FU busy rate (busy events/executed inst) -system.cpu1.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 23 13.29% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11 6.36% # attempts to use FU when none available - MemWrite 139 80.35% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full.end_dist -system.cpu1.iq.ISSUE:issued_per_cycle::samples 399545 -system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 279804 70.03% -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 71581 17.92% -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 25282 6.33% -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 14650 3.67% -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 5420 1.36% -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 2146 0.54% -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 473 0.12% -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 157 0.04% -system.cpu1.iq.ISSUE:issued_per_cycle::8 32 0.01% -system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu1.iq.ISSUE:issued_per_cycle::total 399545 -system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.507322 -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.960841 +system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 23 13.29% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 11 6.36% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 139 80.35% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:issued_per_cycle::samples 399545 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 279804 70.03% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 71581 17.92% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 25282 6.33% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 14650 3.67% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 5420 1.36% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 2146 0.54% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 473 0.12% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 157 0.04% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 32 0.01% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::total 399545 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.507322 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.960841 # Number of insts issued each cycle system.cpu1.iq.ISSUE:rate 0.504155 # Inst issue rate system.cpu1.iq.iqInstsAdded 205352 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqInstsIssued 202698 # Number of instructions issued @@ -736,13 +732,13 @@ system.cpu2.dcache.WriteReq_mshr_hits 379 # nu system.cpu2.dcache.WriteReq_mshr_miss_latency 7752000 # number of WriteReq MSHR miss cycles system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009109 # mshr miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_mshr_misses 198 # number of WriteReq MSHR misses -system.cpu2.dcache.avg_blocked_cycles_no_mshrs 22000 # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs 22000 # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_refs 168.806818 # Average number of references to valid blocks. -system.cpu2.dcache.blocked_no_mshrs 3 # number of cycles access was blocked -system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_mshrs 66000 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_mshrs 66000 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.demand_accesses 46708 # number of demand (read+write) accesses system.cpu2.dcache.demand_avg_miss_latency 40467.796610 # average overall miss latency @@ -761,7 +757,7 @@ system.cpu2.dcache.no_allocate_misses 0 # Nu system.cpu2.dcache.overall_accesses 46708 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 40467.796610 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency 31115.201900 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.overall_hits 45823 # number of overall hits system.cpu2.dcache.overall_miss_latency 35814000 # number of overall miss cycles system.cpu2.dcache.overall_miss_rate 0.018948 # miss rate for overall accesses @@ -795,21 +791,23 @@ system.cpu2.fetch.branchRate 0.162798 # Nu system.cpu2.fetch.icacheStallCycles 88443 # Number of cycles fetch is stalled on an Icache miss system.cpu2.fetch.predictedBranches 44906 # Number of branches that fetch has predicted taken system.cpu2.fetch.rate 1.053532 # Number of inst fetches per cycle -system.cpu2.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist.samples 422806 -system.cpu2.fetch.rateDist.min_value 0 - 0 264558 6257.20% - 1 88255 2087.36% - 2 1011 23.91% - 3 21518 508.93% - 4 1067 25.24% - 5 21230 502.12% - 6 652 15.42% - 7 705 16.67% - 8 23810 563.14% -system.cpu2.fetch.rateDist.max_value 8 -system.cpu2.fetch.rateDist.end_dist - +system.cpu2.fetch.rateDist::samples 422806 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0-1 264558 62.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1-2 88255 20.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2-3 1011 0.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3-4 21518 5.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4-5 1067 0.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5-6 21230 5.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6-7 652 0.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7-8 705 0.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 23810 5.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 422806 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.098792 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.122739 # Number of instructions fetched each cycle (Total) system.cpu2.icache.ReadReq_accesses 88443 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_avg_miss_latency 37054.535017 # average ReadReq miss latency system.cpu2.icache.ReadReq_avg_mshr_miss_latency 35099.253731 # average ReadReq mshr miss latency @@ -821,13 +819,13 @@ system.cpu2.icache.ReadReq_mshr_hits 201 # nu system.cpu2.icache.ReadReq_mshr_miss_latency 23516500 # number of ReadReq MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate 0.007576 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_misses 670 # number of ReadReq MSHR misses -system.cpu2.icache.avg_blocked_cycles_no_mshrs 10250 # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.avg_refs 130.899851 # Average number of references to valid blocks. -system.cpu2.icache.blocked_no_mshrs 2 # number of cycles access was blocked -system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_mshrs 20500 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.demand_accesses 88443 # number of demand (read+write) accesses system.cpu2.icache.demand_avg_miss_latency 37054.535017 # average overall miss latency @@ -846,7 +844,7 @@ system.cpu2.icache.no_allocate_misses 0 # Nu system.cpu2.icache.overall_accesses 88443 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 37054.535017 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency 35099.253731 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.icache.overall_hits 87572 # number of overall hits system.cpu2.icache.overall_miss_latency 32274500 # number of overall miss cycles system.cpu2.icache.overall_miss_rate 0.009848 # miss rate for overall accesses @@ -909,58 +907,54 @@ system.cpu2.iew.predictedNotTakenIncorrect 868 # system.cpu2.iew.predictedTakenIncorrect 42466 # Number of branches that were predicted taken incorrectly system.cpu2.ipc 0.269290 # IPC: Instructions Per Cycle system.cpu2.ipc_total 0.269290 # IPC: Total IPC of All Threads -system.cpu2.iq.ISSUE:FU_type_0 235110 # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 166509 70.82% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 45663 19.42% # Type of FU issued - MemWrite 22938 9.76% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0.end_dist +system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntAlu 166509 70.82% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemRead 45663 19.42% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemWrite 22938 9.76% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::total 235110 # Type of FU issued system.cpu2.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested system.cpu2.iq.ISSUE:fu_busy_rate 0.000566 # FU busy rate (busy events/executed inst) -system.cpu2.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 38 28.57% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 27 20.30% # attempts to use FU when none available - MemWrite 68 51.13% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:fu_full.end_dist -system.cpu2.iq.ISSUE:issued_per_cycle::samples 422806 -system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu2.iq.ISSUE:issued_per_cycle::0-1 286677 67.80% -system.cpu2.iq.ISSUE:issued_per_cycle::1-2 67298 15.92% -system.cpu2.iq.ISSUE:issued_per_cycle::2-3 43645 10.32% -system.cpu2.iq.ISSUE:issued_per_cycle::3-4 22116 5.23% -system.cpu2.iq.ISSUE:issued_per_cycle::4-5 1740 0.41% -system.cpu2.iq.ISSUE:issued_per_cycle::5-6 920 0.22% -system.cpu2.iq.ISSUE:issued_per_cycle::6-7 282 0.07% -system.cpu2.iq.ISSUE:issued_per_cycle::7-8 102 0.02% -system.cpu2.iq.ISSUE:issued_per_cycle::8 26 0.01% -system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu2.iq.ISSUE:issued_per_cycle::total 422806 -system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.556071 -system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.945329 +system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntAlu 38 28.57% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::MemRead 27 20.30% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::MemWrite 68 51.13% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu2.iq.ISSUE:issued_per_cycle::samples 422806 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::0-1 286677 67.80% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::1-2 67298 15.92% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::2-3 43645 10.32% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::3-4 22116 5.23% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::4-5 1740 0.41% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::5-6 920 0.22% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::6-7 282 0.07% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::7-8 102 0.02% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::8 26 0.01% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::total 422806 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.556071 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.945329 # Number of insts issued each cycle system.cpu2.iq.ISSUE:rate 0.533166 # Inst issue rate system.cpu2.iq.iqInstsAdded 239551 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqInstsIssued 235110 # Number of instructions issued @@ -1064,13 +1058,13 @@ system.cpu3.dcache.WriteReq_mshr_hits 18 # nu system.cpu3.dcache.WriteReq_mshr_miss_latency 1635000 # number of WriteReq MSHR miss cycles system.cpu3.dcache.WriteReq_mshr_miss_rate 0.008287 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_misses 111 # number of WriteReq MSHR misses -system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_refs 804.066667 # Average number of references to valid blocks. -system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.demand_accesses 42192 # number of demand (read+write) accesses system.cpu3.dcache.demand_avg_miss_latency 21102.848101 # average overall miss latency @@ -1089,7 +1083,7 @@ system.cpu3.dcache.no_allocate_misses 0 # Nu system.cpu3.dcache.overall_accesses 42192 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 21102.848101 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency 15920.289855 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.dcache.overall_hits 41876 # number of overall hits system.cpu3.dcache.overall_miss_latency 6668500 # number of overall miss cycles system.cpu3.dcache.overall_miss_rate 0.007490 # miss rate for overall accesses @@ -1123,21 +1117,23 @@ system.cpu3.fetch.branchRate 0.195107 # Nu system.cpu3.fetch.icacheStallCycles 81998 # Number of cycles fetch is stalled on an Icache miss system.cpu3.fetch.predictedBranches 51243 # Number of branches that fetch has predicted taken system.cpu3.fetch.rate 1.060607 # Number of inst fetches per cycle -system.cpu3.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist.samples 397135 -system.cpu3.fetch.rateDist.min_value 0 - 0 239656 6034.62% - 1 85048 2141.54% - 2 14012 352.83% - 3 17951 452.01% - 4 2990 75.29% - 5 15291 385.03% - 6 1676 42.20% - 7 2382 59.98% - 8 18129 456.49% -system.cpu3.fetch.rateDist.max_value 8 -system.cpu3.fetch.rateDist.end_dist - +system.cpu3.fetch.rateDist::samples 397135 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0-1 239656 60.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1-2 85048 21.42% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2-3 14012 3.53% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3-4 17951 4.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4-5 2990 0.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5-6 15291 3.85% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6-7 1676 0.42% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7-8 2382 0.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 18129 4.56% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 397135 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.075458 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.013935 # Number of instructions fetched each cycle (Total) system.cpu3.icache.ReadReq_accesses 81998 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_avg_miss_latency 19529.880478 # average ReadReq miss latency system.cpu3.icache.ReadReq_avg_mshr_miss_latency 16592.417062 # average ReadReq mshr miss latency @@ -1149,13 +1145,13 @@ system.cpu3.icache.ReadReq_mshr_hits 120 # nu system.cpu3.icache.ReadReq_mshr_miss_latency 10503000 # number of ReadReq MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate 0.007720 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_misses 633 # number of ReadReq MSHR misses -system.cpu3.icache.avg_blocked_cycles_no_mshrs 32500 # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.avg_refs 128.349131 # Average number of references to valid blocks. -system.cpu3.icache.blocked_no_mshrs 1 # number of cycles access was blocked -system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_mshrs 32500 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.demand_accesses 81998 # number of demand (read+write) accesses system.cpu3.icache.demand_avg_miss_latency 19529.880478 # average overall miss latency @@ -1174,7 +1170,7 @@ system.cpu3.icache.no_allocate_misses 0 # Nu system.cpu3.icache.overall_accesses 81998 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 19529.880478 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency 16592.417062 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.icache.overall_hits 81245 # number of overall hits system.cpu3.icache.overall_miss_latency 14706000 # number of overall miss cycles system.cpu3.icache.overall_miss_rate 0.009183 # miss rate for overall accesses @@ -1237,58 +1233,54 @@ system.cpu3.iew.predictedNotTakenIncorrect 830 # system.cpu3.iew.predictedTakenIncorrect 32515 # Number of branches that were predicted taken incorrectly system.cpu3.ipc 0.274276 # IPC: Instructions Per Cycle system.cpu3.ipc_total 0.274276 # IPC: Total IPC of All Threads -system.cpu3.iq.ISSUE:FU_type_0 213585 # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0.start_dist - No_OpClass 0 0.00% # Type of FU issued - IntAlu 152352 71.33% # Type of FU issued - IntMult 0 0.00% # Type of FU issued - IntDiv 0 0.00% # Type of FU issued - FloatAdd 0 0.00% # Type of FU issued - FloatCmp 0 0.00% # Type of FU issued - FloatCvt 0 0.00% # Type of FU issued - FloatMult 0 0.00% # Type of FU issued - FloatDiv 0 0.00% # Type of FU issued - FloatSqrt 0 0.00% # Type of FU issued - MemRead 45332 21.22% # Type of FU issued - MemWrite 15901 7.44% # Type of FU issued - IprAccess 0 0.00% # Type of FU issued - InstPrefetch 0 0.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0.end_dist +system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntAlu 152352 71.33% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemRead 45332 21.22% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemWrite 15901 7.44% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::total 213585 # Type of FU issued system.cpu3.iq.ISSUE:fu_busy_cnt 168 # FU busy when requested system.cpu3.iq.ISSUE:fu_busy_rate 0.000787 # FU busy rate (busy events/executed inst) -system.cpu3.iq.ISSUE:fu_full.start_dist - No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 18 10.71% # attempts to use FU when none available - IntMult 0 0.00% # attempts to use FU when none available - IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 0 0.00% # attempts to use FU when none available - FloatCmp 0 0.00% # attempts to use FU when none available - FloatCvt 0 0.00% # attempts to use FU when none available - FloatMult 0 0.00% # attempts to use FU when none available - FloatDiv 0 0.00% # attempts to use FU when none available - FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11 6.55% # attempts to use FU when none available - MemWrite 139 82.74% # attempts to use FU when none available - IprAccess 0 0.00% # attempts to use FU when none available - InstPrefetch 0 0.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full.end_dist -system.cpu3.iq.ISSUE:issued_per_cycle::samples 397135 -system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 -system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% -system.cpu3.iq.ISSUE:issued_per_cycle::0-1 274584 69.14% -system.cpu3.iq.ISSUE:issued_per_cycle::1-2 68377 17.22% -system.cpu3.iq.ISSUE:issued_per_cycle::2-3 29162 7.34% -system.cpu3.iq.ISSUE:issued_per_cycle::3-4 16815 4.23% -system.cpu3.iq.ISSUE:issued_per_cycle::4-5 5405 1.36% -system.cpu3.iq.ISSUE:issued_per_cycle::5-6 2141 0.54% -system.cpu3.iq.ISSUE:issued_per_cycle::6-7 468 0.12% -system.cpu3.iq.ISSUE:issued_per_cycle::7-8 158 0.04% -system.cpu3.iq.ISSUE:issued_per_cycle::8 25 0.01% -system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% -system.cpu3.iq.ISSUE:issued_per_cycle::total 397135 -system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 -system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.537815 -system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.988033 +system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntAlu 18 10.71% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemRead 11 6.55% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemWrite 139 82.74% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:issued_per_cycle::samples 397135 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::0-1 274584 69.14% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::1-2 68377 17.22% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::2-3 29162 7.34% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::3-4 16815 4.23% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::4-5 5405 1.36% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::5-6 2141 0.54% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::6-7 468 0.12% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::7-8 158 0.04% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::8 25 0.01% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::total 397135 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.537815 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.988033 # Number of insts issued each cycle system.cpu3.iq.ISSUE:rate 0.530388 # Inst issue rate system.cpu3.iq.iqInstsAdded 217367 # Number of instructions added to the IQ (excludes non-spec) system.cpu3.iq.iqInstsIssued 213585 # Number of instructions issued @@ -1347,13 +1339,13 @@ system.l2c.UpgradeReq_mshr_miss_rate 1 # ms system.l2c.UpgradeReq_mshr_misses 114 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 9 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 3.998131 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 2830 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 52139.534884 # average overall miss latency @@ -1372,7 +1364,7 @@ system.l2c.no_allocate_misses 0 # Nu system.l2c.overall_accesses 2830 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 52139.534884 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40058.565154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits 2142 # number of overall hits system.l2c.overall_miss_latency 35872000 # number of overall miss cycles system.l2c.overall_miss_rate 0.243110 # miss rate for overall accesses diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 2507950f0..077b03b98 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:14:35 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:32:58 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 6e706304f..9d16d1421 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1148641 # Simulator instruction rate (inst/s) -host_mem_usage 1126984 # Number of bytes of host memory used -host_seconds 0.59 # Real time elapsed on the host -host_tick_rate 148677785 # Simulator tick rate (ticks/s) +host_inst_rate 1712699 # Simulator instruction rate (inst/s) +host_mem_usage 1128716 # Number of bytes of host memory used +host_seconds 0.40 # Real time elapsed on the host +host_tick_rate 221634180 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 677340 # Number of instructions simulated sim_seconds 0.000088 # Number of seconds simulated @@ -20,17 +20,17 @@ system.cpu0.dcache.WriteReq_accesses 16107 # nu system.cpu0.dcache.WriteReq_hits 15998 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_rate 0.006767 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_misses 109 # number of WriteReq misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 58461 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.demand_hits 58190 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_rate 0.004636 # miss rate for demand accesses @@ -44,8 +44,8 @@ system.cpu0.dcache.mshr_cap_events 0 # nu system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.overall_accesses 58461 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.overall_hits 58190 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.004636 # miss rate for overall accesses @@ -67,17 +67,17 @@ system.cpu0.icache.ReadReq_accesses 167366 # nu system.cpu0.icache.ReadReq_hits 167008 # number of ReadReq hits system.cpu0.icache.ReadReq_miss_rate 0.002139 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 466.502793 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 167366 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.icache.demand_hits 167008 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu0.icache.demand_miss_rate 0.002139 # miss rate for demand accesses @@ -91,8 +91,8 @@ system.cpu0.icache.mshr_cap_events 0 # nu system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.overall_accesses 167366 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 167008 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.002139 # miss rate for overall accesses @@ -128,17 +128,17 @@ system.cpu1.dcache.WriteReq_accesses 14362 # nu system.cpu1.dcache.WriteReq_hits 14260 # number of WriteReq hits system.cpu1.dcache.WriteReq_miss_rate 0.007102 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_misses 102 # number of WriteReq misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 55820 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.demand_hits 55559 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_rate 0.004676 # miss rate for demand accesses @@ -152,8 +152,8 @@ system.cpu1.dcache.mshr_cap_events 0 # nu system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.overall_accesses 55820 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.overall_hits 55559 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate 0.004676 # miss rate for overall accesses @@ -175,17 +175,17 @@ system.cpu1.icache.ReadReq_accesses 167301 # nu system.cpu1.icache.ReadReq_hits 166942 # number of ReadReq hits system.cpu1.icache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_misses 359 # number of ReadReq misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 465.019499 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 167301 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.icache.demand_hits 166942 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu1.icache.demand_miss_rate 0.002146 # miss rate for demand accesses @@ -199,8 +199,8 @@ system.cpu1.icache.mshr_cap_events 0 # nu system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.overall_accesses 167301 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 166942 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.002146 # miss rate for overall accesses @@ -235,17 +235,17 @@ system.cpu2.dcache.WriteReq_accesses 27755 # nu system.cpu2.dcache.WriteReq_hits 27561 # number of WriteReq hits system.cpu2.dcache.WriteReq_miss_rate 0.006990 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_misses 194 # number of WriteReq misses -system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_refs 362.347059 # Average number of references to valid blocks. -system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.demand_accesses 82337 # number of demand (read+write) accesses system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu2.dcache.demand_hits 81992 # number of demand (read+write) hits system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu2.dcache.demand_miss_rate 0.004190 # miss rate for demand accesses @@ -259,8 +259,8 @@ system.cpu2.dcache.mshr_cap_events 0 # nu system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.overall_accesses 82337 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.overall_hits 81992 # number of overall hits system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu2.dcache.overall_miss_rate 0.004190 # miss rate for overall accesses @@ -282,17 +282,17 @@ system.cpu2.icache.ReadReq_accesses 175401 # nu system.cpu2.icache.ReadReq_hits 174934 # number of ReadReq hits system.cpu2.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses system.cpu2.icache.ReadReq_misses 467 # number of ReadReq misses -system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.avg_refs 374.591006 # Average number of references to valid blocks. -system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.demand_accesses 175401 # number of demand (read+write) accesses system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu2.icache.demand_hits 174934 # number of demand (read+write) hits system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu2.icache.demand_miss_rate 0.002662 # miss rate for demand accesses @@ -306,8 +306,8 @@ system.cpu2.icache.mshr_cap_events 0 # nu system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.overall_accesses 175401 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.icache.overall_hits 174934 # number of overall hits system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu2.icache.overall_miss_rate 0.002662 # miss rate for overall accesses @@ -342,17 +342,17 @@ system.cpu3.dcache.WriteReq_accesses 12669 # nu system.cpu3.dcache.WriteReq_hits 12563 # number of WriteReq hits system.cpu3.dcache.WriteReq_miss_rate 0.008367 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_misses 106 # number of WriteReq misses -system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_refs 960.321429 # Average number of references to valid blocks. -system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.demand_accesses 53313 # number of demand (read+write) accesses system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu3.dcache.demand_hits 53031 # number of demand (read+write) hits system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu3.dcache.demand_miss_rate 0.005290 # miss rate for demand accesses @@ -366,8 +366,8 @@ system.cpu3.dcache.mshr_cap_events 0 # nu system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.overall_accesses 53313 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.dcache.overall_hits 53031 # number of overall hits system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles system.cpu3.dcache.overall_miss_rate 0.005290 # miss rate for overall accesses @@ -389,17 +389,17 @@ system.cpu3.icache.ReadReq_accesses 167430 # nu system.cpu3.icache.ReadReq_hits 167072 # number of ReadReq hits system.cpu3.icache.ReadReq_miss_rate 0.002138 # miss rate for ReadReq accesses system.cpu3.icache.ReadReq_misses 358 # number of ReadReq misses -system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.avg_refs 466.681564 # Average number of references to valid blocks. -system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.demand_accesses 167430 # number of demand (read+write) accesses system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu3.icache.demand_hits 167072 # number of demand (read+write) hits system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles system.cpu3.icache.demand_miss_rate 0.002138 # miss rate for demand accesses @@ -413,8 +413,8 @@ system.cpu3.icache.mshr_cap_events 0 # nu system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.overall_accesses 167430 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.icache.overall_hits 167072 # number of overall hits system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles system.cpu3.icache.overall_miss_rate 0.002138 # miss rate for overall accesses @@ -449,17 +449,17 @@ system.l2c.UpgradeReq_miss_rate 1 # mi system.l2c.UpgradeReq_misses 106 # number of UpgradeReq misses system.l2c.Writeback_accesses 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 9 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 2.968447 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 1785 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.demand_hits 1226 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles system.l2c.demand_miss_rate 0.313165 # miss rate for demand accesses @@ -473,8 +473,8 @@ system.l2c.mshr_cap_events 0 # nu system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.overall_accesses 1785 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits 1226 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles system.l2c.overall_miss_rate 0.313165 # miss rate for overall accesses diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index fc28b1d81..304f6e9bf 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 18:04:32 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 18:04:57 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:47 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:32:59 +M5 executing on maize command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 36df0b10e..bfbb72508 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 700731 # Simulator instruction rate (inst/s) -host_mem_usage 209476 # Number of bytes of host memory used -host_seconds 0.93 # Real time elapsed on the host -host_tick_rate 283592249 # Simulator tick rate (ticks/s) +host_inst_rate 1057647 # Simulator instruction rate (inst/s) +host_mem_usage 211204 # Number of bytes of host memory used +host_seconds 0.62 # Real time elapsed on the host +host_tick_rate 427981185 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 650423 # Number of instructions simulated sim_seconds 0.000263 # Number of seconds simulated @@ -38,13 +38,13 @@ system.cpu0.dcache.WriteReq_misses 107 # nu system.cpu0.dcache.WriteReq_mshr_miss_latency 1649000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_rate 0.006678 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses -system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 1200.035714 # Average number of references to valid blocks. -system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.demand_accesses 56889 # number of demand (read+write) accesses system.cpu0.dcache.demand_avg_miss_latency 16950.381679 # average overall miss latency @@ -63,7 +63,7 @@ system.cpu0.dcache.no_allocate_misses 0 # Nu system.cpu0.dcache.overall_accesses 56889 # number of overall (read+write) accesses system.cpu0.dcache.overall_avg_miss_latency 16950.381679 # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 13950.381679 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.overall_hits 56627 # number of overall hits system.cpu0.dcache.overall_miss_latency 4441000 # number of overall miss cycles system.cpu0.dcache.overall_miss_rate 0.004605 # miss rate for overall accesses @@ -91,13 +91,13 @@ system.cpu0.icache.ReadReq_misses 358 # nu system.cpu0.icache.ReadReq_mshr_miss_latency 4209500 # number of ReadReq MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate 0.002216 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 358 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 450.307263 # Average number of references to valid blocks. -system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.demand_accesses 161568 # number of demand (read+write) accesses system.cpu0.icache.demand_avg_miss_latency 14758.379888 # average overall miss latency @@ -116,7 +116,7 @@ system.cpu0.icache.no_allocate_misses 0 # Nu system.cpu0.icache.overall_accesses 161568 # number of overall (read+write) accesses system.cpu0.icache.overall_avg_miss_latency 14758.379888 # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 11758.379888 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.overall_hits 161210 # number of overall hits system.cpu0.icache.overall_miss_latency 5283500 # number of overall miss cycles system.cpu0.icache.overall_miss_rate 0.002216 # miss rate for overall accesses @@ -170,13 +170,13 @@ system.cpu1.dcache.WriteReq_misses 106 # nu system.cpu1.dcache.WriteReq_mshr_miss_latency 1647000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_rate 0.006860 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses -system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 1120.620690 # Average number of references to valid blocks. -system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.demand_accesses 56189 # number of demand (read+write) accesses system.cpu1.dcache.demand_avg_miss_latency 17095.419847 # average overall miss latency @@ -195,7 +195,7 @@ system.cpu1.dcache.no_allocate_misses 0 # Nu system.cpu1.dcache.overall_accesses 56189 # number of overall (read+write) accesses system.cpu1.dcache.overall_avg_miss_latency 17095.419847 # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 14095.419847 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.overall_hits 55927 # number of overall hits system.cpu1.dcache.overall_miss_latency 4479000 # number of overall miss cycles system.cpu1.dcache.overall_miss_rate 0.004663 # miss rate for overall accesses @@ -223,13 +223,13 @@ system.cpu1.icache.ReadReq_misses 359 # nu system.cpu1.icache.ReadReq_mshr_miss_latency 4089500 # number of ReadReq MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate 0.002213 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 450.816156 # Average number of references to valid blocks. -system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.demand_accesses 162202 # number of demand (read+write) accesses system.cpu1.icache.demand_avg_miss_latency 14391.364903 # average overall miss latency @@ -248,7 +248,7 @@ system.cpu1.icache.no_allocate_misses 0 # Nu system.cpu1.icache.overall_accesses 162202 # number of overall (read+write) accesses system.cpu1.icache.overall_avg_miss_latency 14391.364903 # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11391.364903 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.overall_hits 161843 # number of overall hits system.cpu1.icache.overall_miss_latency 5166500 # number of overall miss cycles system.cpu1.icache.overall_miss_rate 0.002213 # miss rate for overall accesses @@ -301,13 +301,13 @@ system.cpu2.dcache.WriteReq_misses 200 # nu system.cpu2.dcache.WriteReq_mshr_miss_latency 7606000 # number of WriteReq MSHR miss cycles system.cpu2.dcache.WriteReq_mshr_miss_rate 0.008024 # mshr miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses -system.cpu2.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.dcache.avg_refs 329.464706 # Average number of references to valid blocks. -system.cpu2.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.demand_accesses 73844 # number of demand (read+write) accesses system.cpu2.dcache.demand_avg_miss_latency 35787.292818 # average overall miss latency @@ -326,7 +326,7 @@ system.cpu2.dcache.no_allocate_misses 0 # Nu system.cpu2.dcache.overall_accesses 73844 # number of overall (read+write) accesses system.cpu2.dcache.overall_avg_miss_latency 35787.292818 # average overall miss latency system.cpu2.dcache.overall_avg_mshr_miss_latency 32787.292818 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.overall_hits 73482 # number of overall hits system.cpu2.dcache.overall_miss_latency 12955000 # number of overall miss cycles system.cpu2.dcache.overall_miss_rate 0.004902 # miss rate for overall accesses @@ -354,13 +354,13 @@ system.cpu2.icache.ReadReq_misses 467 # nu system.cpu2.icache.ReadReq_mshr_miss_latency 17123000 # number of ReadReq MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate 0.002948 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_misses 467 # number of ReadReq MSHR misses -system.cpu2.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.avg_refs 338.220557 # Average number of references to valid blocks. -system.cpu2.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.demand_accesses 158416 # number of demand (read+write) accesses system.cpu2.icache.demand_avg_miss_latency 39665.952891 # average overall miss latency @@ -379,7 +379,7 @@ system.cpu2.icache.no_allocate_misses 0 # Nu system.cpu2.icache.overall_accesses 158416 # number of overall (read+write) accesses system.cpu2.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency system.cpu2.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.icache.overall_hits 157949 # number of overall hits system.cpu2.icache.overall_miss_latency 18524000 # number of overall miss cycles system.cpu2.icache.overall_miss_rate 0.002948 # miss rate for overall accesses @@ -432,13 +432,13 @@ system.cpu3.dcache.WriteReq_misses 96 # nu system.cpu3.dcache.WriteReq_mshr_miss_latency 1487000 # number of WriteReq MSHR miss cycles system.cpu3.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses -system.cpu3.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_refs 640.392857 # Average number of references to valid blocks. -system.cpu3.dcache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.demand_accesses 46826 # number of demand (read+write) accesses system.cpu3.dcache.demand_avg_miss_latency 19681.159420 # average overall miss latency @@ -457,7 +457,7 @@ system.cpu3.dcache.no_allocate_misses 0 # Nu system.cpu3.dcache.overall_accesses 46826 # number of overall (read+write) accesses system.cpu3.dcache.overall_avg_miss_latency 19681.159420 # average overall miss latency system.cpu3.dcache.overall_avg_mshr_miss_latency 16681.159420 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.dcache.overall_hits 46550 # number of overall hits system.cpu3.dcache.overall_miss_latency 5432000 # number of overall miss cycles system.cpu3.dcache.overall_miss_rate 0.005894 # miss rate for overall accesses @@ -485,13 +485,13 @@ system.cpu3.icache.ReadReq_misses 358 # nu system.cpu3.icache.ReadReq_mshr_miss_latency 6481000 # number of ReadReq MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate 0.002126 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_misses 358 # number of ReadReq MSHR misses -system.cpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.icache.avg_refs 469.379888 # Average number of references to valid blocks. -system.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.demand_accesses 168396 # number of demand (read+write) accesses system.cpu3.icache.demand_avg_miss_latency 21104.748603 # average overall miss latency @@ -510,7 +510,7 @@ system.cpu3.icache.no_allocate_misses 0 # Nu system.cpu3.icache.overall_accesses 168396 # number of overall (read+write) accesses system.cpu3.icache.overall_avg_miss_latency 21104.748603 # average overall miss latency system.cpu3.icache.overall_avg_mshr_miss_latency 18103.351955 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.icache.overall_hits 168038 # number of overall hits system.cpu3.icache.overall_miss_latency 7555500 # number of overall miss cycles system.cpu3.icache.overall_miss_rate 0.002126 # miss rate for overall accesses @@ -564,13 +564,13 @@ system.l2c.UpgradeReq_mshr_miss_rate 1 # ms system.l2c.UpgradeReq_mshr_misses 91 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 9 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 2.953883 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 1785 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 51955.752212 # average overall miss latency @@ -589,7 +589,7 @@ system.l2c.no_allocate_misses 0 # Nu system.l2c.overall_accesses 1785 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency 51955.752212 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40005.366726 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.overall_hits 1220 # number of overall hits system.l2c.overall_miss_latency 29355000 # number of overall miss cycles system.l2c.overall_miss_rate 0.316527 # miss rate for overall accesses diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout index 0a2232d19..eb87c125b 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 16:38:39 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:07:10 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:26 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:17:27 +M5 executing on maize command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt index 451bddd68..0be961e27 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 326608 # Number of bytes of host memory used -host_seconds 197.86 # Real time elapsed on the host -host_tick_rate 1359114 # Simulator tick rate (ticks/s) +host_mem_usage 328320 # Number of bytes of host memory used +host_seconds 137.46 # Real time elapsed on the host +host_tick_rate 1956295 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated sim_ticks 268915439 # Number of ticks simulated @@ -30,13 +30,13 @@ system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 3772.150399 # average number of cycles each access was blocked -system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3772.150399 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 69914 # number of cycles access was blocked -system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 263726123 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 69914 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles::no_mshrs 263726123 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency @@ -100,13 +100,13 @@ system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 3775.982019 # average number of cycles each access was blocked -system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3775.982019 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 69517 # number of cycles access was blocked -system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 262494942 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 69517 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles::no_mshrs 262494942 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency @@ -170,13 +170,13 @@ system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 3785.643263 # average number of cycles each access was blocked -system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3785.643263 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 69704 # number of cycles access was blocked -system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 263874478 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 69704 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles::no_mshrs 263874478 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency @@ -240,13 +240,13 @@ system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 3780.086099 # average number of cycles each access was blocked -system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3780.086099 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69350 # number of cycles access was blocked -system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 262148971 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 69350 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles::no_mshrs 262148971 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency @@ -310,13 +310,13 @@ system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 3787.291600 # average number of cycles each access was blocked -system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3787.291600 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked -system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 263356896 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 69537 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles::no_mshrs 263356896 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency @@ -380,13 +380,13 @@ system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 3783.632237 # average number of cycles each access was blocked -system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3783.632237 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 69474 # number of cycles access was blocked -system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 262864066 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 69474 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles::no_mshrs 262864066 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency @@ -450,13 +450,13 @@ system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 3751.801399 # average number of cycles each access was blocked -system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3751.801399 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 69894 # number of cycles access was blocked -system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 262228407 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 69894 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles::no_mshrs 262228407 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency @@ -520,13 +520,13 @@ system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 3782.889997 # average number of cycles each access was blocked -system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3782.889997 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 69498 # number of cycles access was blocked -system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 262903289 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 69498 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles::no_mshrs 262903289 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency @@ -603,13 +603,13 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency inf system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles system.l2c.Writeback_accesses 86929 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits 86929 # number of Writeback hits -system.l2c.avg_blocked_cycles_no_mshrs 7154.090909 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7154.090909 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 2.005630 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 11 # number of cycles access was blocked -system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 78695 # number of cycles access was blocked -system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 11 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 78695 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed system.l2c.demand_accesses 213064 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency 49775.478970 # average overall miss latency diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index 28985f265..32cc0e397 100755 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 17:45:48 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 17:56:47 -M5 executing on zizzer +M5 compiled Apr 22 2009 06:58:24 +M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff +M5 started Apr 22 2009 07:05:27 +M5 executing on maize command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index ff3dc00d0..3d224466e 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -33,64 +33,64 @@ drivesys.cpu.itb.write_accesses 0 # DT drivesys.cpu.itb.write_acv 0 # DTB write access violations drivesys.cpu.itb.write_hits 0 # DTB write hits drivesys.cpu.itb.write_misses 0 # DTB write misses -drivesys.cpu.kern.callpal 4443 # number of callpals executed -drivesys.cpu.kern.callpal_swpctx 70 1.58% 1.58% # number of callpals executed -drivesys.cpu.kern.callpal_tbi 5 0.11% 1.69% # number of callpals executed -drivesys.cpu.kern.callpal_swpipl 3654 82.24% 83.93% # number of callpals executed -drivesys.cpu.kern.callpal_rdps 359 8.08% 92.01% # number of callpals executed -drivesys.cpu.kern.callpal_rdusp 1 0.02% 92.03% # number of callpals executed -drivesys.cpu.kern.callpal_rti 322 7.25% 99.28% # number of callpals executed -drivesys.cpu.kern.callpal_callsys 25 0.56% 99.84% # number of callpals executed -drivesys.cpu.kern.callpal_imb 7 0.16% 100.00% # number of callpals executed +drivesys.cpu.kern.callpal::swpctx 70 1.58% # number of callpals executed +drivesys.cpu.kern.callpal::tbi 5 0.11% # number of callpals executed +drivesys.cpu.kern.callpal::swpipl 3654 82.24% # number of callpals executed +drivesys.cpu.kern.callpal::rdps 359 8.08% # number of callpals executed +drivesys.cpu.kern.callpal::rdusp 1 0.02% # number of callpals executed +drivesys.cpu.kern.callpal::rti 322 7.25% # number of callpals executed +drivesys.cpu.kern.callpal::callsys 25 0.56% # number of callpals executed +drivesys.cpu.kern.callpal::imb 7 0.16% # number of callpals executed +drivesys.cpu.kern.callpal::total 4443 # number of callpals executed drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed drivesys.cpu.kern.inst.hwrei 5483 # number of hwrei instructions executed drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed -drivesys.cpu.kern.ipl_count 4191 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count_0 1189 28.37% 28.37% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count_21 10 0.24% 28.61% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count_22 205 4.89% 33.50% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count_31 2787 66.50% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good 2593 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199571362884 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199571043172 100.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used_31 0.426624 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.mode_good_kernel 110 -drivesys.cpu.kern.mode_good_user 107 -drivesys.cpu.kern.mode_good_idle 3 -drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches -drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches -drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches -drivesys.cpu.kern.mode_switch_good 1.645945 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 1278343 1.15% 1.39% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 109686421 98.61% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.ipl_count::0 1189 28.37% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::21 10 0.24% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::22 205 4.89% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::31 2787 66.50% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::total 4191 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good::0 1189 45.85% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::21 10 0.39% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::22 205 7.91% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::31 1189 45.85% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::total 2593 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks::0 199571043172 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 1620 0.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::22 17630 0.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::31 300462 0.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 199571362884 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::31 0.426624 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.mode_good::kernel 110 +drivesys.cpu.kern.mode_good::user 107 +drivesys.cpu.kern.mode_good::idle 3 +drivesys.cpu.kern.mode_switch::kernel 174 # number of protection mode switches +drivesys.cpu.kern.mode_switch::user 107 # number of protection mode switches +drivesys.cpu.kern.mode_switch::idle 218 # number of protection mode switches +drivesys.cpu.kern.mode_switch_good::kernel 0.632184 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::idle 0.013761 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::total 1.645945 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks::kernel 263256 0.24% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::user 1278343 1.15% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::idle 109686421 98.61% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed -drivesys.cpu.kern.syscall 22 # number of syscalls executed -drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed -drivesys.cpu.kern.syscall_6 3 13.64% 18.18% # number of syscalls executed -drivesys.cpu.kern.syscall_17 2 9.09% 27.27% # number of syscalls executed -drivesys.cpu.kern.syscall_97 1 4.55% 31.82% # number of syscalls executed -drivesys.cpu.kern.syscall_99 2 9.09% 40.91% # number of syscalls executed -drivesys.cpu.kern.syscall_101 2 9.09% 50.00% # number of syscalls executed -drivesys.cpu.kern.syscall_102 3 13.64% 63.64% # number of syscalls executed -drivesys.cpu.kern.syscall_104 1 4.55% 68.18% # number of syscalls executed -drivesys.cpu.kern.syscall_105 3 13.64% 81.82% # number of syscalls executed -drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # number of syscalls executed -drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed -drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed +drivesys.cpu.kern.syscall::2 1 4.55% # number of syscalls executed +drivesys.cpu.kern.syscall::6 3 13.64% # number of syscalls executed +drivesys.cpu.kern.syscall::17 2 9.09% # number of syscalls executed +drivesys.cpu.kern.syscall::97 1 4.55% # number of syscalls executed +drivesys.cpu.kern.syscall::99 2 9.09% # number of syscalls executed +drivesys.cpu.kern.syscall::101 2 9.09% # number of syscalls executed +drivesys.cpu.kern.syscall::102 3 13.64% # number of syscalls executed +drivesys.cpu.kern.syscall::104 1 4.55% # number of syscalls executed +drivesys.cpu.kern.syscall::105 3 13.64% # number of syscalls executed +drivesys.cpu.kern.syscall::106 1 4.55% # number of syscalls executed +drivesys.cpu.kern.syscall::118 2 9.09% # number of syscalls executed +drivesys.cpu.kern.syscall::150 1 4.55% # number of syscalls executed +drivesys.cpu.kern.syscall::total 22 # number of syscalls executed drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated drivesys.cpu.num_insts 1958129 # Number of instructions executed @@ -155,10 +155,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 160898071 # Simulator instruction rate (inst/s) -host_mem_usage 480604 # Number of bytes of host memory used -host_seconds 1.70 # Real time elapsed on the host -host_tick_rate 117699865039 # Simulator tick rate (ticks/s) +host_inst_rate 246734646 # Simulator instruction rate (inst/s) +host_mem_usage 482136 # Number of bytes of host memory used +host_seconds 1.11 # Real time elapsed on the host +host_tick_rate 180478925530 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -196,74 +196,74 @@ testsys.cpu.itb.write_accesses 0 # DT testsys.cpu.itb.write_acv 0 # DTB write access violations testsys.cpu.itb.write_hits 0 # DTB write hits testsys.cpu.itb.write_misses 0 # DTB write misses -testsys.cpu.kern.callpal 13122 # number of callpals executed -testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed -testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11074 84.39% 87.88% # number of callpals executed -testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed -testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed -testsys.cpu.kern.callpal_rdusp 3 0.02% 90.66% # number of callpals executed -testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # number of callpals executed -testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed -testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed +testsys.cpu.kern.callpal::swpctx 438 3.34% # number of callpals executed +testsys.cpu.kern.callpal::tbi 20 0.15% # number of callpals executed +testsys.cpu.kern.callpal::swpipl 11074 84.39% # number of callpals executed +testsys.cpu.kern.callpal::rdps 359 2.74% # number of callpals executed +testsys.cpu.kern.callpal::wrusp 3 0.02% # number of callpals executed +testsys.cpu.kern.callpal::rdusp 3 0.02% # number of callpals executed +testsys.cpu.kern.callpal::rti 1041 7.93% # number of callpals executed +testsys.cpu.kern.callpal::callsys 140 1.07% # number of callpals executed +testsys.cpu.kern.callpal::imb 44 0.34% # number of callpals executed +testsys.cpu.kern.callpal::total 13122 # number of callpals executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed testsys.cpu.kern.inst.hwrei 19053 # number of hwrei instructions executed testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12504 # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_0 5061 40.48% 40.48% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_21 184 1.47% 41.95% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_22 205 1.64% 43.59% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7054 56.41% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199569460830 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199568845670 100.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 566504 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_31 0.716615 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.mode_good_kernel 654 -testsys.cpu.kern.mode_good_user 649 -testsys.cpu.kern.mode_good_idle 5 -testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches -testsys.cpu.kern.mode_switch_good 1.608210 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1821131 2.10% 2.10% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065606 1.23% 3.32% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 83963628 96.68% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.ipl_count::0 5061 40.48% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 184 1.47% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::22 205 1.64% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::31 7054 56.41% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 12504 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 5055 48.15% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 184 1.75% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::22 205 1.95% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::31 5055 48.15% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 10499 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 199568845670 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 31026 0.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::22 17630 0.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 566504 0.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 199569460830 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_used::0 0.998814 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::31 0.716615 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good::kernel 654 +testsys.cpu.kern.mode_good::user 649 +testsys.cpu.kern.mode_good::idle 5 +testsys.cpu.kern.mode_switch::kernel 1099 # number of protection mode switches +testsys.cpu.kern.mode_switch::user 649 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 381 # number of protection mode switches +testsys.cpu.kern.mode_switch_good::kernel 0.595086 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::idle 0.013123 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::total 1.608210 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks::kernel 1821131 2.10% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::user 1065606 1.23% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::idle 83963628 96.68% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed -testsys.cpu.kern.syscall 83 # number of syscalls executed -testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed -testsys.cpu.kern.syscall_3 7 8.43% 12.05% # number of syscalls executed -testsys.cpu.kern.syscall_4 1 1.20% 13.25% # number of syscalls executed -testsys.cpu.kern.syscall_6 7 8.43% 21.69% # number of syscalls executed -testsys.cpu.kern.syscall_17 7 8.43% 30.12% # number of syscalls executed -testsys.cpu.kern.syscall_19 2 2.41% 32.53% # number of syscalls executed -testsys.cpu.kern.syscall_20 1 1.20% 33.73% # number of syscalls executed -testsys.cpu.kern.syscall_33 3 3.61% 37.35% # number of syscalls executed -testsys.cpu.kern.syscall_45 10 12.05% 49.40% # number of syscalls executed -testsys.cpu.kern.syscall_48 5 6.02% 55.42% # number of syscalls executed -testsys.cpu.kern.syscall_54 1 1.20% 56.63% # number of syscalls executed -testsys.cpu.kern.syscall_59 3 3.61% 60.24% # number of syscalls executed -testsys.cpu.kern.syscall_71 15 18.07% 78.31% # number of syscalls executed -testsys.cpu.kern.syscall_74 4 4.82% 83.13% # number of syscalls executed -testsys.cpu.kern.syscall_97 2 2.41% 85.54% # number of syscalls executed -testsys.cpu.kern.syscall_98 2 2.41% 87.95% # number of syscalls executed -testsys.cpu.kern.syscall_101 2 2.41% 90.36% # number of syscalls executed -testsys.cpu.kern.syscall_102 2 2.41% 92.77% # number of syscalls executed -testsys.cpu.kern.syscall_104 1 1.20% 93.98% # number of syscalls executed -testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed -testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed +testsys.cpu.kern.syscall::2 3 3.61% # number of syscalls executed +testsys.cpu.kern.syscall::3 7 8.43% # number of syscalls executed +testsys.cpu.kern.syscall::4 1 1.20% # number of syscalls executed +testsys.cpu.kern.syscall::6 7 8.43% # number of syscalls executed +testsys.cpu.kern.syscall::17 7 8.43% # number of syscalls executed +testsys.cpu.kern.syscall::19 2 2.41% # number of syscalls executed +testsys.cpu.kern.syscall::20 1 1.20% # number of syscalls executed +testsys.cpu.kern.syscall::33 3 3.61% # number of syscalls executed +testsys.cpu.kern.syscall::45 10 12.05% # number of syscalls executed +testsys.cpu.kern.syscall::48 5 6.02% # number of syscalls executed +testsys.cpu.kern.syscall::54 1 1.20% # number of syscalls executed +testsys.cpu.kern.syscall::59 3 3.61% # number of syscalls executed +testsys.cpu.kern.syscall::71 15 18.07% # number of syscalls executed +testsys.cpu.kern.syscall::74 4 4.82% # number of syscalls executed +testsys.cpu.kern.syscall::97 2 2.41% # number of syscalls executed +testsys.cpu.kern.syscall::98 2 2.41% # number of syscalls executed +testsys.cpu.kern.syscall::101 2 2.41% # number of syscalls executed +testsys.cpu.kern.syscall::102 2 2.41% # number of syscalls executed +testsys.cpu.kern.syscall::104 1 1.20% # number of syscalls executed +testsys.cpu.kern.syscall::105 3 3.61% # number of syscalls executed +testsys.cpu.kern.syscall::118 2 2.41% # number of syscalls executed +testsys.cpu.kern.syscall::total 83 # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated testsys.cpu.num_insts 3560411 # Number of instructions executed @@ -368,19 +368,19 @@ drivesys.cpu.itb.write_misses 0 # DT drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed drivesys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed drivesys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -drivesys.cpu.kern.mode_good_kernel 0 -drivesys.cpu.kern.mode_good_user 0 -drivesys.cpu.kern.mode_good_idle 0 -drivesys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches -drivesys.cpu.kern.mode_switch_user 0 # number of protection mode switches -drivesys.cpu.kern.mode_switch_idle 0 # number of protection mode switches -drivesys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode +drivesys.cpu.kern.mode_good::kernel 0 +drivesys.cpu.kern.mode_good::user 0 +drivesys.cpu.kern.mode_good::idle 0 +drivesys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch::user 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch::idle 0 # number of protection mode switches +drivesys.cpu.kern.mode_switch_good::kernel no_value # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::user no_value # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::total no_value # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed drivesys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles drivesys.cpu.numCycles 0 # number of cpu cycles simulated @@ -398,15 +398,15 @@ drivesys.disk2.dma_read_txs 0 # Nu drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. -drivesys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post -drivesys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post -drivesys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post -drivesys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post -drivesys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -drivesys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +drivesys.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +drivesys.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -429,10 +429,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 125057105672 # Simulator instruction rate (inst/s) -host_mem_usage 480604 # Number of bytes of host memory used +host_inst_rate 133810490945 # Simulator instruction rate (inst/s) +host_mem_usage 482136 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 342026980 # Simulator tick rate (ticks/s) +host_tick_rate 365741275 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated @@ -473,19 +473,19 @@ testsys.cpu.itb.write_misses 0 # DT testsys.cpu.kern.inst.arm 0 # number of arm instructions executed testsys.cpu.kern.inst.hwrei 0 # number of hwrei instructions executed testsys.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -testsys.cpu.kern.mode_good_kernel 0 -testsys.cpu.kern.mode_good_user 0 -testsys.cpu.kern.mode_good_idle 0 -testsys.cpu.kern.mode_switch_kernel 0 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 0 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 0 # number of protection mode switches -testsys.cpu.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel <err: div-0> # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_user <err: div-0> # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 0 # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 0 # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 0 # number of ticks spent at the given mode +testsys.cpu.kern.mode_good::kernel 0 +testsys.cpu.kern.mode_good::user 0 +testsys.cpu.kern.mode_good::idle 0 +testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches +testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 0 # number of protection mode switches +testsys.cpu.kern.mode_switch_good::kernel no_value # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::user no_value # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::total no_value # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode testsys.cpu.kern.swap_context 0 # number of times the context was actually changed testsys.cpu.not_idle_fraction 0 # Percentage of non-idle cycles testsys.cpu.numCycles 0 # number of cpu cycles simulated @@ -503,15 +503,15 @@ testsys.disk2.dma_read_txs 0 # Nu testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. -testsys.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post -testsys.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post -testsys.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post -testsys.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post -testsys.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post -testsys.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post +testsys.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post +testsys.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA |