diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-25 03:46:12 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-25 03:46:12 -0400 |
| commit | 8845aae4da8dd39880a4072a48a58c4c613e6bce (patch) | |
| tree | e0678b736a5cab44eb7702784f30e5b5c7b9986a /tests | |
| parent | bf7e27fe4554cef1fd5eae4ae0a9e0b26ec2db95 (diff) | |
| download | gem5-8845aae4da8dd39880a4072a48a58c4c613e6bce.tar.xz | |
tests: Add a basic memcheck regression
This patch adds a simple regression that calls the existing
memcheck.py script.
--HG--
rename : tests/configs/learning-gem5-p1-simple.py => tests/configs/memcheck.py
rename : tests/quick/se/70.tgen/test.py => tests/quick/se/51.memcheck/test.py
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/SConscript | 2 | ||||
| -rw-r--r-- | tests/configs/memcheck.py | 59 | ||||
| -rw-r--r-- | tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt | 2725 | ||||
| -rw-r--r-- | tests/quick/se/51.memcheck/test.py | 38 |
4 files changed, 2823 insertions, 1 deletions
diff --git a/tests/SConscript b/tests/SConscript index 886b7fe59..9baf0ea75 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -364,7 +364,7 @@ else: 'simple-timing', 'simple-timing-mp', 'minor-timing', 'minor-timing-mp', 'o3-timing', 'o3-timing-mt', 'o3-timing-mp', - 'rubytest', 'memtest', 'memtest-filter', + 'rubytest', 'memcheck', 'memtest', 'memtest-filter', 'tgen-simple-mem', 'tgen-dram-ctrl'] configs += ['learning-gem5-p1-simple', 'learning-gem5-p1-two-level'] diff --git a/tests/configs/memcheck.py b/tests/configs/memcheck.py new file mode 100644 index 000000000..52931a0b3 --- /dev/null +++ b/tests/configs/memcheck.py @@ -0,0 +1,59 @@ +# Copyright (c) 2016 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Copyright (c) 2015 Jason Lowe-Power +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Jason Lowe-Power +# Andreas Hansson + +# A wrapper around configs/example/memcheck.py + +# For some reason, this is implicitly needed by run.py +root = None + +def run_test(root): + # Called from tests/run.py + + # The path to this script is the only parameter. Delete it so + # we can execute the script that we want to execute. + import sys + del sys.argv[1:] + + # Add a specific max tick + sys.argv.append('-m %d' % maxtick) + + # Execute the script we are wrapping + execfile('configs/example/memcheck.py', globals()) diff --git a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt new file mode 100644 index 000000000..18987ac29 --- /dev/null +++ b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt @@ -0,0 +1,2725 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.010000 # Number of seconds simulated +sim_ticks 10000000000 # Number of ticks simulated +final_tick 10000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_tick_rate 995173175 # Simulator tick rate (ticks/s) +host_mem_usage 1449604 # Number of bytes of host memory used +host_seconds 10.05 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::l0subsys0.tester0 2151552 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys0.tester1 2168960 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys1.tester0 2107520 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys1.tester1 2291904 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys2.tester0 2067776 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys2.tester1 2030080 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys3.tester0 2082688 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys3.tester1 1995392 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys4.tester0 2164544 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys4.tester1 2010944 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys5.tester0 2155328 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys5.tester1 2130240 # Number of bytes read from this memory +system.physmem.bytes_read::l2subsys0.tester 2177536 # Number of bytes read from this memory +system.physmem.bytes_read::total 27534464 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 9685696 # Number of bytes written to this memory +system.physmem.bytes_written::total 9685696 # Number of bytes written to this memory +system.physmem.num_reads::l0subsys0.tester0 33618 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys0.tester1 33890 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys1.tester0 32930 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys1.tester1 35811 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys2.tester0 32309 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys2.tester1 31720 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys3.tester0 32542 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys3.tester1 31178 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys4.tester0 33821 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys4.tester1 31421 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys5.tester0 33677 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys5.tester1 33285 # Number of read requests responded to by this memory +system.physmem.num_reads::l2subsys0.tester 34024 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430226 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 151339 # Number of write requests responded to by this memory +system.physmem.num_writes::total 151339 # Number of write requests responded to by this memory +system.physmem.bw_read::l0subsys0.tester0 215155200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys0.tester1 216896000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys1.tester0 210752000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys1.tester1 229190400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys2.tester0 206777600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys2.tester1 203008000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys3.tester0 208268800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys3.tester1 199539200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys4.tester0 216454400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys4.tester1 201094400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys5.tester0 215532800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys5.tester1 213024000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l2subsys0.tester 217753600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2753446400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 968569600 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 968569600 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 968569600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys0.tester0 215155200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys0.tester1 216896000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys1.tester0 210752000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys1.tester1 229190400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys2.tester0 206777600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys2.tester1 203008000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys3.tester0 208268800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys3.tester1 199539200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys4.tester0 216454400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys4.tester1 201094400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys5.tester0 215532800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys5.tester1 213024000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l2subsys0.tester 217753600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3722016000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430231 # Number of read requests accepted +system.physmem.writeReqs 151339 # Number of write requests accepted +system.physmem.readBursts 430231 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 151339 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27531200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue +system.physmem.bytesWritten 9684288 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27534784 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9685696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26877 # Per bank write bursts +system.physmem.perBankRdBursts::1 26937 # Per bank write bursts +system.physmem.perBankRdBursts::2 26857 # Per bank write bursts +system.physmem.perBankRdBursts::3 26981 # Per bank write bursts +system.physmem.perBankRdBursts::4 26710 # Per bank write bursts +system.physmem.perBankRdBursts::5 26644 # Per bank write bursts +system.physmem.perBankRdBursts::6 26827 # Per bank write bursts +system.physmem.perBankRdBursts::7 26908 # Per bank write bursts +system.physmem.perBankRdBursts::8 26975 # Per bank write bursts +system.physmem.perBankRdBursts::9 26813 # Per bank write bursts +system.physmem.perBankRdBursts::10 27050 # Per bank write bursts +system.physmem.perBankRdBursts::11 26884 # Per bank write bursts +system.physmem.perBankRdBursts::12 26917 # Per bank write bursts +system.physmem.perBankRdBursts::13 26720 # Per bank write bursts +system.physmem.perBankRdBursts::14 26856 # Per bank write bursts +system.physmem.perBankRdBursts::15 27219 # Per bank write bursts +system.physmem.perBankWrBursts::0 9454 # Per bank write bursts +system.physmem.perBankWrBursts::1 9383 # Per bank write bursts +system.physmem.perBankWrBursts::2 9499 # Per bank write bursts +system.physmem.perBankWrBursts::3 9581 # Per bank write bursts +system.physmem.perBankWrBursts::4 9343 # Per bank write bursts +system.physmem.perBankWrBursts::5 9358 # Per bank write bursts +system.physmem.perBankWrBursts::6 9421 # Per bank write bursts +system.physmem.perBankWrBursts::7 9630 # Per bank write bursts +system.physmem.perBankWrBursts::8 9324 # Per bank write bursts +system.physmem.perBankWrBursts::9 9571 # Per bank write bursts +system.physmem.perBankWrBursts::10 9542 # Per bank write bursts +system.physmem.perBankWrBursts::11 9440 # Per bank write bursts +system.physmem.perBankWrBursts::12 9456 # Per bank write bursts +system.physmem.perBankWrBursts::13 9411 # Per bank write bursts +system.physmem.perBankWrBursts::14 9459 # Per bank write bursts +system.physmem.perBankWrBursts::15 9445 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 9999931000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 430231 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 151339 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 40581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 84851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 88171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 66344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 45057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 31235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 5414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 10107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 574593 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 64.767764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 64.530995 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 7.164333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 567789 98.82% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6802 1.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 574593 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 9452 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 45.511532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 43.175305 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 49.584245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 9449 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 2 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-4863 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 9452 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 9451 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.009311 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.008638 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.155730 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9411 99.58% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 8 0.08% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20 0.21% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 10 0.11% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 9451 # Writes before turning the bus around for reads +system.physmem.totQLat 23573477583 # Total ticks spent queuing +system.physmem.totMemAccLat 31639258833 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2150875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 54799.10 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.94 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 73548.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2753.12 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 968.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2753.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 968.57 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 29.07 # Data bus utilization in percentage +system.physmem.busUtilRead 21.51 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 7.57 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 3.99 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.91 # Average write queue length when enqueuing +system.physmem.readRowHits 2754 # Number of row buffer hits during reads +system.physmem.writeRowHits 4139 # Number of row buffer hits during writes +system.physmem.readRowHitRate 0.64 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 2.73 # Row buffer hit rate for writes +system.physmem.avgGap 17194.72 # Average gap between requests +system.physmem.pageHitRate 1.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2169221040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1183602750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1674394800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 490140720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 652991040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6786500940 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 45612000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13002463290 # Total energy per rank (pJ) +system.physmem_0.averagePower 1300.531796 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39716528 # Time in different power states +system.physmem_0.memoryStateTime::REF 333840000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9624262222 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2173220280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1185784875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1679862600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 489998160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 652991040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6784084710 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 47754750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13013696415 # Total energy per rank (pJ) +system.physmem_1.averagePower 1301.650310 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 43432412 # Time in different power states +system.physmem_1.memoryStateTime::REF 333840000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9620586338 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.l0subsys0.tester0.numPackets 67424 # Number of packets generated +system.l0subsys0.tester0.numRetries 2732 # Number of retries +system.l0subsys0.tester0.retryTicks 71787172 # Time spent waiting due to back-pressure (ticks) +system.l0subsys0.tester1.numPackets 67451 # Number of packets generated +system.l0subsys0.tester1.numRetries 2817 # Number of retries +system.l0subsys0.tester1.retryTicks 69161680 # Time spent waiting due to back-pressure (ticks) +system.l0subsys0.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.l0subsys0.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l0subsys0.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l0subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l0subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys0.xbar.trans_dist::ReadReq 86409 # Transaction distribution +system.l0subsys0.xbar.trans_dist::ReadResp 82049 # Transaction distribution +system.l0subsys0.xbar.trans_dist::ReadRespWithInvalidate 4359 # Transaction distribution +system.l0subsys0.xbar.trans_dist::WriteReq 48466 # Transaction distribution +system.l0subsys0.xbar.trans_dist::WriteResp 48465 # Transaction distribution +system.l0subsys0.xbar.trans_dist::WritebackDirty 24314 # Transaction distribution +system.l0subsys0.xbar.trans_dist::CleanEvict 58742 # Transaction distribution +system.l0subsys0.xbar.trans_dist::UpgradeReq 16073 # Transaction distribution +system.l0subsys0.xbar.trans_dist::ReadExReq 19288 # Transaction distribution +system.l0subsys0.xbar.trans_dist::ReadSharedReq 26254 # Transaction distribution +system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 134847 # Packet count per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 134901 # Packet count per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_count::total 269748 # Packet count per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 539392 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 539600 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_size::total 1078992 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys0.xbar.snoops 144671 # Total snoops (count) +system.l0subsys0.xbar.snoop_fanout::samples 282356 # Request fanout histogram +system.l0subsys0.xbar.snoop_fanout::mean 0 # Request fanout histogram +system.l0subsys0.xbar.snoop_fanout::stdev 0 # Request fanout histogram +system.l0subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l0subsys0.xbar.snoop_fanout::0 282356 100.00% 100.00% # Request fanout histogram +system.l0subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l0subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l0subsys0.xbar.snoop_fanout::max_value 0 # Request fanout histogram +system.l0subsys0.xbar.snoop_fanout::total 282356 # Request fanout histogram +system.l0subsys0.xbar.reqLayer0.occupancy 255038046 # Layer occupancy (ticks) +system.l0subsys0.xbar.reqLayer0.utilization 2.6 # Layer utilization (%) +system.l0subsys0.xbar.respLayer0.occupancy 116989147 # Layer occupancy (ticks) +system.l0subsys0.xbar.respLayer0.utilization 1.2 # Layer utilization (%) +system.l0subsys0.xbar.respLayer1.occupancy 116411811 # Layer occupancy (ticks) +system.l0subsys0.xbar.respLayer1.utilization 1.2 # Layer utilization (%) +system.l0subsys1.tester0.numPackets 65180 # Number of packets generated +system.l0subsys1.tester0.numRetries 2851 # Number of retries +system.l0subsys1.tester0.retryTicks 74729692 # Time spent waiting due to back-pressure (ticks) +system.l0subsys1.tester1.numPackets 68174 # Number of packets generated +system.l0subsys1.tester1.numRetries 2790 # Number of retries +system.l0subsys1.tester1.retryTicks 74335880 # Time spent waiting due to back-pressure (ticks) +system.l0subsys1.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.l0subsys1.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l0subsys1.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys1.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l0subsys1.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l0subsys1.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys1.xbar.trans_dist::ReadReq 85972 # Transaction distribution +system.l0subsys1.xbar.trans_dist::ReadResp 82000 # Transaction distribution +system.l0subsys1.xbar.trans_dist::ReadRespWithInvalidate 3972 # Transaction distribution +system.l0subsys1.xbar.trans_dist::WriteReq 47382 # Transaction distribution +system.l0subsys1.xbar.trans_dist::WriteResp 47382 # Transaction distribution +system.l0subsys1.xbar.trans_dist::WritebackDirty 24686 # Transaction distribution +system.l0subsys1.xbar.trans_dist::CleanEvict 59276 # Transaction distribution +system.l0subsys1.xbar.trans_dist::UpgradeReq 14812 # Transaction distribution +system.l0subsys1.xbar.trans_dist::ReadExReq 17637 # Transaction distribution +system.l0subsys1.xbar.trans_dist::ReadSharedReq 23647 # Transaction distribution +system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 130360 # Packet count per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 136348 # Packet count per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_count::total 266708 # Packet count per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 521440 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 545392 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_size::total 1066832 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys1.xbar.snoops 140058 # Total snoops (count) +system.l0subsys1.xbar.snoop_fanout::samples 276384 # Request fanout histogram +system.l0subsys1.xbar.snoop_fanout::mean 0 # Request fanout histogram +system.l0subsys1.xbar.snoop_fanout::stdev 0 # Request fanout histogram +system.l0subsys1.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l0subsys1.xbar.snoop_fanout::0 276384 100.00% 100.00% # Request fanout histogram +system.l0subsys1.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l0subsys1.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l0subsys1.xbar.snoop_fanout::max_value 0 # Request fanout histogram +system.l0subsys1.xbar.snoop_fanout::total 276384 # Request fanout histogram +system.l0subsys1.xbar.reqLayer0.occupancy 252009041 # Layer occupancy (ticks) +system.l0subsys1.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) +system.l0subsys1.xbar.respLayer0.occupancy 113396564 # Layer occupancy (ticks) +system.l0subsys1.xbar.respLayer0.utilization 1.1 # Layer utilization (%) +system.l0subsys1.xbar.respLayer1.occupancy 118377078 # Layer occupancy (ticks) +system.l0subsys1.xbar.respLayer1.utilization 1.2 # Layer utilization (%) +system.l0subsys2.tester0.numPackets 65223 # Number of packets generated +system.l0subsys2.tester0.numRetries 2584 # Number of retries +system.l0subsys2.tester0.retryTicks 64900705 # Time spent waiting due to back-pressure (ticks) +system.l0subsys2.tester1.numPackets 65256 # Number of packets generated +system.l0subsys2.tester1.numRetries 2558 # Number of retries +system.l0subsys2.tester1.retryTicks 64249844 # Time spent waiting due to back-pressure (ticks) +system.l0subsys2.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.l0subsys2.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l0subsys2.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys2.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l0subsys2.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l0subsys2.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys2.xbar.trans_dist::ReadReq 84127 # Transaction distribution +system.l0subsys2.xbar.trans_dist::ReadResp 80122 # Transaction distribution +system.l0subsys2.xbar.trans_dist::ReadRespWithInvalidate 4004 # Transaction distribution +system.l0subsys2.xbar.trans_dist::WriteReq 46352 # Transaction distribution +system.l0subsys2.xbar.trans_dist::WriteResp 46352 # Transaction distribution +system.l0subsys2.xbar.trans_dist::WritebackDirty 22898 # Transaction distribution +system.l0subsys2.xbar.trans_dist::CleanEvict 55455 # Transaction distribution +system.l0subsys2.xbar.trans_dist::UpgradeReq 15512 # Transaction distribution +system.l0subsys2.xbar.trans_dist::ReadExReq 18753 # Transaction distribution +system.l0subsys2.xbar.trans_dist::ReadSharedReq 25514 # Transaction distribution +system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 130445 # Packet count per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 130512 # Packet count per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_count::total 260957 # Packet count per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 521776 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 522048 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_size::total 1043824 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys2.xbar.snoops 138132 # Total snoops (count) +system.l0subsys2.xbar.snoop_fanout::samples 271270 # Request fanout histogram +system.l0subsys2.xbar.snoop_fanout::mean 0 # Request fanout histogram +system.l0subsys2.xbar.snoop_fanout::stdev 0 # Request fanout histogram +system.l0subsys2.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l0subsys2.xbar.snoop_fanout::0 271270 100.00% 100.00% # Request fanout histogram +system.l0subsys2.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l0subsys2.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l0subsys2.xbar.snoop_fanout::max_value 0 # Request fanout histogram +system.l0subsys2.xbar.snoop_fanout::total 271270 # Request fanout histogram +system.l0subsys2.xbar.reqLayer0.occupancy 246097783 # Layer occupancy (ticks) +system.l0subsys2.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) +system.l0subsys2.xbar.respLayer0.occupancy 113755357 # Layer occupancy (ticks) +system.l0subsys2.xbar.respLayer0.utilization 1.1 # Layer utilization (%) +system.l0subsys2.xbar.respLayer1.occupancy 113314488 # Layer occupancy (ticks) +system.l0subsys2.xbar.respLayer1.utilization 1.1 # Layer utilization (%) +system.l0subsys3.tester0.numPackets 66015 # Number of packets generated +system.l0subsys3.tester0.numRetries 2474 # Number of retries +system.l0subsys3.tester0.retryTicks 61325178 # Time spent waiting due to back-pressure (ticks) +system.l0subsys3.tester1.numPackets 63774 # Number of packets generated +system.l0subsys3.tester1.numRetries 2406 # Number of retries +system.l0subsys3.tester1.retryTicks 60532485 # Time spent waiting due to back-pressure (ticks) +system.l0subsys3.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.l0subsys3.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l0subsys3.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys3.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l0subsys3.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l0subsys3.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys3.xbar.trans_dist::ReadReq 83355 # Transaction distribution +system.l0subsys3.xbar.trans_dist::ReadResp 78973 # Transaction distribution +system.l0subsys3.xbar.trans_dist::ReadRespWithInvalidate 4382 # Transaction distribution +system.l0subsys3.xbar.trans_dist::WriteReq 46434 # Transaction distribution +system.l0subsys3.xbar.trans_dist::WriteResp 46434 # Transaction distribution +system.l0subsys3.xbar.trans_dist::WritebackDirty 22791 # Transaction distribution +system.l0subsys3.xbar.trans_dist::CleanEvict 55545 # Transaction distribution +system.l0subsys3.xbar.trans_dist::UpgradeReq 16499 # Transaction distribution +system.l0subsys3.xbar.trans_dist::ReadExReq 19577 # Transaction distribution +system.l0subsys3.xbar.trans_dist::ReadSharedReq 26175 # Transaction distribution +system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 132030 # Packet count per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 127548 # Packet count per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_count::total 259578 # Packet count per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 528120 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 510192 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_size::total 1038312 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys3.xbar.snoops 140587 # Total snoops (count) +system.l0subsys3.xbar.snoop_fanout::samples 272839 # Request fanout histogram +system.l0subsys3.xbar.snoop_fanout::mean 0 # Request fanout histogram +system.l0subsys3.xbar.snoop_fanout::stdev 0 # Request fanout histogram +system.l0subsys3.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l0subsys3.xbar.snoop_fanout::0 272839 100.00% 100.00% # Request fanout histogram +system.l0subsys3.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l0subsys3.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l0subsys3.xbar.snoop_fanout::max_value 0 # Request fanout histogram +system.l0subsys3.xbar.snoop_fanout::total 272839 # Request fanout histogram +system.l0subsys3.xbar.reqLayer0.occupancy 244629226 # Layer occupancy (ticks) +system.l0subsys3.xbar.reqLayer0.utilization 2.4 # Layer utilization (%) +system.l0subsys3.xbar.respLayer0.occupancy 114100947 # Layer occupancy (ticks) +system.l0subsys3.xbar.respLayer0.utilization 1.1 # Layer utilization (%) +system.l0subsys3.xbar.respLayer1.occupancy 110374985 # Layer occupancy (ticks) +system.l0subsys3.xbar.respLayer1.utilization 1.1 # Layer utilization (%) +system.l0subsys4.tester0.numPackets 67184 # Number of packets generated +system.l0subsys4.tester0.numRetries 2523 # Number of retries +system.l0subsys4.tester0.retryTicks 66430147 # Time spent waiting due to back-pressure (ticks) +system.l0subsys4.tester1.numPackets 65756 # Number of packets generated +system.l0subsys4.tester1.numRetries 2580 # Number of retries +system.l0subsys4.tester1.retryTicks 67683660 # Time spent waiting due to back-pressure (ticks) +system.l0subsys4.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.l0subsys4.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l0subsys4.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys4.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l0subsys4.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l0subsys4.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys4.xbar.trans_dist::ReadReq 85507 # Transaction distribution +system.l0subsys4.xbar.trans_dist::ReadResp 81442 # Transaction distribution +system.l0subsys4.xbar.trans_dist::ReadRespWithInvalidate 4064 # Transaction distribution +system.l0subsys4.xbar.trans_dist::WriteReq 47433 # Transaction distribution +system.l0subsys4.xbar.trans_dist::WriteResp 47433 # Transaction distribution +system.l0subsys4.xbar.trans_dist::WritebackDirty 23550 # Transaction distribution +system.l0subsys4.xbar.trans_dist::CleanEvict 56716 # Transaction distribution +system.l0subsys4.xbar.trans_dist::UpgradeReq 15634 # Transaction distribution +system.l0subsys4.xbar.trans_dist::ReadExReq 17863 # Transaction distribution +system.l0subsys4.xbar.trans_dist::ReadSharedReq 24215 # Transaction distribution +system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 134368 # Packet count per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 131511 # Packet count per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_count::total 265879 # Packet count per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 537472 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 526040 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_size::total 1063512 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys4.xbar.snoops 137978 # Total snoops (count) +system.l0subsys4.xbar.snoop_fanout::samples 273585 # Request fanout histogram +system.l0subsys4.xbar.snoop_fanout::mean 0 # Request fanout histogram +system.l0subsys4.xbar.snoop_fanout::stdev 0 # Request fanout histogram +system.l0subsys4.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l0subsys4.xbar.snoop_fanout::0 273585 100.00% 100.00% # Request fanout histogram +system.l0subsys4.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l0subsys4.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l0subsys4.xbar.snoop_fanout::max_value 0 # Request fanout histogram +system.l0subsys4.xbar.snoop_fanout::total 273585 # Request fanout histogram +system.l0subsys4.xbar.reqLayer0.occupancy 250950593 # Layer occupancy (ticks) +system.l0subsys4.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) +system.l0subsys4.xbar.respLayer0.occupancy 116964811 # Layer occupancy (ticks) +system.l0subsys4.xbar.respLayer0.utilization 1.2 # Layer utilization (%) +system.l0subsys4.xbar.respLayer1.occupancy 114597175 # Layer occupancy (ticks) +system.l0subsys4.xbar.respLayer1.utilization 1.1 # Layer utilization (%) +system.l0subsys5.tester0.numPackets 67119 # Number of packets generated +system.l0subsys5.tester0.numRetries 2560 # Number of retries +system.l0subsys5.tester0.retryTicks 65403498 # Time spent waiting due to back-pressure (ticks) +system.l0subsys5.tester1.numPackets 65308 # Number of packets generated +system.l0subsys5.tester1.numRetries 2642 # Number of retries +system.l0subsys5.tester1.retryTicks 65659220 # Time spent waiting due to back-pressure (ticks) +system.l0subsys5.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.l0subsys5.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l0subsys5.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys5.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l0subsys5.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l0subsys5.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l0subsys5.xbar.trans_dist::ReadReq 85511 # Transaction distribution +system.l0subsys5.xbar.trans_dist::ReadResp 81276 # Transaction distribution +system.l0subsys5.xbar.trans_dist::ReadRespWithInvalidate 4233 # Transaction distribution +system.l0subsys5.xbar.trans_dist::WriteReq 46916 # Transaction distribution +system.l0subsys5.xbar.trans_dist::WriteResp 46916 # Transaction distribution +system.l0subsys5.xbar.trans_dist::WritebackDirty 23832 # Transaction distribution +system.l0subsys5.xbar.trans_dist::CleanEvict 57742 # Transaction distribution +system.l0subsys5.xbar.trans_dist::UpgradeReq 16247 # Transaction distribution +system.l0subsys5.xbar.trans_dist::ReadExReq 18726 # Transaction distribution +system.l0subsys5.xbar.trans_dist::ReadSharedReq 25287 # Transaction distribution +system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 134237 # Packet count per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 130615 # Packet count per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_count::total 264852 # Packet count per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 536944 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 522456 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_size::total 1059400 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys5.xbar.snoops 141834 # Total snoops (count) +system.l0subsys5.xbar.snoop_fanout::samples 276831 # Request fanout histogram +system.l0subsys5.xbar.snoop_fanout::mean 0 # Request fanout histogram +system.l0subsys5.xbar.snoop_fanout::stdev 0 # Request fanout histogram +system.l0subsys5.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l0subsys5.xbar.snoop_fanout::0 276831 100.00% 100.00% # Request fanout histogram +system.l0subsys5.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l0subsys5.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l0subsys5.xbar.snoop_fanout::max_value 0 # Request fanout histogram +system.l0subsys5.xbar.snoop_fanout::total 276831 # Request fanout histogram +system.l0subsys5.xbar.reqLayer0.occupancy 249400901 # Layer occupancy (ticks) +system.l0subsys5.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) +system.l0subsys5.xbar.respLayer0.occupancy 116426882 # Layer occupancy (ticks) +system.l0subsys5.xbar.respLayer0.utilization 1.2 # Layer utilization (%) +system.l0subsys5.xbar.respLayer1.occupancy 112976792 # Layer occupancy (ticks) +system.l0subsys5.xbar.respLayer1.utilization 1.1 # Layer utilization (%) +system.l1subsys0.cache0.tags.replacements 67551 # number of replacements +system.l1subsys0.cache0.tags.tagsinuse 502.758409 # Cycle average of tags in use +system.l1subsys0.cache0.tags.total_refs 31003 # Total number of references to valid blocks. +system.l1subsys0.cache0.tags.sampled_refs 68058 # Sample count of references to valid blocks. +system.l1subsys0.cache0.tags.avg_refs 0.455538 # Average number of references to valid blocks. +system.l1subsys0.cache0.tags.warmup_cycle 710764000 # Cycle when the warmup percentage was hit. +system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester0 249.937583 # Average occupied blocks per requestor +system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester1 252.820826 # Average occupied blocks per requestor +system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester0 0.488159 # Average percentage of cache occupancy +system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester1 0.493791 # Average percentage of cache occupancy +system.l1subsys0.cache0.tags.occ_percent::total 0.981950 # Average percentage of cache occupancy +system.l1subsys0.cache0.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id +system.l1subsys0.cache0.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.l1subsys0.cache0.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.l1subsys0.cache0.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.l1subsys0.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id +system.l1subsys0.cache0.tags.tag_accesses 641417 # Number of tag accesses +system.l1subsys0.cache0.tags.data_accesses 641417 # Number of data accesses +system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester0 9938 # number of ReadReq hits +system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester1 9361 # number of ReadReq hits +system.l1subsys0.cache0.ReadReq_hits::total 19299 # number of ReadReq hits +system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester0 1368 # number of WriteReq hits +system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester1 1240 # number of WriteReq hits +system.l1subsys0.cache0.WriteReq_hits::total 2608 # number of WriteReq hits +system.l1subsys0.cache0.demand_hits::l0subsys0.tester0 11306 # number of demand (read+write) hits +system.l1subsys0.cache0.demand_hits::l0subsys0.tester1 10601 # number of demand (read+write) hits +system.l1subsys0.cache0.demand_hits::total 21907 # number of demand (read+write) hits +system.l1subsys0.cache0.overall_hits::l0subsys0.tester0 11306 # number of overall hits +system.l1subsys0.cache0.overall_hits::l0subsys0.tester1 10601 # number of overall hits +system.l1subsys0.cache0.overall_hits::total 21907 # number of overall hits +system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester0 33357 # number of ReadReq misses +system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester1 33753 # number of ReadReq misses +system.l1subsys0.cache0.ReadReq_misses::total 67110 # number of ReadReq misses +system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester0 22761 # number of WriteReq misses +system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester1 23097 # number of WriteReq misses +system.l1subsys0.cache0.WriteReq_misses::total 45858 # number of WriteReq misses +system.l1subsys0.cache0.demand_misses::l0subsys0.tester0 56118 # number of demand (read+write) misses +system.l1subsys0.cache0.demand_misses::l0subsys0.tester1 56850 # number of demand (read+write) misses +system.l1subsys0.cache0.demand_misses::total 112968 # number of demand (read+write) misses +system.l1subsys0.cache0.overall_misses::l0subsys0.tester0 56118 # number of overall misses +system.l1subsys0.cache0.overall_misses::l0subsys0.tester1 56850 # number of overall misses +system.l1subsys0.cache0.overall_misses::total 112968 # number of overall misses +system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester0 3073108727 # number of ReadReq miss cycles +system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester1 3087222111 # number of ReadReq miss cycles +system.l1subsys0.cache0.ReadReq_miss_latency::total 6160330838 # number of ReadReq miss cycles +system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester0 1908688077 # number of WriteReq miss cycles +system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester1 1921428264 # number of WriteReq miss cycles +system.l1subsys0.cache0.WriteReq_miss_latency::total 3830116341 # number of WriteReq miss cycles +system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester0 4981796804 # number of demand (read+write) miss cycles +system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester1 5008650375 # number of demand (read+write) miss cycles +system.l1subsys0.cache0.demand_miss_latency::total 9990447179 # number of demand (read+write) miss cycles +system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester0 4981796804 # number of overall miss cycles +system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester1 5008650375 # number of overall miss cycles +system.l1subsys0.cache0.overall_miss_latency::total 9990447179 # number of overall miss cycles +system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester0 43295 # number of ReadReq accesses(hits+misses) +system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester1 43114 # number of ReadReq accesses(hits+misses) +system.l1subsys0.cache0.ReadReq_accesses::total 86409 # number of ReadReq accesses(hits+misses) +system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester0 24129 # number of WriteReq accesses(hits+misses) +system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester1 24337 # number of WriteReq accesses(hits+misses) +system.l1subsys0.cache0.WriteReq_accesses::total 48466 # number of WriteReq accesses(hits+misses) +system.l1subsys0.cache0.demand_accesses::l0subsys0.tester0 67424 # number of demand (read+write) accesses +system.l1subsys0.cache0.demand_accesses::l0subsys0.tester1 67451 # number of demand (read+write) accesses +system.l1subsys0.cache0.demand_accesses::total 134875 # number of demand (read+write) accesses +system.l1subsys0.cache0.overall_accesses::l0subsys0.tester0 67424 # number of overall (read+write) accesses +system.l1subsys0.cache0.overall_accesses::l0subsys0.tester1 67451 # number of overall (read+write) accesses +system.l1subsys0.cache0.overall_accesses::total 134875 # number of overall (read+write) accesses +system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester0 0.770458 # miss rate for ReadReq accesses +system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester1 0.782878 # miss rate for ReadReq accesses +system.l1subsys0.cache0.ReadReq_miss_rate::total 0.776655 # miss rate for ReadReq accesses +system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester0 0.943305 # miss rate for WriteReq accesses +system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester1 0.949049 # miss rate for WriteReq accesses +system.l1subsys0.cache0.WriteReq_miss_rate::total 0.946189 # miss rate for WriteReq accesses +system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester0 0.832315 # miss rate for demand accesses +system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester1 0.842834 # miss rate for demand accesses +system.l1subsys0.cache0.demand_miss_rate::total 0.837576 # miss rate for demand accesses +system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester0 0.832315 # miss rate for overall accesses +system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester1 0.842834 # miss rate for overall accesses +system.l1subsys0.cache0.overall_miss_rate::total 0.837576 # miss rate for overall accesses +system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester0 92127.851036 # average ReadReq miss latency +system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester1 91465.117501 # average ReadReq miss latency +system.l1subsys0.cache0.ReadReq_avg_miss_latency::total 91794.528952 # average ReadReq miss latency +system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester0 83857.830368 # average WriteReq miss latency +system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester1 83189.516561 # average WriteReq miss latency +system.l1subsys0.cache0.WriteReq_avg_miss_latency::total 83521.225108 # average WriteReq miss latency +system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester0 88773.598560 # average overall miss latency +system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester1 88102.908971 # average overall miss latency +system.l1subsys0.cache0.demand_avg_miss_latency::total 88436.080828 # average overall miss latency +system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester0 88773.598560 # average overall miss latency +system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester1 88102.908971 # average overall miss latency +system.l1subsys0.cache0.overall_avg_miss_latency::total 88436.080828 # average overall miss latency +system.l1subsys0.cache0.blocked_cycles::no_mshrs 271859 # number of cycles access was blocked +system.l1subsys0.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l1subsys0.cache0.blocked::no_mshrs 8472 # number of cycles access was blocked +system.l1subsys0.cache0.blocked::no_targets 0 # number of cycles access was blocked +system.l1subsys0.cache0.avg_blocked_cycles::no_mshrs 32.089117 # average number of cycles each access was blocked +system.l1subsys0.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l1subsys0.cache0.writebacks::writebacks 24312 # number of writebacks +system.l1subsys0.cache0.writebacks::total 24312 # number of writebacks +system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester0 1310 # number of ReadReq MSHR hits +system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester1 1307 # number of ReadReq MSHR hits +system.l1subsys0.cache0.ReadReq_mshr_hits::total 2617 # number of ReadReq MSHR hits +system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester0 720 # number of WriteReq MSHR hits +system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester1 761 # number of WriteReq MSHR hits +system.l1subsys0.cache0.WriteReq_mshr_hits::total 1481 # number of WriteReq MSHR hits +system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester0 2030 # number of demand (read+write) MSHR hits +system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester1 2068 # number of demand (read+write) MSHR hits +system.l1subsys0.cache0.demand_mshr_hits::total 4098 # number of demand (read+write) MSHR hits +system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester0 2030 # number of overall MSHR hits +system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester1 2068 # number of overall MSHR hits +system.l1subsys0.cache0.overall_mshr_hits::total 4098 # number of overall MSHR hits +system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester0 32047 # number of ReadReq MSHR misses +system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester1 32446 # number of ReadReq MSHR misses +system.l1subsys0.cache0.ReadReq_mshr_misses::total 64493 # number of ReadReq MSHR misses +system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester0 22041 # number of WriteReq MSHR misses +system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester1 22336 # number of WriteReq MSHR misses +system.l1subsys0.cache0.WriteReq_mshr_misses::total 44377 # number of WriteReq MSHR misses +system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester0 54088 # number of demand (read+write) MSHR misses +system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester1 54782 # number of demand (read+write) MSHR misses +system.l1subsys0.cache0.demand_mshr_misses::total 108870 # number of demand (read+write) MSHR misses +system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester0 54088 # number of overall MSHR misses +system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester1 54782 # number of overall MSHR misses +system.l1subsys0.cache0.overall_mshr_misses::total 108870 # number of overall MSHR misses +system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester0 3011177002 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester1 3025731013 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache0.ReadReq_mshr_miss_latency::total 6036908015 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester0 1877689400 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester1 1889694563 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache0.WriteReq_mshr_miss_latency::total 3767383963 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester0 4888866402 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester1 4915425576 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache0.demand_mshr_miss_latency::total 9804291978 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester0 4888866402 # number of overall MSHR miss cycles +system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester1 4915425576 # number of overall MSHR miss cycles +system.l1subsys0.cache0.overall_mshr_miss_latency::total 9804291978 # number of overall MSHR miss cycles +system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester0 0.740201 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester1 0.752563 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache0.ReadReq_mshr_miss_rate::total 0.746369 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester0 0.913465 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester1 0.917780 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache0.WriteReq_mshr_miss_rate::total 0.915632 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester0 0.802207 # mshr miss rate for demand accesses +system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester1 0.812175 # mshr miss rate for demand accesses +system.l1subsys0.cache0.demand_mshr_miss_rate::total 0.807192 # mshr miss rate for demand accesses +system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester0 0.802207 # mshr miss rate for overall accesses +system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester1 0.812175 # mshr miss rate for overall accesses +system.l1subsys0.cache0.overall_mshr_miss_rate::total 0.807192 # mshr miss rate for overall accesses +system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester0 93961.275689 # average ReadReq mshr miss latency +system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester1 93254.361493 # average ReadReq mshr miss latency +system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 93605.631852 # average ReadReq mshr miss latency +system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester0 85190.753596 # average WriteReq mshr miss latency +system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester1 84603.087527 # average WriteReq mshr miss latency +system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 84894.967280 # average WriteReq mshr miss latency +system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester0 90387.265234 # average overall mshr miss latency +system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester1 89727.019386 # average overall mshr miss latency +system.l1subsys0.cache0.demand_avg_mshr_miss_latency::total 90055.037917 # average overall mshr miss latency +system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester0 90387.265234 # average overall mshr miss latency +system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester1 89727.019386 # average overall mshr miss latency +system.l1subsys0.cache0.overall_avg_mshr_miss_latency::total 90055.037917 # average overall mshr miss latency +system.l1subsys0.cache1.tags.replacements 68848 # number of replacements +system.l1subsys0.cache1.tags.tagsinuse 504.594743 # Cycle average of tags in use +system.l1subsys0.cache1.tags.total_refs 31105 # Total number of references to valid blocks. +system.l1subsys0.cache1.tags.sampled_refs 69348 # Sample count of references to valid blocks. +system.l1subsys0.cache1.tags.avg_refs 0.448535 # Average number of references to valid blocks. +system.l1subsys0.cache1.tags.warmup_cycle 229896000 # Cycle when the warmup percentage was hit. +system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 242.878191 # Average occupied blocks per requestor +system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 261.716552 # Average occupied blocks per requestor +system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.474371 # Average percentage of cache occupancy +system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.511165 # Average percentage of cache occupancy +system.l1subsys0.cache1.tags.occ_percent::total 0.985537 # Average percentage of cache occupancy +system.l1subsys0.cache1.tags.occ_task_id_blocks::1024 500 # Occupied blocks per task id +system.l1subsys0.cache1.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.l1subsys0.cache1.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id +system.l1subsys0.cache1.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.l1subsys0.cache1.tags.occ_task_id_percent::1024 0.976562 # Percentage of cache occupancy per task id +system.l1subsys0.cache1.tags.tag_accesses 633805 # Number of tag accesses +system.l1subsys0.cache1.tags.data_accesses 633805 # Number of data accesses +system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester0 9817 # number of ReadReq hits +system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester1 9861 # number of ReadReq hits +system.l1subsys0.cache1.ReadReq_hits::total 19678 # number of ReadReq hits +system.l1subsys0.cache1.WriteReq_hits::l0subsys1.tester0 1351 # number of WriteReq hits +system.l1subsys0.cache1.WriteReq_hits::l0subsys1.tester1 1518 # number of WriteReq hits +system.l1subsys0.cache1.WriteReq_hits::total 2869 # number of WriteReq hits +system.l1subsys0.cache1.demand_hits::l0subsys1.tester0 11168 # number of demand (read+write) hits +system.l1subsys0.cache1.demand_hits::l0subsys1.tester1 11379 # number of demand (read+write) hits +system.l1subsys0.cache1.demand_hits::total 22547 # number of demand (read+write) hits +system.l1subsys0.cache1.overall_hits::l0subsys1.tester0 11168 # number of overall hits +system.l1subsys0.cache1.overall_hits::l0subsys1.tester1 11379 # number of overall hits +system.l1subsys0.cache1.overall_hits::total 22547 # number of overall hits +system.l1subsys0.cache1.ReadReq_misses::l0subsys1.tester0 32254 # number of ReadReq misses +system.l1subsys0.cache1.ReadReq_misses::l0subsys1.tester1 34040 # number of ReadReq misses +system.l1subsys0.cache1.ReadReq_misses::total 66294 # number of ReadReq misses +system.l1subsys0.cache1.WriteReq_misses::l0subsys1.tester0 21758 # number of WriteReq misses +system.l1subsys0.cache1.WriteReq_misses::l0subsys1.tester1 22755 # number of WriteReq misses +system.l1subsys0.cache1.WriteReq_misses::total 44513 # number of WriteReq misses +system.l1subsys0.cache1.demand_misses::l0subsys1.tester0 54012 # number of demand (read+write) misses +system.l1subsys0.cache1.demand_misses::l0subsys1.tester1 56795 # number of demand (read+write) misses +system.l1subsys0.cache1.demand_misses::total 110807 # number of demand (read+write) misses +system.l1subsys0.cache1.overall_misses::l0subsys1.tester0 54012 # number of overall misses +system.l1subsys0.cache1.overall_misses::l0subsys1.tester1 56795 # number of overall misses +system.l1subsys0.cache1.overall_misses::total 110807 # number of overall misses +system.l1subsys0.cache1.ReadReq_miss_latency::l0subsys1.tester0 3004206885 # number of ReadReq miss cycles +system.l1subsys0.cache1.ReadReq_miss_latency::l0subsys1.tester1 3239071777 # number of ReadReq miss cycles +system.l1subsys0.cache1.ReadReq_miss_latency::total 6243278662 # number of ReadReq miss cycles +system.l1subsys0.cache1.WriteReq_miss_latency::l0subsys1.tester0 1840884693 # number of WriteReq miss cycles +system.l1subsys0.cache1.WriteReq_miss_latency::l0subsys1.tester1 1956345465 # number of WriteReq miss cycles +system.l1subsys0.cache1.WriteReq_miss_latency::total 3797230158 # number of WriteReq miss cycles +system.l1subsys0.cache1.demand_miss_latency::l0subsys1.tester0 4845091578 # number of demand (read+write) miss cycles +system.l1subsys0.cache1.demand_miss_latency::l0subsys1.tester1 5195417242 # number of demand (read+write) miss cycles +system.l1subsys0.cache1.demand_miss_latency::total 10040508820 # number of demand (read+write) miss cycles +system.l1subsys0.cache1.overall_miss_latency::l0subsys1.tester0 4845091578 # number of overall miss cycles +system.l1subsys0.cache1.overall_miss_latency::l0subsys1.tester1 5195417242 # number of overall miss cycles +system.l1subsys0.cache1.overall_miss_latency::total 10040508820 # number of overall miss cycles +system.l1subsys0.cache1.ReadReq_accesses::l0subsys1.tester0 42071 # number of ReadReq accesses(hits+misses) +system.l1subsys0.cache1.ReadReq_accesses::l0subsys1.tester1 43901 # number of ReadReq accesses(hits+misses) +system.l1subsys0.cache1.ReadReq_accesses::total 85972 # number of ReadReq accesses(hits+misses) +system.l1subsys0.cache1.WriteReq_accesses::l0subsys1.tester0 23109 # number of WriteReq accesses(hits+misses) +system.l1subsys0.cache1.WriteReq_accesses::l0subsys1.tester1 24273 # number of WriteReq accesses(hits+misses) +system.l1subsys0.cache1.WriteReq_accesses::total 47382 # number of WriteReq accesses(hits+misses) +system.l1subsys0.cache1.demand_accesses::l0subsys1.tester0 65180 # number of demand (read+write) accesses +system.l1subsys0.cache1.demand_accesses::l0subsys1.tester1 68174 # number of demand (read+write) accesses +system.l1subsys0.cache1.demand_accesses::total 133354 # number of demand (read+write) accesses +system.l1subsys0.cache1.overall_accesses::l0subsys1.tester0 65180 # number of overall (read+write) accesses +system.l1subsys0.cache1.overall_accesses::l0subsys1.tester1 68174 # number of overall (read+write) accesses +system.l1subsys0.cache1.overall_accesses::total 133354 # number of overall (read+write) accesses +system.l1subsys0.cache1.ReadReq_miss_rate::l0subsys1.tester0 0.766656 # miss rate for ReadReq accesses +system.l1subsys0.cache1.ReadReq_miss_rate::l0subsys1.tester1 0.775381 # miss rate for ReadReq accesses +system.l1subsys0.cache1.ReadReq_miss_rate::total 0.771112 # miss rate for ReadReq accesses +system.l1subsys0.cache1.WriteReq_miss_rate::l0subsys1.tester0 0.941538 # miss rate for WriteReq accesses +system.l1subsys0.cache1.WriteReq_miss_rate::l0subsys1.tester1 0.937461 # miss rate for WriteReq accesses +system.l1subsys0.cache1.WriteReq_miss_rate::total 0.939450 # miss rate for WriteReq accesses +system.l1subsys0.cache1.demand_miss_rate::l0subsys1.tester0 0.828659 # miss rate for demand accesses +system.l1subsys0.cache1.demand_miss_rate::l0subsys1.tester1 0.833089 # miss rate for demand accesses +system.l1subsys0.cache1.demand_miss_rate::total 0.830924 # miss rate for demand accesses +system.l1subsys0.cache1.overall_miss_rate::l0subsys1.tester0 0.828659 # miss rate for overall accesses +system.l1subsys0.cache1.overall_miss_rate::l0subsys1.tester1 0.833089 # miss rate for overall accesses +system.l1subsys0.cache1.overall_miss_rate::total 0.830924 # miss rate for overall accesses +system.l1subsys0.cache1.ReadReq_avg_miss_latency::l0subsys1.tester0 93142.149346 # average ReadReq miss latency +system.l1subsys0.cache1.ReadReq_avg_miss_latency::l0subsys1.tester1 95154.870065 # average ReadReq miss latency +system.l1subsys0.cache1.ReadReq_avg_miss_latency::total 94175.621655 # average ReadReq miss latency +system.l1subsys0.cache1.WriteReq_avg_miss_latency::l0subsys1.tester0 84607.256779 # average WriteReq miss latency +system.l1subsys0.cache1.WriteReq_avg_miss_latency::l0subsys1.tester1 85974.311800 # average WriteReq miss latency +system.l1subsys0.cache1.WriteReq_avg_miss_latency::total 85306.093905 # average WriteReq miss latency +system.l1subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester0 89703.983892 # average overall miss latency +system.l1subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester1 91476.665939 # average overall miss latency +system.l1subsys0.cache1.demand_avg_miss_latency::total 90612.586028 # average overall miss latency +system.l1subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester0 89703.983892 # average overall miss latency +system.l1subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester1 91476.665939 # average overall miss latency +system.l1subsys0.cache1.overall_avg_miss_latency::total 90612.586028 # average overall miss latency +system.l1subsys0.cache1.blocked_cycles::no_mshrs 280334 # number of cycles access was blocked +system.l1subsys0.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l1subsys0.cache1.blocked::no_mshrs 8630 # number of cycles access was blocked +system.l1subsys0.cache1.blocked::no_targets 0 # number of cycles access was blocked +system.l1subsys0.cache1.avg_blocked_cycles::no_mshrs 32.483662 # average number of cycles each access was blocked +system.l1subsys0.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l1subsys0.cache1.writebacks::writebacks 24682 # number of writebacks +system.l1subsys0.cache1.writebacks::total 24682 # number of writebacks +system.l1subsys0.cache1.ReadReq_mshr_hits::l0subsys1.tester0 1198 # number of ReadReq MSHR hits +system.l1subsys0.cache1.ReadReq_mshr_hits::l0subsys1.tester1 1188 # number of ReadReq MSHR hits +system.l1subsys0.cache1.ReadReq_mshr_hits::total 2386 # number of ReadReq MSHR hits +system.l1subsys0.cache1.WriteReq_mshr_hits::l0subsys1.tester0 668 # number of WriteReq MSHR hits +system.l1subsys0.cache1.WriteReq_mshr_hits::l0subsys1.tester1 692 # number of WriteReq MSHR hits +system.l1subsys0.cache1.WriteReq_mshr_hits::total 1360 # number of WriteReq MSHR hits +system.l1subsys0.cache1.demand_mshr_hits::l0subsys1.tester0 1866 # number of demand (read+write) MSHR hits +system.l1subsys0.cache1.demand_mshr_hits::l0subsys1.tester1 1880 # number of demand (read+write) MSHR hits +system.l1subsys0.cache1.demand_mshr_hits::total 3746 # number of demand (read+write) MSHR hits +system.l1subsys0.cache1.overall_mshr_hits::l0subsys1.tester0 1866 # number of overall MSHR hits +system.l1subsys0.cache1.overall_mshr_hits::l0subsys1.tester1 1880 # number of overall MSHR hits +system.l1subsys0.cache1.overall_mshr_hits::total 3746 # number of overall MSHR hits +system.l1subsys0.cache1.ReadReq_mshr_misses::l0subsys1.tester0 31056 # number of ReadReq MSHR misses +system.l1subsys0.cache1.ReadReq_mshr_misses::l0subsys1.tester1 32852 # number of ReadReq MSHR misses +system.l1subsys0.cache1.ReadReq_mshr_misses::total 63908 # number of ReadReq MSHR misses +system.l1subsys0.cache1.WriteReq_mshr_misses::l0subsys1.tester0 21090 # number of WriteReq MSHR misses +system.l1subsys0.cache1.WriteReq_mshr_misses::l0subsys1.tester1 22063 # number of WriteReq MSHR misses +system.l1subsys0.cache1.WriteReq_mshr_misses::total 43153 # number of WriteReq MSHR misses +system.l1subsys0.cache1.demand_mshr_misses::l0subsys1.tester0 52146 # number of demand (read+write) MSHR misses +system.l1subsys0.cache1.demand_mshr_misses::l0subsys1.tester1 54915 # number of demand (read+write) MSHR misses +system.l1subsys0.cache1.demand_mshr_misses::total 107061 # number of demand (read+write) MSHR misses +system.l1subsys0.cache1.overall_mshr_misses::l0subsys1.tester0 52146 # number of overall MSHR misses +system.l1subsys0.cache1.overall_mshr_misses::l0subsys1.tester1 54915 # number of overall MSHR misses +system.l1subsys0.cache1.overall_mshr_misses::total 107061 # number of overall MSHR misses +system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester0 2946301712 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester1 3181085510 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache1.ReadReq_mshr_miss_latency::total 6127387222 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester0 1810955934 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester1 1924620571 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache1.WriteReq_mshr_miss_latency::total 3735576505 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 4757257646 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester1 5105706081 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache1.demand_mshr_miss_latency::total 9862963727 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester0 4757257646 # number of overall MSHR miss cycles +system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester1 5105706081 # number of overall MSHR miss cycles +system.l1subsys0.cache1.overall_mshr_miss_latency::total 9862963727 # number of overall MSHR miss cycles +system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester0 0.738181 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester1 0.748320 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache1.ReadReq_mshr_miss_rate::total 0.743358 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester0 0.912631 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester1 0.908952 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache1.WriteReq_mshr_miss_rate::total 0.910747 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.800031 # mshr miss rate for demand accesses +system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.805512 # mshr miss rate for demand accesses +system.l1subsys0.cache1.demand_mshr_miss_rate::total 0.802833 # mshr miss rate for demand accesses +system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.800031 # mshr miss rate for overall accesses +system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.805512 # mshr miss rate for overall accesses +system.l1subsys0.cache1.overall_mshr_miss_rate::total 0.802833 # mshr miss rate for overall accesses +system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester0 94870.611540 # average ReadReq mshr miss latency +system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester1 96830.802082 # average ReadReq mshr miss latency +system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::total 95878.250329 # average ReadReq mshr miss latency +system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester0 85867.991181 # average WriteReq mshr miss latency +system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester1 87232.949780 # average WriteReq mshr miss latency +system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::total 86565.858805 # average WriteReq mshr miss latency +system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 91229.579373 # average overall mshr miss latency +system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 92974.707839 # average overall mshr miss latency +system.l1subsys0.cache1.demand_avg_mshr_miss_latency::total 92124.711398 # average overall mshr miss latency +system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 91229.579373 # average overall mshr miss latency +system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 92974.707839 # average overall mshr miss latency +system.l1subsys0.cache1.overall_avg_mshr_miss_latency::total 92124.711398 # average overall mshr miss latency +system.l1subsys0.xbar.snoop_filter.tot_requests 354135 # Total number of requests made to the snoop filter. +system.l1subsys0.xbar.snoop_filter.hit_single_requests 168078 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l1subsys0.xbar.snoop_filter.hit_multi_requests 8556 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys0.xbar.snoop_filter.tot_snoops 114062 # Total number of snoops made to the snoop filter. +system.l1subsys0.xbar.snoop_filter.hit_single_snoops 98725 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l1subsys0.xbar.snoop_filter.hit_multi_snoops 15337 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys0.xbar.trans_dist::ReadResp 154200 # Transaction distribution +system.l1subsys0.xbar.trans_dist::ReadRespWithInvalidate 3741 # Transaction distribution +system.l1subsys0.xbar.trans_dist::WritebackDirty 97097 # Transaction distribution +system.l1subsys0.xbar.trans_dist::CleanEvict 173883 # Transaction distribution +system.l1subsys0.xbar.trans_dist::UpgradeReq 38331 # Transaction distribution +system.l1subsys0.xbar.trans_dist::UpgradeResp 23879 # Transaction distribution +system.l1subsys0.xbar.trans_dist::ReadExReq 99951 # Transaction distribution +system.l1subsys0.xbar.trans_dist::ReadExResp 92343 # Transaction distribution +system.l1subsys0.xbar.trans_dist::ReadSharedReq 167597 # Transaction distribution +system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 309959 # Packet count per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 304154 # Packet count per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_count::total 614113 # Packet count per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 9308608 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 9043712 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_size::total 18352320 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys0.xbar.snoops 293338 # Total snoops (count) +system.l1subsys0.xbar.snoop_fanout::samples 440460 # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::mean 0.353033 # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::stdev 0.545932 # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::0 300300 68.18% 68.18% # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::1 124823 28.34% 96.52% # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::2 15337 3.48% 100.00% # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::max_value 2 # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::total 440460 # Request fanout histogram +system.l1subsys0.xbar.reqLayer0.occupancy 551865865 # Layer occupancy (ticks) +system.l1subsys0.xbar.reqLayer0.utilization 5.5 # Layer utilization (%) +system.l1subsys0.xbar.snoopLayer0.occupancy 170972115 # Layer occupancy (ticks) +system.l1subsys0.xbar.snoopLayer0.utilization 1.7 # Layer utilization (%) +system.l1subsys0.xbar.respLayer0.occupancy 318997409 # Layer occupancy (ticks) +system.l1subsys0.xbar.respLayer0.utilization 3.2 # Layer utilization (%) +system.l1subsys0.xbar.respLayer1.occupancy 314273952 # Layer occupancy (ticks) +system.l1subsys0.xbar.respLayer1.utilization 3.1 # Layer utilization (%) +system.l1subsys1.cache0.tags.replacements 64055 # number of replacements +system.l1subsys1.cache0.tags.tagsinuse 501.915078 # Cycle average of tags in use +system.l1subsys1.cache0.tags.total_refs 31614 # Total number of references to valid blocks. +system.l1subsys1.cache0.tags.sampled_refs 64566 # Sample count of references to valid blocks. +system.l1subsys1.cache0.tags.avg_refs 0.489639 # Average number of references to valid blocks. +system.l1subsys1.cache0.tags.warmup_cycle 361927000 # Cycle when the warmup percentage was hit. +system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester0 251.524472 # Average occupied blocks per requestor +system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester1 250.390607 # Average occupied blocks per requestor +system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester0 0.491259 # Average percentage of cache occupancy +system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester1 0.489044 # Average percentage of cache occupancy +system.l1subsys1.cache0.tags.occ_percent::total 0.980303 # Average percentage of cache occupancy +system.l1subsys1.cache0.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.l1subsys1.cache0.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.l1subsys1.cache0.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id +system.l1subsys1.cache0.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.l1subsys1.cache0.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.l1subsys1.cache0.tags.tag_accesses 619158 # Number of tag accesses +system.l1subsys1.cache0.tags.data_accesses 619158 # Number of data accesses +system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester0 10039 # number of ReadReq hits +system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester1 9798 # number of ReadReq hits +system.l1subsys1.cache0.ReadReq_hits::total 19837 # number of ReadReq hits +system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester0 1458 # number of WriteReq hits +system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester1 1375 # number of WriteReq hits +system.l1subsys1.cache0.WriteReq_hits::total 2833 # number of WriteReq hits +system.l1subsys1.cache0.demand_hits::l0subsys2.tester0 11497 # number of demand (read+write) hits +system.l1subsys1.cache0.demand_hits::l0subsys2.tester1 11173 # number of demand (read+write) hits +system.l1subsys1.cache0.demand_hits::total 22670 # number of demand (read+write) hits +system.l1subsys1.cache0.overall_hits::l0subsys2.tester0 11497 # number of overall hits +system.l1subsys1.cache0.overall_hits::l0subsys2.tester1 11173 # number of overall hits +system.l1subsys1.cache0.overall_hits::total 22670 # number of overall hits +system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester0 32196 # number of ReadReq misses +system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester1 32094 # number of ReadReq misses +system.l1subsys1.cache0.ReadReq_misses::total 64290 # number of ReadReq misses +system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester0 21530 # number of WriteReq misses +system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester1 21989 # number of WriteReq misses +system.l1subsys1.cache0.WriteReq_misses::total 43519 # number of WriteReq misses +system.l1subsys1.cache0.demand_misses::l0subsys2.tester0 53726 # number of demand (read+write) misses +system.l1subsys1.cache0.demand_misses::l0subsys2.tester1 54083 # number of demand (read+write) misses +system.l1subsys1.cache0.demand_misses::total 107809 # number of demand (read+write) misses +system.l1subsys1.cache0.overall_misses::l0subsys2.tester0 53726 # number of overall misses +system.l1subsys1.cache0.overall_misses::l0subsys2.tester1 54083 # number of overall misses +system.l1subsys1.cache0.overall_misses::total 107809 # number of overall misses +system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester0 2965752810 # number of ReadReq miss cycles +system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester1 2931730977 # number of ReadReq miss cycles +system.l1subsys1.cache0.ReadReq_miss_latency::total 5897483787 # number of ReadReq miss cycles +system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester0 1800358800 # number of WriteReq miss cycles +system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester1 1820867176 # number of WriteReq miss cycles +system.l1subsys1.cache0.WriteReq_miss_latency::total 3621225976 # number of WriteReq miss cycles +system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester0 4766111610 # number of demand (read+write) miss cycles +system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester1 4752598153 # number of demand (read+write) miss cycles +system.l1subsys1.cache0.demand_miss_latency::total 9518709763 # number of demand (read+write) miss cycles +system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester0 4766111610 # number of overall miss cycles +system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester1 4752598153 # number of overall miss cycles +system.l1subsys1.cache0.overall_miss_latency::total 9518709763 # number of overall miss cycles +system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester0 42235 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester1 41892 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache0.ReadReq_accesses::total 84127 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester0 22988 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester1 23364 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache0.WriteReq_accesses::total 46352 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache0.demand_accesses::l0subsys2.tester0 65223 # number of demand (read+write) accesses +system.l1subsys1.cache0.demand_accesses::l0subsys2.tester1 65256 # number of demand (read+write) accesses +system.l1subsys1.cache0.demand_accesses::total 130479 # number of demand (read+write) accesses +system.l1subsys1.cache0.overall_accesses::l0subsys2.tester0 65223 # number of overall (read+write) accesses +system.l1subsys1.cache0.overall_accesses::l0subsys2.tester1 65256 # number of overall (read+write) accesses +system.l1subsys1.cache0.overall_accesses::total 130479 # number of overall (read+write) accesses +system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester0 0.762306 # miss rate for ReadReq accesses +system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester1 0.766113 # miss rate for ReadReq accesses +system.l1subsys1.cache0.ReadReq_miss_rate::total 0.764202 # miss rate for ReadReq accesses +system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester0 0.936576 # miss rate for WriteReq accesses +system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester1 0.941149 # miss rate for WriteReq accesses +system.l1subsys1.cache0.WriteReq_miss_rate::total 0.938881 # miss rate for WriteReq accesses +system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester0 0.823728 # miss rate for demand accesses +system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester1 0.828782 # miss rate for demand accesses +system.l1subsys1.cache0.demand_miss_rate::total 0.826256 # miss rate for demand accesses +system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester0 0.823728 # miss rate for overall accesses +system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester1 0.828782 # miss rate for overall accesses +system.l1subsys1.cache0.overall_miss_rate::total 0.826256 # miss rate for overall accesses +system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester0 92115.567462 # average ReadReq miss latency +system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester1 91348.257525 # average ReadReq miss latency +system.l1subsys1.cache0.ReadReq_avg_miss_latency::total 91732.521185 # average ReadReq miss latency +system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester0 83620.938226 # average WriteReq miss latency +system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester1 82808.093865 # average WriteReq miss latency +system.l1subsys1.cache0.WriteReq_avg_miss_latency::total 83210.229463 # average WriteReq miss latency +system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester0 88711.454603 # average overall miss latency +system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester1 87876.008228 # average overall miss latency +system.l1subsys1.cache0.demand_avg_miss_latency::total 88292.348162 # average overall miss latency +system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester0 88711.454603 # average overall miss latency +system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester1 87876.008228 # average overall miss latency +system.l1subsys1.cache0.overall_avg_miss_latency::total 88292.348162 # average overall miss latency +system.l1subsys1.cache0.blocked_cycles::no_mshrs 257225 # number of cycles access was blocked +system.l1subsys1.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l1subsys1.cache0.blocked::no_mshrs 7861 # number of cycles access was blocked +system.l1subsys1.cache0.blocked::no_targets 0 # number of cycles access was blocked +system.l1subsys1.cache0.avg_blocked_cycles::no_mshrs 32.721664 # average number of cycles each access was blocked +system.l1subsys1.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l1subsys1.cache0.writebacks::writebacks 22897 # number of writebacks +system.l1subsys1.cache0.writebacks::total 22897 # number of writebacks +system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester0 1156 # number of ReadReq MSHR hits +system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester1 1188 # number of ReadReq MSHR hits +system.l1subsys1.cache0.ReadReq_mshr_hits::total 2344 # number of ReadReq MSHR hits +system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester0 629 # number of WriteReq MSHR hits +system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester1 630 # number of WriteReq MSHR hits +system.l1subsys1.cache0.WriteReq_mshr_hits::total 1259 # number of WriteReq MSHR hits +system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester0 1785 # number of demand (read+write) MSHR hits +system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester1 1818 # number of demand (read+write) MSHR hits +system.l1subsys1.cache0.demand_mshr_hits::total 3603 # number of demand (read+write) MSHR hits +system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester0 1785 # number of overall MSHR hits +system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester1 1818 # number of overall MSHR hits +system.l1subsys1.cache0.overall_mshr_hits::total 3603 # number of overall MSHR hits +system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester0 31040 # number of ReadReq MSHR misses +system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester1 30906 # number of ReadReq MSHR misses +system.l1subsys1.cache0.ReadReq_mshr_misses::total 61946 # number of ReadReq MSHR misses +system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester0 20901 # number of WriteReq MSHR misses +system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester1 21359 # number of WriteReq MSHR misses +system.l1subsys1.cache0.WriteReq_mshr_misses::total 42260 # number of WriteReq MSHR misses +system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester0 51941 # number of demand (read+write) MSHR misses +system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester1 52265 # number of demand (read+write) MSHR misses +system.l1subsys1.cache0.demand_mshr_misses::total 104206 # number of demand (read+write) MSHR misses +system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester0 51941 # number of overall MSHR misses +system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester1 52265 # number of overall MSHR misses +system.l1subsys1.cache0.overall_mshr_misses::total 104206 # number of overall MSHR misses +system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester0 2909591102 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester1 2874236758 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache0.ReadReq_mshr_miss_latency::total 5783827860 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester0 1771691969 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester1 1791296943 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache0.WriteReq_mshr_miss_latency::total 3562988912 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester0 4681283071 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester1 4665533701 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache0.demand_mshr_miss_latency::total 9346816772 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester0 4681283071 # number of overall MSHR miss cycles +system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester1 4665533701 # number of overall MSHR miss cycles +system.l1subsys1.cache0.overall_mshr_miss_latency::total 9346816772 # number of overall MSHR miss cycles +system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester0 0.734935 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester1 0.737754 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache0.ReadReq_mshr_miss_rate::total 0.736339 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester0 0.909214 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester1 0.914184 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache0.WriteReq_mshr_miss_rate::total 0.911719 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester0 0.796360 # mshr miss rate for demand accesses +system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester1 0.800923 # mshr miss rate for demand accesses +system.l1subsys1.cache0.demand_mshr_miss_rate::total 0.798642 # mshr miss rate for demand accesses +system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester0 0.796360 # mshr miss rate for overall accesses +system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester1 0.800923 # mshr miss rate for overall accesses +system.l1subsys1.cache0.overall_mshr_miss_rate::total 0.798642 # mshr miss rate for overall accesses +system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester0 93736.826740 # average ReadReq mshr miss latency +system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester1 92999.312690 # average ReadReq mshr miss latency +system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::total 93368.867401 # average ReadReq mshr miss latency +system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester0 84765.894885 # average WriteReq mshr miss latency +system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester1 83866.142750 # average WriteReq mshr miss latency +system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::total 84311.143209 # average WriteReq mshr miss latency +system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester0 90126.933848 # average overall mshr miss latency +system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester1 89266.884167 # average overall mshr miss latency +system.l1subsys1.cache0.demand_avg_mshr_miss_latency::total 89695.571963 # average overall mshr miss latency +system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester0 90126.933848 # average overall mshr miss latency +system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester1 89266.884167 # average overall mshr miss latency +system.l1subsys1.cache0.overall_avg_mshr_miss_latency::total 89695.571963 # average overall mshr miss latency +system.l1subsys1.cache1.tags.replacements 63731 # number of replacements +system.l1subsys1.cache1.tags.tagsinuse 503.303418 # Cycle average of tags in use +system.l1subsys1.cache1.tags.total_refs 29004 # Total number of references to valid blocks. +system.l1subsys1.cache1.tags.sampled_refs 64234 # Sample count of references to valid blocks. +system.l1subsys1.cache1.tags.avg_refs 0.451537 # Average number of references to valid blocks. +system.l1subsys1.cache1.tags.warmup_cycle 167138000 # Cycle when the warmup percentage was hit. +system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester0 256.700726 # Average occupied blocks per requestor +system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester1 246.602692 # Average occupied blocks per requestor +system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester0 0.501369 # Average percentage of cache occupancy +system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester1 0.481646 # Average percentage of cache occupancy +system.l1subsys1.cache1.tags.occ_percent::total 0.983014 # Average percentage of cache occupancy +system.l1subsys1.cache1.tags.occ_task_id_blocks::1024 503 # Occupied blocks per task id +system.l1subsys1.cache1.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.l1subsys1.cache1.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id +system.l1subsys1.cache1.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id +system.l1subsys1.cache1.tags.occ_task_id_percent::1024 0.982422 # Percentage of cache occupancy per task id +system.l1subsys1.cache1.tags.tag_accesses 617940 # Number of tag accesses +system.l1subsys1.cache1.tags.data_accesses 617940 # Number of data accesses +system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester0 9182 # number of ReadReq hits +system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester1 9019 # number of ReadReq hits +system.l1subsys1.cache1.ReadReq_hits::total 18201 # number of ReadReq hits +system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester0 1038 # number of WriteReq hits +system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester1 1002 # number of WriteReq hits +system.l1subsys1.cache1.WriteReq_hits::total 2040 # number of WriteReq hits +system.l1subsys1.cache1.demand_hits::l0subsys3.tester0 10220 # number of demand (read+write) hits +system.l1subsys1.cache1.demand_hits::l0subsys3.tester1 10021 # number of demand (read+write) hits +system.l1subsys1.cache1.demand_hits::total 20241 # number of demand (read+write) hits +system.l1subsys1.cache1.overall_hits::l0subsys3.tester0 10220 # number of overall hits +system.l1subsys1.cache1.overall_hits::l0subsys3.tester1 10021 # number of overall hits +system.l1subsys1.cache1.overall_hits::total 20241 # number of overall hits +system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester0 33178 # number of ReadReq misses +system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester1 31976 # number of ReadReq misses +system.l1subsys1.cache1.ReadReq_misses::total 65154 # number of ReadReq misses +system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester0 22617 # number of WriteReq misses +system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester1 21777 # number of WriteReq misses +system.l1subsys1.cache1.WriteReq_misses::total 44394 # number of WriteReq misses +system.l1subsys1.cache1.demand_misses::l0subsys3.tester0 55795 # number of demand (read+write) misses +system.l1subsys1.cache1.demand_misses::l0subsys3.tester1 53753 # number of demand (read+write) misses +system.l1subsys1.cache1.demand_misses::total 109548 # number of demand (read+write) misses +system.l1subsys1.cache1.overall_misses::l0subsys3.tester0 55795 # number of overall misses +system.l1subsys1.cache1.overall_misses::l0subsys3.tester1 53753 # number of overall misses +system.l1subsys1.cache1.overall_misses::total 109548 # number of overall misses +system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester0 3002523024 # number of ReadReq miss cycles +system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester1 2896966528 # number of ReadReq miss cycles +system.l1subsys1.cache1.ReadReq_miss_latency::total 5899489552 # number of ReadReq miss cycles +system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester0 1848932916 # number of WriteReq miss cycles +system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester1 1787708045 # number of WriteReq miss cycles +system.l1subsys1.cache1.WriteReq_miss_latency::total 3636640961 # number of WriteReq miss cycles +system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester0 4851455940 # number of demand (read+write) miss cycles +system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester1 4684674573 # number of demand (read+write) miss cycles +system.l1subsys1.cache1.demand_miss_latency::total 9536130513 # number of demand (read+write) miss cycles +system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester0 4851455940 # number of overall miss cycles +system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester1 4684674573 # number of overall miss cycles +system.l1subsys1.cache1.overall_miss_latency::total 9536130513 # number of overall miss cycles +system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester0 42360 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester1 40995 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache1.ReadReq_accesses::total 83355 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester0 23655 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester1 22779 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache1.WriteReq_accesses::total 46434 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache1.demand_accesses::l0subsys3.tester0 66015 # number of demand (read+write) accesses +system.l1subsys1.cache1.demand_accesses::l0subsys3.tester1 63774 # number of demand (read+write) accesses +system.l1subsys1.cache1.demand_accesses::total 129789 # number of demand (read+write) accesses +system.l1subsys1.cache1.overall_accesses::l0subsys3.tester0 66015 # number of overall (read+write) accesses +system.l1subsys1.cache1.overall_accesses::l0subsys3.tester1 63774 # number of overall (read+write) accesses +system.l1subsys1.cache1.overall_accesses::total 129789 # number of overall (read+write) accesses +system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester0 0.783239 # miss rate for ReadReq accesses +system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester1 0.779998 # miss rate for ReadReq accesses +system.l1subsys1.cache1.ReadReq_miss_rate::total 0.781645 # miss rate for ReadReq accesses +system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester0 0.956119 # miss rate for WriteReq accesses +system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester1 0.956012 # miss rate for WriteReq accesses +system.l1subsys1.cache1.WriteReq_miss_rate::total 0.956067 # miss rate for WriteReq accesses +system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester0 0.845187 # miss rate for demand accesses +system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester1 0.842867 # miss rate for demand accesses +system.l1subsys1.cache1.demand_miss_rate::total 0.844047 # miss rate for demand accesses +system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester0 0.845187 # miss rate for overall accesses +system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester1 0.842867 # miss rate for overall accesses +system.l1subsys1.cache1.overall_miss_rate::total 0.844047 # miss rate for overall accesses +system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester0 90497.408644 # average ReadReq miss latency +system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester1 90598.152614 # average ReadReq miss latency +system.l1subsys1.cache1.ReadReq_avg_miss_latency::total 90546.851337 # average ReadReq miss latency +system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester0 81749.697838 # average WriteReq miss latency +system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester1 82091.566561 # average WriteReq miss latency +system.l1subsys1.cache1.WriteReq_avg_miss_latency::total 81917.397869 # average WriteReq miss latency +system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester0 86951.446187 # average overall miss latency +system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester1 87151.871951 # average overall miss latency +system.l1subsys1.cache1.demand_avg_miss_latency::total 87049.791078 # average overall miss latency +system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester0 86951.446187 # average overall miss latency +system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester1 87151.871951 # average overall miss latency +system.l1subsys1.cache1.overall_avg_miss_latency::total 87049.791078 # average overall miss latency +system.l1subsys1.cache1.blocked_cycles::no_mshrs 234934 # number of cycles access was blocked +system.l1subsys1.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l1subsys1.cache1.blocked::no_mshrs 7262 # number of cycles access was blocked +system.l1subsys1.cache1.blocked::no_targets 0 # number of cycles access was blocked +system.l1subsys1.cache1.avg_blocked_cycles::no_mshrs 32.351143 # average number of cycles each access was blocked +system.l1subsys1.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l1subsys1.cache1.writebacks::writebacks 22786 # number of writebacks +system.l1subsys1.cache1.writebacks::total 22786 # number of writebacks +system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester0 1232 # number of ReadReq MSHR hits +system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester1 1248 # number of ReadReq MSHR hits +system.l1subsys1.cache1.ReadReq_mshr_hits::total 2480 # number of ReadReq MSHR hits +system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester0 756 # number of WriteReq MSHR hits +system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester1 697 # number of WriteReq MSHR hits +system.l1subsys1.cache1.WriteReq_mshr_hits::total 1453 # number of WriteReq MSHR hits +system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester0 1988 # number of demand (read+write) MSHR hits +system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester1 1945 # number of demand (read+write) MSHR hits +system.l1subsys1.cache1.demand_mshr_hits::total 3933 # number of demand (read+write) MSHR hits +system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester0 1988 # number of overall MSHR hits +system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester1 1945 # number of overall MSHR hits +system.l1subsys1.cache1.overall_mshr_hits::total 3933 # number of overall MSHR hits +system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester0 31946 # number of ReadReq MSHR misses +system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester1 30728 # number of ReadReq MSHR misses +system.l1subsys1.cache1.ReadReq_mshr_misses::total 62674 # number of ReadReq MSHR misses +system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester0 21861 # number of WriteReq MSHR misses +system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester1 21080 # number of WriteReq MSHR misses +system.l1subsys1.cache1.WriteReq_mshr_misses::total 42941 # number of WriteReq MSHR misses +system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester0 53807 # number of demand (read+write) MSHR misses +system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester1 51808 # number of demand (read+write) MSHR misses +system.l1subsys1.cache1.demand_mshr_misses::total 105615 # number of demand (read+write) MSHR misses +system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester0 53807 # number of overall MSHR misses +system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester1 51808 # number of overall MSHR misses +system.l1subsys1.cache1.overall_mshr_misses::total 105615 # number of overall MSHR misses +system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester0 2943009333 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester1 2838633361 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache1.ReadReq_mshr_miss_latency::total 5781642694 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester0 1816893974 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester1 1757317060 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache1.WriteReq_mshr_miss_latency::total 3574211034 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester0 4759903307 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester1 4595950421 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache1.demand_mshr_miss_latency::total 9355853728 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester0 4759903307 # number of overall MSHR miss cycles +system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester1 4595950421 # number of overall MSHR miss cycles +system.l1subsys1.cache1.overall_mshr_miss_latency::total 9355853728 # number of overall MSHR miss cycles +system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester0 0.754155 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester1 0.749555 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache1.ReadReq_mshr_miss_rate::total 0.751893 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester0 0.924160 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester1 0.925414 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache1.WriteReq_mshr_miss_rate::total 0.924775 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester0 0.815072 # mshr miss rate for demand accesses +system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester1 0.812369 # mshr miss rate for demand accesses +system.l1subsys1.cache1.demand_mshr_miss_rate::total 0.813744 # mshr miss rate for demand accesses +system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester0 0.815072 # mshr miss rate for overall accesses +system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester1 0.812369 # mshr miss rate for overall accesses +system.l1subsys1.cache1.overall_mshr_miss_rate::total 0.813744 # mshr miss rate for overall accesses +system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester0 92124.501753 # average ReadReq mshr miss latency +system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester1 92379.372592 # average ReadReq mshr miss latency +system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::total 92249.460606 # average ReadReq mshr miss latency +system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester0 83111.201409 # average WriteReq mshr miss latency +system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester1 83364.186907 # average WriteReq mshr miss latency +system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::total 83235.393540 # average WriteReq mshr miss latency +system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester0 88462.529169 # average overall mshr miss latency +system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester1 88711.211029 # average overall mshr miss latency +system.l1subsys1.cache1.demand_avg_mshr_miss_latency::total 88584.516669 # average overall mshr miss latency +system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester0 88462.529169 # average overall mshr miss latency +system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester1 88711.211029 # average overall mshr miss latency +system.l1subsys1.cache1.overall_avg_mshr_miss_latency::total 88584.516669 # average overall mshr miss latency +system.l1subsys1.xbar.snoop_filter.tot_requests 339288 # Total number of requests made to the snoop filter. +system.l1subsys1.xbar.snoop_filter.hit_single_requests 160503 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l1subsys1.xbar.snoop_filter.hit_multi_requests 8795 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys1.xbar.snoop_filter.tot_snoops 114270 # Total number of snoops made to the snoop filter. +system.l1subsys1.xbar.snoop_filter.hit_single_snoops 97861 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l1subsys1.xbar.snoop_filter.hit_multi_snoops 16409 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys1.xbar.trans_dist::ReadResp 151000 # Transaction distribution +system.l1subsys1.xbar.trans_dist::ReadRespWithInvalidate 3767 # Transaction distribution +system.l1subsys1.xbar.trans_dist::WritebackDirty 90510 # Transaction distribution +system.l1subsys1.xbar.trans_dist::CleanEvict 163308 # Transaction distribution +system.l1subsys1.xbar.trans_dist::UpgradeReq 39129 # Transaction distribution +system.l1subsys1.xbar.trans_dist::UpgradeResp 23998 # Transaction distribution +system.l1subsys1.xbar.trans_dist::ReadExReq 98068 # Transaction distribution +system.l1subsys1.xbar.trans_dist::ReadExResp 90220 # Transaction distribution +system.l1subsys1.xbar.trans_dist::ReadSharedReq 164629 # Transaction distribution +system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 294526 # Packet count per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 298625 # Packet count per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_count::total 593151 # Packet count per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 8784576 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 8958272 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_size::total 17742848 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys1.xbar.snoops 288962 # Total snoops (count) +system.l1subsys1.xbar.snoop_fanout::samples 427858 # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::mean 0.369602 # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::stdev 0.556507 # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::0 286130 66.87% 66.87% # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::1 125319 29.29% 96.16% # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::2 16409 3.84% 100.00% # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::max_value 2 # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::total 427858 # Request fanout histogram +system.l1subsys1.xbar.reqLayer0.occupancy 528036324 # Layer occupancy (ticks) +system.l1subsys1.xbar.reqLayer0.utilization 5.3 # Layer utilization (%) +system.l1subsys1.xbar.snoopLayer0.occupancy 174007827 # Layer occupancy (ticks) +system.l1subsys1.xbar.snoopLayer0.utilization 1.7 # Layer utilization (%) +system.l1subsys1.xbar.respLayer0.occupancy 305008955 # Layer occupancy (ticks) +system.l1subsys1.xbar.respLayer0.utilization 3.1 # Layer utilization (%) +system.l1subsys1.xbar.respLayer1.occupancy 309946184 # Layer occupancy (ticks) +system.l1subsys1.xbar.respLayer1.utilization 3.1 # Layer utilization (%) +system.l1subsys2.cache0.tags.replacements 65353 # number of replacements +system.l1subsys2.cache0.tags.tagsinuse 504.458871 # Cycle average of tags in use +system.l1subsys2.cache0.tags.total_refs 33188 # Total number of references to valid blocks. +system.l1subsys2.cache0.tags.sampled_refs 65858 # Sample count of references to valid blocks. +system.l1subsys2.cache0.tags.avg_refs 0.503933 # Average number of references to valid blocks. +system.l1subsys2.cache0.tags.warmup_cycle 466915000 # Cycle when the warmup percentage was hit. +system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester0 261.436019 # Average occupied blocks per requestor +system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester1 243.022852 # Average occupied blocks per requestor +system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester0 0.510617 # Average percentage of cache occupancy +system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester1 0.474654 # Average percentage of cache occupancy +system.l1subsys2.cache0.tags.occ_percent::total 0.985271 # Average percentage of cache occupancy +system.l1subsys2.cache0.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id +system.l1subsys2.cache0.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.l1subsys2.cache0.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id +system.l1subsys2.cache0.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.l1subsys2.cache0.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id +system.l1subsys2.cache0.tags.tag_accesses 629863 # Number of tag accesses +system.l1subsys2.cache0.tags.data_accesses 629863 # Number of data accesses +system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester0 10527 # number of ReadReq hits +system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester1 10271 # number of ReadReq hits +system.l1subsys2.cache0.ReadReq_hits::total 20798 # number of ReadReq hits +system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester0 1671 # number of WriteReq hits +system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester1 1543 # number of WriteReq hits +system.l1subsys2.cache0.WriteReq_hits::total 3214 # number of WriteReq hits +system.l1subsys2.cache0.demand_hits::l0subsys4.tester0 12198 # number of demand (read+write) hits +system.l1subsys2.cache0.demand_hits::l0subsys4.tester1 11814 # number of demand (read+write) hits +system.l1subsys2.cache0.demand_hits::total 24012 # number of demand (read+write) hits +system.l1subsys2.cache0.overall_hits::l0subsys4.tester0 12198 # number of overall hits +system.l1subsys2.cache0.overall_hits::l0subsys4.tester1 11814 # number of overall hits +system.l1subsys2.cache0.overall_hits::total 24012 # number of overall hits +system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester0 32645 # number of ReadReq misses +system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester1 32064 # number of ReadReq misses +system.l1subsys2.cache0.ReadReq_misses::total 64709 # number of ReadReq misses +system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester0 22341 # number of WriteReq misses +system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester1 21878 # number of WriteReq misses +system.l1subsys2.cache0.WriteReq_misses::total 44219 # number of WriteReq misses +system.l1subsys2.cache0.demand_misses::l0subsys4.tester0 54986 # number of demand (read+write) misses +system.l1subsys2.cache0.demand_misses::l0subsys4.tester1 53942 # number of demand (read+write) misses +system.l1subsys2.cache0.demand_misses::total 108928 # number of demand (read+write) misses +system.l1subsys2.cache0.overall_misses::l0subsys4.tester0 54986 # number of overall misses +system.l1subsys2.cache0.overall_misses::l0subsys4.tester1 53942 # number of overall misses +system.l1subsys2.cache0.overall_misses::total 108928 # number of overall misses +system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester0 3071371580 # number of ReadReq miss cycles +system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester1 2941118083 # number of ReadReq miss cycles +system.l1subsys2.cache0.ReadReq_miss_latency::total 6012489663 # number of ReadReq miss cycles +system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester0 1903624532 # number of WriteReq miss cycles +system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester1 1804246122 # number of WriteReq miss cycles +system.l1subsys2.cache0.WriteReq_miss_latency::total 3707870654 # number of WriteReq miss cycles +system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester0 4974996112 # number of demand (read+write) miss cycles +system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester1 4745364205 # number of demand (read+write) miss cycles +system.l1subsys2.cache0.demand_miss_latency::total 9720360317 # number of demand (read+write) miss cycles +system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester0 4974996112 # number of overall miss cycles +system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester1 4745364205 # number of overall miss cycles +system.l1subsys2.cache0.overall_miss_latency::total 9720360317 # number of overall miss cycles +system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester0 43172 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester1 42335 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache0.ReadReq_accesses::total 85507 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester0 24012 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester1 23421 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache0.WriteReq_accesses::total 47433 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache0.demand_accesses::l0subsys4.tester0 67184 # number of demand (read+write) accesses +system.l1subsys2.cache0.demand_accesses::l0subsys4.tester1 65756 # number of demand (read+write) accesses +system.l1subsys2.cache0.demand_accesses::total 132940 # number of demand (read+write) accesses +system.l1subsys2.cache0.overall_accesses::l0subsys4.tester0 67184 # number of overall (read+write) accesses +system.l1subsys2.cache0.overall_accesses::l0subsys4.tester1 65756 # number of overall (read+write) accesses +system.l1subsys2.cache0.overall_accesses::total 132940 # number of overall (read+write) accesses +system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester0 0.756161 # miss rate for ReadReq accesses +system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester1 0.757388 # miss rate for ReadReq accesses +system.l1subsys2.cache0.ReadReq_miss_rate::total 0.756768 # miss rate for ReadReq accesses +system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester0 0.930410 # miss rate for WriteReq accesses +system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester1 0.934119 # miss rate for WriteReq accesses +system.l1subsys2.cache0.WriteReq_miss_rate::total 0.932241 # miss rate for WriteReq accesses +system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester0 0.818439 # miss rate for demand accesses +system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester1 0.820336 # miss rate for demand accesses +system.l1subsys2.cache0.demand_miss_rate::total 0.819377 # miss rate for demand accesses +system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester0 0.818439 # miss rate for overall accesses +system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester1 0.820336 # miss rate for overall accesses +system.l1subsys2.cache0.overall_miss_rate::total 0.819377 # miss rate for overall accesses +system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester0 94083.981620 # average ReadReq miss latency +system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester1 91726.487120 # average ReadReq miss latency +system.l1subsys2.cache0.ReadReq_avg_miss_latency::total 92915.817939 # average ReadReq miss latency +system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester0 85207.668949 # average WriteReq miss latency +system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester1 82468.512753 # average WriteReq miss latency +system.l1subsys2.cache0.WriteReq_avg_miss_latency::total 83852.431172 # average WriteReq miss latency +system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester0 90477.505401 # average overall miss latency +system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester1 87971.602925 # average overall miss latency +system.l1subsys2.cache0.demand_avg_miss_latency::total 89236.562840 # average overall miss latency +system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester0 90477.505401 # average overall miss latency +system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester1 87971.602925 # average overall miss latency +system.l1subsys2.cache0.overall_avg_miss_latency::total 89236.562840 # average overall miss latency +system.l1subsys2.cache0.blocked_cycles::no_mshrs 258782 # number of cycles access was blocked +system.l1subsys2.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l1subsys2.cache0.blocked::no_mshrs 7946 # number of cycles access was blocked +system.l1subsys2.cache0.blocked::no_targets 0 # number of cycles access was blocked +system.l1subsys2.cache0.avg_blocked_cycles::no_mshrs 32.567581 # average number of cycles each access was blocked +system.l1subsys2.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l1subsys2.cache0.writebacks::writebacks 23544 # number of writebacks +system.l1subsys2.cache0.writebacks::total 23544 # number of writebacks +system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester0 1133 # number of ReadReq MSHR hits +system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester1 1138 # number of ReadReq MSHR hits +system.l1subsys2.cache0.ReadReq_mshr_hits::total 2271 # number of ReadReq MSHR hits +system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester0 612 # number of WriteReq MSHR hits +system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester1 631 # number of WriteReq MSHR hits +system.l1subsys2.cache0.WriteReq_mshr_hits::total 1243 # number of WriteReq MSHR hits +system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester0 1745 # number of demand (read+write) MSHR hits +system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester1 1769 # number of demand (read+write) MSHR hits +system.l1subsys2.cache0.demand_mshr_hits::total 3514 # number of demand (read+write) MSHR hits +system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester0 1745 # number of overall MSHR hits +system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester1 1769 # number of overall MSHR hits +system.l1subsys2.cache0.overall_mshr_hits::total 3514 # number of overall MSHR hits +system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester0 31512 # number of ReadReq MSHR misses +system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester1 30926 # number of ReadReq MSHR misses +system.l1subsys2.cache0.ReadReq_mshr_misses::total 62438 # number of ReadReq MSHR misses +system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester0 21729 # number of WriteReq MSHR misses +system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester1 21247 # number of WriteReq MSHR misses +system.l1subsys2.cache0.WriteReq_mshr_misses::total 42976 # number of WriteReq MSHR misses +system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester0 53241 # number of demand (read+write) MSHR misses +system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester1 52173 # number of demand (read+write) MSHR misses +system.l1subsys2.cache0.demand_mshr_misses::total 105414 # number of demand (read+write) MSHR misses +system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester0 53241 # number of overall MSHR misses +system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester1 52173 # number of overall MSHR misses +system.l1subsys2.cache0.overall_mshr_misses::total 105414 # number of overall MSHR misses +system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester0 3015074118 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester1 2885020824 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache0.ReadReq_mshr_miss_latency::total 5900094942 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester0 1873671122 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester1 1773541684 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache0.WriteReq_mshr_miss_latency::total 3647212806 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester0 4888745240 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester1 4658562508 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache0.demand_mshr_miss_latency::total 9547307748 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester0 4888745240 # number of overall MSHR miss cycles +system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester1 4658562508 # number of overall MSHR miss cycles +system.l1subsys2.cache0.overall_mshr_miss_latency::total 9547307748 # number of overall MSHR miss cycles +system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester0 0.729918 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester1 0.730507 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache0.ReadReq_mshr_miss_rate::total 0.730209 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester0 0.904923 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester1 0.907177 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache0.WriteReq_mshr_miss_rate::total 0.906036 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester0 0.792465 # mshr miss rate for demand accesses +system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester1 0.793433 # mshr miss rate for demand accesses +system.l1subsys2.cache0.demand_mshr_miss_rate::total 0.792944 # mshr miss rate for demand accesses +system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester0 0.792465 # mshr miss rate for overall accesses +system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester1 0.793433 # mshr miss rate for overall accesses +system.l1subsys2.cache0.overall_mshr_miss_rate::total 0.792944 # mshr miss rate for overall accesses +system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester0 95680.189071 # average ReadReq mshr miss latency +system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester1 93287.875057 # average ReadReq mshr miss latency +system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::total 94495.258368 # average ReadReq mshr miss latency +system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester0 86229.054351 # average WriteReq mshr miss latency +system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester1 83472.569492 # average WriteReq mshr miss latency +system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::total 84866.269685 # average WriteReq mshr miss latency +system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester0 91822.941718 # average overall mshr miss latency +system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester1 89290.677324 # average overall mshr miss latency +system.l1subsys2.cache0.demand_avg_mshr_miss_latency::total 90569.637316 # average overall mshr miss latency +system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester0 91822.941718 # average overall mshr miss latency +system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester1 89290.677324 # average overall mshr miss latency +system.l1subsys2.cache0.overall_avg_mshr_miss_latency::total 90569.637316 # average overall mshr miss latency +system.l1subsys2.cache1.tags.replacements 67065 # number of replacements +system.l1subsys2.cache1.tags.tagsinuse 502.741649 # Cycle average of tags in use +system.l1subsys2.cache1.tags.total_refs 30001 # Total number of references to valid blocks. +system.l1subsys2.cache1.tags.sampled_refs 67574 # Sample count of references to valid blocks. +system.l1subsys2.cache1.tags.avg_refs 0.443973 # Average number of references to valid blocks. +system.l1subsys2.cache1.tags.warmup_cycle 917087000 # Cycle when the warmup percentage was hit. +system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester0 252.168064 # Average occupied blocks per requestor +system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester1 250.573585 # Average occupied blocks per requestor +system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester0 0.492516 # Average percentage of cache occupancy +system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester1 0.489402 # Average percentage of cache occupancy +system.l1subsys2.cache1.tags.occ_percent::total 0.981917 # Average percentage of cache occupancy +system.l1subsys2.cache1.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.l1subsys2.cache1.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.l1subsys2.cache1.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id +system.l1subsys2.cache1.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.l1subsys2.cache1.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.l1subsys2.cache1.tags.tag_accesses 630788 # Number of tag accesses +system.l1subsys2.cache1.tags.data_accesses 630788 # Number of data accesses +system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester0 9835 # number of ReadReq hits +system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester1 9033 # number of ReadReq hits +system.l1subsys2.cache1.ReadReq_hits::total 18868 # number of ReadReq hits +system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester0 1234 # number of WriteReq hits +system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester1 1110 # number of WriteReq hits +system.l1subsys2.cache1.WriteReq_hits::total 2344 # number of WriteReq hits +system.l1subsys2.cache1.demand_hits::l0subsys5.tester0 11069 # number of demand (read+write) hits +system.l1subsys2.cache1.demand_hits::l0subsys5.tester1 10143 # number of demand (read+write) hits +system.l1subsys2.cache1.demand_hits::total 21212 # number of demand (read+write) hits +system.l1subsys2.cache1.overall_hits::l0subsys5.tester0 11069 # number of overall hits +system.l1subsys2.cache1.overall_hits::l0subsys5.tester1 10143 # number of overall hits +system.l1subsys2.cache1.overall_hits::total 21212 # number of overall hits +system.l1subsys2.cache1.ReadReq_misses::l0subsys5.tester0 33507 # number of ReadReq misses +system.l1subsys2.cache1.ReadReq_misses::l0subsys5.tester1 33136 # number of ReadReq misses +system.l1subsys2.cache1.ReadReq_misses::total 66643 # number of ReadReq misses +system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester0 22543 # number of WriteReq misses +system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester1 22029 # number of WriteReq misses +system.l1subsys2.cache1.WriteReq_misses::total 44572 # number of WriteReq misses +system.l1subsys2.cache1.demand_misses::l0subsys5.tester0 56050 # number of demand (read+write) misses +system.l1subsys2.cache1.demand_misses::l0subsys5.tester1 55165 # number of demand (read+write) misses +system.l1subsys2.cache1.demand_misses::total 111215 # number of demand (read+write) misses +system.l1subsys2.cache1.overall_misses::l0subsys5.tester0 56050 # number of overall misses +system.l1subsys2.cache1.overall_misses::l0subsys5.tester1 55165 # number of overall misses +system.l1subsys2.cache1.overall_misses::total 111215 # number of overall misses +system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester0 3090757790 # number of ReadReq miss cycles +system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester1 3059427771 # number of ReadReq miss cycles +system.l1subsys2.cache1.ReadReq_miss_latency::total 6150185561 # number of ReadReq miss cycles +system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester0 1875123029 # number of WriteReq miss cycles +system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester1 1846091566 # number of WriteReq miss cycles +system.l1subsys2.cache1.WriteReq_miss_latency::total 3721214595 # number of WriteReq miss cycles +system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester0 4965880819 # number of demand (read+write) miss cycles +system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester1 4905519337 # number of demand (read+write) miss cycles +system.l1subsys2.cache1.demand_miss_latency::total 9871400156 # number of demand (read+write) miss cycles +system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester0 4965880819 # number of overall miss cycles +system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester1 4905519337 # number of overall miss cycles +system.l1subsys2.cache1.overall_miss_latency::total 9871400156 # number of overall miss cycles +system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester0 43342 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester1 42169 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache1.ReadReq_accesses::total 85511 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester0 23777 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester1 23139 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache1.WriteReq_accesses::total 46916 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache1.demand_accesses::l0subsys5.tester0 67119 # number of demand (read+write) accesses +system.l1subsys2.cache1.demand_accesses::l0subsys5.tester1 65308 # number of demand (read+write) accesses +system.l1subsys2.cache1.demand_accesses::total 132427 # number of demand (read+write) accesses +system.l1subsys2.cache1.overall_accesses::l0subsys5.tester0 67119 # number of overall (read+write) accesses +system.l1subsys2.cache1.overall_accesses::l0subsys5.tester1 65308 # number of overall (read+write) accesses +system.l1subsys2.cache1.overall_accesses::total 132427 # number of overall (read+write) accesses +system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester0 0.773084 # miss rate for ReadReq accesses +system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester1 0.785791 # miss rate for ReadReq accesses +system.l1subsys2.cache1.ReadReq_miss_rate::total 0.779350 # miss rate for ReadReq accesses +system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester0 0.948101 # miss rate for WriteReq accesses +system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester1 0.952029 # miss rate for WriteReq accesses +system.l1subsys2.cache1.WriteReq_miss_rate::total 0.950038 # miss rate for WriteReq accesses +system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester0 0.835084 # miss rate for demand accesses +system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester1 0.844690 # miss rate for demand accesses +system.l1subsys2.cache1.demand_miss_rate::total 0.839821 # miss rate for demand accesses +system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester0 0.835084 # miss rate for overall accesses +system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester1 0.844690 # miss rate for overall accesses +system.l1subsys2.cache1.overall_miss_rate::total 0.839821 # miss rate for overall accesses +system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester0 92242.152088 # average ReadReq miss latency +system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester1 92329.423316 # average ReadReq miss latency +system.l1subsys2.cache1.ReadReq_avg_miss_latency::total 92285.544783 # average ReadReq miss latency +system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester0 83179.835381 # average WriteReq miss latency +system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester1 83802.785692 # average WriteReq miss latency +system.l1subsys2.cache1.WriteReq_avg_miss_latency::total 83487.718635 # average WriteReq miss latency +system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester0 88597.338430 # average overall miss latency +system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester1 88924.487211 # average overall miss latency +system.l1subsys2.cache1.demand_avg_miss_latency::total 88759.611168 # average overall miss latency +system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester0 88597.338430 # average overall miss latency +system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester1 88924.487211 # average overall miss latency +system.l1subsys2.cache1.overall_avg_miss_latency::total 88759.611168 # average overall miss latency +system.l1subsys2.cache1.blocked_cycles::no_mshrs 248353 # number of cycles access was blocked +system.l1subsys2.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l1subsys2.cache1.blocked::no_mshrs 7598 # number of cycles access was blocked +system.l1subsys2.cache1.blocked::no_targets 0 # number of cycles access was blocked +system.l1subsys2.cache1.avg_blocked_cycles::no_mshrs 32.686628 # average number of cycles each access was blocked +system.l1subsys2.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l1subsys2.cache1.writebacks::writebacks 23828 # number of writebacks +system.l1subsys2.cache1.writebacks::total 23828 # number of writebacks +system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester0 949 # number of ReadReq MSHR hits +system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester1 1026 # number of ReadReq MSHR hits +system.l1subsys2.cache1.ReadReq_mshr_hits::total 1975 # number of ReadReq MSHR hits +system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester0 516 # number of WriteReq MSHR hits +system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester1 532 # number of WriteReq MSHR hits +system.l1subsys2.cache1.WriteReq_mshr_hits::total 1048 # number of WriteReq MSHR hits +system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester0 1465 # number of demand (read+write) MSHR hits +system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester1 1558 # number of demand (read+write) MSHR hits +system.l1subsys2.cache1.demand_mshr_hits::total 3023 # number of demand (read+write) MSHR hits +system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester0 1465 # number of overall MSHR hits +system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester1 1558 # number of overall MSHR hits +system.l1subsys2.cache1.overall_mshr_hits::total 3023 # number of overall MSHR hits +system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester0 32558 # number of ReadReq MSHR misses +system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester1 32110 # number of ReadReq MSHR misses +system.l1subsys2.cache1.ReadReq_mshr_misses::total 64668 # number of ReadReq MSHR misses +system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester0 22027 # number of WriteReq MSHR misses +system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester1 21497 # number of WriteReq MSHR misses +system.l1subsys2.cache1.WriteReq_mshr_misses::total 43524 # number of WriteReq MSHR misses +system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester0 54585 # number of demand (read+write) MSHR misses +system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester1 53607 # number of demand (read+write) MSHR misses +system.l1subsys2.cache1.demand_mshr_misses::total 108192 # number of demand (read+write) MSHR misses +system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester0 54585 # number of overall MSHR misses +system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester1 53607 # number of overall MSHR misses +system.l1subsys2.cache1.overall_mshr_misses::total 108192 # number of overall MSHR misses +system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester0 3037433156 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester1 3005867164 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache1.ReadReq_mshr_miss_latency::total 6043300320 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester0 1845702999 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester1 1817333709 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache1.WriteReq_mshr_miss_latency::total 3663036708 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester0 4883136155 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester1 4823200873 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache1.demand_mshr_miss_latency::total 9706337028 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester0 4883136155 # number of overall MSHR miss cycles +system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester1 4823200873 # number of overall MSHR miss cycles +system.l1subsys2.cache1.overall_mshr_miss_latency::total 9706337028 # number of overall MSHR miss cycles +system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester0 0.751188 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester1 0.761460 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache1.ReadReq_mshr_miss_rate::total 0.756254 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester0 0.926399 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester1 0.929038 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache1.WriteReq_mshr_miss_rate::total 0.927701 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester0 0.813257 # mshr miss rate for demand accesses +system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester1 0.820834 # mshr miss rate for demand accesses +system.l1subsys2.cache1.demand_mshr_miss_rate::total 0.816994 # mshr miss rate for demand accesses +system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester0 0.813257 # mshr miss rate for overall accesses +system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester1 0.820834 # mshr miss rate for overall accesses +system.l1subsys2.cache1.overall_mshr_miss_rate::total 0.816994 # mshr miss rate for overall accesses +system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester0 93292.989619 # average ReadReq mshr miss latency +system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester1 93611.559140 # average ReadReq mshr miss latency +system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::total 93451.170904 # average ReadReq mshr miss latency +system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester0 83792.754302 # average WriteReq mshr miss latency +system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester1 84538.945388 # average WriteReq mshr miss latency +system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::total 84161.306589 # average WriteReq mshr miss latency +system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester0 89459.304846 # average overall mshr miss latency +system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester1 89973.340664 # average overall mshr miss latency +system.l1subsys2.cache1.demand_avg_mshr_miss_latency::total 89713.999445 # average overall mshr miss latency +system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester0 89459.304846 # average overall mshr miss latency +system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester1 89973.340664 # average overall mshr miss latency +system.l1subsys2.cache1.overall_avg_mshr_miss_latency::total 89713.999445 # average overall mshr miss latency +system.l1subsys2.xbar.snoop_filter.tot_requests 347420 # Total number of requests made to the snoop filter. +system.l1subsys2.xbar.snoop_filter.hit_single_requests 164404 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l1subsys2.xbar.snoop_filter.hit_multi_requests 8459 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys2.xbar.snoop_filter.tot_snoops 114014 # Total number of snoops made to the snoop filter. +system.l1subsys2.xbar.snoop_filter.hit_single_snoops 99574 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l1subsys2.xbar.snoop_filter.hit_multi_snoops 14440 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys2.xbar.trans_dist::ReadResp 152712 # Transaction distribution +system.l1subsys2.xbar.trans_dist::ReadRespWithInvalidate 3827 # Transaction distribution +system.l1subsys2.xbar.trans_dist::WritebackDirty 93911 # Transaction distribution +system.l1subsys2.xbar.trans_dist::CleanEvict 169169 # Transaction distribution +system.l1subsys2.xbar.trans_dist::UpgradeReq 39714 # Transaction distribution +system.l1subsys2.xbar.trans_dist::UpgradeResp 24494 # Transaction distribution +system.l1subsys2.xbar.trans_dist::ReadExReq 98494 # Transaction distribution +system.l1subsys2.xbar.trans_dist::ReadExResp 90450 # Transaction distribution +system.l1subsys2.xbar.trans_dist::ReadSharedReq 166204 # Transaction distribution +system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 298570 # Packet count per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 306224 # Packet count per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_count::total 604794 # Packet count per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 8902976 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 9148608 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_size::total 18051584 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys2.xbar.snoops 290665 # Total snoops (count) +system.l1subsys2.xbar.snoop_fanout::samples 435074 # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::mean 0.354188 # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::stdev 0.543249 # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::0 295416 67.90% 67.90% # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::1 125218 28.78% 96.68% # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::2 14440 3.32% 100.00% # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::max_value 2 # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::total 435074 # Request fanout histogram +system.l1subsys2.xbar.reqLayer0.occupancy 541007805 # Layer occupancy (ticks) +system.l1subsys2.xbar.reqLayer0.utilization 5.4 # Layer utilization (%) +system.l1subsys2.xbar.snoopLayer0.occupancy 170855469 # Layer occupancy (ticks) +system.l1subsys2.xbar.snoopLayer0.utilization 1.7 # Layer utilization (%) +system.l1subsys2.xbar.respLayer0.occupancy 307826729 # Layer occupancy (ticks) +system.l1subsys2.xbar.respLayer0.utilization 3.1 # Layer utilization (%) +system.l1subsys2.xbar.respLayer1.occupancy 316356652 # Layer occupancy (ticks) +system.l1subsys2.xbar.respLayer1.utilization 3.2 # Layer utilization (%) +system.l2subsys0.cache0.tags.replacements 33571 # number of replacements +system.l2subsys0.cache0.tags.tagsinuse 498.351113 # Cycle average of tags in use +system.l2subsys0.cache0.tags.total_refs 14579 # Total number of references to valid blocks. +system.l2subsys0.cache0.tags.sampled_refs 34078 # Sample count of references to valid blocks. +system.l2subsys0.cache0.tags.avg_refs 0.427813 # Average number of references to valid blocks. +system.l2subsys0.cache0.tags.warmup_cycle 663555000 # Cycle when the warmup percentage was hit. +system.l2subsys0.cache0.tags.occ_blocks::l2subsys0.tester 498.351113 # Average occupied blocks per requestor +system.l2subsys0.cache0.tags.occ_percent::l2subsys0.tester 0.973342 # Average percentage of cache occupancy +system.l2subsys0.cache0.tags.occ_percent::total 0.973342 # Average percentage of cache occupancy +system.l2subsys0.cache0.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id +system.l2subsys0.cache0.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.l2subsys0.cache0.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id +system.l2subsys0.cache0.tags.age_task_id_blocks_1024::2 218 # Occupied blocks per task id +system.l2subsys0.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id +system.l2subsys0.cache0.tags.tag_accesses 327999 # Number of tag accesses +system.l2subsys0.cache0.tags.data_accesses 327999 # Number of data accesses +system.l2subsys0.cache0.ReadReq_hits::l2subsys0.tester 9421 # number of ReadReq hits +system.l2subsys0.cache0.ReadReq_hits::total 9421 # number of ReadReq hits +system.l2subsys0.cache0.WriteReq_hits::l2subsys0.tester 1165 # number of WriteReq hits +system.l2subsys0.cache0.WriteReq_hits::total 1165 # number of WriteReq hits +system.l2subsys0.cache0.demand_hits::l2subsys0.tester 10586 # number of demand (read+write) hits +system.l2subsys0.cache0.demand_hits::total 10586 # number of demand (read+write) hits +system.l2subsys0.cache0.overall_hits::l2subsys0.tester 10586 # number of overall hits +system.l2subsys0.cache0.overall_hits::total 10586 # number of overall hits +system.l2subsys0.cache0.ReadReq_misses::l2subsys0.tester 34778 # number of ReadReq misses +system.l2subsys0.cache0.ReadReq_misses::total 34778 # number of ReadReq misses +system.l2subsys0.cache0.WriteReq_misses::l2subsys0.tester 23153 # number of WriteReq misses +system.l2subsys0.cache0.WriteReq_misses::total 23153 # number of WriteReq misses +system.l2subsys0.cache0.demand_misses::l2subsys0.tester 57931 # number of demand (read+write) misses +system.l2subsys0.cache0.demand_misses::total 57931 # number of demand (read+write) misses +system.l2subsys0.cache0.overall_misses::l2subsys0.tester 57931 # number of overall misses +system.l2subsys0.cache0.overall_misses::total 57931 # number of overall misses +system.l2subsys0.cache0.ReadReq_miss_latency::l2subsys0.tester 2442508704 # number of ReadReq miss cycles +system.l2subsys0.cache0.ReadReq_miss_latency::total 2442508704 # number of ReadReq miss cycles +system.l2subsys0.cache0.WriteReq_miss_latency::l2subsys0.tester 1393937168 # number of WriteReq miss cycles +system.l2subsys0.cache0.WriteReq_miss_latency::total 1393937168 # number of WriteReq miss cycles +system.l2subsys0.cache0.demand_miss_latency::l2subsys0.tester 3836445872 # number of demand (read+write) miss cycles +system.l2subsys0.cache0.demand_miss_latency::total 3836445872 # number of demand (read+write) miss cycles +system.l2subsys0.cache0.overall_miss_latency::l2subsys0.tester 3836445872 # number of overall miss cycles +system.l2subsys0.cache0.overall_miss_latency::total 3836445872 # number of overall miss cycles +system.l2subsys0.cache0.ReadReq_accesses::l2subsys0.tester 44199 # number of ReadReq accesses(hits+misses) +system.l2subsys0.cache0.ReadReq_accesses::total 44199 # number of ReadReq accesses(hits+misses) +system.l2subsys0.cache0.WriteReq_accesses::l2subsys0.tester 24318 # number of WriteReq accesses(hits+misses) +system.l2subsys0.cache0.WriteReq_accesses::total 24318 # number of WriteReq accesses(hits+misses) +system.l2subsys0.cache0.demand_accesses::l2subsys0.tester 68517 # number of demand (read+write) accesses +system.l2subsys0.cache0.demand_accesses::total 68517 # number of demand (read+write) accesses +system.l2subsys0.cache0.overall_accesses::l2subsys0.tester 68517 # number of overall (read+write) accesses +system.l2subsys0.cache0.overall_accesses::total 68517 # number of overall (read+write) accesses +system.l2subsys0.cache0.ReadReq_miss_rate::l2subsys0.tester 0.786850 # miss rate for ReadReq accesses +system.l2subsys0.cache0.ReadReq_miss_rate::total 0.786850 # miss rate for ReadReq accesses +system.l2subsys0.cache0.WriteReq_miss_rate::l2subsys0.tester 0.952093 # miss rate for WriteReq accesses +system.l2subsys0.cache0.WriteReq_miss_rate::total 0.952093 # miss rate for WriteReq accesses +system.l2subsys0.cache0.demand_miss_rate::l2subsys0.tester 0.845498 # miss rate for demand accesses +system.l2subsys0.cache0.demand_miss_rate::total 0.845498 # miss rate for demand accesses +system.l2subsys0.cache0.overall_miss_rate::l2subsys0.tester 0.845498 # miss rate for overall accesses +system.l2subsys0.cache0.overall_miss_rate::total 0.845498 # miss rate for overall accesses +system.l2subsys0.cache0.ReadReq_avg_miss_latency::l2subsys0.tester 70231.430905 # average ReadReq miss latency +system.l2subsys0.cache0.ReadReq_avg_miss_latency::total 70231.430905 # average ReadReq miss latency +system.l2subsys0.cache0.WriteReq_avg_miss_latency::l2subsys0.tester 60205.466592 # average WriteReq miss latency +system.l2subsys0.cache0.WriteReq_avg_miss_latency::total 60205.466592 # average WriteReq miss latency +system.l2subsys0.cache0.demand_avg_miss_latency::l2subsys0.tester 66224.402686 # average overall miss latency +system.l2subsys0.cache0.demand_avg_miss_latency::total 66224.402686 # average overall miss latency +system.l2subsys0.cache0.overall_avg_miss_latency::l2subsys0.tester 66224.402686 # average overall miss latency +system.l2subsys0.cache0.overall_avg_miss_latency::total 66224.402686 # average overall miss latency +system.l2subsys0.cache0.blocked_cycles::no_mshrs 26017 # number of cycles access was blocked +system.l2subsys0.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2subsys0.cache0.blocked::no_mshrs 506 # number of cycles access was blocked +system.l2subsys0.cache0.blocked::no_targets 0 # number of cycles access was blocked +system.l2subsys0.cache0.avg_blocked_cycles::no_mshrs 51.416996 # average number of cycles each access was blocked +system.l2subsys0.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2subsys0.cache0.writebacks::writebacks 11870 # number of writebacks +system.l2subsys0.cache0.writebacks::total 11870 # number of writebacks +system.l2subsys0.cache0.ReadReq_mshr_hits::l2subsys0.tester 3 # number of ReadReq MSHR hits +system.l2subsys0.cache0.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.l2subsys0.cache0.WriteReq_mshr_hits::l2subsys0.tester 5 # number of WriteReq MSHR hits +system.l2subsys0.cache0.WriteReq_mshr_hits::total 5 # number of WriteReq MSHR hits +system.l2subsys0.cache0.demand_mshr_hits::l2subsys0.tester 8 # number of demand (read+write) MSHR hits +system.l2subsys0.cache0.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.l2subsys0.cache0.overall_mshr_hits::l2subsys0.tester 8 # number of overall MSHR hits +system.l2subsys0.cache0.overall_mshr_hits::total 8 # number of overall MSHR hits +system.l2subsys0.cache0.ReadReq_mshr_misses::l2subsys0.tester 34775 # number of ReadReq MSHR misses +system.l2subsys0.cache0.ReadReq_mshr_misses::total 34775 # number of ReadReq MSHR misses +system.l2subsys0.cache0.WriteReq_mshr_misses::l2subsys0.tester 23148 # number of WriteReq MSHR misses +system.l2subsys0.cache0.WriteReq_mshr_misses::total 23148 # number of WriteReq MSHR misses +system.l2subsys0.cache0.demand_mshr_misses::l2subsys0.tester 57923 # number of demand (read+write) MSHR misses +system.l2subsys0.cache0.demand_mshr_misses::total 57923 # number of demand (read+write) MSHR misses +system.l2subsys0.cache0.overall_mshr_misses::l2subsys0.tester 57923 # number of overall MSHR misses +system.l2subsys0.cache0.overall_mshr_misses::total 57923 # number of overall MSHR misses +system.l2subsys0.cache0.ReadReq_mshr_miss_latency::l2subsys0.tester 2407714740 # number of ReadReq MSHR miss cycles +system.l2subsys0.cache0.ReadReq_mshr_miss_latency::total 2407714740 # number of ReadReq MSHR miss cycles +system.l2subsys0.cache0.WriteReq_mshr_miss_latency::l2subsys0.tester 1370739559 # number of WriteReq MSHR miss cycles +system.l2subsys0.cache0.WriteReq_mshr_miss_latency::total 1370739559 # number of WriteReq MSHR miss cycles +system.l2subsys0.cache0.demand_mshr_miss_latency::l2subsys0.tester 3778454299 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache0.demand_mshr_miss_latency::total 3778454299 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache0.overall_mshr_miss_latency::l2subsys0.tester 3778454299 # number of overall MSHR miss cycles +system.l2subsys0.cache0.overall_mshr_miss_latency::total 3778454299 # number of overall MSHR miss cycles +system.l2subsys0.cache0.ReadReq_mshr_miss_rate::l2subsys0.tester 0.786783 # mshr miss rate for ReadReq accesses +system.l2subsys0.cache0.ReadReq_mshr_miss_rate::total 0.786783 # mshr miss rate for ReadReq accesses +system.l2subsys0.cache0.WriteReq_mshr_miss_rate::l2subsys0.tester 0.951887 # mshr miss rate for WriteReq accesses +system.l2subsys0.cache0.WriteReq_mshr_miss_rate::total 0.951887 # mshr miss rate for WriteReq accesses +system.l2subsys0.cache0.demand_mshr_miss_rate::l2subsys0.tester 0.845381 # mshr miss rate for demand accesses +system.l2subsys0.cache0.demand_mshr_miss_rate::total 0.845381 # mshr miss rate for demand accesses +system.l2subsys0.cache0.overall_mshr_miss_rate::l2subsys0.tester 0.845381 # mshr miss rate for overall accesses +system.l2subsys0.cache0.overall_mshr_miss_rate::total 0.845381 # mshr miss rate for overall accesses +system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::l2subsys0.tester 69236.944357 # average ReadReq mshr miss latency +system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 69236.944357 # average ReadReq mshr miss latency +system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::l2subsys0.tester 59216.327933 # average WriteReq mshr miss latency +system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 59216.327933 # average WriteReq mshr miss latency +system.l2subsys0.cache0.demand_avg_mshr_miss_latency::l2subsys0.tester 65232.365364 # average overall mshr miss latency +system.l2subsys0.cache0.demand_avg_mshr_miss_latency::total 65232.365364 # average overall mshr miss latency +system.l2subsys0.cache0.overall_avg_mshr_miss_latency::l2subsys0.tester 65232.365364 # average overall mshr miss latency +system.l2subsys0.cache0.overall_avg_mshr_miss_latency::total 65232.365364 # average overall mshr miss latency +system.l2subsys0.cache1.tags.replacements 134581 # number of replacements +system.l2subsys0.cache1.tags.tagsinuse 1490.708088 # Cycle average of tags in use +system.l2subsys0.cache1.tags.total_refs 68619 # Total number of references to valid blocks. +system.l2subsys0.cache1.tags.sampled_refs 136082 # Sample count of references to valid blocks. +system.l2subsys0.cache1.tags.avg_refs 0.504247 # Average number of references to valid blocks. +system.l2subsys0.cache1.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2subsys0.cache1.tags.occ_blocks::writebacks 429.815840 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester0 261.351611 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester1 262.808878 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 256.750011 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 279.981748 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_percent::writebacks 0.279828 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester0 0.170151 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester1 0.171100 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.167155 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.182280 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::total 0.970513 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_task_id_blocks::1024 1501 # Occupied blocks per task id +system.l2subsys0.cache1.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.l2subsys0.cache1.tags.age_task_id_blocks_1024::1 848 # Occupied blocks per task id +system.l2subsys0.cache1.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.l2subsys0.cache1.tags.occ_task_id_percent::1024 0.977214 # Percentage of cache occupancy per task id +system.l2subsys0.cache1.tags.tag_accesses 4309680 # Number of tag accesses +system.l2subsys0.cache1.tags.data_accesses 4309680 # Number of data accesses +system.l2subsys0.cache1.WritebackDirty_hits::writebacks 48994 # number of WritebackDirty hits +system.l2subsys0.cache1.WritebackDirty_hits::total 48994 # number of WritebackDirty hits +system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester0 45 # number of ReadExReq hits +system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester1 48 # number of ReadExReq hits +system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester0 49 # number of ReadExReq hits +system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester1 69 # number of ReadExReq hits +system.l2subsys0.cache1.ReadExReq_hits::total 211 # number of ReadExReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester0 593 # number of ReadSharedReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester1 551 # number of ReadSharedReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester0 635 # number of ReadSharedReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester1 706 # number of ReadSharedReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::total 2485 # number of ReadSharedReq hits +system.l2subsys0.cache1.demand_hits::l0subsys0.tester0 638 # number of demand (read+write) hits +system.l2subsys0.cache1.demand_hits::l0subsys0.tester1 599 # number of demand (read+write) hits +system.l2subsys0.cache1.demand_hits::l0subsys1.tester0 684 # number of demand (read+write) hits +system.l2subsys0.cache1.demand_hits::l0subsys1.tester1 775 # number of demand (read+write) hits +system.l2subsys0.cache1.demand_hits::total 2696 # number of demand (read+write) hits +system.l2subsys0.cache1.overall_hits::l0subsys0.tester0 638 # number of overall hits +system.l2subsys0.cache1.overall_hits::l0subsys0.tester1 599 # number of overall hits +system.l2subsys0.cache1.overall_hits::l0subsys1.tester0 684 # number of overall hits +system.l2subsys0.cache1.overall_hits::l0subsys1.tester1 775 # number of overall hits +system.l2subsys0.cache1.overall_hits::total 2696 # number of overall hits +system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester0 3840 # number of UpgradeReq misses +system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester1 3889 # number of UpgradeReq misses +system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester0 3668 # number of UpgradeReq misses +system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester1 3541 # number of UpgradeReq misses +system.l2subsys0.cache1.UpgradeReq_misses::total 14938 # number of UpgradeReq misses +system.l2subsys0.cache1.ReadExReq_misses::l0subsys0.tester0 17049 # number of ReadExReq misses +system.l2subsys0.cache1.ReadExReq_misses::l0subsys0.tester1 17258 # number of ReadExReq misses +system.l2subsys0.cache1.ReadExReq_misses::l0subsys1.tester0 16261 # number of ReadExReq misses +system.l2subsys0.cache1.ReadExReq_misses::l0subsys1.tester1 17121 # number of ReadExReq misses +system.l2subsys0.cache1.ReadExReq_misses::total 67689 # number of ReadExReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys0.tester0 29631 # number of ReadSharedReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys0.tester1 29938 # number of ReadSharedReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys1.tester0 28534 # number of ReadSharedReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys1.tester1 30125 # number of ReadSharedReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::total 118228 # number of ReadSharedReq misses +system.l2subsys0.cache1.demand_misses::l0subsys0.tester0 46680 # number of demand (read+write) misses +system.l2subsys0.cache1.demand_misses::l0subsys0.tester1 47196 # number of demand (read+write) misses +system.l2subsys0.cache1.demand_misses::l0subsys1.tester0 44795 # number of demand (read+write) misses +system.l2subsys0.cache1.demand_misses::l0subsys1.tester1 47246 # number of demand (read+write) misses +system.l2subsys0.cache1.demand_misses::total 185917 # number of demand (read+write) misses +system.l2subsys0.cache1.overall_misses::l0subsys0.tester0 46680 # number of overall misses +system.l2subsys0.cache1.overall_misses::l0subsys0.tester1 47196 # number of overall misses +system.l2subsys0.cache1.overall_misses::l0subsys1.tester0 44795 # number of overall misses +system.l2subsys0.cache1.overall_misses::l0subsys1.tester1 47246 # number of overall misses +system.l2subsys0.cache1.overall_misses::total 185917 # number of overall misses +system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys0.tester0 66953620 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys0.tester1 64831058 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys1.tester0 65919546 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys1.tester1 63268681 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.UpgradeReq_miss_latency::total 260972905 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys0.tester0 1641905219 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys0.tester1 1650456796 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys1.tester0 1582415666 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys1.tester1 1694756023 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::total 6569533704 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys0.tester0 2850992349 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys0.tester1 2862959666 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys1.tester0 2786932114 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys1.tester1 3012471447 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::total 11513355576 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.demand_miss_latency::l0subsys0.tester0 4492897568 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.demand_miss_latency::l0subsys0.tester1 4513416462 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.demand_miss_latency::l0subsys1.tester0 4369347780 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.demand_miss_latency::l0subsys1.tester1 4707227470 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.demand_miss_latency::total 18082889280 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.overall_miss_latency::l0subsys0.tester0 4492897568 # number of overall miss cycles +system.l2subsys0.cache1.overall_miss_latency::l0subsys0.tester1 4513416462 # number of overall miss cycles +system.l2subsys0.cache1.overall_miss_latency::l0subsys1.tester0 4369347780 # number of overall miss cycles +system.l2subsys0.cache1.overall_miss_latency::l0subsys1.tester1 4707227470 # number of overall miss cycles +system.l2subsys0.cache1.overall_miss_latency::total 18082889280 # number of overall miss cycles +system.l2subsys0.cache1.WritebackDirty_accesses::writebacks 48994 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache1.WritebackDirty_accesses::total 48994 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys0.tester0 3840 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys0.tester1 3889 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys1.tester0 3668 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys1.tester1 3541 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::total 14938 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::l0subsys0.tester0 17094 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::l0subsys0.tester1 17306 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::l0subsys1.tester0 16310 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::l0subsys1.tester1 17190 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::total 67900 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys0.tester0 30224 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys0.tester1 30489 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys1.tester0 29169 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys1.tester1 30831 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::total 120713 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.demand_accesses::l0subsys0.tester0 47318 # number of demand (read+write) accesses +system.l2subsys0.cache1.demand_accesses::l0subsys0.tester1 47795 # number of demand (read+write) accesses +system.l2subsys0.cache1.demand_accesses::l0subsys1.tester0 45479 # number of demand (read+write) accesses +system.l2subsys0.cache1.demand_accesses::l0subsys1.tester1 48021 # number of demand (read+write) accesses +system.l2subsys0.cache1.demand_accesses::total 188613 # number of demand (read+write) accesses +system.l2subsys0.cache1.overall_accesses::l0subsys0.tester0 47318 # number of overall (read+write) accesses +system.l2subsys0.cache1.overall_accesses::l0subsys0.tester1 47795 # number of overall (read+write) accesses +system.l2subsys0.cache1.overall_accesses::l0subsys1.tester0 45479 # number of overall (read+write) accesses +system.l2subsys0.cache1.overall_accesses::l0subsys1.tester1 48021 # number of overall (read+write) accesses +system.l2subsys0.cache1.overall_accesses::total 188613 # number of overall (read+write) accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys0.tester0 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys0.tester1 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys1.tester0 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys1.tester1 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys0.tester0 0.997367 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys0.tester1 0.997226 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys1.tester0 0.996996 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys1.tester1 0.995986 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::total 0.996892 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys0.tester0 0.980380 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys0.tester1 0.981928 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys1.tester0 0.978230 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys1.tester1 0.977101 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::total 0.979414 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.demand_miss_rate::l0subsys0.tester0 0.986517 # miss rate for demand accesses +system.l2subsys0.cache1.demand_miss_rate::l0subsys0.tester1 0.987467 # miss rate for demand accesses +system.l2subsys0.cache1.demand_miss_rate::l0subsys1.tester0 0.984960 # miss rate for demand accesses +system.l2subsys0.cache1.demand_miss_rate::l0subsys1.tester1 0.983861 # miss rate for demand accesses +system.l2subsys0.cache1.demand_miss_rate::total 0.985706 # miss rate for demand accesses +system.l2subsys0.cache1.overall_miss_rate::l0subsys0.tester0 0.986517 # miss rate for overall accesses +system.l2subsys0.cache1.overall_miss_rate::l0subsys0.tester1 0.987467 # miss rate for overall accesses +system.l2subsys0.cache1.overall_miss_rate::l0subsys1.tester0 0.984960 # miss rate for overall accesses +system.l2subsys0.cache1.overall_miss_rate::l0subsys1.tester1 0.983861 # miss rate for overall accesses +system.l2subsys0.cache1.overall_miss_rate::total 0.985706 # miss rate for overall accesses +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys0.tester0 17435.838542 # average UpgradeReq miss latency +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys0.tester1 16670.367190 # average UpgradeReq miss latency +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys1.tester0 17971.522901 # average UpgradeReq miss latency +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys1.tester1 17867.461452 # average UpgradeReq miss latency +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::total 17470.404673 # average UpgradeReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys0.tester0 96305.074726 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys0.tester1 95634.302700 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys1.tester0 97313.551811 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys1.tester1 98986.976403 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::total 97054.672162 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys0.tester0 96216.541764 # average ReadSharedReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys0.tester1 95629.623422 # average ReadSharedReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester0 97670.572440 # average ReadSharedReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester1 99999.052183 # average ReadSharedReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::total 97382.646886 # average ReadSharedReq miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys0.tester0 96248.876778 # average overall miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys0.tester1 95631.334477 # average overall miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester0 97540.970644 # average overall miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester1 99632.296279 # average overall miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::total 97263.237251 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys0.tester0 96248.876778 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys0.tester1 95631.334477 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester0 97540.970644 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester1 99632.296279 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::total 97263.237251 # average overall miss latency +system.l2subsys0.cache1.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2subsys0.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2subsys0.cache1.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2subsys0.cache1.blocked::no_targets 0 # number of cycles access was blocked +system.l2subsys0.cache1.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2subsys0.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2subsys0.cache1.writebacks::writebacks 48103 # number of writebacks +system.l2subsys0.cache1.writebacks::total 48103 # number of writebacks +system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys0.tester0 269 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys0.tester1 310 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys1.tester0 278 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys1.tester1 276 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadExReq_mshr_hits::total 1133 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys0.tester0 458 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys0.tester1 558 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys1.tester0 503 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys1.tester1 524 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::total 2043 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache1.demand_mshr_hits::l0subsys0.tester0 727 # number of demand (read+write) MSHR hits +system.l2subsys0.cache1.demand_mshr_hits::l0subsys0.tester1 868 # number of demand (read+write) MSHR hits +system.l2subsys0.cache1.demand_mshr_hits::l0subsys1.tester0 781 # number of demand (read+write) MSHR hits +system.l2subsys0.cache1.demand_mshr_hits::l0subsys1.tester1 800 # number of demand (read+write) MSHR hits +system.l2subsys0.cache1.demand_mshr_hits::total 3176 # number of demand (read+write) MSHR hits +system.l2subsys0.cache1.overall_mshr_hits::l0subsys0.tester0 727 # number of overall MSHR hits +system.l2subsys0.cache1.overall_mshr_hits::l0subsys0.tester1 868 # number of overall MSHR hits +system.l2subsys0.cache1.overall_mshr_hits::l0subsys1.tester0 781 # number of overall MSHR hits +system.l2subsys0.cache1.overall_mshr_hits::l0subsys1.tester1 800 # number of overall MSHR hits +system.l2subsys0.cache1.overall_mshr_hits::total 3176 # number of overall MSHR hits +system.l2subsys0.cache1.CleanEvict_mshr_misses::writebacks 30416 # number of CleanEvict MSHR misses +system.l2subsys0.cache1.CleanEvict_mshr_misses::total 30416 # number of CleanEvict MSHR misses +system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys0.tester0 3840 # number of UpgradeReq MSHR misses +system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys0.tester1 3889 # number of UpgradeReq MSHR misses +system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys1.tester0 3668 # number of UpgradeReq MSHR misses +system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys1.tester1 3541 # number of UpgradeReq MSHR misses +system.l2subsys0.cache1.UpgradeReq_mshr_misses::total 14938 # number of UpgradeReq MSHR misses +system.l2subsys0.cache1.ReadExReq_mshr_misses::l0subsys0.tester0 16780 # number of ReadExReq MSHR misses +system.l2subsys0.cache1.ReadExReq_mshr_misses::l0subsys0.tester1 16948 # number of ReadExReq MSHR misses +system.l2subsys0.cache1.ReadExReq_mshr_misses::l0subsys1.tester0 15983 # number of ReadExReq MSHR misses +system.l2subsys0.cache1.ReadExReq_mshr_misses::l0subsys1.tester1 16845 # number of ReadExReq MSHR misses +system.l2subsys0.cache1.ReadExReq_mshr_misses::total 66556 # number of ReadExReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys0.tester0 29173 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys0.tester1 29380 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys1.tester0 28031 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys1.tester1 29601 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::total 116185 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.demand_mshr_misses::l0subsys0.tester0 45953 # number of demand (read+write) MSHR misses +system.l2subsys0.cache1.demand_mshr_misses::l0subsys0.tester1 46328 # number of demand (read+write) MSHR misses +system.l2subsys0.cache1.demand_mshr_misses::l0subsys1.tester0 44014 # number of demand (read+write) MSHR misses +system.l2subsys0.cache1.demand_mshr_misses::l0subsys1.tester1 46446 # number of demand (read+write) MSHR misses +system.l2subsys0.cache1.demand_mshr_misses::total 182741 # number of demand (read+write) MSHR misses +system.l2subsys0.cache1.overall_mshr_misses::l0subsys0.tester0 45953 # number of overall MSHR misses +system.l2subsys0.cache1.overall_mshr_misses::l0subsys0.tester1 46328 # number of overall MSHR misses +system.l2subsys0.cache1.overall_mshr_misses::l0subsys1.tester0 44014 # number of overall MSHR misses +system.l2subsys0.cache1.overall_mshr_misses::l0subsys1.tester1 46446 # number of overall MSHR misses +system.l2subsys0.cache1.overall_mshr_misses::total 182741 # number of overall MSHR misses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::l0subsys0.tester0 89776482 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::l0subsys0.tester1 89918378 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::l0subsys1.tester0 87815748 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::l0subsys1.tester1 84457073 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::total 351967681 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys0.tester0 1465201403 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys0.tester1 1471590277 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys1.tester0 1414212313 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys1.tester1 1517911340 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::total 5868915333 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys0.tester0 2547272284 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys0.tester1 2554397032 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys1.tester0 2493574245 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys1.tester1 2703309675 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::total 10298553236 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester0 4012473687 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester1 4025987309 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 3907786558 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester1 4221221015 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::total 16167468569 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys0.tester0 4012473687 # number of overall MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys0.tester1 4025987309 # number of overall MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester0 3907786558 # number of overall MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester1 4221221015 # number of overall MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::total 16167468569 # number of overall MSHR miss cycles +system.l2subsys0.cache1.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2subsys0.cache1.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester0 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester1 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester0 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester1 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester0 0.981631 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester1 0.979314 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester0 0.979951 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester1 0.979930 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::total 0.980206 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester0 0.965226 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester1 0.963626 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester0 0.960986 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester1 0.960105 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::total 0.962490 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester0 0.971153 # mshr miss rate for demand accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester1 0.969306 # mshr miss rate for demand accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.967787 # mshr miss rate for demand accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.967202 # mshr miss rate for demand accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::total 0.968867 # mshr miss rate for demand accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester0 0.971153 # mshr miss rate for overall accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester1 0.969306 # mshr miss rate for overall accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.967787 # mshr miss rate for overall accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.967202 # mshr miss rate for overall accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::total 0.968867 # mshr miss rate for overall accesses +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester0 23379.292187 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester1 23121.208023 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester0 23941.043621 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester1 23851.192601 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::total 23561.901259 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester0 87318.319607 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester1 86829.730765 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester0 88482.281987 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester1 90110.498071 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::total 88180.108976 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester0 87316.089672 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester1 86943.397958 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester0 88957.734116 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester1 91324.944259 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::total 88639.266997 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester0 87316.903945 # average overall mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester1 86901.815511 # average overall mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 88785.081065 # average overall mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 90884.489838 # average overall mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::total 88472.037304 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester0 87316.903945 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester1 86901.815511 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 88785.081065 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 90884.489838 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::total 88472.037304 # average overall mshr miss latency +system.l2subsys0.cache2.tags.replacements 126032 # number of replacements +system.l2subsys0.cache2.tags.tagsinuse 1489.728979 # Cycle average of tags in use +system.l2subsys0.cache2.tags.total_refs 65365 # Total number of references to valid blocks. +system.l2subsys0.cache2.tags.sampled_refs 127529 # Sample count of references to valid blocks. +system.l2subsys0.cache2.tags.avg_refs 0.512550 # Average number of references to valid blocks. +system.l2subsys0.cache2.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2subsys0.cache2.tags.occ_blocks::writebacks 427.527348 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester0 271.510882 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester1 262.023740 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester0 270.301105 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester1 258.365905 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_percent::writebacks 0.278338 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester0 0.176765 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester1 0.170588 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester0 0.175977 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester1 0.168207 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::total 0.969876 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_task_id_blocks::1024 1497 # Occupied blocks per task id +system.l2subsys0.cache2.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.l2subsys0.cache2.tags.age_task_id_blocks_1024::1 1033 # Occupied blocks per task id +system.l2subsys0.cache2.tags.age_task_id_blocks_1024::2 358 # Occupied blocks per task id +system.l2subsys0.cache2.tags.occ_task_id_percent::1024 0.974609 # Percentage of cache occupancy per task id +system.l2subsys0.cache2.tags.tag_accesses 4109673 # Number of tag accesses +system.l2subsys0.cache2.tags.data_accesses 4109673 # Number of data accesses +system.l2subsys0.cache2.WritebackDirty_hits::writebacks 45683 # number of WritebackDirty hits +system.l2subsys0.cache2.WritebackDirty_hits::total 45683 # number of WritebackDirty hits +system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester0 37 # number of ReadExReq hits +system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester1 43 # number of ReadExReq hits +system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester0 54 # number of ReadExReq hits +system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester1 63 # number of ReadExReq hits +system.l2subsys0.cache2.ReadExReq_hits::total 197 # number of ReadExReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester0 624 # number of ReadSharedReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester1 645 # number of ReadSharedReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester0 739 # number of ReadSharedReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester1 680 # number of ReadSharedReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::total 2688 # number of ReadSharedReq hits +system.l2subsys0.cache2.demand_hits::l0subsys2.tester0 661 # number of demand (read+write) hits +system.l2subsys0.cache2.demand_hits::l0subsys2.tester1 688 # number of demand (read+write) hits +system.l2subsys0.cache2.demand_hits::l0subsys3.tester0 793 # number of demand (read+write) hits +system.l2subsys0.cache2.demand_hits::l0subsys3.tester1 743 # number of demand (read+write) hits +system.l2subsys0.cache2.demand_hits::total 2885 # number of demand (read+write) hits +system.l2subsys0.cache2.overall_hits::l0subsys2.tester0 661 # number of overall hits +system.l2subsys0.cache2.overall_hits::l0subsys2.tester1 688 # number of overall hits +system.l2subsys0.cache2.overall_hits::l0subsys3.tester0 793 # number of overall hits +system.l2subsys0.cache2.overall_hits::l0subsys3.tester1 743 # number of overall hits +system.l2subsys0.cache2.overall_hits::total 2885 # number of overall hits +system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester0 3779 # number of UpgradeReq misses +system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester1 3809 # number of UpgradeReq misses +system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester0 3732 # number of UpgradeReq misses +system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester1 3718 # number of UpgradeReq misses +system.l2subsys0.cache2.UpgradeReq_misses::total 15038 # number of UpgradeReq misses +system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester0 15930 # number of ReadExReq misses +system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester1 16135 # number of ReadExReq misses +system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester0 16698 # number of ReadExReq misses +system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester1 16012 # number of ReadExReq misses +system.l2subsys0.cache2.ReadExReq_misses::total 64775 # number of ReadExReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester0 28567 # number of ReadSharedReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester1 28110 # number of ReadSharedReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester0 28999 # number of ReadSharedReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester1 28006 # number of ReadSharedReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::total 113682 # number of ReadSharedReq misses +system.l2subsys0.cache2.demand_misses::l0subsys2.tester0 44497 # number of demand (read+write) misses +system.l2subsys0.cache2.demand_misses::l0subsys2.tester1 44245 # number of demand (read+write) misses +system.l2subsys0.cache2.demand_misses::l0subsys3.tester0 45697 # number of demand (read+write) misses +system.l2subsys0.cache2.demand_misses::l0subsys3.tester1 44018 # number of demand (read+write) misses +system.l2subsys0.cache2.demand_misses::total 178457 # number of demand (read+write) misses +system.l2subsys0.cache2.overall_misses::l0subsys2.tester0 44497 # number of overall misses +system.l2subsys0.cache2.overall_misses::l0subsys2.tester1 44245 # number of overall misses +system.l2subsys0.cache2.overall_misses::l0subsys3.tester0 45697 # number of overall misses +system.l2subsys0.cache2.overall_misses::l0subsys3.tester1 44018 # number of overall misses +system.l2subsys0.cache2.overall_misses::total 178457 # number of overall misses +system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys2.tester0 67563408 # number of UpgradeReq miss cycles +system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys2.tester1 65236743 # number of UpgradeReq miss cycles +system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys3.tester0 64646512 # number of UpgradeReq miss cycles +system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys3.tester1 61011114 # number of UpgradeReq miss cycles +system.l2subsys0.cache2.UpgradeReq_miss_latency::total 258457777 # number of UpgradeReq miss cycles +system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys2.tester0 1543612037 # number of ReadExReq miss cycles +system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys2.tester1 1560300540 # number of ReadExReq miss cycles +system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys3.tester0 1583219117 # number of ReadExReq miss cycles +system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys3.tester1 1530352863 # number of ReadExReq miss cycles +system.l2subsys0.cache2.ReadExReq_miss_latency::total 6217484557 # number of ReadExReq miss cycles +system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys2.tester0 2752412028 # number of ReadSharedReq miss cycles +system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys2.tester1 2714107363 # number of ReadSharedReq miss cycles +system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys3.tester0 2778714049 # number of ReadSharedReq miss cycles +system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys3.tester1 2679096326 # number of ReadSharedReq miss cycles +system.l2subsys0.cache2.ReadSharedReq_miss_latency::total 10924329766 # number of ReadSharedReq miss cycles +system.l2subsys0.cache2.demand_miss_latency::l0subsys2.tester0 4296024065 # number of demand (read+write) miss cycles +system.l2subsys0.cache2.demand_miss_latency::l0subsys2.tester1 4274407903 # number of demand (read+write) miss cycles +system.l2subsys0.cache2.demand_miss_latency::l0subsys3.tester0 4361933166 # number of demand (read+write) miss cycles +system.l2subsys0.cache2.demand_miss_latency::l0subsys3.tester1 4209449189 # number of demand (read+write) miss cycles +system.l2subsys0.cache2.demand_miss_latency::total 17141814323 # number of demand (read+write) miss cycles +system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester0 4296024065 # number of overall miss cycles +system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester1 4274407903 # number of overall miss cycles +system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester0 4361933166 # number of overall miss cycles +system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester1 4209449189 # number of overall miss cycles +system.l2subsys0.cache2.overall_miss_latency::total 17141814323 # number of overall miss cycles +system.l2subsys0.cache2.WritebackDirty_accesses::writebacks 45683 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache2.WritebackDirty_accesses::total 45683 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester0 3779 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester1 3809 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester0 3732 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester1 3718 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::total 15038 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester0 15967 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester1 16178 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester0 16752 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester1 16075 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::total 64972 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester0 29191 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester1 28755 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester0 29738 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester1 28686 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::total 116370 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.demand_accesses::l0subsys2.tester0 45158 # number of demand (read+write) accesses +system.l2subsys0.cache2.demand_accesses::l0subsys2.tester1 44933 # number of demand (read+write) accesses +system.l2subsys0.cache2.demand_accesses::l0subsys3.tester0 46490 # number of demand (read+write) accesses +system.l2subsys0.cache2.demand_accesses::l0subsys3.tester1 44761 # number of demand (read+write) accesses +system.l2subsys0.cache2.demand_accesses::total 181342 # number of demand (read+write) accesses +system.l2subsys0.cache2.overall_accesses::l0subsys2.tester0 45158 # number of overall (read+write) accesses +system.l2subsys0.cache2.overall_accesses::l0subsys2.tester1 44933 # number of overall (read+write) accesses +system.l2subsys0.cache2.overall_accesses::l0subsys3.tester0 46490 # number of overall (read+write) accesses +system.l2subsys0.cache2.overall_accesses::l0subsys3.tester1 44761 # number of overall (read+write) accesses +system.l2subsys0.cache2.overall_accesses::total 181342 # number of overall (read+write) accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester0 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester1 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester0 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester1 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester0 0.997683 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester1 0.997342 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester0 0.996777 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester1 0.996081 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::total 0.996968 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester0 0.978624 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester1 0.977569 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester0 0.975150 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester1 0.976295 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::total 0.976901 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester0 0.985363 # miss rate for demand accesses +system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester1 0.984688 # miss rate for demand accesses +system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester0 0.982943 # miss rate for demand accesses +system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester1 0.983401 # miss rate for demand accesses +system.l2subsys0.cache2.demand_miss_rate::total 0.984091 # miss rate for demand accesses +system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester0 0.985363 # miss rate for overall accesses +system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester1 0.984688 # miss rate for overall accesses +system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester0 0.982943 # miss rate for overall accesses +system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester1 0.983401 # miss rate for overall accesses +system.l2subsys0.cache2.overall_miss_rate::total 0.984091 # miss rate for overall accesses +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester0 17878.647261 # average UpgradeReq miss latency +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester1 17127 # average UpgradeReq miss latency +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester0 17322.216506 # average UpgradeReq miss latency +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester1 16409.659494 # average UpgradeReq miss latency +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::total 17186.978122 # average UpgradeReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester0 96899.688449 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester1 96702.853424 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester0 94814.895017 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester1 95575.372408 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::total 95985.867341 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester0 96349.355130 # average ReadSharedReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester1 96553.090110 # average ReadSharedReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester0 95821.030001 # average ReadSharedReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester1 95661.512747 # average ReadSharedReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::total 96095.509984 # average ReadSharedReq miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester0 96546.375374 # average overall miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester1 96607.704893 # average overall miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester0 95453.381316 # average overall miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester1 95630.178313 # average overall miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::total 96055.712710 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester0 96546.375374 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester1 96607.704893 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester0 95453.381316 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester1 95630.178313 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::total 96055.712710 # average overall miss latency +system.l2subsys0.cache2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2subsys0.cache2.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2subsys0.cache2.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2subsys0.cache2.blocked::no_targets 0 # number of cycles access was blocked +system.l2subsys0.cache2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2subsys0.cache2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2subsys0.cache2.writebacks::writebacks 44827 # number of writebacks +system.l2subsys0.cache2.writebacks::total 44827 # number of writebacks +system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester0 237 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester1 298 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester0 265 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester1 283 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadExReq_mshr_hits::total 1083 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester0 402 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester1 551 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester0 515 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester1 507 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::total 1975 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester0 639 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester1 849 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester0 780 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester1 790 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::total 3058 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester0 639 # number of overall MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester1 849 # number of overall MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester0 780 # number of overall MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester1 790 # number of overall MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::total 3058 # number of overall MSHR hits +system.l2subsys0.cache2.CleanEvict_mshr_misses::writebacks 28677 # number of CleanEvict MSHR misses +system.l2subsys0.cache2.CleanEvict_mshr_misses::total 28677 # number of CleanEvict MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester0 3779 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester1 3809 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester0 3732 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester1 3718 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::total 15038 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester0 15693 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester1 15837 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester0 16433 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester1 15729 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::total 63692 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester0 28165 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester1 27559 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester0 28484 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester1 27499 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::total 111707 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester0 43858 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester1 43396 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester0 44917 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester1 43228 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::total 175399 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester0 43858 # number of overall MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester1 43396 # number of overall MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester0 44917 # number of overall MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester1 43228 # number of overall MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::total 175399 # number of overall MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester0 87716721 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester1 87523068 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester0 86908752 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester1 86127988 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::total 348276529 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester0 1378577336 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester1 1392761675 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester0 1410632488 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester1 1363736548 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::total 5545708047 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester0 2460445117 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester1 2424688757 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester0 2480742193 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester1 2390942670 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::total 9756818737 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester0 3839022453 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester1 3817450432 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester0 3891374681 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester1 3754679218 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::total 15302526784 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester0 3839022453 # number of overall MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester1 3817450432 # number of overall MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester0 3891374681 # number of overall MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester1 3754679218 # number of overall MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::total 15302526784 # number of overall MSHR miss cycles +system.l2subsys0.cache2.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2subsys0.cache2.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester0 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester1 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester0 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester1 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester0 0.982840 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester1 0.978922 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester0 0.980957 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester1 0.978476 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::total 0.980299 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester0 0.964852 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester1 0.958407 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester0 0.957832 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester1 0.958621 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::total 0.959930 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester0 0.971212 # mshr miss rate for demand accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester1 0.965794 # mshr miss rate for demand accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester0 0.966165 # mshr miss rate for demand accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester1 0.965751 # mshr miss rate for demand accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::total 0.967228 # mshr miss rate for demand accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester0 0.971212 # mshr miss rate for overall accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester1 0.965794 # mshr miss rate for overall accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester0 0.966165 # mshr miss rate for overall accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester1 0.965751 # mshr miss rate for overall accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::total 0.967228 # mshr miss rate for overall accesses +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester0 23211.622387 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester1 22977.964820 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester0 23287.446945 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester1 23165.139322 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::total 23159.763865 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester0 87846.640923 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester1 87943.529393 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester0 85841.446358 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester1 86702.050226 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::total 87070.716055 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester0 87358.250204 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester1 87981.739432 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester0 87092.479743 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester1 86946.531510 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::total 87342.948401 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester0 87533.003169 # average overall mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester1 87967.795004 # average overall mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester0 86634.785961 # average overall mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester1 86857.574211 # average overall mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::total 87244.093661 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester0 87533.003169 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester1 87967.795004 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester0 86634.785961 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester1 86857.574211 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::total 87244.093661 # average overall mshr miss latency +system.l2subsys0.cache3.tags.replacements 130662 # number of replacements +system.l2subsys0.cache3.tags.tagsinuse 1489.946036 # Cycle average of tags in use +system.l2subsys0.cache3.tags.total_refs 67604 # Total number of references to valid blocks. +system.l2subsys0.cache3.tags.sampled_refs 132161 # Sample count of references to valid blocks. +system.l2subsys0.cache3.tags.avg_refs 0.511528 # Average number of references to valid blocks. +system.l2subsys0.cache3.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2subsys0.cache3.tags.occ_blocks::writebacks 425.979862 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester0 268.595502 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester1 251.873835 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester0 272.521788 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester1 270.975049 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_percent::writebacks 0.277331 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::l0subsys4.tester0 0.174867 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::l0subsys4.tester1 0.163980 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::l0subsys5.tester0 0.177423 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::l0subsys5.tester1 0.176416 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::total 0.970017 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_task_id_blocks::1024 1499 # Occupied blocks per task id +system.l2subsys0.cache3.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.l2subsys0.cache3.tags.age_task_id_blocks_1024::1 983 # Occupied blocks per task id +system.l2subsys0.cache3.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id +system.l2subsys0.cache3.tags.occ_task_id_percent::1024 0.975911 # Percentage of cache occupancy per task id +system.l2subsys0.cache3.tags.tag_accesses 4225473 # Number of tag accesses +system.l2subsys0.cache3.tags.data_accesses 4225473 # Number of data accesses +system.l2subsys0.cache3.WritebackDirty_hits::writebacks 47372 # number of WritebackDirty hits +system.l2subsys0.cache3.WritebackDirty_hits::total 47372 # number of WritebackDirty hits +system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester0 45 # number of ReadExReq hits +system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester1 48 # number of ReadExReq hits +system.l2subsys0.cache3.ReadExReq_hits::l0subsys5.tester0 51 # number of ReadExReq hits +system.l2subsys0.cache3.ReadExReq_hits::l0subsys5.tester1 43 # number of ReadExReq hits +system.l2subsys0.cache3.ReadExReq_hits::total 187 # number of ReadExReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys4.tester0 655 # number of ReadSharedReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys4.tester1 678 # number of ReadSharedReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys5.tester0 569 # number of ReadSharedReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys5.tester1 592 # number of ReadSharedReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::total 2494 # number of ReadSharedReq hits +system.l2subsys0.cache3.demand_hits::l0subsys4.tester0 700 # number of demand (read+write) hits +system.l2subsys0.cache3.demand_hits::l0subsys4.tester1 726 # number of demand (read+write) hits +system.l2subsys0.cache3.demand_hits::l0subsys5.tester0 620 # number of demand (read+write) hits +system.l2subsys0.cache3.demand_hits::l0subsys5.tester1 635 # number of demand (read+write) hits +system.l2subsys0.cache3.demand_hits::total 2681 # number of demand (read+write) hits +system.l2subsys0.cache3.overall_hits::l0subsys4.tester0 700 # number of overall hits +system.l2subsys0.cache3.overall_hits::l0subsys4.tester1 726 # number of overall hits +system.l2subsys0.cache3.overall_hits::l0subsys5.tester0 620 # number of overall hits +system.l2subsys0.cache3.overall_hits::l0subsys5.tester1 635 # number of overall hits +system.l2subsys0.cache3.overall_hits::total 2681 # number of overall hits +system.l2subsys0.cache3.UpgradeReq_misses::l0subsys4.tester0 3869 # number of UpgradeReq misses +system.l2subsys0.cache3.UpgradeReq_misses::l0subsys4.tester1 3840 # number of UpgradeReq misses +system.l2subsys0.cache3.UpgradeReq_misses::l0subsys5.tester0 3845 # number of UpgradeReq misses +system.l2subsys0.cache3.UpgradeReq_misses::l0subsys5.tester1 3621 # number of UpgradeReq misses +system.l2subsys0.cache3.UpgradeReq_misses::total 15175 # number of UpgradeReq misses +system.l2subsys0.cache3.ReadExReq_misses::l0subsys4.tester0 16646 # number of ReadExReq misses +system.l2subsys0.cache3.ReadExReq_misses::l0subsys4.tester1 16118 # number of ReadExReq misses +system.l2subsys0.cache3.ReadExReq_misses::l0subsys5.tester0 16903 # number of ReadExReq misses +system.l2subsys0.cache3.ReadExReq_misses::l0subsys5.tester1 16518 # number of ReadExReq misses +system.l2subsys0.cache3.ReadExReq_misses::total 66185 # number of ReadExReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys4.tester0 28947 # number of ReadSharedReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys4.tester1 28300 # number of ReadSharedReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys5.tester0 30131 # number of ReadSharedReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys5.tester1 29474 # number of ReadSharedReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::total 116852 # number of ReadSharedReq misses +system.l2subsys0.cache3.demand_misses::l0subsys4.tester0 45593 # number of demand (read+write) misses +system.l2subsys0.cache3.demand_misses::l0subsys4.tester1 44418 # number of demand (read+write) misses +system.l2subsys0.cache3.demand_misses::l0subsys5.tester0 47034 # number of demand (read+write) misses +system.l2subsys0.cache3.demand_misses::l0subsys5.tester1 45992 # number of demand (read+write) misses +system.l2subsys0.cache3.demand_misses::total 183037 # number of demand (read+write) misses +system.l2subsys0.cache3.overall_misses::l0subsys4.tester0 45593 # number of overall misses +system.l2subsys0.cache3.overall_misses::l0subsys4.tester1 44418 # number of overall misses +system.l2subsys0.cache3.overall_misses::l0subsys5.tester0 47034 # number of overall misses +system.l2subsys0.cache3.overall_misses::l0subsys5.tester1 45992 # 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number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys4.tester1 28978 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys5.tester0 30700 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys5.tester1 30066 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.ReadSharedReq_accesses::total 119346 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.demand_accesses::l0subsys4.tester0 46293 # number of demand (read+write) accesses +system.l2subsys0.cache3.demand_accesses::l0subsys4.tester1 45144 # number of demand (read+write) accesses +system.l2subsys0.cache3.demand_accesses::l0subsys5.tester0 47654 # number of demand (read+write) accesses +system.l2subsys0.cache3.demand_accesses::l0subsys5.tester1 46627 # number of demand (read+write) accesses +system.l2subsys0.cache3.demand_accesses::total 185718 # number of demand (read+write) accesses +system.l2subsys0.cache3.overall_accesses::l0subsys4.tester0 46293 # number of overall (read+write) accesses +system.l2subsys0.cache3.overall_accesses::l0subsys4.tester1 45144 # number of overall (read+write) accesses +system.l2subsys0.cache3.overall_accesses::l0subsys5.tester0 47654 # number of overall (read+write) accesses +system.l2subsys0.cache3.overall_accesses::l0subsys5.tester1 46627 # number of overall (read+write) accesses +system.l2subsys0.cache3.overall_accesses::total 185718 # number of overall (read+write) accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys4.tester0 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys4.tester1 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys5.tester0 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys5.tester1 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys4.tester0 0.997304 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys4.tester1 0.997031 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys5.tester0 0.996992 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys5.tester1 0.997404 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::total 0.997183 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys4.tester0 0.977873 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys4.tester1 0.976603 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys5.tester0 0.981466 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys5.tester1 0.980310 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::total 0.979103 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.demand_miss_rate::l0subsys4.tester0 0.984879 # miss rate for demand accesses +system.l2subsys0.cache3.demand_miss_rate::l0subsys4.tester1 0.983918 # miss rate for demand accesses +system.l2subsys0.cache3.demand_miss_rate::l0subsys5.tester0 0.986990 # miss rate for demand accesses +system.l2subsys0.cache3.demand_miss_rate::l0subsys5.tester1 0.986381 # miss rate for demand accesses +system.l2subsys0.cache3.demand_miss_rate::total 0.985564 # miss rate for demand accesses +system.l2subsys0.cache3.overall_miss_rate::l0subsys4.tester0 0.984879 # miss rate for overall accesses +system.l2subsys0.cache3.overall_miss_rate::l0subsys4.tester1 0.983918 # miss rate for overall accesses +system.l2subsys0.cache3.overall_miss_rate::l0subsys5.tester0 0.986990 # miss rate for overall accesses +system.l2subsys0.cache3.overall_miss_rate::l0subsys5.tester1 0.986381 # miss rate for overall accesses +system.l2subsys0.cache3.overall_miss_rate::total 0.985564 # miss rate for overall accesses +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys4.tester0 17474.131300 # average UpgradeReq miss latency +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys4.tester1 17930.472135 # average UpgradeReq miss latency +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys5.tester0 17288.811964 # average UpgradeReq miss latency +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys5.tester1 16633.862745 # average UpgradeReq miss latency +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::total 17342.149984 # average UpgradeReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys4.tester0 98442.248468 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys4.tester1 95593.674587 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys5.tester0 95440.544696 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys5.tester1 96478.450842 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::total 96491.819793 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys4.tester0 98633.134176 # average ReadSharedReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys4.tester1 96373.657385 # average ReadSharedReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys5.tester0 95472.860044 # average ReadSharedReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys5.tester1 96448.926138 # average ReadSharedReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::total 96720.092373 # average ReadSharedReq miss latency +system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys4.tester0 98563.441822 # average overall miss latency +system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys4.tester1 96090.624319 # average overall miss latency +system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys5.tester0 95461.246609 # average overall miss latency +system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys5.tester1 96459.529918 # average overall miss latency +system.l2subsys0.cache3.demand_avg_miss_latency::total 96637.550479 # average overall miss latency +system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys4.tester0 98563.441822 # average overall miss latency +system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys4.tester1 96090.624319 # average overall miss latency +system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys5.tester0 95461.246609 # average overall miss latency +system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys5.tester1 96459.529918 # average overall miss latency +system.l2subsys0.cache3.overall_avg_miss_latency::total 96637.550479 # average overall miss latency +system.l2subsys0.cache3.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2subsys0.cache3.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2subsys0.cache3.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2subsys0.cache3.blocked::no_targets 0 # number of cycles access was blocked +system.l2subsys0.cache3.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2subsys0.cache3.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2subsys0.cache3.writebacks::writebacks 46539 # number of writebacks +system.l2subsys0.cache3.writebacks::total 46539 # number of writebacks +system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys4.tester0 245 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys4.tester1 276 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys5.tester0 228 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys5.tester1 276 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadExReq_mshr_hits::total 1025 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys4.tester0 453 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys4.tester1 535 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys5.tester0 383 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys5.tester1 507 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::total 1878 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache3.demand_mshr_hits::l0subsys4.tester0 698 # number of demand (read+write) MSHR hits +system.l2subsys0.cache3.demand_mshr_hits::l0subsys4.tester1 811 # number of demand (read+write) MSHR hits +system.l2subsys0.cache3.demand_mshr_hits::l0subsys5.tester0 611 # number of demand (read+write) MSHR hits +system.l2subsys0.cache3.demand_mshr_hits::l0subsys5.tester1 783 # number of demand (read+write) MSHR hits +system.l2subsys0.cache3.demand_mshr_hits::total 2903 # number of demand (read+write) MSHR hits +system.l2subsys0.cache3.overall_mshr_hits::l0subsys4.tester0 698 # number of overall MSHR hits +system.l2subsys0.cache3.overall_mshr_hits::l0subsys4.tester1 811 # number of overall MSHR hits +system.l2subsys0.cache3.overall_mshr_hits::l0subsys5.tester0 611 # number of overall MSHR hits +system.l2subsys0.cache3.overall_mshr_hits::l0subsys5.tester1 783 # number of overall MSHR hits +system.l2subsys0.cache3.overall_mshr_hits::total 2903 # number of overall MSHR hits +system.l2subsys0.cache3.CleanEvict_mshr_misses::writebacks 29209 # number of CleanEvict MSHR misses +system.l2subsys0.cache3.CleanEvict_mshr_misses::total 29209 # number of CleanEvict MSHR misses +system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys4.tester0 3869 # number of UpgradeReq MSHR misses +system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys4.tester1 3840 # number of UpgradeReq MSHR misses +system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys5.tester0 3845 # number of UpgradeReq MSHR misses +system.l2subsys0.cache3.UpgradeReq_mshr_misses::l0subsys5.tester1 3621 # number of UpgradeReq MSHR misses +system.l2subsys0.cache3.UpgradeReq_mshr_misses::total 15175 # number of UpgradeReq MSHR misses +system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys4.tester0 16401 # number of ReadExReq MSHR misses +system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys4.tester1 15842 # number of ReadExReq MSHR misses +system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys5.tester0 16675 # number of ReadExReq MSHR misses +system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys5.tester1 16242 # number of ReadExReq MSHR misses +system.l2subsys0.cache3.ReadExReq_mshr_misses::total 65160 # number of ReadExReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys4.tester0 28494 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys4.tester1 27765 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys5.tester0 29748 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys5.tester1 28967 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::total 114974 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::l0subsys4.tester0 44895 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::l0subsys4.tester1 43607 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::l0subsys5.tester0 46423 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::l0subsys5.tester1 45209 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::total 180134 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::l0subsys4.tester0 44895 # number of overall MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::l0subsys4.tester1 43607 # number of overall MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::l0subsys5.tester0 46423 # number of overall MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::l0subsys5.tester1 45209 # number of overall MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::total 180134 # number of overall MSHR misses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys4.tester0 91886600 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys4.tester1 90820502 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys5.tester0 89848757 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys5.tester1 84122080 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::total 356677939 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys4.tester0 1466459451 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys4.tester1 1373906273 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys5.tester0 1438641443 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys5.tester1 1422719440 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::total 5701726607 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys4.tester0 2558187069 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys4.tester1 2436289189 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys5.tester0 2569282728 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys5.tester1 2539630448 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::total 10103389434 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys4.tester0 4024646520 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys4.tester1 3810195462 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys5.tester0 4007924171 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys5.tester1 3962349888 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::total 15805116041 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys4.tester0 4024646520 # number of overall MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys4.tester1 3810195462 # number of overall MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys5.tester0 4007924171 # number of overall MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys5.tester1 3962349888 # number of overall MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::total 15805116041 # number of overall MSHR miss cycles +system.l2subsys0.cache3.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2subsys0.cache3.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester0 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester1 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester0 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester1 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester0 0.982625 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester1 0.979958 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester0 0.983544 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester1 0.980738 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::total 0.981739 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester0 0.962570 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester1 0.958141 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester0 0.968990 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester1 0.963447 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::total 0.963367 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester0 0.969801 # mshr miss rate for demand accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester1 0.965953 # mshr miss rate for demand accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester0 0.974168 # mshr miss rate for demand accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester1 0.969588 # mshr miss rate for demand accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::total 0.969933 # mshr miss rate for demand accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester0 0.969801 # mshr miss rate for overall accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester1 0.965953 # mshr miss rate for overall accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester0 0.974168 # mshr miss rate for overall accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester1 0.969588 # mshr miss rate for overall accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::total 0.969933 # mshr miss rate for overall accesses +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester0 23749.444301 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester1 23651.172396 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester0 23367.687126 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester1 23231.726043 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::total 23504.312290 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester0 89412.807207 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester1 86725.556937 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester0 86275.348906 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester1 87595.089275 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::total 87503.477701 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester0 89779.850811 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester1 87746.774320 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester0 86368.250908 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester1 87673.229813 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::total 87875.427784 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester0 89645.762780 # average overall mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester1 87375.775953 # average overall mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester0 86334.880792 # average overall mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester1 87645.156672 # average overall mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::total 87740.882016 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester0 89645.762780 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester1 87375.775953 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester0 86334.880792 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester1 87645.156672 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::total 87740.882016 # average overall mshr miss latency +system.l2subsys0.tester.numPackets 68517 # Number of packets generated +system.l2subsys0.tester.numRetries 121 # Number of retries +system.l2subsys0.tester.retryTicks 5829034 # Time spent waiting due to back-pressure (ticks) +system.l2subsys0.xbar.snoop_filter.tot_requests 1076493 # Total number of requests made to the snoop filter. +system.l2subsys0.xbar.snoop_filter.hit_single_requests 529775 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2subsys0.xbar.snoop_filter.hit_multi_requests 120892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.l2subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l2subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2subsys0.xbar.trans_dist::ReadResp 374921 # Transaction distribution +system.l2subsys0.xbar.trans_dist::ReadRespWithInvalidate 1348 # Transaction distribution +system.l2subsys0.xbar.trans_dist::WritebackDirty 151339 # Transaction distribution +system.l2subsys0.xbar.trans_dist::CleanEvict 272890 # Transaction distribution +system.l2subsys0.xbar.trans_dist::UpgradeReq 55357 # Transaction distribution +system.l2subsys0.xbar.trans_dist::UpgradeResp 28680 # Transaction distribution +system.l2subsys0.xbar.trans_dist::ReadExReq 220635 # Transaction distribution +system.l2subsys0.xbar.trans_dist::ReadExResp 216743 # Transaction distribution +system.l2subsys0.xbar.trans_dist::ReadSharedReq 376272 # Transaction distribution +system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache1.mem_side::system.physmem.port 471947 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache2.mem_side::system.physmem.port 447710 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache3.mem_side::system.physmem.port 461540 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache0.mem_side::system.physmem.port 125522 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_count::total 1506719 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache1.mem_side::system.physmem.port 11798528 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache2.mem_side::system.physmem.port 11044864 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache3.mem_side::system.physmem.port 11439552 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache0.mem_side::system.physmem.port 2937216 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size::total 37220160 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.snoops 200506 # Total snoops (count) +system.l2subsys0.xbar.snoop_fanout::samples 652264 # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::mean 0.480016 # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::stdev 0.745912 # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::0 429345 65.82% 65.82% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::1 142615 21.86% 87.69% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::2 70430 10.80% 98.49% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::3 9874 1.51% 100.00% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::max_value 3 # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::total 652264 # Request fanout histogram +system.l2subsys0.xbar.reqLayer0.occupancy 1612904465 # Layer occupancy (ticks) +system.l2subsys0.xbar.reqLayer0.utilization 16.1 # Layer utilization (%) +system.l2subsys0.xbar.respLayer0.occupancy 655215336 # Layer occupancy (ticks) +system.l2subsys0.xbar.respLayer0.utilization 6.6 # Layer utilization (%) +system.l2subsys0.xbar.respLayer1.occupancy 628908219 # Layer occupancy (ticks) +system.l2subsys0.xbar.respLayer1.utilization 6.3 # Layer utilization (%) +system.l2subsys0.xbar.respLayer2.occupancy 645551493 # Layer occupancy (ticks) +system.l2subsys0.xbar.respLayer2.utilization 6.5 # Layer utilization (%) +system.l2subsys0.xbar.respLayer3.occupancy 182844725 # Layer occupancy (ticks) +system.l2subsys0.xbar.respLayer3.utilization 1.8 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/51.memcheck/test.py b/tests/quick/se/51.memcheck/test.py new file mode 100644 index 000000000..0f7835f6f --- /dev/null +++ b/tests/quick/se/51.memcheck/test.py @@ -0,0 +1,38 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Hansson + +maxtick = 10000000000 |