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author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-15 23:22:04 -0400 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-15 23:22:04 -0400 |
commit | d5bb145590a16165c362c6157801b7fbab4a0486 (patch) | |
tree | daae998c411bace2532ca75f452c768cf306142c /tests | |
parent | 658eeee50715d9fd334ae3fd3e0e21b6db6de0c4 (diff) | |
parent | 884807a68ad7e4f390660b3becfe4ee094334e95 (diff) | |
download | gem5-d5bb145590a16165c362c6157801b7fbab4a0486.tar.xz |
Merge from head.
--HG--
extra : convert_revision : c5d045208e521f0bc9e47484a380917e27066798
Diffstat (limited to 'tests')
-rw-r--r-- | tests/configs/memtest.py | 1 | ||||
-rw-r--r-- | tests/configs/o3-timing-mp.py | 1 | ||||
-rw-r--r-- | tests/configs/simple-atomic-mp.py | 1 | ||||
-rw-r--r-- | tests/configs/simple-timing-mp.py | 1 | ||||
-rw-r--r-- | tests/configs/tsunami-simple-atomic-dual.py | 1 | ||||
-rw-r--r-- | tests/configs/tsunami-simple-atomic.py | 1 | ||||
-rw-r--r-- | tests/configs/tsunami-simple-timing-dual.py | 1 | ||||
-rw-r--r-- | tests/configs/tsunami-simple-timing.py | 1 |
8 files changed, 0 insertions, 8 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index 6fe244acf..93ea4cc0e 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -38,7 +38,6 @@ class L1(BaseCache): block_size = 64 mshrs = 12 tgts_per_mshr = 8 - protocol = CoherenceProtocol(protocol='moesi') # ---------------------- # Base L2 Cache diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 1ac9bd2e4..fc6a72a82 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -39,7 +39,6 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 - protocol = CoherenceProtocol(protocol='moesi') # ---------------------- # Base L2 Cache diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index de0793d1c..bc0ced250 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -38,7 +38,6 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 - protocol = CoherenceProtocol(protocol='moesi') # ---------------------- # Base L2 Cache diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index 1fd0e8c3c..0b400e6b7 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -38,7 +38,6 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 - protocol = CoherenceProtocol(protocol='moesi') # ---------------------- # Base L2 Cache diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 131095055..de8fe2474 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -40,7 +40,6 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 - protocol = CoherenceProtocol(protocol='moesi') # ---------------------- # Base L2 Cache diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 595b1aeda..2ba50273a 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -40,7 +40,6 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 - protocol = CoherenceProtocol(protocol='moesi') # ---------------------- # Base L2 Cache diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 47fba30ff..3b1a4f5cf 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -40,7 +40,6 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 - protocol = CoherenceProtocol(protocol='moesi') # ---------------------- # Base L2 Cache diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 999bde087..3f18c6848 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -41,7 +41,6 @@ class L1(BaseCache): block_size = 64 mshrs = 4 tgts_per_mshr = 8 - protocol = CoherenceProtocol(protocol='moesi') # ---------------------- # Base L2 Cache |