config: Use SimpleDRAM in full-system, and with o3 and inorder

This patch favours using SimpleDRAM with the default timing instead of
SimpleMemory for all regressions that involve the o3 or inorder CPU,
or are full system (in other words, where the actual performance of
the memory is important for the overall performance).

Moving forward, the solution for FSConfig and the users of fs.py and
se.py is probably something similar to what we use to choose the CPU
type. I envision a few pre-set configurations SimpleLPDDR2,
SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on
this part is welcome.

This patch changes plenty stats and adds all the DRAM controller
related stats. A follow-on patch updates the relevant statistics. The
total run-time for the entire regression goes up with ~5% with this
patch due to the added complexity of the SimpleDRAM model. This is a
concious trade-off to ensure that the model is properly tested.

4 files changed, 4 insertions, 4 deletions

diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 5f2156ff9..edec312d0 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -50,7 +50,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
-                physmem = SimpleMemory(),
+                physmem = SimpleDRAM(),
                 membus = CoherentBus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index a54c9b7ca..4ff3f0187 100644
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -63,7 +63,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
-                physmem = SimpleMemory(),
+                physmem = SimpleDRAM(),
                 membus = CoherentBus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index b02b43d03..2b611fb9d 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -35,7 +35,7 @@ nb_cores = 4
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
+system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index f87e0e355..b9bc40bc2 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -52,7 +52,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
 cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
-                physmem = SimpleMemory(),
+                physmem = SimpleDRAM(),
                 membus = CoherentBus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master