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authorRon Dreslinski <rdreslin@umich.edu>2006-10-19 21:26:46 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-19 21:26:46 -0400
commit780aa0a0ebb765781a31d0fb58257b1efb1f324a (patch)
treeae6dbaca9ea90d3fa7ed3b16c633229a7f995dd0 /tests
parentcc1feb9f6ddf9d0a58365ffa9f7ae948bf19901d (diff)
downloadgem5-780aa0a0ebb765781a31d0fb58257b1efb1f324a.tar.xz
Fix corner case on assertion.
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere. Still a functional access bug someplace I need to track down in timing mode. src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Fix corner case on assertion tests/configs/memtest.py: Updated memtester with uncacheable addresses and functional accesses --HG-- extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/memtest.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 116e71af6..2b990418c 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -53,7 +53,7 @@ class L2(BaseCache):
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
-cpus = [ MemTest(max_loads=1e12, percent_uncacheable=0, progress_interval=1000) for i in xrange(nb_cores) ]
+cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, funcmem = PhysicalMemory(),
@@ -90,6 +90,6 @@ system.physmem.port = system.membus.port
root = Root( system = system )
root.system.mem_mode = 'timing'
-#root.trace.flags="Cache CachePort Bus"
-#root.trace.cycle=3810800
+#root.trace.flags="Cache CachePort MemoryAccess"
+#root.trace.cycle=1