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authorNilay Vaish <nilay@cs.wisc.edu>2013-07-02 10:10:58 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2013-07-02 10:10:58 -0500
commitaf58313fd61e7f7278af7d3bf97ba98e79e2ab90 (patch)
treee2c1539a0c071f87107fd6ea45db1b6a0c195f67 /tests
parent1be0098c0bbb7c4b5dbc51657cb8b53aa6a284d1 (diff)
downloadgem5-af58313fd61e7f7278af7d3bf97ba98e79e2ab90.tar.xz
regressions: update a couple of configs
The configs for pc-simple-timing-ruby, t1000-simple-atomic had not been updated correctly in the patch 6e6cefc1db1f.
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/pc-simple-timing-ruby.py7
-rw-r--r--tests/configs/t1000-simple-atomic.py4
2 files changed, 8 insertions, 3 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 5799c0c7a..e0ef72db9 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -56,10 +56,13 @@ options.num_cpus = 2
#the system
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
- mdesc=mdesc, Ruby=True,
+ mdesc=mdesc, Ruby=True)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
-system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
+system.clk_domain = SrcClockDomain(clock = '1GHz')
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
+ for i in xrange(options.num_cpus)]
Ruby.create_system(options, system, system.piobus, system._dma_ports)
diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index 7f04751b8..c0744a6a2 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -31,8 +31,10 @@ from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-cpu = AtomicSimpleCPU(cpu_id=0)
system = FSConfig.makeSparcSystem('atomic', SimpleMemory)
+system.clk_domain = SrcClockDomain(clock = '1GHz')
+system.cpu_clk_domain = SrcClockDomain(clock = '1GHz')
+cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
system.cpu = cpu
# create the interrupt controller
cpu.createInterruptController()