diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-13 17:44:32 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-13 17:44:32 -0800 |
| commit | b046f3feb6e54f128e8868fcb807d0d5ac0d7ba7 (patch) | |
| tree | 7b91be055f2b91c0707ca431adf22dc157bfa7f4 /tests | |
| parent | 4e1adf85f77edf761466af3568576d3f9134a14c (diff) | |
| download | gem5-b046f3feb6e54f128e8868fcb807d0d5ac0d7ba7.tar.xz | |
X86: Update stats for the reduced register reads.
Diffstat (limited to 'tests')
42 files changed, 1860 insertions, 1864 deletions
diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index 3dbb4b0b4..49d802c81 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -1067,4 +1067,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 772390499500 because target called exit() +Exiting @ tick 758990697000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 05b37528b..919310d13 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 168346 # Simulator instruction rate (inst/s) -host_mem_usage 232444 # Number of bytes of host memory used -host_seconds 9631.89 # Real time elapsed on the host -host_tick_rate 80190939 # Simulator tick rate (ticks/s) +host_inst_rate 248801 # Simulator instruction rate (inst/s) +host_mem_usage 232880 # Number of bytes of host memory used +host_seconds 6517.22 # Real time elapsed on the host +host_tick_rate 116459266 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated -sim_seconds 0.772390 # Number of seconds simulated -sim_ticks 772390499500 # Number of ticks simulated +sim_seconds 0.758991 # Number of seconds simulated +sim_ticks 758990697000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 126254885 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 126894033 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 123829137 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 124444739 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5933287 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 126894073 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 126894073 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 5933451 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 124445048 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 124445048 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 107161579 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3710402 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 4428744 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1511501895 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.072770 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.173458 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1488500908 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.089347 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.266465 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 505879323 33.47% 33.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 677452709 44.82% 78.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 153213861 10.14% 88.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 112394621 7.44% 95.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 32585093 2.16% 98.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 19016713 1.26% 99.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 5421676 0.36% 99.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1827497 0.12% 99.75% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3710402 0.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 544771983 36.60% 36.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 603082048 40.52% 77.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 142955782 9.60% 86.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 121627881 8.17% 94.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 42142525 2.83% 97.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 19097450 1.28% 99.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 4632040 0.31% 99.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 5762455 0.39% 99.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 4428744 0.30% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1511501895 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1488500908 # Number of insts commited each cycle system.cpu.commit.COM:count 1621493982 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,422 +44,422 @@ system.cpu.commit.COM:loads 419042125 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5933318 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 5933482 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 227874068 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 174503493 # The number of squashed insts skipped by commit system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.952690 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.952690 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 326327666 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10363.748203 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7391.735933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 326125265 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2097633000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000620 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 202401 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1725 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1483344000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000615 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 200676 # number of ReadReq MSHR misses +system.cpu.cpi 0.936162 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.936162 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 328666076 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10263.411891 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7269.320090 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 328458033 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2135231000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000633 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 208043 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1354 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1502488500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000629 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 206689 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19667.198248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10021.451346 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 186945733 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 24393698000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006591 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1240324 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 994745 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2461058000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001305 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 245579 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 19664.658707 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9970.057484 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 186942755 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 24449109500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006607 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1243302 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 995928 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2466333000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001315 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 247374 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15789.833755 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1149.728625 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 15814.402211 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1135.086514 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29234 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29308 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 461600000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 463488500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 514513723 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18362.010085 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8838.897043 # average overall mshr miss latency -system.cpu.dcache.demand_hits 513070998 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26491331000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002804 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1442725 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 996470 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3944402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000867 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 446255 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 516852133 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18317.037300 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8740.684663 # average overall mshr miss latency +system.cpu.dcache.demand_hits 515400788 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26584340500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002808 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1451345 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 997282 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 3968821500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000879 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 454063 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.101758 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 514513723 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18362.010085 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8838.897043 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999777 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.087002 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 516852133 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18317.037300 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8740.684663 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 513070998 # number of overall hits -system.cpu.dcache.overall_miss_latency 26491331000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002804 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1442725 # number of overall misses -system.cpu.dcache.overall_mshr_hits 996470 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3944402000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000867 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 446255 # number of overall MSHR misses +system.cpu.dcache.overall_hits 515400788 # number of overall hits +system.cpu.dcache.overall_miss_latency 26584340500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002808 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1451345 # number of overall misses +system.cpu.dcache.overall_mshr_hits 997282 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 3968821500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000879 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 454063 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 442158 # number of replacements -system.cpu.dcache.sampled_refs 446254 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 449967 # number of replacements +system.cpu.dcache.sampled_refs 454063 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.101758 # Cycle average of tags in use -system.cpu.dcache.total_refs 513070998 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 331552000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 398281 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 176333648 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 1886463332 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 320369444 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 981528406 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 33063147 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 33270397 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 126894073 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 119630706 # Number of cache lines fetched -system.cpu.fetch.Cycles 1056772647 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 432705 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1026147627 # Number of instructions fetch has processed +system.cpu.dcache.tagsinuse 4095.087002 # Cycle average of tags in use +system.cpu.dcache.total_refs 515400788 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 331273000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 403776 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 134525635 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 1844468999 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 346793246 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 965499551 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 29266045 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 41682476 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 124445048 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 129713560 # Number of cache lines fetched +system.cpu.fetch.Cycles 1050276779 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 844154 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1022007635 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 9324994 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.082144 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 119630706 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 126254885 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.664267 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1544565042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.230490 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.292215 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 12829021 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.081981 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 129713560 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 123829137 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.673268 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1517766953 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.229744 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.282154 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 522111775 33.80% 33.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 496583342 32.15% 65.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 273451194 17.70% 83.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224891951 14.56% 98.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8280335 0.54% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1557581 0.10% 98.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 722 0.00% 98.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8665 0.00% 98.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 17679477 1.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 499259849 32.89% 32.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 507370292 33.43% 66.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 273389808 18.01% 84.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 210662042 13.88% 98.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8152383 0.54% 98.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1243560 0.08% 98.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 720 0.00% 98.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8664 0.00% 98.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 17679635 1.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1544565042 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1517766953 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 2 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 119630706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37171.926007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 119629787 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 34161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000008 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 919 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 127 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 28063500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 129713560 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 37165.425532 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35455.808081 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 129712620 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 34935500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 940 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 148 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 28081000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 792 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 151047.710859 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 163778.560606 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 119630706 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37171.926007 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35433.712121 # average overall mshr miss latency -system.cpu.icache.demand_hits 119629787 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 34161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000008 # miss rate for demand accesses -system.cpu.icache.demand_misses 919 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 127 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 28063500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 129713560 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 37165.425532 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35455.808081 # average overall mshr miss latency +system.cpu.icache.demand_hits 129712620 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 34935500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_misses 940 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 148 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 28081000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 792 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.352078 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 721.055018 # Average occupied blocks per context -system.cpu.icache.overall_accesses 119630706 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37171.926007 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35433.712121 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.352940 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 722.820283 # Average occupied blocks per context +system.cpu.icache.overall_accesses 129713560 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 37165.425532 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35455.808081 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 119629787 # number of overall hits -system.cpu.icache.overall_miss_latency 34161000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000008 # miss rate for overall accesses -system.cpu.icache.overall_misses 919 # number of overall misses -system.cpu.icache.overall_mshr_hits 127 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 28063500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 129712620 # number of overall hits +system.cpu.icache.overall_miss_latency 34935500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_misses 940 # number of overall misses +system.cpu.icache.overall_mshr_hits 148 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 28081000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 792 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 4 # number of replacements system.cpu.icache.sampled_refs 792 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 721.055018 # Cycle average of tags in use -system.cpu.icache.total_refs 119629787 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 722.820283 # Cycle average of tags in use +system.cpu.icache.total_refs 129712620 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 215958 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 108586362 # Number of branches executed +system.cpu.idleCycles 214442 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 108628514 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.090888 # Inst execution rate -system.cpu.iew.EXEC:refs 624680336 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 190102881 # Number of stores executed +system.cpu.iew.EXEC:rate 1.113825 # Inst execution rate +system.cpu.iew.EXEC:refs 627755630 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 190105687 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2506292363 # num instructions consuming a value -system.cpu.iew.WB:count 1680860111 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.529936 # average fanout of values written-back +system.cpu.iew.WB:consumers 2045668274 # num instructions consuming a value +system.cpu.iew.WB:count 1687762822 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.647025 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1328173821 # num instructions producing a value -system.cpu.iew.WB:rate 1.088090 # insts written-back per cycle -system.cpu.iew.WB:sent 1681411195 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6122546 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1253236 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 492554241 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 66 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3215387 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 210212351 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1849358863 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 434577455 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8332046 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1685183738 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 18939 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1323598001 # num instructions producing a value +system.cpu.iew.WB:rate 1.111847 # insts written-back per cycle +system.cpu.iew.WB:sent 1688206003 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6113342 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1234561 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 466864036 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3697894 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 198431314 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1795988309 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 437649943 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8316492 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1690766136 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 11689 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 33063147 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 72665 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 29266045 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 61051 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 29234 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 108234700 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 16690 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 29308 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 108968785 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 18692 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3968261 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 13 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 73512116 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 22026294 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3968261 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 6120468 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 4148897019 # number of integer regfile reads -system.cpu.int_regfile_writes 1677631671 # number of integer regfile writes -system.cpu.ipc 1.049659 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.049659 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24157467 1.43% 1.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1040578234 61.44% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 438214492 25.88% 88.75% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 190565591 11.25% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 6882405 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 14 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 47821911 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 10245257 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6882405 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2235 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 6111107 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3449745474 # number of integer regfile reads +system.cpu.int_regfile_writes 1684589292 # number of integer regfile writes +system.cpu.ipc 1.068191 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.068191 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24153767 1.42% 1.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1042557757 61.36% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 442155303 26.02% 88.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 190215801 11.20% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1693515784 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 252744 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000149 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1699082628 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 898465 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.000529 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 40 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 250833 99.24% 99.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1871 0.74% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 2 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 782842 87.13% 87.13% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 115621 12.87% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1544565042 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.096435 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.983023 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1517766953 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.119462 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.970342 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 454758636 29.44% 29.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 667103033 43.19% 72.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 281275831 18.21% 90.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 105166888 6.81% 97.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 33264638 2.15% 99.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2679834 0.17% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 311387 0.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 3979 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 816 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 418312841 27.56% 27.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 673262157 44.36% 71.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 290551111 19.14% 91.06% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 102329684 6.74% 97.81% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 29422654 1.94% 99.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 3376155 0.22% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 428915 0.03% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 83172 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 264 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1544565042 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.096282 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 1517766953 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.119304 # Inst issue rate system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1669611057 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 4931850619 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1680860109 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 2080058032 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1849358797 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1693515784 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 66 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 226765112 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1273 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 584800312 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 245580 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34276.926221 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.745964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 186864 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2012604000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.239091 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58716 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1824643500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.239091 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58716 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 201467 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34133.939861 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.577487 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 169042 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1106793000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.160944 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32425 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1005291000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.160944 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32425 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 398281 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 398281 # number of Writeback hits +system.cpu.iq.int_alu_accesses 1675827322 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4916833706 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1687762820 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 1976960091 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1795988242 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1699082628 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 174090375 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 3040 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 340356814 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 247374 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34288.873379 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31083.636921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 188632 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2014197000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.237462 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58742 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825915000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.237462 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58742 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 207481 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34134.816432 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.350224 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 174959 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1110132500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.156747 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32522 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1008356000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156747 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32522 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 403776 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 403776 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.844642 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.963363 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 447047 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34226.056330 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.070769 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 355906 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3119397000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.203873 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91141 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 454855 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34233.975061 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31055.739393 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 363591 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3124329500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.200644 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91264 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2829934500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.203873 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91141 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2834271000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.200644 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91264 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.058867 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.490866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1928.938344 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16084.711341 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 447047 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34226.056330 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.070769 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.058891 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.491980 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1929.753834 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16121.198217 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 454855 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34233.975061 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31055.739393 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 355906 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3119397000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.203873 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91141 # number of overall misses +system.cpu.l2cache.overall_hits 363591 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3124329500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.200644 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91264 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2829934500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.203873 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91141 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2834271000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.200644 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91264 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72873 # number of replacements -system.cpu.l2cache.sampled_refs 88473 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 72998 # number of replacements +system.cpu.l2cache.sampled_refs 88598 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18013.649684 # Cycle average of tags in use -system.cpu.l2cache.total_refs 428620 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18050.952051 # Cycle average of tags in use +system.cpu.l2cache.total_refs 439744 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58405 # number of writebacks -system.cpu.memDep0.conflictingLoads 289036318 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 113016383 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 492554241 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210212351 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 864820574 # number of misc regfile reads -system.cpu.numCycles 1544781000 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 58419 # number of writebacks +system.cpu.memDep0.conflictingLoads 312249439 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 119901234 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 466864036 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 198431314 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 865536711 # number of misc regfile reads +system.cpu.numCycles 1517981395 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 55578139 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 28986025 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 65710608 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 361165681 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 36822801 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 5668050381 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1874385455 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1871676358 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 968560202 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 33063147 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 126195704 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 253681708 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 33672472 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 389992916 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 45640252 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 23 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4730693313 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1827559293 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1825935922 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 951399892 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 29266045 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 118119949 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 207941272 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5668050349 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 2169 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 67 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 186996608 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 71 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3357159543 # The number of ROB reads -system.cpu.rob.rob_writes 3732197477 # The number of ROB writes -system.cpu.timesIdled 45108 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 4730693281 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 2126 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 68 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 172417007 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 68 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3280069639 # The number of ROB reads +system.cpu.rob.rob_writes 3621261017 # The number of ROB writes +system.cpu.timesIdled 45168 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 1dd3bb0d2..72e931207 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:38:48 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index ce8635d17..e077de326 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1066510 # Simulator instruction rate (inst/s) -host_mem_usage 223440 # Number of bytes of host memory used -host_seconds 1520.37 # Real time elapsed on the host -host_tick_rate 634049597 # Simulator tick rate (ticks/s) +host_inst_rate 2143892 # Simulator instruction rate (inst/s) +host_mem_usage 223996 # Number of bytes of host memory used +host_seconds 756.33 # Real time elapsed on the host +host_tick_rate 1274562548 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 0.963993 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_int_insts 1621354493 # number of integer instructions -system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_reads 4205693190 # number of times the integer registers were read system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_mem_refs 607228182 # number of memory refs diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 889c6868b..e3aac138f 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:35 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 46400c920..c5653609a 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 685934 # Simulator instruction rate (inst/s) -host_mem_usage 231240 # Number of bytes of host memory used -host_seconds 2363.92 # Real time elapsed on the host -host_tick_rate 762824620 # Simulator tick rate (ticks/s) +host_inst_rate 1483739 # Simulator instruction rate (inst/s) +host_mem_usage 231720 # Number of bytes of host memory used +host_seconds 1092.84 # Real time elapsed on the host +host_tick_rate 1650061335 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 1.803259 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_int_insts 1621354493 # number of integer instructions -system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_reads 4205693190 # number of times the integer registers were read system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_mem_refs 607228182 # number of memory refs diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 1d5316147..38bf6ae35 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:04:06 -M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch -M5 started Feb 7 2011 01:04:09 +M5 compiled Feb 7 2011 20:06:47 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:51 M5 executing on burrito -command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic +command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112051463500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 1cabd6a2d..8bbe54cee 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2329852 # Simulator instruction rate (inst/s) -host_mem_usage 370744 # Number of bytes of host memory used -host_seconds 174.53 # Real time elapsed on the host -host_tick_rate 29290692573 # Simulator tick rate (ticks/s) +host_inst_rate 1847456 # Simulator instruction rate (inst/s) +host_mem_usage 370792 # Number of bytes of host memory used +host_seconds 220.10 # Real time elapsed on the host +host_tick_rate 23226044729 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 406624453 # Number of instructions simulated sim_seconds 5.112051 # Number of seconds simulated @@ -341,7 +341,7 @@ system.cpu.num_idle_cycles 9770620811.997942 system.cpu.num_insts 406624453 # Number of instructions executed system.cpu.num_int_alu_accesses 391833833 # Number of integer alu accesses system.cpu.num_int_insts 391833833 # number of integer instructions -system.cpu.num_int_register_reads 1007515486 # number of times the integer registers were read +system.cpu.num_int_register_reads 896752479 # number of times the integer registers were read system.cpu.num_int_register_writes 419160860 # number of times the integer registers were written system.cpu.num_load_insts 29720540 # Number of load instructions system.cpu.num_mem_refs 38133606 # number of memory refs diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 6d191e20f..2c385565e 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:04:06 -M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch -M5 started Feb 7 2011 01:04:09 +M5 compiled Feb 7 2011 20:06:47 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:51 M5 executing on burrito -command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing +command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5187506658000 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index b4552b7b7..78f75199b 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1700985 # Simulator instruction rate (inst/s) -host_mem_usage 367580 # Number of bytes of host memory used -host_seconds 155.42 # Real time elapsed on the host -host_tick_rate 33377224644 # Simulator tick rate (ticks/s) +host_inst_rate 1318453 # Simulator instruction rate (inst/s) +host_mem_usage 367344 # Number of bytes of host memory used +host_seconds 200.51 # Real time elapsed on the host +host_tick_rate 25871076282 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 264367743 # Number of instructions simulated sim_seconds 5.187507 # Number of seconds simulated @@ -395,7 +395,7 @@ system.cpu.num_idle_cycles 9771315874.126116 system.cpu.num_insts 264367743 # Number of instructions executed system.cpu.num_int_alu_accesses 249584659 # Number of integer alu accesses system.cpu.num_int_insts 249584659 # number of integer instructions -system.cpu.num_int_register_reads 660399505 # number of times the integer registers were read +system.cpu.num_int_register_reads 590325911 # number of times the integer registers were read system.cpu.num_int_register_writes 266062505 # number of times the integer registers were written system.cpu.num_load_insts 14817593 # Number of load instructions system.cpu.num_mem_refs 23178416 # number of memory refs diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index bf0cc96de..b6199beb5 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 170680631000 because target called exit() +Exiting @ tick 137353348000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 3db6ff161..b4318c66f 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 83481 # Simulator instruction rate (inst/s) -host_mem_usage 366872 # Number of bytes of host memory used -host_seconds 3332.41 # Real time elapsed on the host -host_tick_rate 51218385 # Simulator tick rate (ticks/s) +host_inst_rate 206155 # Simulator instruction rate (inst/s) +host_mem_usage 367336 # Number of bytes of host memory used +host_seconds 1349.43 # Real time elapsed on the host +host_tick_rate 101786117 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated -sim_seconds 0.170681 # Number of seconds simulated -sim_ticks 170680631000 # Number of ticks simulated +sim_seconds 0.137353 # Number of seconds simulated +sim_ticks 137353348000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 50810617 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 51416767 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 43044448 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 43605632 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4328981 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 51416803 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 51416803 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 4328985 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 43605708 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 43605708 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 29309710 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2488105 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2295915 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 321793097 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.864507 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.425920 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 264042401 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.053590 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.542507 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 183622049 57.06% 57.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 75902754 23.59% 80.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 27223254 8.46% 89.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 17908154 5.57% 94.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 5463718 1.70% 96.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 3630830 1.13% 97.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 4674698 1.45% 98.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 879535 0.27% 99.23% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2488105 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 131063071 49.64% 49.64% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 68068160 25.78% 75.42% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 28810036 10.91% 86.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 19729094 7.47% 93.80% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 3997193 1.51% 95.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 3201909 1.21% 96.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 5187793 1.96% 98.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1689230 0.64% 99.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2295915 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 321793097 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 264042401 # Number of insts commited each cycle system.cpu.commit.COM:count 278192519 # Number of instructions committed system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,421 +44,423 @@ system.cpu.commit.COM:loads 90779388 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 122219139 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4328992 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4328993 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 111464423 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61447181 # The number of squashed insts skipped by commit system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 1.227068 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.227068 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 82779625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5978.815311 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2941.059048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 80764514 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12047976500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.024343 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 2015111 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 45360 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5793154000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.023795 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1969751 # number of ReadReq MSHR misses +system.cpu.cpi 0.987470 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.987470 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 78473515 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5892.080019 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2802.465298 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 76426591 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12060640000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.026084 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 2046924 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 76655 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5521610500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.025107 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1970269 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 20696.077989 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 15440.513442 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 31284703 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3208885500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.004932 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 155048 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48629 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1643164000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106419 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 21791.452056 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 16914.293943 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 31282890 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3418228961 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.004989 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 156861 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 50497 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1799071961 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003383 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 106364 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3035.211268 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 53.969218 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.avg_refs 51.867365 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 71 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 215500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 114219376 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7030.296858 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3581.748123 # average overall mshr miss latency -system.cpu.dcache.demand_hits 112049217 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15256862000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.019000 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2170159 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 93989 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7436318000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.018177 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2076170 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 109913266 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7023.765459 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3525.265399 # average overall mshr miss latency +system.cpu.dcache.demand_hits 107709481 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 15478868961 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020050 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2203785 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 127152 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7320682461 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.018893 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2076633 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995143 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4076.104755 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 114219376 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7030.296858 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3581.748123 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.994785 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4074.637859 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 109913266 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7023.765459 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3525.265399 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 112049217 # number of overall hits -system.cpu.dcache.overall_miss_latency 15256862000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.019000 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2170159 # number of overall misses -system.cpu.dcache.overall_mshr_hits 93989 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7436318000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.018177 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2076170 # number of overall MSHR misses +system.cpu.dcache.overall_hits 107709481 # number of overall hits +system.cpu.dcache.overall_miss_latency 15478868961 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020050 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2203785 # number of overall misses +system.cpu.dcache.overall_mshr_hits 127152 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7320682461 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.018893 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2076633 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2072073 # number of replacements -system.cpu.dcache.sampled_refs 2076169 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2072537 # number of replacements +system.cpu.dcache.sampled_refs 2076633 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.104755 # Cycle average of tags in use -system.cpu.dcache.total_refs 112049217 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 66009760000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1440063 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 922031 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 437195268 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 92021485 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 228705655 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 19453848 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 143926 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 51416803 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 39245397 # Number of cache lines fetched -system.cpu.fetch.Cycles 242939967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 793923 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 249694241 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 9845420 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.150623 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 39245397 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50810617 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.731466 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 341246945 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.321737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.251135 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4074.637859 # Cycle average of tags in use +system.cpu.dcache.total_refs 107709481 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 54571641000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1440067 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 1078320 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 365035506 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 68035567 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 194761019 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 10324266 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 167495 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 43605708 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 29060081 # Number of cache lines fetched +system.cpu.fetch.Cycles 205057262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 469074 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 209709437 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 4648806 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.158736 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 29060081 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 43044448 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.763394 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 274366667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.362439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.220161 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 105340577 30.87% 30.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 115413940 33.82% 64.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 47580781 13.94% 78.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 58732555 17.21% 95.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7189604 2.11% 97.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6451059 1.89% 99.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 527277 0.15% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 932 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10220 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75544313 27.53% 27.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 99907030 36.41% 63.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38310109 13.96% 77.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 50324165 18.34% 96.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5339949 1.95% 98.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4719664 1.72% 99.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 210294 0.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 928 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10215 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 341246945 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 44 # number of floating regfile reads -system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 39245397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37208.490566 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35316.192560 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 39244337 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 39441000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1060 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 146 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32279000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 914 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 274366667 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 46 # number of floating regfile reads +system.cpu.fp_regfile_writes 32 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 29060081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 37083.333333 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35353.296703 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 29059007 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 39827500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1074 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32171500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 42936.911379 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 31932.974725 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 39245397 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37208.490566 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35316.192560 # average overall mshr miss latency -system.cpu.icache.demand_hits 39244337 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 39441000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses -system.cpu.icache.demand_misses 1060 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32279000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000023 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 914 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 29060081 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 37083.333333 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35353.296703 # average overall mshr miss latency +system.cpu.icache.demand_hits 29059007 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 39827500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000037 # miss rate for demand accesses +system.cpu.icache.demand_misses 1074 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32171500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.360466 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 738.235227 # Average occupied blocks per context -system.cpu.icache.overall_accesses 39245397 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37208.490566 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35316.192560 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.357987 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 733.158070 # Average occupied blocks per context +system.cpu.icache.overall_accesses 29060081 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 37083.333333 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35353.296703 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 39244337 # number of overall hits -system.cpu.icache.overall_miss_latency 39441000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses -system.cpu.icache.overall_misses 1060 # number of overall misses -system.cpu.icache.overall_mshr_hits 146 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32279000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000023 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 914 # number of overall MSHR misses +system.cpu.icache.overall_hits 29059007 # number of overall hits +system.cpu.icache.overall_miss_latency 39827500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000037 # miss rate for overall accesses +system.cpu.icache.overall_misses 1074 # number of overall misses +system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32171500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 37 # number of replacements -system.cpu.icache.sampled_refs 914 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 738.235227 # Cycle average of tags in use -system.cpu.icache.total_refs 39244337 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 733.158070 # Cycle average of tags in use +system.cpu.icache.total_refs 29059007 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 114318 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 31118985 # Number of branches executed +system.cpu.idleCycles 340030 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 31975279 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.940576 # Inst execution rate -system.cpu.iew.EXEC:refs 137464023 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 32172568 # Number of stores executed +system.cpu.iew.EXEC:rate 1.141834 # Inst execution rate +system.cpu.iew.EXEC:refs 137788104 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 32893684 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 361852587 # num instructions consuming a value -system.cpu.iew.WB:count 317781549 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.623035 # average fanout of values written-back +system.cpu.iew.WB:consumers 277834485 # num instructions consuming a value +system.cpu.iew.WB:count 310858537 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.803184 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 225446782 # num instructions producing a value -system.cpu.iew.WB:rate 0.930924 # insts written-back per cycle -system.cpu.iew.WB:sent 318008427 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 5390321 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 197365 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 131280417 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 455 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3671049 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 41039188 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 389592858 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 105291455 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12266571 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 321076071 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2799 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 223152216 # num instructions producing a value +system.cpu.iew.WB:rate 1.131602 # insts written-back per cycle +system.cpu.iew.WB:sent 311298125 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 5432801 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 434257 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 113153901 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 453 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3329994 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 36225707 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 339638144 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 104894420 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7540683 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 313669330 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1132 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1704 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 19453848 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 10507 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 39972 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 10324266 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 75875 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 22405068 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 64376 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 6157 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 26233968 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 75546 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5520980 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 373621 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 2668 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 40501029 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 9599437 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5520980 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 16897 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5373424 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 754340794 # number of integer regfile reads -system.cpu.int_regfile_writes 286169707 # number of integer regfile writes -system.cpu.ipc 0.814950 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.814950 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 22374513 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4785956 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 373621 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 7861 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5424940 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 583701883 # number of integer regfile reads +system.cpu.int_regfile_writes 279097661 # number of integer regfile writes +system.cpu.ipc 1.012689 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.012689 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16700 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 193455065 58.03% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 107162338 32.15% 90.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 32708524 9.81% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 181103840 56.38% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 106927667 33.29% 89.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 33161791 10.32% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 333342642 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 98152 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000294 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 321210013 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1288241 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.004011 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 15 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 97651 99.49% 99.50% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 486 0.50% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1088765 84.52% 84.52% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 199475 15.48% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 341246945 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.976837 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.032280 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 274366667 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.170733 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.057250 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 143332703 42.00% 42.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 98734149 28.93% 70.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 68142120 19.97% 90.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 26890607 7.88% 98.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 3089152 0.91% 99.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1054470 0.31% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 2951 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 576 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 217 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 85009751 30.98% 30.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 94999011 34.62% 65.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 64668868 23.57% 89.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 24623631 8.97% 98.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 3181639 1.16% 99.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1035626 0.38% 99.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 839375 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 8691 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 75 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 341246945 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.976510 # Inst issue rate -system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 110 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 49 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 110 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 333424039 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1008030271 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 317781500 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 504991584 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 389592403 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 333342642 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 455 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 109882124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 237362106 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 106419 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34277.831445 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.336758 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 63976 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 1454854000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.398829 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 42443 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317827000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398829 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 42443 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1970665 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34310.495712 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31007.530164 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1936270 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1180109500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.017453 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34395 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1066504000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017453 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34395 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1440063 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1440063 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.iq.ISSUE:issued_per_cycle::total 274366667 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.169284 # Inst issue rate +system.cpu.iq.fp_alu_accesses 58 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 116 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 102 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 322481496 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 918075310 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 310858485 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 400954774 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 339637691 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 321210013 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 453 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 61001038 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 492 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 78304745 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 106364 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34222.852226 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31038.534987 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 63948 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 1451596500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.398782 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 42416 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1316530500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398782 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 42416 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1971179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34221.265286 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31012.315915 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1936752 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1178135500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.017465 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34427 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1067661000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017465 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34427 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1440067 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1440067 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1272.727273 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 42.751383 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 42.754105 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 14000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2077084 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34292.452953 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.622869 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2000246 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2634963500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.036993 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 76838 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 2077543 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34222.141249 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31026.788387 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2000700 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2629732000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.036987 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 76843 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2384331000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.036993 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 76838 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2384191500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.036987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 76843 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.192442 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.349126 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 6305.950681 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11440.167306 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2077084 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34292.452953 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.622869 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.188685 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.343727 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 6182.815069 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11263.234870 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2077543 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34222.141249 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31026.788387 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2000246 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2634963500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.036993 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 76838 # number of overall misses +system.cpu.l2cache.overall_hits 2000700 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2629732000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.036987 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 76843 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2384331000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.036993 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 76838 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2384191500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.036987 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 76843 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 49392 # number of replacements -system.cpu.l2cache.sampled_refs 77392 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 49399 # number of replacements +system.cpu.l2cache.sampled_refs 77399 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17746.117987 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3308615 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17446.049939 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3309125 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 29474 # number of writebacks -system.cpu.memDep0.conflictingLoads 22358679 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3757180 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 131280417 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 41039188 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 204301939 # number of misc regfile reads -system.cpu.numCycles 341361263 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 29483 # number of writebacks +system.cpu.memDep0.conflictingLoads 30510087 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6437799 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 113153901 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36225707 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 204124363 # number of misc regfile reads +system.cpu.numCycles 274706697 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 486743 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 682912 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 12249 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 98511117 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 368076 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 1292599643 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 423407319 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 377348250 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 222275258 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 19453848 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 514692 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 129004058 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 291 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 1292599352 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 5287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 454 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 779091 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 708961934 # The number of ROB reads -system.cpu.rob.rob_writes 799263493 # The number of ROB writes -system.cpu.timesIdled 5627 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 11638 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 72242818 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 253088 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 902485567 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 357042681 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 317208618 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 190696526 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 10324266 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 414923 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 68864426 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 276 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 902485291 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 5222 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 452 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 585103 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 450 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 601386186 # The number of ROB reads +system.cpu.rob.rob_writes 689603687 # The number of ROB writes +system.cpu.timesIdled 20021 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index e76d60819..2624a92df 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index bcab65c40..53aa79f38 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 722489 # Simulator instruction rate (inst/s) -host_mem_usage 358012 # Number of bytes of host memory used -host_seconds 385.05 # Real time elapsed on the host -host_tick_rate 438776725 # Simulator tick rate (ticks/s) +host_inst_rate 1484941 # Simulator instruction rate (inst/s) +host_mem_usage 358488 # Number of bytes of host memory used +host_seconds 187.34 # Real time elapsed on the host +host_tick_rate 901823457 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.168950 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_int_insts 278186228 # number of integer instructions -system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_reads 713132571 # number of times the integer registers were read system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 0b92276cc..dba2fbaff 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index cf6f03e98..9b901367a 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 424375 # Simulator instruction rate (inst/s) -host_mem_usage 365728 # Number of bytes of host memory used -host_seconds 655.54 # Real time elapsed on the host -host_tick_rate 564440982 # Simulator tick rate (ticks/s) +host_inst_rate 949258 # Simulator instruction rate (inst/s) +host_mem_usage 366212 # Number of bytes of host memory used +host_seconds 293.06 # Real time elapsed on the host +host_tick_rate 1262562260 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.370011 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_int_insts 278186228 # number of integer instructions -system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_reads 713132571 # number of times the integer registers were read system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 8363ae747..da344ea4b 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 4d3b5f29b..50a40bebc 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 10 2011 20:38:27 +M5 revision 944f6c89dbb7 7941 default qtip regwidthdecstats.patch tip +M5 started Feb 10 2011 20:38:30 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,10 +26,10 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success +info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 817002039000 because target called exit() +Exiting @ tick 698491025500 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index c39e8dfae..76386c514 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 160923 # Simulator instruction rate (inst/s) -host_mem_usage 240360 # Number of bytes of host memory used -host_seconds 9501.35 # Real time elapsed on the host -host_tick_rate 85987979 # Simulator tick rate (ticks/s) +host_inst_rate 136830 # Simulator instruction rate (inst/s) +host_mem_usage 244640 # Number of bytes of host memory used +host_seconds 11174.38 # Real time elapsed on the host +host_tick_rate 62508267 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988756 # Number of instructions simulated -sim_seconds 0.817002 # Number of seconds simulated -sim_ticks 817002039000 # Number of ticks simulated +sim_seconds 0.698491 # Number of seconds simulated +sim_ticks 698491025500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 197674461 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 215147546 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 172887264 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 187312240 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 17901021 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 215739151 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 215739151 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 17887438 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 187888188 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 187888188 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 149758588 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8186576 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 10029766 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1552269342 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.985002 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.301395 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1350871673 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.131853 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.433209 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 694185983 44.72% 44.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 509617235 32.83% 77.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 176087126 11.34% 88.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 105147186 6.77% 95.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 31137095 2.01% 97.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 11224991 0.72% 98.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 11192282 0.72% 99.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 5490868 0.35% 99.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 8186576 0.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 568349245 42.07% 42.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 413717350 30.63% 72.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 172321570 12.76% 85.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 110104358 8.15% 93.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 43035291 3.19% 96.79% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 18507275 1.37% 98.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 8248201 0.61% 98.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 6558617 0.49% 99.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 10029766 0.74% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1552269342 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1350871673 # Number of insts commited each cycle system.cpu.commit.COM:count 1528988756 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,432 +44,432 @@ system.cpu.commit.COM:loads 384102160 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 533262345 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 17902344 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 17888761 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 459109010 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257046446 # The number of squashed insts skipped by commit system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 1.068683 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.068683 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 352008034 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14100.976079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8499.435037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 350035037 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27821183500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005605 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1972997 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 237485 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 14750871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1735512 # number of ReadReq MSHR misses +system.cpu.cpi 0.913664 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.913664 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 334229227 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14263.584813 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8537.168964 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 332171764 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 29346798000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.006156 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 2057463 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 319131 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 14840434000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005201 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1738332 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 15942.157352 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12645.445755 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 148213244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 15096537500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006349 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 946957 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 159966 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 9951852000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 16290.992476 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12654.921756 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 148197195 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 15688323500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006456 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 963006 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 176041 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 9958980500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005276 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 786991 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 786965 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 197.709284 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 190.400689 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 501168235 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14698.081203 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency -system.cpu.dcache.demand_hits 498248281 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 42917721000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005826 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2919954 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 397451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 24702723500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2522503 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 483389428 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 14909.976398 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9820.395185 # average overall mshr miss latency +system.cpu.dcache.demand_hits 480368959 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 45035121500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.006249 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3020469 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 495172 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 24799414500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005224 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2525297 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997749 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4086.780222 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 501168235 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14698.081203 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.997741 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4086.747665 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 483389428 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 14909.976398 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9820.395185 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 498248281 # number of overall hits -system.cpu.dcache.overall_miss_latency 42917721000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005826 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2919954 # number of overall misses -system.cpu.dcache.overall_mshr_hits 397451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 24702723500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2522503 # number of overall MSHR misses +system.cpu.dcache.overall_hits 480368959 # number of overall hits +system.cpu.dcache.overall_miss_latency 45035121500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.006249 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3020469 # number of overall misses +system.cpu.dcache.overall_mshr_hits 495172 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 24799414500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005224 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2525297 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2516044 # number of replacements -system.cpu.dcache.sampled_refs 2520140 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2518885 # number of replacements +system.cpu.dcache.sampled_refs 2522981 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.780222 # Cycle average of tags in use -system.cpu.dcache.total_refs 498255076 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3876881000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2224034 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 25470243 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 2119227193 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 403203369 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1116867689 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 71636028 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 6728041 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 215739151 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 165973622 # Number of cache lines fetched -system.cpu.fetch.Cycles 1190006834 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 2725815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1144873460 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 1839 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 29822694 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.132031 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 165973622 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 197674461 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.700655 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1623905370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.336094 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.273592 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4086.747665 # Cycle average of tags in use +system.cpu.dcache.total_refs 480377321 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 3312879000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2225275 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 18280435 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 1869219380 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 343093281 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 984893533 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 39316255 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 4604424 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 187888188 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 144979108 # Number of cache lines fetched +system.cpu.fetch.Cycles 1039380252 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2070461 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 999560833 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1828 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 17988626 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.134496 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 144979108 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 172887264 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.715514 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1390187928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.363495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.275570 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 477535637 29.41% 29.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 564706157 34.77% 64.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 259330057 15.97% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 261180842 16.08% 96.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 22809127 1.40% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 31399021 1.93% 99.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 502829 0.03% 99.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12 0.00% 99.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6441688 0.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 388271402 27.93% 27.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 493387093 35.49% 63.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 229970387 16.54% 79.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224046516 16.12% 96.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21915192 1.58% 97.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25802023 1.86% 99.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 493192 0.04% 99.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12 0.00% 99.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6302111 0.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1623905370 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 10 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 165973622 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 22741.617211 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19372.661290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 165966882 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 153278500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 6740 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 540 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120110500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 6200 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1390187928 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 9 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 144979108 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 22807.726664 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 19441.756997 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 144972391 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 153199500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 6717 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120169500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000043 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 6181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 49795.025203 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 43679.520036 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 165973622 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 22741.617211 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency -system.cpu.icache.demand_hits 165966882 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 153278500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses -system.cpu.icache.demand_misses 6740 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 540 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120110500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 6200 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 144979108 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 22807.726664 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 19441.756997 # average overall mshr miss latency +system.cpu.icache.demand_hits 144972391 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 153199500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses +system.cpu.icache.demand_misses 6717 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 536 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120169500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 6181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.436573 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 894.100654 # Average occupied blocks per context -system.cpu.icache.overall_accesses 165973622 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 22741.617211 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.450710 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 923.054085 # Average occupied blocks per context +system.cpu.icache.overall_accesses 144979108 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 22807.726664 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 19441.756997 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 165966882 # number of overall hits -system.cpu.icache.overall_miss_latency 153278500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses -system.cpu.icache.overall_misses 6740 # number of overall misses -system.cpu.icache.overall_mshr_hits 540 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120110500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 6200 # number of overall MSHR misses +system.cpu.icache.overall_hits 144972391 # number of overall hits +system.cpu.icache.overall_miss_latency 153199500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses +system.cpu.icache.overall_misses 6717 # number of overall misses +system.cpu.icache.overall_mshr_hits 536 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120169500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 6181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1750 # number of replacements -system.cpu.icache.sampled_refs 3333 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1737 # number of replacements +system.cpu.icache.sampled_refs 3319 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 894.100654 # Cycle average of tags in use -system.cpu.icache.total_refs 165966819 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 923.054085 # Cycle average of tags in use +system.cpu.icache.total_refs 144972327 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 10098709 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 158001976 # Number of branches executed +system.cpu.idleCycles 6794124 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 154306305 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.044762 # Inst execution rate -system.cpu.iew.EXEC:refs 586795750 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 160862585 # Number of stores executed +system.cpu.iew.EXEC:rate 1.173655 # Inst execution rate +system.cpu.iew.EXEC:refs 571924541 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 156120222 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2114014731 # num instructions consuming a value -system.cpu.iew.WB:count 1694146367 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.583880 # average fanout of values written-back +system.cpu.iew.WB:consumers 1636048139 # num instructions consuming a value +system.cpu.iew.WB:count 1628444279 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.722963 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1234331323 # num instructions producing a value -system.cpu.iew.WB:rate 1.036807 # insts written-back per cycle -system.cpu.iew.WB:sent 1697627373 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 18573506 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 6103126 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 508224738 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 579 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 12080656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 194089353 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1988097398 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 425933165 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 26013466 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1707144682 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 381189 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1182802327 # num instructions producing a value +system.cpu.iew.WB:rate 1.165687 # insts written-back per cycle +system.cpu.iew.WB:sent 1630313962 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 18753816 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4588629 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 454402470 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 11948307 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 170547501 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1786034876 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 415804319 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21119599 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1639574511 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 357621 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 10588 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 71636028 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 847228 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9695 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 39316255 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 668139 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 72909425 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 277837 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 80610216 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 294173 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 11954619 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 832 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 124122578 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 44929168 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 11954619 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 280770 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 18292736 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 3876226209 # number of integer regfile reads -system.cpu.int_regfile_writes 1582892637 # number of integer regfile writes -system.cpu.ipc 0.935731 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.935731 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1927969 0.11% 0.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1131725915 65.30% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 435582288 25.13% 90.54% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 163921976 9.46% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 154646 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 837 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 70300310 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 21387316 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 154646 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 515713 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 18238103 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3040879637 # number of integer regfile reads +system.cpu.int_regfile_writes 1524435086 # number of integer regfile writes +system.cpu.ipc 1.094494 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.094494 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1929805 0.12% 0.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1078730229 64.96% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 421270517 25.37% 90.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 158763559 9.56% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1733158148 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1029171 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000594 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1660694110 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 783660 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.000472 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 182 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 466697 45.35% 45.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 562292 54.64% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 37602 4.80% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 575954 73.50% 78.29% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 170104 21.71% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1623905370 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.067278 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.066518 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1390187928 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.194582 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.080366 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 608633589 37.48% 37.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 503635145 31.01% 68.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 353739534 21.78% 90.28% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 117719188 7.25% 97.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 32883027 2.02% 99.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 6737765 0.41% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 234496 0.01% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 322546 0.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 80 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 424313305 30.52% 30.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 484307598 34.84% 65.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 321495427 23.13% 88.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 117467117 8.45% 96.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 33024815 2.38% 99.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 8635258 0.62% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 892156 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 52195 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 57 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1623905370 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.060682 # Inst issue rate -system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 48 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses +system.cpu.iq.ISSUE:issued_per_cycle::total 1390187928 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.188773 # Inst issue rate +system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 9 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1732259326 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5091250901 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1694146357 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 2453039449 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1988096819 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1733158148 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 452995728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1010995901 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 789062 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34275.179377 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.682665 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 541538 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 8483929500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.313694 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247524 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7673660500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313694 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247524 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1734408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34153.383782 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31001.108327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1401925 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 11355419500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.191698 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 332483 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10307341500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191698 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 332483 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2863 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 24.346581 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.148228 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 70 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 0.975550 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 2793 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 86589000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.975550 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 2793 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2224034 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2224034 # number of Writeback hits +system.cpu.iq.int_alu_accesses 1659547943 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 4712390399 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1628444270 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 2036676469 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 1786034306 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1660694110 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 250539717 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 30635 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 457117092 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 789066 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34257.778038 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.587520 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 541510 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 8480718500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.313733 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 247556 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7674629000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313733 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 247556 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1737232 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34158.153227 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.616867 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1403818 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 11388806500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.191923 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 333414 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 10336706500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191923 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 333414 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 2858 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 24.740050 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.358551 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits 69 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_latency 69000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 0.975857 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 2789 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 86460000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.975857 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 2789 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2225275 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2225275 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.356881 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.353417 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2523470 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34205.361315 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1943463 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19839349000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.229845 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 580007 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 2526298 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34200.604162 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.178254 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1945328 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 19869525000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.229969 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 580970 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17981002000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.229845 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 580007 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 18011335500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.229969 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 580970 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.233067 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.421257 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 7637.149597 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13803.753842 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2523470 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34205.361315 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.234251 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.418210 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 7675.941579 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13703.908999 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2526298 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34200.604162 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.178254 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1943463 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19839349000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.229845 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 580007 # number of overall misses +system.cpu.l2cache.overall_hits 1945328 # number of overall hits +system.cpu.l2cache.overall_miss_latency 19869525000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.229969 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 580970 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17981002000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.229845 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 580007 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 18011335500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.229969 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 580970 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 569254 # number of replacements -system.cpu.l2cache.sampled_refs 588327 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 570217 # number of replacements +system.cpu.l2cache.sampled_refs 589293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 21440.903439 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3151598 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 469235659000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 411363 # number of writebacks -system.cpu.memDep0.conflictingLoads 151128770 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 47539398 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 508224738 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194089353 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 947795380 # number of misc regfile reads -system.cpu.numCycles 1634004079 # number of cpu cycles simulated +system.cpu.l2cache.tagsinuse 21379.850577 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3154731 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 377230361000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 411577 # number of writebacks +system.cpu.memDep0.conflictingLoads 169465698 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40622935 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 454402470 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 170547499 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 909615360 # number of misc regfile reads +system.cpu.numCycles 1396982052 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 11181498 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 7556367 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 8162354 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 430755417 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1988994 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 37 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 6064799926 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2072679155 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1965930252 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1095363349 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 71636028 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 14962968 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 538631225 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 5884693 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 361176398 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2156935 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 61 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4527342452 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1840516856 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1743217369 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 971079353 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 39316255 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11053475 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 315918342 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 168 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 6064799758 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 6110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 566 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 21122292 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 563 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3532180532 # The number of ROB reads -system.cpu.rob.rob_writes 4048956705 # The number of ROB writes -system.cpu.timesIdled 351337 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 4527342284 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 6080 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 557 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 18505861 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 554 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3126877109 # The number of ROB reads +system.cpu.rob.rob_writes 3611419620 # The number of ROB writes +system.cpu.timesIdled 237370 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 70ab31a10..ac3a396e6 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 836ed1519..8c759990e 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 904614 # Simulator instruction rate (inst/s) -host_mem_usage 227300 # Number of bytes of host memory used -host_seconds 1690.21 # Real time elapsed on the host -host_tick_rate 523739013 # Simulator tick rate (ticks/s) +host_inst_rate 2138348 # Simulator instruction rate (inst/s) +host_mem_usage 227776 # Number of bytes of host memory used +host_seconds 715.03 # Real time elapsed on the host +host_tick_rate 1238025751 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 0.885229 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_reads 3724500872 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 9e491e500..881a57025 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:36:47 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 2cd323573..ea3a6a172 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 738382 # Simulator instruction rate (inst/s) -host_mem_usage 235020 # Number of bytes of host memory used -host_seconds 2070.73 # Real time elapsed on the host -host_tick_rate 801036637 # Simulator tick rate (ticks/s) +host_inst_rate 1467057 # Simulator instruction rate (inst/s) +host_mem_usage 235504 # Number of bytes of host memory used +host_seconds 1042.22 # Real time elapsed on the host +host_tick_rate 1591542347 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 1.658730 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_reads 3724500872 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 228e6ab0c..d408e2ee2 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index a0361e843..573c3c43c 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1421831 # Simulator instruction rate (inst/s) -host_mem_usage 223380 # Number of bytes of host memory used -host_seconds 3296.36 # Real time elapsed on the host -host_tick_rate 863379215 # Simulator tick rate (ticks/s) +host_inst_rate 2678815 # Simulator instruction rate (inst/s) +host_mem_usage 223852 # Number of bytes of host memory used +host_seconds 1749.60 # Real time elapsed on the host +host_tick_rate 1626658976 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 2.846007 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 4686862651 # Number of instructions executed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_int_insts 4686862580 # number of integer instructions -system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_reads 12056454713 # number of times the integer registers were read system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 2ae184132..4edb2cc19 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:51 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 21d2dce98..f19e2a330 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 980837 # Simulator instruction rate (inst/s) -host_mem_usage 231100 # Number of bytes of host memory used -host_seconds 4778.43 # Real time elapsed on the host -host_tick_rate 1239642391 # Simulator tick rate (ticks/s) +host_inst_rate 1551749 # Simulator instruction rate (inst/s) +host_mem_usage 231572 # Number of bytes of host memory used +host_seconds 3020.38 # Real time elapsed on the host +host_tick_rate 1961196022 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 5.923548 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 4686862651 # Number of instructions executed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_int_insts 4686862580 # number of integer instructions -system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_reads 12056454713 # number of times the integer registers were read system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index e89403a2f..d93c504a4 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +27,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 127560542500 because target called exit() +122 123 124 Exiting @ tick 114045138500 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 58c1a1259..e6efdadf9 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 87424 # Simulator instruction rate (inst/s) -host_mem_usage 240332 # Number of bytes of host memory used -host_seconds 2532.06 # Real time elapsed on the host -host_tick_rate 50378144 # Simulator tick rate (ticks/s) +host_inst_rate 194147 # Simulator instruction rate (inst/s) +host_mem_usage 240836 # Number of bytes of host memory used +host_seconds 1140.18 # Real time elapsed on the host +host_tick_rate 100023677 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated -sim_seconds 0.127561 # Number of seconds simulated -sim_ticks 127560542500 # Number of ticks simulated +sim_seconds 0.114045 # Number of seconds simulated +sim_ticks 114045138500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 16939138 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 19067543 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 15975516 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 17934192 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3582609 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 19223942 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19223942 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 3581786 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 18022710 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 18022710 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 12326943 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 324452 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 723634 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 243992167 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.907255 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.057266 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 220177428 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.005385 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.254706 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 97637775 40.02% 40.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 102801930 42.13% 82.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 24473335 10.03% 92.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 10688182 4.38% 96.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 6438517 2.64% 99.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 836047 0.34% 99.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 523551 0.21% 99.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 268378 0.11% 99.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 324452 0.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 88641889 40.26% 40.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 86561337 39.31% 79.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 21386723 9.71% 89.29% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 12188145 5.54% 94.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 6588488 2.99% 97.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 2070275 0.94% 98.76% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 1149159 0.52% 99.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 867778 0.39% 99.67% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 723634 0.33% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 243992167 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 220177428 # Number of insts commited each cycle system.cpu.commit.COM:count 221363017 # Number of instructions committed system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,259 +44,259 @@ system.cpu.commit.COM:loads 56649590 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 77165306 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 3582617 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 3581794 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 70151117 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 48027716 # The number of squashed insts skipped by commit system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 1.152501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.152501 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 51727133 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34247.563353 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34193.055556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 51726620 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 17569000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 513 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 153 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 12309500 # number of ReadReq MSHR miss cycles +system.cpu.cpi 1.030390 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.030390 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 50422643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 32842.809365 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34433.615819 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 50422045 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 19640000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 598 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 244 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 12189500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26394.870828 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35294.285714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20510427 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 139972000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5303 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 3728 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 55588500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 26406.061747 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35285.532995 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20510418 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 140269000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000259 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 5312 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 3736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 55610000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1575 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1576 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 37331.807235 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 36752.571503 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 72242863 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27087.517194 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35089.405685 # average overall mshr miss latency -system.cpu.dcache.demand_hits 72237047 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 157541000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000081 # miss rate for demand accesses -system.cpu.dcache.demand_misses 5816 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3881 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 67898000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 70938373 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 27057.360406 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35129.274611 # average overall mshr miss latency +system.cpu.dcache.demand_hits 70932463 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 159909000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000083 # miss rate for demand accesses +system.cpu.dcache.demand_misses 5910 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 3980 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 67799500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1935 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1930 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.336997 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1380.340507 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 72242863 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27087.517194 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35089.405685 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.336507 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1378.331851 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 70938373 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 27057.360406 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35129.274611 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 72237047 # number of overall hits -system.cpu.dcache.overall_miss_latency 157541000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000081 # miss rate for overall accesses -system.cpu.dcache.overall_misses 5816 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3881 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 67898000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 70932463 # number of overall hits +system.cpu.dcache.overall_miss_latency 159909000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000083 # miss rate for overall accesses +system.cpu.dcache.overall_misses 5910 # number of overall misses +system.cpu.dcache.overall_mshr_hits 3980 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 67799500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1935 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1930 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 46 # number of replacements -system.cpu.dcache.sampled_refs 1935 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 47 # number of replacements +system.cpu.dcache.sampled_refs 1930 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1380.340507 # Cycle average of tags in use -system.cpu.dcache.total_refs 72237047 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1378.331851 # Cycle average of tags in use +system.cpu.dcache.total_refs 70932463 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 9 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5656231 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 309852988 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 53029625 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 184220573 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 11003980 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 1085738 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 19223942 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 20440935 # Number of cache lines fetched -system.cpu.fetch.Cycles 196264127 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 182297 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 184675827 # Number of instructions fetch has processed +system.cpu.dcache.writebacks 10 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 1914286 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 286005423 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 48312658 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 169297181 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 7787199 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 653303 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 18022710 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 18867666 # Number of cache lines fetched +system.cpu.fetch.Cycles 179995924 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 191272 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 169328996 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 4455378 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.075352 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 20440935 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 16939138 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.723875 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 254996147 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.239017 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.348981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.SquashCycles 3686154 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.079016 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 18867666 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 15975516 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.742377 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 227964627 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.282286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.366402 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66307953 26.00% 26.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 121646972 47.71% 73.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37731127 14.80% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20479784 8.03% 96.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1948325 0.76% 97.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108960 0.43% 97.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1062530 0.42% 98.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1340 0.00% 98.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4709156 1.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 54957212 24.11% 24.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 110607036 48.52% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 34696842 15.22% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 19348316 8.49% 96.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1875902 0.82% 97.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1062317 0.47% 97.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 939798 0.41% 98.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1341 0.00% 98.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4475863 1.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254996147 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 3212472 # number of floating regfile reads -system.cpu.fp_regfile_writes 2049220 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 20440935 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25661.556820 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22374.875175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 20435488 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 139778500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000266 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 5447 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 440 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 112031000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000245 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 5007 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 227964627 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 3211744 # number of floating regfile reads +system.cpu.fp_regfile_writes 2048533 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 18867666 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 25730.265551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 22379.751901 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 18862168 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 141465000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000291 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 5498 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 111854000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000265 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 4998 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4082.198961 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3774.698419 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 20440935 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25661.556820 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22374.875175 # average overall mshr miss latency -system.cpu.icache.demand_hits 20435488 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 139778500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000266 # miss rate for demand accesses -system.cpu.icache.demand_misses 5447 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 440 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 112031000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000245 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 5007 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 18867666 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 25730.265551 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 22379.751901 # average overall mshr miss latency +system.cpu.icache.demand_hits 18862168 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 141465000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000291 # miss rate for demand accesses +system.cpu.icache.demand_misses 5498 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 111854000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000265 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 4998 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.746987 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1529.828433 # Average occupied blocks per context -system.cpu.icache.overall_accesses 20440935 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25661.556820 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22374.875175 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.745890 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1527.583314 # Average occupied blocks per context +system.cpu.icache.overall_accesses 18867666 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 25730.265551 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 22379.751901 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 20435488 # number of overall hits -system.cpu.icache.overall_miss_latency 139778500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000266 # miss rate for overall accesses -system.cpu.icache.overall_misses 5447 # number of overall misses -system.cpu.icache.overall_mshr_hits 440 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 112031000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000245 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 5007 # number of overall MSHR misses +system.cpu.icache.overall_hits 18862168 # number of overall hits +system.cpu.icache.overall_miss_latency 141465000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000291 # miss rate for overall accesses +system.cpu.icache.overall_misses 5498 # number of overall misses +system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 111854000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000265 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 4998 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 3101 # number of replacements -system.cpu.icache.sampled_refs 5006 # Sample count of references to valid blocks. +system.cpu.icache.replacements 3094 # number of replacements +system.cpu.icache.sampled_refs 4997 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1529.828433 # Cycle average of tags in use -system.cpu.icache.total_refs 20435488 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1527.583314 # Cycle average of tags in use +system.cpu.icache.total_refs 18862168 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 124939 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 13366188 # Number of branches executed +system.cpu.idleCycles 125651 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 13177188 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.954963 # Inst execution rate -system.cpu.iew.EXEC:refs 84717237 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 21535662 # Number of stores executed +system.cpu.iew.EXEC:rate 1.062789 # Inst execution rate +system.cpu.iew.EXEC:refs 86183722 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 21962366 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 389337537 # num instructions consuming a value -system.cpu.iew.WB:count 241459353 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.499412 # average fanout of values written-back +system.cpu.iew.WB:consumers 309612264 # num instructions consuming a value +system.cpu.iew.WB:count 239588905 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.616985 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 194439848 # num instructions producing a value -system.cpu.iew.WB:rate 0.946450 # insts written-back per cycle -system.cpu.iew.WB:sent 242120517 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3656523 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 214895 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 75869162 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1275 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2489008 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 25600521 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 291514094 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 63181575 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4005104 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 243631219 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 25200 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 191026075 # num instructions producing a value +system.cpu.iew.WB:rate 1.050413 # insts written-back per cycle +system.cpu.iew.WB:sent 240106417 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3659082 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1291 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 69776556 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1273 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2389686 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 24137923 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 269390730 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 64221356 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3582148 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 242411882 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 11003980 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 40028 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 7787199 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 324 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 11103688 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 71380 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 13515418 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 128079 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 879354 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 44904 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 19219572 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 5084805 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 879354 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 151398 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3505125 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 614135119 # number of integer regfile reads -system.cpu.int_regfile_writes 252115460 # number of integer regfile writes -system.cpu.ipc 0.867678 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.867678 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1180294 0.48% 0.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 158353329 63.95% 64.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 64.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 64.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1520272 0.61% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 64587764 26.08% 91.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 21994664 8.88% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 128891 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 44661 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13126966 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3622207 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 128891 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 152659 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3506423 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 508933345 # number of integer regfile reads +system.cpu.int_regfile_writes 250225793 # number of integer regfile writes +system.cpu.ipc 0.970506 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.970506 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1179793 0.48% 0.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 155739742 63.31% 63.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1520188 0.62% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 64.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 65456200 26.61% 91.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 22098107 8.98% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 247636323 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 40899 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000165 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 245994030 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 166267 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.000676 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 4 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available @@ -325,142 +325,142 @@ system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 37912 92.70% 92.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 2987 7.30% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 131346 79.00% 79.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 34917 21.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 254996147 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.971138 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.960460 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 227964627 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.079089 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.987640 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 97493255 38.23% 38.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 86911390 34.08% 72.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 54912481 21.53% 93.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 12234045 4.80% 98.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 3109625 1.22% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 255105 0.10% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 77911 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 2335 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 72171112 31.66% 31.66% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 90119003 39.53% 71.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 46322685 20.32% 91.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 15038489 6.60% 98.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 3583873 1.57% 99.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 613391 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 102303 0.04% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 12243 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 1528 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 7 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 254996147 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.970662 # Inst issue rate -system.cpu.iq.fp_alu_accesses 2542426 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 5084249 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2387245 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 3193021 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 243954502 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 745226741 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 239072108 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 358869082 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 291512819 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 247636323 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 1275 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 69673728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1298 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 182988092 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34364.012739 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31058.917197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 5 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 53951500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.996825 # miss rate for ReadExReq accesses +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 227964627 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.078494 # Inst issue rate +system.cpu.iq.fp_alu_accesses 2547074 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 5090153 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2386799 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 3193028 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 242433430 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 715029059 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 237202106 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 313965679 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 269389457 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 245994030 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 1273 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 47650161 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 258 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 93569764 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 1576 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34382.484076 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31064.649682 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 53980500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.996193 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1570 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48762500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996825 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48771500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996193 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1570 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5367 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34265.528407 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.178098 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1970 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 116400000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.632942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3397 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105426500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.632942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3397 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 9 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 9 # number of Writeback hits +system.cpu.l2cache.ReadReq_accesses 5352 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34258.559622 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.566706 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1964 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 116068000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.633034 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3388 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 105148500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.633034 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3388 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.579412 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.579180 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 6942 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34296.657942 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31042.681699 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1975 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 170351500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.715500 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4967 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 6928 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34297.801533 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31044.776119 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1970 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 170048500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.715647 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4958 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 154189000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.715500 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4967 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 153920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.715647 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4958 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.068086 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.067776 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2231.049035 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.015700 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 6942 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34296.657942 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.681699 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2220.891460 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.016755 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 6928 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34297.801533 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31044.776119 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1975 # number of overall hits -system.cpu.l2cache.overall_miss_latency 170351500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.715500 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4967 # number of overall misses +system.cpu.l2cache.overall_hits 1970 # number of overall hits +system.cpu.l2cache.overall_miss_latency 170048500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.715647 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4958 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 154189000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.715500 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4967 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 153920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.715647 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4958 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3400 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2232.064735 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1970 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2221.908214 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1964 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 21807942 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4495847 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 75869162 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 25600521 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 125958118 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 28553702 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6206376 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 69776556 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 24137923 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 125230087 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.numCycles 255121086 # number of cpu cycles simulated +system.cpu.numCycles 228090278 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 1303093 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 31917 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2662460 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 57579297 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 975892 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 963293874 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 304077108 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 331962025 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 180705413 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 11003980 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4387817 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 97598616 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 7191870 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 956102004 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 16547 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1274 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 8156807 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 1279 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 535181849 # The number of ROB reads -system.cpu.rob.rob_writes 594057529 # The number of ROB writes -system.cpu.timesIdled 2349 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 638720 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 52054674 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 682190 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 755867290 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 280433210 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 305502440 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 166205742 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 7787199 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1869216 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 71139031 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 7184355 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 748682935 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 15879 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1273 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3670415 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 1276 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 488844527 # The number of ROB reads +system.cpu.rob.rob_writes 546568715 # The number of ROB writes +system.cpu.timesIdled 2341 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 3569c883b..98509c55c 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:36:47 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:51 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index da648dcbf..b1d39d4bb 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 777141 # Simulator instruction rate (inst/s) -host_mem_usage 230844 # Number of bytes of host memory used -host_seconds 284.84 # Real time elapsed on the host -host_tick_rate 461282227 # Simulator tick rate (ticks/s) +host_inst_rate 1450024 # Simulator instruction rate (inst/s) +host_mem_usage 231316 # Number of bytes of host memory used +host_seconds 152.66 # Real time elapsed on the host +host_tick_rate 860680554 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.131393 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 221363018 # Number of instructions executed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_int_insts 220339607 # number of integer instructions -system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_reads 587077446 # number of times the integer registers were read system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 31ab1843b..1bc7094fb 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index ebc389a3a..9fa2651f7 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 446836 # Simulator instruction rate (inst/s) -host_mem_usage 238556 # Number of bytes of host memory used -host_seconds 495.40 # Real time elapsed on the host -host_tick_rate 506580174 # Simulator tick rate (ticks/s) +host_inst_rate 935342 # Simulator instruction rate (inst/s) +host_mem_usage 239036 # Number of bytes of host memory used +host_seconds 236.67 # Real time elapsed on the host +host_tick_rate 1060402082 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 221363018 # Number of instructions executed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_int_insts 220339607 # number of integer instructions -system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_reads 587077446 # number of times the integer registers were read system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 0767b9777..ed8d3c506 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! -Exiting @ tick 13766000 because target called exit() +Exiting @ tick 13637500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 182e72d25..805380c67 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 47133 # Simulator instruction rate (inst/s) -host_mem_usage 227692 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 66053082 # Simulator tick rate (ticks/s) +host_inst_rate 74664 # Simulator instruction rate (inst/s) +host_mem_usage 228156 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 103594447 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13766000 # Number of ticks simulated +sim_ticks 13637500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1892 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 715 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1829 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1920 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 1920 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 455 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1876 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 1876 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1214 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 37 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 22 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 15124 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.648572 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.100130 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 15018 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.653150 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.090994 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9612 63.55% 63.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 3088 20.42% 83.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1220 8.07% 92.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 836 5.53% 97.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 232 1.53% 99.10% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 57 0.38% 99.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 30 0.20% 99.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 12 0.08% 99.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 37 0.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 9552 63.60% 63.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 2996 19.95% 83.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 1196 7.96% 91.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 909 6.05% 97.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 244 1.62% 99.19% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 60 0.40% 99.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 31 0.21% 99.80% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 8 0.05% 99.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 22 0.15% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 15018 # Number of insts commited each cycle system.cpu.commit.COM:count 9809 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,256 +44,256 @@ system.cpu.commit.COM:loads 1056 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1990 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 455 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3832 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3810 # The number of squashed insts skipped by commit system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.806912 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.806912 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1244 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37105.263158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35048.387097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1168 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2820000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061093 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 76 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2173000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.049839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 62 # number of ReadReq MSHR misses +system.cpu.cpi 2.780712 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.780712 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1299 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34989.361702 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34992.307692 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1205 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3289000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.072363 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 94 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2274500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.050038 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35775.641026 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35814.102564 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2790500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2793500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.870504 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.859155 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2178 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33913.881748 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1789 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13192500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.178604 # miss rate for demand accesses -system.cpu.dcache.demand_misses 389 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 249 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4963500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.064279 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2233 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33566.339066 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1826 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 13661500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.182266 # miss rate for demand accesses +system.cpu.dcache.demand_misses 407 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 264 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5068000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.064039 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 143 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.020744 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 84.965644 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2178 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33913.881748 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.021266 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 87.104239 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2233 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33566.339066 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1789 # number of overall hits -system.cpu.dcache.overall_miss_latency 13192500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.178604 # miss rate for overall accesses -system.cpu.dcache.overall_misses 389 # number of overall misses -system.cpu.dcache.overall_mshr_hits 249 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4963500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.064279 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 140 # number of overall MSHR misses +system.cpu.dcache.overall_hits 1826 # number of overall hits +system.cpu.dcache.overall_miss_latency 13661500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.182266 # miss rate for overall accesses +system.cpu.dcache.overall_misses 407 # number of overall misses +system.cpu.dcache.overall_mshr_hits 264 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5068000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.064039 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 139 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.965644 # Cycle average of tags in use -system.cpu.dcache.total_refs 1789 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.104239 # Cycle average of tags in use +system.cpu.dcache.total_refs 1826 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 464 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 15304 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 6233 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 8371 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 721 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 56 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1920 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1255 # Number of cache lines fetched -system.cpu.fetch.Cycles 9031 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 8830 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.069735 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1255 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.320706 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15845 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.178869 # Number of instructions fetched each cycle (Total) +system.cpu.decode.DECODE:BlockedCycles 420 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 15296 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 6181 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 8360 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 701 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 57 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 1876 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1264 # Number of cache lines fetched +system.cpu.fetch.Cycles 9026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 121 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 8825 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 464 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.068778 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1264 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 715 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.323545 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.009352 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179835 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 7129 44.99% 44.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4489 28.33% 73.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1878 11.85% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2046 12.91% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 57 0.36% 98.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 227 1.43% 99.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 7007 44.58% 44.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4504 28.65% 73.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1838 11.69% 84.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2072 13.18% 98.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 57 0.36% 98.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 222 1.41% 99.88% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15719 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 2 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 970 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.227092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 285 # number of ReadReq misses +system.cpu.icache.ReadReq_accesses 1264 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 37405.594406 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35046.332046 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 978 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 10698000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.226266 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 286 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 9040500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.205578 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 258 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency 9077000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.204905 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 259 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.759690 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.776062 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1255 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37417.543860 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency -system.cpu.icache.demand_hits 970 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.227092 # miss rate for demand accesses -system.cpu.icache.demand_misses 285 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 1264 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 37405.594406 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency +system.cpu.icache.demand_hits 978 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 10698000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.226266 # miss rate for demand accesses +system.cpu.icache.demand_misses 286 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9040500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.205578 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 258 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 9077000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.204905 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 259 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.061525 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 126.002915 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1255 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37417.543860 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.062320 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 127.631724 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1264 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 37405.594406 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 970 # number of overall hits -system.cpu.icache.overall_miss_latency 10664000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.227092 # miss rate for overall accesses -system.cpu.icache.overall_misses 285 # number of overall misses +system.cpu.icache.overall_hits 978 # number of overall hits +system.cpu.icache.overall_miss_latency 10698000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.226266 # miss rate for overall accesses +system.cpu.icache.overall_misses 286 # number of overall misses system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9040500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.205578 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 258 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 9077000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.204905 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 259 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 258 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 259 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 126.002915 # Cycle average of tags in use -system.cpu.icache.total_refs 970 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 127.631724 # Cycle average of tags in use +system.cpu.icache.total_refs 978 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11688 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1318 # Number of branches executed +system.cpu.idleCycles 11557 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1339 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.434678 # Inst execution rate -system.cpu.iew.EXEC:refs 2353 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1060 # Number of stores executed +system.cpu.iew.EXEC:rate 0.445373 # Inst execution rate +system.cpu.iew.EXEC:refs 2437 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1088 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10358 # num instructions consuming a value -system.cpu.iew.WB:count 11818 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.702935 # average fanout of values written-back +system.cpu.iew.WB:consumers 9392 # num instructions consuming a value +system.cpu.iew.WB:count 11991 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.786095 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7281 # num instructions producing a value -system.cpu.iew.WB:rate 0.429230 # insts written-back per cycle -system.cpu.iew.WB:sent 11866 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 487 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 58 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1535 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 418 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1238 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 13635 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1293 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 536 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 11968 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7383 # num instructions producing a value +system.cpu.iew.WB:rate 0.439617 # insts written-back per cycle +system.cpu.iew.WB:sent 12024 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 40 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1510 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 16 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 13620 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1349 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 556 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 12148 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 701 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 21 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 479 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 304 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 25083 # number of integer regfile reads -system.cpu.int_regfile_writes 11189 # number of integer regfile writes -system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 454 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 296 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 21267 # number of integer regfile reads +system.cpu.int_regfile_writes 11326 # number of integer regfile writes +system.cpu.ipc 0.359620 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.359620 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 10018 80.12% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1360 10.88% 91.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1123 8.98% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 10141 79.83% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 79.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1414 11.13% 90.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1146 9.02% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 12504 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 12704 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000320 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.000315 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available @@ -324,135 +324,136 @@ system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3 75.00% 75.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1 25.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 4 100.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.789145 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.977935 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 15719 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.808194 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.980491 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8160 51.50% 51.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 4079 25.74% 77.24% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 2594 16.37% 93.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 834 5.26% 98.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 157 0.99% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 19 0.12% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 2 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 7896 50.23% 50.23% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 4146 26.38% 76.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 2688 17.10% 93.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 806 5.13% 98.84% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 156 0.99% 99.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 22 0.14% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 15719 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.465757 # Inst issue rate system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 12501 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 40849 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 11816 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 16975 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3342 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5066 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.int_alu_accesses 12701 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 41124 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 11989 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 16903 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 13604 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 12704 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 16 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3282 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4201 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.589744 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.923077 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2690500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.820513 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31358.974359 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2692000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2443500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2446000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 320 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34188.679245 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 324 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34181.677019 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 30998.447205 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 10872000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.993750 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 318 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9859500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993750 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 318 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 11006500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.993827 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 322 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 9981500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993827 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 322 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006309 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006231 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 398 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34248.737374 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 402 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34246.250000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.994975 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 396 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 13698500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995025 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 400 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12303000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.994975 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 396 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12427500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995025 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 400 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.004816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 157.820330 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 398 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34248.737374 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.004917 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 161.123348 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 402 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34246.250000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.994975 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 396 # number of overall misses +system.cpu.l2cache.overall_miss_latency 13698500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995025 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 400 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12303000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.994975 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 396 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12427500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995025 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 400 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 317 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 321 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 157.820330 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 161.123348 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 5334 # number of misc regfile reads -system.cpu.numCycles 27533 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 1510 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1230 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 5444 # number of misc regfile reads +system.cpu.numCycles 27276 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 87 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 6603 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 6548 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 38664 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 14745 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 13787 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8027 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:RenameLookups 33593 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 14729 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 13866 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 8021 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 701 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 105 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4498 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 38648 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 28728 # The number of ROB reads -system.cpu.rob.rob_writes 28005 # The number of ROB writes -system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 33577 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 257 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 19 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 159 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 16 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 28615 # The number of ROB reads +system.cpu.rob.rob_writes 27943 # The number of ROB writes +system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 09f4d0b50..ee83c97b8 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 1dca11ec5..b4b5a17be 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 180423 # Simulator instruction rate (inst/s) -host_mem_usage 219128 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 103433649 # Simulator tick rate (ticks/s) +host_inst_rate 164320 # Simulator instruction rate (inst/s) +host_mem_usage 219604 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 94262580 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 22822 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index a12716c02..6a1d7db8d 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/07/2011 02:32:13 +Real time: Feb/07/2011 20:06:52 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.32 +Virtual_time_in_minutes: 0.00533333 +Virtual_time_in_hours: 8.88889e-05 +Virtual_time_in_days: 3.7037e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 38.6094 -mbytes_total: 231.508 -resident_ratio: 0.16679 +mbytes_resident: 38.6328 +mbytes_total: 231.969 +resident_ratio: 0.16656 ruby_cycles_executed: [ 276485 ] @@ -125,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10950 +page_reclaims: 10987 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index 877c8d9b9..30cafb0c9 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:51 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index b88df01c5..39decc037 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32378 # Simulator instruction rate (inst/s) -host_mem_usage 237068 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 911908 # Simulator tick rate (ticks/s) +host_inst_rate 41724 # Simulator instruction rate (inst/s) +host_mem_usage 237540 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 1174763 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000276 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 22822 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index d6afbecf0..c2fc4cf4c 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 7 2011 20:06:49 +M5 revision 698a266e9195 7937 default qtip regwidthdecstats.patch tip +M5 started Feb 7 2011 20:06:52 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index 0c21882f5..3f9779fa0 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 594010 # Simulator instruction rate (inst/s) -host_mem_usage 226844 # Number of bytes of host memory used +host_inst_rate 498409 # Simulator instruction rate (inst/s) +host_mem_usage 227324 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1712507148 # Simulator tick rate (ticks/s) +host_tick_rate 1439810006 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -208,7 +208,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 22822 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs |