Bus: Split the bus into a non-coherent and coherent bus

This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.

--HG--
rename : src/mem/bus.cc => src/mem/coherent_bus.cc
rename : src/mem/bus.hh => src/mem/coherent_bus.hh
rename : src/mem/bus.cc => src/mem/noncoherent_bus.cc
rename : src/mem/bus.hh => src/mem/noncoherent_bus.hh

30 files changed, 34 insertions, 34 deletions

diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index ea9c37ef9..3e285af77 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -49,7 +49,7 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
-                membus = Bus())
+                membus = CoherentBus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 9876c07b9..0add2158f 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -58,10 +58,10 @@ cpus = [ MemTest() for i in xrange(nb_cores) ]
 # system simulated
 system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
                 physmem = SimpleMemory(),
-                membus = Bus(clock="500GHz", width=16))
+                membus = CoherentBus(clock="500GHz", width=16))
 
 # l2cache & bus
-system.toL2Bus = Bus(clock="500GHz", width=16)
+system.toL2Bus = CoherentBus(clock="500GHz", width=16)
 system.l2c = L2(size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index 68429de04..0bbe9b00a 100644
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -60,7 +60,7 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
-                membus = Bus())
+                membus = CoherentBus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 cpu.connectAllPorts(system.membus)
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 0bc54f0f0..a58bc50ec 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -37,7 +37,7 @@ import ruby_config
 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
 
 for cpu in cpus:
     # create the interrupt controller
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index ee0f29570..2aec2bb1d 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -56,10 +56,10 @@ nb_cores = 4
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, physmem = SimpleMemory(), membus = Bus())
+system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
 
 # l2cache & bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.l2c = L2(size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 8debc7d3d..db8ccdc7b 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -39,7 +39,7 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = ruby_memory,
-                membus = Bus())
+                membus = CoherentBus())
 system.physmem.port = system.membus.master
 # create the interrupt controller
 cpu.createInterruptController()
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 732cd2d43..a10079ab8 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -49,7 +49,7 @@ cpu.clock = '2GHz'
 
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
-                membus = Bus())
+                membus = CoherentBus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index 0b8b9381f..2d3019daf 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -92,7 +92,7 @@ system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index 77cd1319f..f0d168c1a 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -94,7 +94,7 @@ system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index fbe6b4c4f..4347b78d3 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -90,7 +90,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py
index c07c2ca9e..b263adee0 100644
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -83,7 +83,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 71b4f06dd..e6ca2d7bd 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -77,7 +77,7 @@ system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index db64ccc60..e231df9f2 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -74,7 +74,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index eef5e90c5..e3a73305c 100644
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -77,7 +77,7 @@ system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 0544c98b6..fdfac1cc6 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -76,7 +76,7 @@ system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index edc2b7a95..825b67d05 100644
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -77,7 +77,7 @@ system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 6e539624b..786b42e20 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -74,7 +74,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/simple-atomic-dummychecker.py b/tests/configs/simple-atomic-dummychecker.py
index 2e672924d..5192afb1c 100644
--- a/tests/configs/simple-atomic-dummychecker.py
+++ b/tests/configs/simple-atomic-dummychecker.py
@@ -40,7 +40,7 @@ from m5.objects import *
 
 system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 physmem = SimpleMemory(),
-                membus = Bus())
+                membus = CoherentBus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 system.cpu.addCheckerCpu()
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index a9ee3c4d0..50d3349dd 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -37,7 +37,7 @@ import ruby_config
 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
 
 # add L1 caches
 for cpu in cpus:
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index af9f3bc09..8161a93f2 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -57,10 +57,10 @@ cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 # system simulated
 system = System(cpu = cpus,
                 physmem = SimpleMemory(range = AddrRange('1024MB')),
-                membus = Bus())
+                membus = CoherentBus())
 
 # l2cache & bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.l2c = L2(size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index b1aa31d80..3b81d9769 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -31,7 +31,7 @@ from m5.objects import *
 
 system = System(cpu = AtomicSimpleCPU(cpu_id=0),
                 physmem = SimpleMemory(),
-                membus = Bus())
+                membus = CoherentBus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 5bb0194aa..2a4075624 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -55,10 +55,10 @@ nb_cores = 4
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, physmem = SimpleMemory(), membus = Bus())
+system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
 
 # l2cache & bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.l2c = L2(size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 5269f4127..33d03f6cf 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -45,7 +45,7 @@ cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
                               MyCache(size = '2MB', latency='10ns'))
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
-                membus = Bus())
+                membus = CoherentBus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
 # create the interrupt controller
diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index 41df45fab..6435e5a78 100644
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -78,7 +78,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index d50a45b07..c4e69266d 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -75,7 +75,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index c5a3236a5..dba8f9dd3 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -75,7 +75,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 57672b0e1..90f6c7f0b 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -77,7 +77,7 @@ system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 8a03760e3..5065f3346 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -77,7 +77,7 @@ system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 1b905a8d0..c9bcc59c7 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -77,7 +77,7 @@ system.iocache.mem_side = system.membus.slave
 
 system.cpu = cpus
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index e4920ddf4..eb62b20d8 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -75,7 +75,7 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 
 system.cpu = cpu
 #create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
 system.iocache = IOCache()
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave