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authorAndreas Hansson <andreas.hansson@arm.com>2014-09-20 17:18:33 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-09-20 17:18:33 -0400
commit2b0438a11eb6a9640b06da91e8a300d0ac3ad81a (patch)
treeb90e573355fa96faad69371f12394c749d9db13d /tests
parent1f6d5f8f849f50a3646f586b1274708537124ef3 (diff)
downloadgem5-2b0438a11eb6a9640b06da91e8a300d0ac3ad81a.tar.xz
tests: Use more representative configs for ARM tests
This patch changes the CPU and cache configurations used in the ARM SE and FS regressions to make them more representative, and also get better code coverage by exercising different replacement policies and use an L2 prefetcher.
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/arm_generic.py26
-rw-r--r--tests/configs/o3-timing.py14
2 files changed, 37 insertions, 3 deletions
diff --git a/tests/configs/arm_generic.py b/tests/configs/arm_generic.py
index ada49ba97..b880919e6 100644
--- a/tests/configs/arm_generic.py
+++ b/tests/configs/arm_generic.py
@@ -43,6 +43,25 @@ m5.util.addToPath('../configs/common')
import FSConfig
from Caches import *
from base_config import *
+from O3_ARM_v7a import *
+
+class ArmSESystemUniprocessor(BaseSESystemUniprocessor):
+ """Syscall-emulation builder for ARM uniprocessor systems.
+
+ A small tweak of the syscall-emulation builder to use more
+ representative cache configurations.
+ """
+
+ def __init__(self, **kwargs):
+ BaseSESystem.__init__(self, **kwargs)
+
+ def create_caches_private(self, cpu):
+ # The atomic SE configurations do not use caches
+ if self.mem_mode == "timing":
+ # Use the more representative cache configuration
+ cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
+ O3_ARM_v7a_DCache(),
+ O3_ARM_v7aL2())
class LinuxArmSystemBuilder(object):
"""Mix-in that implements create_system.
@@ -87,6 +106,12 @@ class LinuxArmFSSystem(LinuxArmSystemBuilder,
BaseSystem.__init__(self, **kwargs)
LinuxArmSystemBuilder.__init__(self, machine_type)
+ def create_caches_private(self, cpu):
+ # Use the more representative cache configuration
+ cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
+ O3_ARM_v7a_DCache(),
+ O3_ARM_v7aL2())
+
class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder,
BaseFSSystemUniprocessor):
"""Basic ARM full system builder for uniprocessor systems.
@@ -100,7 +125,6 @@ class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder,
BaseFSSystemUniprocessor.__init__(self, **kwargs)
LinuxArmSystemBuilder.__init__(self, machine_type)
-
class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo):
"""Uniprocessor ARM system prepared for CPU switching"""
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 2f9ea52c2..7aa4793ac 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -39,7 +39,17 @@
# Authors: Andreas Hansson
from m5.objects import *
+from m5.defines import buildEnv
from base_config import *
+from arm_generic import *
+from O3_ARM_v7a import O3_ARM_v7a_3
-root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
- cpu_class=DerivO3CPU).create_root()
+# If we are running ARM regressions, use a more sensible CPU
+# configuration. This makes the results more meaningful, and also
+# increases the coverage of the regressions.
+if buildEnv['TARGET_ISA'] == "arm":
+ root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+ cpu_class=O3_ARM_v7a_3).create_root()
+else:
+ root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+ cpu_class=DerivO3CPU).create_root()