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authorSteve Reinhardt <stever@gmail.com>2014-05-12 17:22:17 -0400
committerSteve Reinhardt <stever@gmail.com>2014-05-12 17:22:17 -0400
commit72403cb59561a37d42e5b5bc4b0499ddaf9012cf (patch)
treecdcbda23c81414783fb9482c30d1b63c4511225c /tests
parent2136feaa55af60d407fe51df5309494dd9c374fb (diff)
downloadgem5-72403cb59561a37d42e5b5bc4b0499ddaf9012cf.tar.xz
tests: update t1000 & pc-switcheroo-full stats
committed reference config.json files too
Diffstat (limited to 'tests')
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini38
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json2374
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout8
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt124
-rw-r--r--tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal2
-rw-r--r--tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini52
-rw-r--r--tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json717
-rwxr-xr-xtests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr2
-rwxr-xr-xtests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout8
-rw-r--r--tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt109
10 files changed, 3308 insertions, 126 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
index 42cb40700..42bed7716 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -20,13 +20,14 @@ eventq_index=0
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
+load_offset=0
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-readfile=tests/halt.sh
+readfile=/z/stever/hg/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
@@ -88,6 +89,7 @@ voltage_domain=system.voltage_domain
[system.cpu0]
type=AtomicSimpleCPU
children=apic_clk_domain dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
@@ -115,6 +117,7 @@ simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
+socket_id=0
switched_out=false
system=system
tracer=system.cpu0.tracer
@@ -252,6 +255,7 @@ eventq_index=0
[system.cpu1]
type=TimingSimpleCPU
children=dtb isa itb tracer
+branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
@@ -273,6 +277,7 @@ numThreads=1
profile=0
progress_interval=0
simpoint_start_insts=
+socket_id=0
switched_out=true
system=system
tracer=system.cpu1.tracer
@@ -390,6 +395,7 @@ smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=true
@@ -1591,7 +1597,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@@ -1614,7 +1620,7 @@ table_size=65536
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
@@ -1803,9 +1809,9 @@ system=system
pio=system.iobus.master[9]
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
@@ -1816,27 +1822,33 @@ device_rowbuffer_size=1024
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[3]
[system.smbios_table]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
new file mode 100644
index 000000000..4aa2b2aae
--- /dev/null
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json
@@ -0,0 +1,2374 @@
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "bridge": {
+ "slave": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "name": "bridge",
+ "req_size": 16,
+ "delay": 5.0000000000000004e-08,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.iobus.slave[0]",
+ "role": "MASTER"
+ },
+ "cxx_class": "Bridge",
+ "path": "system.bridge",
+ "resp_size": 16,
+ "type": "Bridge"
+ },
+ "l2c": {
+ "assoc": 8,
+ "mem_side": {
+ "peer": "system.membus.slave[2]",
+ "role": "MASTER"
+ },
+ "cpu_side": {
+ "peer": "system.toL2Bus.master[0]",
+ "role": "SLAVE"
+ },
+ "name": "l2c",
+ "tags": {
+ "name": "tags",
+ "eventq_index": 0,
+ "hit_latency": 20,
+ "sequential_access": false,
+ "assoc": 8,
+ "cxx_class": "LRU",
+ "path": "system.l2c.tags",
+ "block_size": 64,
+ "type": "LRU",
+ "size": 4194304
+ },
+ "hit_latency": 20,
+ "mshrs": 20,
+ "response_latency": 20,
+ "is_top_level": false,
+ "tgts_per_mshr": 12,
+ "sequential_access": false,
+ "max_miss_count": 0,
+ "eventq_index": 0,
+ "prefetch_on_access": false,
+ "cxx_class": "BaseCache",
+ "path": "system.l2c",
+ "write_buffers": 8,
+ "two_queue": false,
+ "type": "BaseCache",
+ "forward_snoops": true,
+ "size": 4194304
+ },
+ "acpi_description_table_pointer": {
+ "name": "acpi_description_table_pointer",
+ "xsdt": {
+ "name": "xsdt",
+ "creator_revision": 0,
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::ACPI::XSDT",
+ "path": "system.acpi_description_table_pointer.xsdt",
+ "oem_revision": 0,
+ "type": "X86ACPIXSDT"
+ },
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::ACPI::RSDP",
+ "path": "system.acpi_description_table_pointer",
+ "type": "X86ACPIRSDP",
+ "revision": 2
+ },
+ "membus": {
+ "slave": {
+ "peer": [
+ "system.apicbridge.master",
+ "system.system_port",
+ "system.l2c.mem_side",
+ "system.cpu0.interrupts.int_master",
+ "system.iocache.mem_side"
+ ],
+ "role": "SLAVE"
+ },
+ "name": "membus",
+ "badaddr_responder": {
+ "ret_data8": 255,
+ "name": "badaddr_responder",
+ "pio": {
+ "peer": "system.membus.default",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": true,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": false,
+ "ret_data64": 18446744073709551615,
+ "cxx_class": "IsaFake",
+ "path": "system.membus.badaddr_responder",
+ "pio_addr": 0,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "default": {
+ "peer": "system.membus.badaddr_responder.pio",
+ "role": "MASTER"
+ },
+ "header_cycles": 1,
+ "width": 8,
+ "eventq_index": 0,
+ "master": {
+ "peer": [
+ "system.bridge.slave",
+ "system.cpu0.interrupts.pio",
+ "system.cpu0.interrupts.int_slave",
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "cxx_class": "CoherentBus",
+ "path": "system.membus",
+ "type": "CoherentBus",
+ "use_default_range": false
+ },
+ "iobus": {
+ "slave": {
+ "peer": [
+ "system.bridge.master",
+ "system.pc.south_bridge.ide.dma",
+ "system.pc.south_bridge.io_apic.int_master"
+ ],
+ "role": "SLAVE"
+ },
+ "name": "iobus",
+ "default": {
+ "peer": "system.pc.pciconfig.pio",
+ "role": "MASTER"
+ },
+ "header_cycles": 1,
+ "width": 8,
+ "eventq_index": 0,
+ "master": {
+ "peer": [
+ "system.apicbridge.slave",
+ "system.pc.south_bridge.cmos.pio",
+ "system.pc.south_bridge.dma1.pio",
+ "system.pc.south_bridge.ide.pio",
+ "system.pc.south_bridge.ide.config",
+ "system.pc.south_bridge.keyboard.pio",
+ "system.pc.south_bridge.pic1.pio",
+ "system.pc.south_bridge.pic2.pio",
+ "system.pc.south_bridge.pit.pio",
+ "system.pc.south_bridge.speaker.pio",
+ "system.pc.south_bridge.io_apic.pio",
+ "system.pc.i_dont_exist.pio",
+ "system.pc.behind_pci.pio",
+ "system.pc.com_1.pio",
+ "system.pc.fake_com_2.pio",
+ "system.pc.fake_com_3.pio",
+ "system.pc.fake_com_4.pio",
+ "system.pc.fake_floppy.pio",
+ "system.iocache.cpu_side"
+ ],
+ "role": "MASTER"
+ },
+ "cxx_class": "NoncoherentBus",
+ "path": "system.iobus",
+ "type": "NoncoherentBus",
+ "use_default_range": true
+ },
+ "physmem": [
+ {
+ "static_frontend_latency": 1e-08,
+ "tRFC": 2.6e-07,
+ "activation_limit": 4,
+ "tWTR": 7.500000000000001e-09,
+ "write_low_thresh_perc": 50,
+ "channels": 1,
+ "write_buffer_size": 64,
+ "device_bus_width": 8,
+ "write_high_thresh_perc": 85,
+ "cxx_class": "DRAMCtrl",
+ "null": false,
+ "port": {
+ "peer": "system.membus.master[3]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true,
+ "tRRD": 6.000000000000001e-09,
+ "tRTW": 2.5e-09,
+ "max_accesses_per_row": 16,
+ "burst_length": 8,
+ "tRTP": 7.500000000000001e-09,
+ "tWR": 1.5000000000000002e-08,
+ "eventq_index": 0,
+ "static_backend_latency": 1e-08,
+ "banks_per_rank": 8,
+ "addr_mapping": "RoRaBaChCo",
+ "tRCD": 1.375e-08,
+ "type": "DRAMCtrl",
+ "min_writes_per_switch": 16,
+ "ranks_per_channel": 2,
+ "page_policy": "open_adaptive",
+ "tCL": 1.375e-08,
+ "read_buffer_size": 32,
+ "conf_table_reported": true,
+ "tCK": 1.25e-09,
+ "tRAS": 3.5e-08,
+ "tBURST": 5e-09,
+ "path": "system.physmem",
+ "devices_per_rank": 8,
+ "name": "physmem",
+ "tXAW": 3.0000000000000004e-08,
+ "tREFI": 7.8e-06,
+ "mem_sched_policy": "frfcfs",
+ "tRP": 1.375e-08,
+ "device_rowbuffer_size": 1024
+ }
+ ],
+ "apicbridge": {
+ "slave": {
+ "peer": "system.iobus.master[0]",
+ "role": "SLAVE"
+ },
+ "name": "apicbridge",
+ "req_size": 16,
+ "delay": 5.0000000000000004e-08,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "cxx_class": "Bridge",
+ "path": "system.apicbridge",
+ "resp_size": 16,
+ "type": "Bridge"
+ },
+ "intel_mp_table": {
+ "oem_table_addr": 0,
+ "name": "intel_mp_table",
+ "ext_entries": [
+ {
+ "parent_bus": 1,
+ "name": "ext_entries",
+ "type": "X86IntelMPBusHierarchy",
+ "subtractive_decode": true,
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::IntelMP::BusHierarchy",
+ "path": "system.intel_mp_table.ext_entries",
+ "bus_id": 0
+ }
+ ],
+ "spec_rev": 4,
+ "eventq_index": 0,
+ "base_entries": [
+ {
+ "enable": true,
+ "local_apic_version": 20,
+ "name": "base_entries00",
+ "family": 0,
+ "local_apic_id": 0,
+ "bootstrap": true,
+ "feature_flags": 0,
+ "eventq_index": 0,
+ "stepping": 0,
+ "cxx_class": "X86ISA::IntelMP::Processor",
+ "path": "system.intel_mp_table.base_entries00",
+ "model": 0,
+ "type": "X86IntelMPProcessor"
+ },
+ {
+ "enable": true,
+ "name": "base_entries01",
+ "cxx_class": "X86ISA::IntelMP::IOAPIC",
+ "version": 17,
+ "eventq_index": 0,
+ "address": 4273995776,
+ "path": "system.intel_mp_table.base_entries01",
+ "type": "X86IntelMPIOAPIC",
+ "id": 1
+ },
+ {
+ "name": "base_entries02",
+ "type": "X86IntelMPBus",
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::IntelMP::Bus",
+ "path": "system.intel_mp_table.base_entries02",
+ "bus_id": 0
+ },
+ {
+ "name": "base_entries03",
+ "type": "X86IntelMPBus",
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::IntelMP::Bus",
+ "path": "system.intel_mp_table.base_entries03",
+ "bus_id": 1
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries04",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 1,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 16,
+ "path": "system.intel_mp_table.base_entries04",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 16
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries05",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries05",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 0
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries06",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 2,
+ "path": "system.intel_mp_table.base_entries06",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 0
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries07",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries07",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 1
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries08",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 1,
+ "path": "system.intel_mp_table.base_entries08",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 1
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries09",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries09",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 3
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries10",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 3,
+ "path": "system.intel_mp_table.base_entries10",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 3
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries11",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries11",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 4
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries12",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 4,
+ "path": "system.intel_mp_table.base_entries12",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 4
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries13",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries13",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 5
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries14",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 5,
+ "path": "system.intel_mp_table.base_entries14",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 5
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries15",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries15",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 6
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries16",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 6,
+ "path": "system.intel_mp_table.base_entries16",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 6
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries17",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries17",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 7
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries18",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 7,
+ "path": "system.intel_mp_table.base_entries18",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 7
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries19",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries19",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 8
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries20",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
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+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 8,
+ "path": "system.intel_mp_table.base_entries20",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 8
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries21",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries21",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 9
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries22",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 9,
+ "path": "system.intel_mp_table.base_entries22",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 9
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries23",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
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+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries23",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 10
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries24",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
+ "eventq_index": 0,
+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 10,
+ "path": "system.intel_mp_table.base_entries24",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 10
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries25",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
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+ "source_bus_id": 0,
+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
+ "dest_io_apic_intin": 0,
+ "path": "system.intel_mp_table.base_entries25",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 11
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries26",
+ "interrupt_type": "INT",
+ "trigger": "ConformTrigger",
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+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
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+ "path": "system.intel_mp_table.base_entries26",
+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 11
+ },
+ {
+ "polarity": "ConformPolarity",
+ "dest_io_apic_id": 1,
+ "name": "base_entries27",
+ "interrupt_type": "ExtInt",
+ "trigger": "ConformTrigger",
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+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 12
+ },
+ {
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+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 12
+ },
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+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 13
+ },
+ {
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+ "path": "system.intel_mp_table.base_entries30",
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+ "source_bus_irq": 13
+ },
+ {
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+ "type": "X86IntelMPIOIntAssignment",
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+ },
+ {
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+ "cxx_class": "X86ISA::IntelMP::IOIntAssignment",
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+ "type": "X86IntelMPIOIntAssignment",
+ "source_bus_irq": 14
+ }
+ ],
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+ "path": "system.clk_domain",
+ "type": "SrcClockDomain"
+ },
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+ "name": "fake_com_4",
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+ "role": "SLAVE"
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+ "cxx_class": "IsaFake",
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+ "type": "IsaFake",
+ "ret_data16": 65535
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+ "type": "PciConfigAll",
+ "size": 16777216
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+ "name": "fake_com_2",
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+ "cxx_class": "X86ISA::IntSinkPin",
+ "path": "system.pc.south_bridge.int_lines1.sink",
+ "type": "X86IntSinkPin"
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+ "path": "system.pc.south_bridge.int_lines1",
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+ "path": "system.pc.south_bridge.int_lines2.sink",
+ "type": "X86IntSinkPin"
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+ "type": "X86IntLine"
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+ "cxx_class": "X86ISA::IntSinkPin",
+ "path": "system.pc.south_bridge.int_lines3.sink",
+ "type": "X86IntSinkPin"
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+ "cxx_class": "X86ISA::IntLine",
+ "path": "system.pc.south_bridge.int_lines3",
+ "type": "X86IntLine"
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+ "cxx_class": "X86ISA::IntSinkPin",
+ "path": "system.pc.south_bridge.int_lines4.sink",
+ "type": "X86IntSinkPin"
+ },
+ "cxx_class": "X86ISA::IntLine",
+ "path": "system.pc.south_bridge.int_lines4",
+ "type": "X86IntLine"
+ },
+ {
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+ "cxx_class": "X86ISA::IntSinkPin",
+ "path": "system.pc.south_bridge.int_lines5.sink",
+ "type": "X86IntSinkPin"
+ },
+ "cxx_class": "X86ISA::IntLine",
+ "path": "system.pc.south_bridge.int_lines5",
+ "type": "X86IntLine"
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+ {
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+ "cxx_class": "X86ISA::IntSinkPin",
+ "path": "system.pc.south_bridge.int_lines6.sink",
+ "type": "X86IntSinkPin"
+ },
+ "cxx_class": "X86ISA::IntLine",
+ "path": "system.pc.south_bridge.int_lines6",
+ "type": "X86IntLine"
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+ "name": "south_bridge",
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+ "path": "system.pc.south_bridge.speaker",
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+ "type": "PcSpeaker"
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+ "name": "keyboard",
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+ "role": "SLAVE"
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+ "mouse_int_pin": {
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+ "path": "system.pc.south_bridge.keyboard.mouse_int_pin",
+ "type": "X86IntSourcePin",
+ "name": "mouse_int_pin",
+ "cxx_class": "X86ISA::IntSourcePin"
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+ "pio_latency": 1.0000000000000001e-07,
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+ "path": "system.pc.south_bridge.keyboard.keyboard_int_pin",
+ "type": "X86IntSourcePin",
+ "name": "keyboard_int_pin",
+ "cxx_class": "X86ISA::IntSourcePin"
+ },
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::I8042",
+ "path": "system.pc.south_bridge.keyboard",
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+ "type": "I8042"
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+ "role": "SLAVE"
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+ "int_pin": {
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+ "path": "system.pc.south_bridge.pit.int_pin",
+ "type": "X86IntSourcePin",
+ "name": "int_pin",
+ "cxx_class": "X86ISA::IntSourcePin"
+ },
+ "pio_latency": 1.0000000000000001e-07,
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+ "cxx_class": "X86ISA::I8254",
+ "path": "system.pc.south_bridge.pit",
+ "pio_addr": 9223372036854775872,
+ "type": "I8254"
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+ "io_apic": {
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+ "role": "MASTER"
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+ "name": "io_apic",
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+ "cxx_class": "X86ISA::I82094AA",
+ "path": "system.pc.south_bridge.io_apic",
+ "pio_addr": 4273995776,
+ "type": "I82094AA"
+ },
+ "pic1": {
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+ "path": "system.pc.south_bridge.pic1.output",
+ "type": "X86IntSourcePin",
+ "name": "output",
+ "cxx_class": "X86ISA::IntSourcePin"
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+ "mode": "I8259Master",
+ "cxx_class": "X86ISA::I8259",
+ "path": "system.pc.south_bridge.pic1",
+ "pio_addr": 9223372036854775840,
+ "type": "I8259"
+ },
+ "pic2": {
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+ "output": {
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+ "path": "system.pc.south_bridge.pic2.output",
+ "type": "X86IntSourcePin",
+ "name": "output",
+ "cxx_class": "X86ISA::IntSourcePin"
+ },
+ "pio": {
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+ "role": "SLAVE"
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+ "mode": "I8259Slave",
+ "cxx_class": "X86ISA::I8259",
+ "path": "system.pc.south_bridge.pic2",
+ "pio_addr": 9223372036854775968,
+ "type": "I8259"
+ },
+ "dma1": {
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+ "pio": {
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+ },
+ "pio_latency": 1.0000000000000001e-07,
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+ "cxx_class": "X86ISA::I8237",
+ "path": "system.pc.south_bridge.dma1",
+ "pio_addr": 9223372036854775808,
+ "type": "I8237"
+ },
+ "eventq_index": 0,
+ "cxx_class": "SouthBridge",
+ "path": "system.pc.south_bridge",
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+ "InterruptPin": 1,
+ "HeaderType": 0,
+ "VendorID": 32902,
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+ "MSIXCAPCapId": 0,
+ "BAR3Size": 3,
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+ "BAR4": 1,
+ "BAR1": 1012,
+ "BAR0": 496,
+ "BAR3": 884,
+ "BAR2": 368,
+ "BAR5": 1,
+ "PXCAPDevStatus": 0,
+ "disks": [
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+ "name": "disks0",
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+ "name": "image",
+ "child": {
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+ "name": "child",
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+ "cxx_class": "RawDiskImage",
+ "path": "system.pc.south_bridge.ide.disks0.image.child",
+ "type": "RawDiskImage"
+ },
+ "eventq_index": 0,
+ "cxx_class": "CowDiskImage",
+ "path": "system.pc.south_bridge.ide.disks0.image",
+ "table_size": 65536,
+ "type": "CowDiskImage"
+ },
+ "delay": 1e-06,
+ "eventq_index": 0,
+ "cxx_class": "IdeDisk",
+ "path": "system.pc.south_bridge.ide.disks0",
+ "type": "IdeDisk"
+ },
+ {
+ "driveID": "master",
+ "name": "disks1",
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+ "name": "image",
+ "child": {
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+ "name": "child",
+ "eventq_index": 0,
+ "cxx_class": "RawDiskImage",
+ "path": "system.pc.south_bridge.ide.disks1.image.child",
+ "type": "RawDiskImage"
+ },
+ "eventq_index": 0,
+ "cxx_class": "CowDiskImage",
+ "path": "system.pc.south_bridge.ide.disks1.image",
+ "table_size": 65536,
+ "type": "CowDiskImage"
+ },
+ "delay": 1e-06,
+ "eventq_index": 0,
+ "cxx_class": "IdeDisk",
+ "path": "system.pc.south_bridge.ide.disks1",
+ "type": "IdeDisk"
+ }
+ ],
+ "BAR2Size": 8,
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+ "ExpansionROM": 0,
+ "MSICAPMsgCtrl": 0,
+ "BAR5Size": 0,
+ "CardbusCIS": 0,
+ "MSIXPbaOffset": 0,
+ "MSICAPBaseOffset": 0,
+ "MaximumLatency": 0,
+ "BAR2LegacyIO": true,
+ "LatencyTimer": 0,
+ "BAR4LegacyIO": false,
+ "PXCAPLinkStatus": 0,
+ "PXCAPDevCap2": 0,
+ "PXCAPDevCtrl": 0,
+ "MSICAPMaskBits": 0,
+ "Command": 0,
+ "SubClassCode": 1,
+ "pci_func": 0,
+ "BAR5LegacyIO": false,
+ "MSICAPMsgData": 0,
+ "BIST": 0,
+ "PXCAPDevCtrl2": 0,
+ "pci_bus": 0,
+ "InterruptLine": 14,
+ "MSICAPMsgAddr": 0,
+ "BAR3LegacyIO": true,
+ "BAR4Size": 16,
+ "path": "system.pc.south_bridge.ide",
+ "MinimumGrant": 0,
+ "Status": 640,
+ "BAR0Size": 8,
+ "name": "ide",
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+ "eventq_index": 0,
+ "type": "IdeController",
+ "ctrl_offset": 0,
+ "PXCAPBaseOffset": 0,
+ "DeviceID": 28945,
+ "io_shift": 0,
+ "CacheLineSize": 0,
+ "dma": {
+ "peer": "system.iobus.slave[1]",
+ "role": "MASTER"
+ },
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+ "config_latency": 2e-08,
+ "BAR1Size": 3,
+ "pio": {
+ "peer": "system.iobus.master[3]",
+ "role": "SLAVE"
+ },
+ "pci_dev": 4,
+ "PMCAPCtrlStatus": 0,
+ "cxx_class": "IdeController",
+ "SubsystemVendorID": 0,
+ "PMCAPBaseOffset": 0,
+ "config": {
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+ "role": "SLAVE"
+ },
+ "MSICAPPendingBits": 0,
+ "MSIXTableOffset": 0,
+ "MSICAPMsgUpperAddr": 0,
+ "MSICAPCapId": 0,
+ "BAR0LegacyIO": true,
+ "ProgIF": 128,
+ "BAR1LegacyIO": true,
+ "PMCAPCapabilities": 0,
+ "ClassCode": 1
+ },
+ "type": "SouthBridge",
+ "cmos": {
+ "name": "cmos",
+ "pio": {
+ "peer": "system.iobus.master[1]",
+ "role": "SLAVE"
+ },
+ "int_pin": {
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+ "path": "system.pc.south_bridge.cmos.int_pin",
+ "type": "X86IntSourcePin",
+ "name": "int_pin",
+ "cxx_class": "X86ISA::IntSourcePin"
+ },
+ "time": "Sun Jan 1 00:00:00 2012",
+ "pio_latency": 1.0000000000000001e-07,
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::Cmos",
+ "path": "system.pc.south_bridge.cmos",
+ "pio_addr": 9223372036854775920,
+ "type": "Cmos"
+ }
+ },
+ "fake_floppy": {
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+ "name": "fake_floppy",
+ "pio": {
+ "peer": "system.iobus.master[17]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
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+ "ret_data64": 18446744073709551615,
+ "cxx_class": "IsaFake",
+ "path": "system.pc.fake_floppy",
+ "pio_addr": 9223372036854776818,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "com_1": {
+ "name": "com_1",
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+ "peer": "system.iobus.master[13]",
+ "role": "SLAVE"
+ },
+ "pio_latency": 1.0000000000000001e-07,
+ "terminal": {
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+ "output": true,
+ "number": 0,
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+ "path": "system.pc.com_1.terminal",
+ "type": "Terminal",
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+ "type": "Uart8250"
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+ "path": "system.pc",
+ "behind_pci": {
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+ "name": "behind_pci",
+ "pio": {
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+ "role": "SLAVE"
+ },
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+ "cxx_class": "IsaFake",
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+ "type": "IsaFake",
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+ },
+ "type": "Pc",
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+ "name": "i_dont_exist",
+ "pio": {
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+ "role": "SLAVE"
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+ "type": "IsaFake",
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+ },
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+ "name": "fake_com_3",
+ "pio": {
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+ "role": "SLAVE"
+ },
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+ "cxx_class": "IsaFake",
+ "path": "system.pc.fake_com_3",
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+ "type": "IsaFake",
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+ "path": "system.smbios_table",
+ "type": "X86SMBiosSMBiosTable"
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+ "type": "SrcClockDomain"
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+ "opLat": 4,
+ "name": "opList0",
+ "eventq_index": 0,
+ "opClass": "FloatMult",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList3.opList0",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 12,
+ "opLat": 12,
+ "name": "opList1",
+ "eventq_index": 0,
+ "opClass": "FloatDiv",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList3.opList1",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 24,
+ "opLat": 24,
+ "name": "opList2",
+ "eventq_index": 0,
+ "opClass": "FloatSqrt",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList3.opList2",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList3",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu2.fuPool.FUList3",
+ "type": "FUDesc"
+ },
+ {
+ "count": 0,
+ "opList": [
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList",
+ "eventq_index": 0,
+ "opClass": "MemRead",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList4.opList",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList4",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu2.fuPool.FUList4",
+ "type": "FUDesc"
+ },
+ {
+ "count": 4,
+ "opList": [
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList00",
+ "eventq_index": 0,
+ "opClass": "SimdAdd",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList00",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList01",
+ "eventq_index": 0,
+ "opClass": "SimdAddAcc",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList01",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList02",
+ "eventq_index": 0,
+ "opClass": "SimdAlu",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList02",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList03",
+ "eventq_index": 0,
+ "opClass": "SimdCmp",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList03",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList04",
+ "eventq_index": 0,
+ "opClass": "SimdCvt",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList04",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList05",
+ "eventq_index": 0,
+ "opClass": "SimdMisc",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList05",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList06",
+ "eventq_index": 0,
+ "opClass": "SimdMult",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList06",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList07",
+ "eventq_index": 0,
+ "opClass": "SimdMultAcc",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList07",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList08",
+ "eventq_index": 0,
+ "opClass": "SimdShift",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList08",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList09",
+ "eventq_index": 0,
+ "opClass": "SimdShiftAcc",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList09",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList10",
+ "eventq_index": 0,
+ "opClass": "SimdSqrt",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList10",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList11",
+ "eventq_index": 0,
+ "opClass": "SimdFloatAdd",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList11",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList12",
+ "eventq_index": 0,
+ "opClass": "SimdFloatAlu",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList12",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList13",
+ "eventq_index": 0,
+ "opClass": "SimdFloatCmp",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList13",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList14",
+ "eventq_index": 0,
+ "opClass": "SimdFloatCvt",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList14",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList15",
+ "eventq_index": 0,
+ "opClass": "SimdFloatDiv",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList15",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList16",
+ "eventq_index": 0,
+ "opClass": "SimdFloatMisc",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList16",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList17",
+ "eventq_index": 0,
+ "opClass": "SimdFloatMult",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList17",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList18",
+ "eventq_index": 0,
+ "opClass": "SimdFloatMultAcc",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList18",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList19",
+ "eventq_index": 0,
+ "opClass": "SimdFloatSqrt",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList5.opList19",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList5",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu2.fuPool.FUList5",
+ "type": "FUDesc"
+ },
+ {
+ "count": 0,
+ "opList": [
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList",
+ "eventq_index": 0,
+ "opClass": "MemWrite",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList6.opList",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList6",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu2.fuPool.FUList6",
+ "type": "FUDesc"
+ },
+ {
+ "count": 4,
+ "opList": [
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList0",
+ "eventq_index": 0,
+ "opClass": "MemRead",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList7.opList0",
+ "type": "OpDesc"
+ },
+ {
+ "issueLat": 1,
+ "opLat": 1,
+ "name": "opList1",
+ "eventq_index": 0,
+ "opClass": "MemWrite",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList7.opList1",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList7",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu2.fuPool.FUList7",
+ "type": "FUDesc"
+ },
+ {
+ "count": 1,
+ "opList": [
+ {
+ "issueLat": 3,
+ "opLat": 3,
+ "name": "opList",
+ "eventq_index": 0,
+ "opClass": "IprAccess",
+ "cxx_class": "OpDesc",
+ "path": "system.cpu2.fuPool.FUList8.opList",
+ "type": "OpDesc"
+ }
+ ],
+ "name": "FUList8",
+ "eventq_index": 0,
+ "cxx_class": "FUDesc",
+ "path": "system.cpu2.fuPool.FUList8",
+ "type": "FUDesc"
+ }
+ ],
+ "eventq_index": 0,
+ "cxx_class": "FUPool",
+ "path": "system.cpu2.fuPool",
+ "type": "FUPool"
+ },
+ "cachePorts": 200,
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "store_set_clear_period": 250000,
+ "numPhysFloatRegs": 256,
+ "eventq_index": 0,
+ "smtNumFetchingThreads": 1,
+ "numThreads": 1,
+ "numPhysIntRegs": 256,
+ "do_quiesce": true,
+ "type": "DerivO3CPU",
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu2.isa",
+ "type": "X86ISA",
+ "name": "isa",
+ "cxx_class": "X86ISA::ISA"
+ }
+ ],
+ "smtROBThreshold": 100,
+ "profile": 0.0,
+ "renameToROBDelay": 1,
+ "commitToFetchDelay": 1,
+ "fetchTrapLatency": 1,
+ "progress_interval": 0.0,
+ "commitWidth": 8,
+ "branchPred": {
+ "choiceCtrBits": 2,
+ "name": "branchPred",
+ "globalCtrBits": 2,
+ "numThreads": 1,
+ "localHistoryTableSize": 2048,
+ "choicePredictorSize": 8192,
+ "instShiftAmt": 2,
+ "localCtrBits": 2,
+ "eventq_index": 0,
+ "BTBTagSize": 16,
+ "BTBEntries": 4096,
+ "cxx_class": "BPredUnit",
+ "path": "system.cpu2.branchPred",
+ "localPredictorSize": 2048,
+ "type": "BranchPredictor",
+ "RASSize": 16,
+ "globalPredictorSize": 8192
+ },
+ "socket_id": 0,
+ "numPhysCCRegs": 1280,
+ "renameToFetchDelay": 1,
+ "LSQDepCheckShift": 4,
+ "decodeWidth": 8,
+ "trapLatency": 13,
+ "needsTSO": true,
+ "renameWidth": 8,
+ "path": "system.cpu2",
+ "max_insts_all_threads": 0,
+ "max_loads_any_thread": 0,
+ "numRobs": 1,
+ "iewToDecodeDelay": 1,
+ "max_insts_any_thread": 0,
+ "issueToExecuteDelay": 1,
+ "name": "cpu2",
+ "fetchBufferSize": 64,
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::TLB",
+ "walker": {
+ "name": "walker",
+ "eventq_index": 0,
+ "cxx_class": "X86ISA::Walker",
+ "path": "system.cpu2.dtb.walker",
+ "type": "X86PagetableWalker",
+ "num_squash_per_cycle": 4
+ },
+ "path": "system.cpu2.dtb",
+ "type": "X86TLB",
+ "size": 64
+ },
+ "SSITSize": 1024,
+ "LQEntries": 32,
+ "numIQEntries": 64,
+ "activity": 0,
+ "LFSTSize": 1024,
+ "iewToCommitDelay": 1,
+ "renameToIEWDelay": 2,
+ "iewToFetchDelay": 1,
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu2.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ },
+ "decodeToFetchDelay": 1,
+ "smtIQThreshold": 100
+ }
+ ],
+ "intrctrl": {
+ "eventq_index": 0,
+ "path": "system.intrctrl",
+ "type": "IntrControl",
+ "name": "intrctrl",
+ "cxx_class": "IntrControl"
+ },
+ "num_work_ids": 16,
+ "work_item_id": -1,
+ "work_begin_cpu_id_exit": -1
+ },
+ "time_sync_period": 0.1,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 9.999999999999999e-05,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": true
+} \ No newline at end of file
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
index 860a4f6c8..ad22be7e5 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 17:10:34
-gem5 started Jan 22 2014 22:25:31
-gem5 executing on u200540-lin
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
+gem5 compiled May 12 2014 12:50:47
+gem5 started May 12 2014 15:35:34
+gem5 executing on zizzer
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /z/stever/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
Global frequency set at 1000000000000 ticks per second
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 66a37e2a3..3f4f8d0c7 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
@@ -4,13 +4,13 @@ sim_seconds 5.133875 # Nu
sim_ticks 5133874673500 # Number of ticks simulated
final_tick 5133874673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 230895 # Simulator instruction rate (inst/s)
-host_op_rate 458967 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4861072606 # Simulator tick rate (ticks/s)
-host_mem_usage 966208 # Number of bytes of host memory used
-host_seconds 1056.12 # Real time elapsed on the host
-sim_insts 243852608 # Number of instructions simulated
-sim_ops 484724489 # Number of ops (including micro ops) simulated
+host_inst_rate 236000 # Simulator instruction rate (inst/s)
+host_op_rate 469116 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4968557721 # Simulator tick rate (ticks/s)
+host_mem_usage 928744 # Number of bytes of host memory used
+host_seconds 1033.27 # Real time elapsed on the host
+sim_insts 243852609 # Number of instructions simulated
+sim_ops 484724493 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::pc.south_bridge.ide 2445440 # Number of bytes read from this memory
@@ -309,10 +309,10 @@ system.physmem.readRowHitRate 82.04 # Ro
system.physmem.writeRowHitRate 74.97 # Row buffer hit rate for writes
system.physmem.avgGap 30177935.67 # Average gap between requests
system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 4939989046000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 4939989054000 # Time in different power states
system.physmem.memoryStateTime::REF 171431260000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 22454250000 # Time in different power states
+system.physmem.memoryStateTime::ACT 22454242000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 6437004 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 422289 # Transaction distribution
@@ -1045,9 +1045,9 @@ system.cpu0.kern.inst.arm 0 # nu
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 850385 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.795763 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 129494150 # Total number of references to valid blocks.
+system.cpu0.icache.tags.total_refs 129494152 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 850897 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 152.185458 # Average number of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 152.185461 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 147465545000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 306.120317 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.033154 # Average occupied blocks per requestor
@@ -1061,20 +1061,20 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 101
system.cpu0.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 131214877 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 131214877 # Number of data accesses
+system.cpu0.icache.tags.tag_accesses 131214879 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 131214879 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 88330268 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 38415628 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 38415630 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2748254 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 129494150 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 129494152 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 88330268 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 38415628 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 38415630 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2748254 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 129494150 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 129494152 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 88330268 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 38415628 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 38415630 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2748254 # number of overall hits
-system.cpu0.icache.overall_hits::total 129494150 # number of overall hits
+system.cpu0.icache.overall_hits::total 129494152 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 347417 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 153575 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 368828 # number of ReadReq misses
@@ -1097,17 +1097,17 @@ system.cpu0.icache.overall_miss_latency::cpu1.inst 2140572500
system.cpu0.icache.overall_miss_latency::cpu2.inst 5126974995 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 7267547495 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 88677685 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 38569203 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 38569205 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3117082 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 130363970 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 130363972 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 88677685 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 38569203 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 38569205 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3117082 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 130363970 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 130363972 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 88677685 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 38569203 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 38569205 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3117082 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 130363970 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 130363972 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003918 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003982 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.118325 # miss rate for ReadReq accesses
@@ -1182,9 +1182,9 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::total 12079.025728
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 1632172 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999414 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 19616448 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs 19616450 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1632684 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 12.014847 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 12.014848 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 243.807235 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 263.156885 # Average occupied blocks per requestor
@@ -1198,24 +1198,24 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 88185531 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 88185531 # Number of data accesses
+system.cpu0.dcache.tags.tag_accesses 88185539 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 88185539 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 5216887 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 2373281 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 2373282 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 3941483 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 11531651 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 11531652 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3654093 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 1632237 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 1632238 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 2796808 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 8083138 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 8083139 # number of WriteReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8870980 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 4005518 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 4005520 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 6738291 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 19614789 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 19614791 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8870980 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 4005518 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 4005520 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 6738291 # number of overall hits
-system.cpu0.dcache.overall_hits::total 19614789 # number of overall hits
+system.cpu0.dcache.overall_hits::total 19614791 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 535895 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 223619 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 948939 # number of ReadReq misses
@@ -1245,21 +1245,21 @@ system.cpu0.dcache.overall_miss_latency::cpu1.data 5349158328
system.cpu0.dcache.overall_miss_latency::cpu2.data 18666142786 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 24015301114 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5752782 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 2596900 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 2596901 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4890422 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 13240104 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 13240105 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3798594 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 1694395 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 1694396 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2905116 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 8398105 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 8398106 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 9551376 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 4291295 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 4291297 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7795538 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 21638209 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 21638211 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 9551376 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 4291295 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 4291297 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7795538 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 21638209 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 21638211 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093154 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086110 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.194040 # miss rate for ReadReq accesses
@@ -1376,30 +1376,30 @@ system.cpu0.dcache.no_allocate_misses 0 # Nu
system.cpu1.numCycles 2606021866 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 34914128 # Number of instructions committed
-system.cpu1.committedOps 67869824 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 62995293 # Number of integer alu accesses
+system.cpu1.committedInsts 34914129 # Number of instructions committed
+system.cpu1.committedOps 67869828 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 62995297 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 438942 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6428622 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 62995293 # number of integer instructions
+system.cpu1.num_int_insts 62995297 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 116271698 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 54373004 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 116271710 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 54373007 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 35773637 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 26686134 # number of times the CC registers were written
-system.cpu1.num_mem_refs 4480510 # number of memory refs
-system.cpu1.num_load_insts 2784988 # Number of load instructions
-system.cpu1.num_store_insts 1695522 # Number of store instructions
-system.cpu1.num_idle_cycles 2483027078.364504 # Number of idle cycles
-system.cpu1.num_busy_cycles 122994787.635496 # Number of busy cycles
+system.cpu1.num_cc_register_reads 35773638 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 26686136 # number of times the CC registers were written
+system.cpu1.num_mem_refs 4480512 # number of memory refs
+system.cpu1.num_load_insts 2784989 # Number of load instructions
+system.cpu1.num_store_insts 1695523 # Number of store instructions
+system.cpu1.num_idle_cycles 2483027076.334052 # Number of idle cycles
+system.cpu1.num_busy_cycles 122994789.665948 # Number of busy cycles
system.cpu1.not_idle_fraction 0.047196 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.952804 # Percentage of idle cycles
system.cpu1.Branches 7029914 # Number of branches fetched
system.cpu1.op_class::No_OpClass 31008 0.05% 0.05% # Class of executed instruction
-system.cpu1.op_class::IntAlu 63308001 93.28% 93.32% # Class of executed instruction
+system.cpu1.op_class::IntAlu 63308003 93.28% 93.32% # Class of executed instruction
system.cpu1.op_class::IntMult 28040 0.04% 93.37% # Class of executed instruction
system.cpu1.op_class::IntDiv 22580 0.03% 93.40% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 93.40% # Class of executed instruction
@@ -1428,11 +1428,11 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.40% # Cl
system.cpu1.op_class::SimdFloatMult 0 0.00% 93.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.40% # Class of executed instruction
-system.cpu1.op_class::MemRead 2784988 4.10% 97.50% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1695522 2.50% 100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead 2784989 4.10% 97.50% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1695523 2.50% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 67870139 # Class of executed instruction
+system.cpu1.op_class::total 67870143 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 28758894 # Number of BP lookups
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
index ff5b8aa75..08dac49a9 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
@@ -44,7 +44,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812463
+result 7812444
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index 8dffb60f8..477b3f3c7 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=true
+sim_quantum=0
time_sync_enable=false
time_sync_period=200000000
time_sync_spin_threshold=200000
@@ -12,6 +14,7 @@ children=bridge clk_domain cpu cpu_clk_domain disk0 hypervisor_desc intrctrl iob
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
hypervisor_addr=1099243257856
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
hypervisor_desc=system.hypervisor_desc
@@ -20,9 +23,10 @@ hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=atomic
mem_ranges=1048576:68157439 2147483648:2415919103
-memories=system.rom system.physmem1 system.hypervisor_desc system.physmem0 system.nvram system.partition_desc
+memories=system.nvram system.rom system.hypervisor_desc system.physmem0 system.physmem1 system.partition_desc
num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
@@ -32,7 +36,7 @@ openboot_bin=/dist/m5/system/binaries/openboot_new.bin
partition_desc=system.partition_desc
partition_desc_addr=133445976064
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
-readfile=tests/halt.sh
+readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr=1099243192320
reset_bin=/dist/m5/system/binaries/reset_new.bin
rom=system.rom
@@ -50,6 +54,7 @@ system_port=system.membus.slave[0]
type=Bridge
clk_domain=system.clk_domain
delay=100
+eventq_index=0
ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
req_size=16
resp_size=16
@@ -59,11 +64,13 @@ slave=system.membus.master[2]
[system.clk_domain]
type=SrcClockDomain
clock=2
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer
+branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
@@ -71,6 +78,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
@@ -90,6 +98,7 @@ simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
+socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
@@ -100,30 +109,37 @@ icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=SparcTLB
+eventq_index=0
size=64
[system.cpu.interrupts]
type=SparcInterrupts
+eventq_index=0
[system.cpu.isa]
type=SparcISA
+eventq_index=0
[system.cpu.itb]
type=SparcTLB
+eventq_index=0
size=64
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=2
+eventq_index=0
voltage_domain=system.voltage_domain
[system.disk0]
type=MmDisk
children=image
clk_domain=system.clk_domain
+eventq_index=0
image=system.disk0.image
pio_addr=134217728000
pio_latency=200
@@ -134,12 +150,14 @@ pio=system.iobus.master[14]
type=CowDiskImage
children=child
child=system.disk0.image.child
+eventq_index=0
image_file=
read_only=false
table_size=65536
[system.disk0.image.child]
type=RawDiskImage
+eventq_index=0
image_file=/dist/m5/system/disks/disk.s10hw2
read_only=true
@@ -148,6 +166,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=60
latency_var=0
@@ -157,11 +176,13 @@ port=system.membus.master[5]
[system.intrctrl]
type=IntrControl
+eventq_index=0
sys=system
[system.iobus]
type=NoncoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
use_default_range=false
width=8
@@ -172,6 +193,7 @@ slave=system.bridge.master
type=CoherentBus
children=badaddr_responder
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -183,6 +205,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=200
@@ -202,6 +225,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=60
latency_var=0
@@ -214,6 +238,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=60
latency_var=0
@@ -226,6 +251,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=60
latency_var=0
@@ -238,6 +264,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=60
latency_var=0
@@ -250,6 +277,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=60
latency_var=0
@@ -260,12 +288,14 @@ port=system.membus.master[3]
[system.t1000]
type=T1000
children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
+eventq_index=0
intrctrl=system.intrctrl
system=system
[system.t1000.fake_clk]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=644245094400
pio_latency=200
@@ -283,6 +313,7 @@ pio=system.iobus.master[0]
[system.t1000.fake_jbi]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=549755813888
pio_latency=200
@@ -300,6 +331,7 @@ pio=system.iobus.master[11]
[system.t1000.fake_l2_1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=725849473024
pio_latency=200
@@ -317,6 +349,7 @@ pio=system.iobus.master[2]
[system.t1000.fake_l2_2]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=725849473088
pio_latency=200
@@ -334,6 +367,7 @@ pio=system.iobus.master[3]
[system.t1000.fake_l2_3]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=725849473152
pio_latency=200
@@ -351,6 +385,7 @@ pio=system.iobus.master[4]
[system.t1000.fake_l2_4]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=725849473216
pio_latency=200
@@ -368,6 +403,7 @@ pio=system.iobus.master[5]
[system.t1000.fake_l2esr_1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=734439407616
pio_latency=200
@@ -385,6 +421,7 @@ pio=system.iobus.master[6]
[system.t1000.fake_l2esr_2]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=734439407680
pio_latency=200
@@ -402,6 +439,7 @@ pio=system.iobus.master[7]
[system.t1000.fake_l2esr_3]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=734439407744
pio_latency=200
@@ -419,6 +457,7 @@ pio=system.iobus.master[8]
[system.t1000.fake_l2esr_4]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=734439407808
pio_latency=200
@@ -436,6 +475,7 @@ pio=system.iobus.master[9]
[system.t1000.fake_membnks]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=648540061696
pio_latency=200
@@ -453,6 +493,7 @@ pio=system.iobus.master[1]
[system.t1000.fake_ssi]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=1095216660480
pio_latency=200
@@ -469,6 +510,7 @@ pio=system.iobus.master[10]
[system.t1000.hterm]
type=Terminal
+eventq_index=0
intr_control=system.intrctrl
number=0
output=true
@@ -477,6 +519,7 @@ port=3456
[system.t1000.htod]
type=DumbTOD
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=1099255906296
pio_latency=200
system=system
@@ -486,6 +529,7 @@ pio=system.membus.master[1]
[system.t1000.hvuart]
type=Uart8250
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=1099255955456
pio_latency=200
platform=system.t1000
@@ -496,6 +540,7 @@ pio=system.iobus.master[13]
[system.t1000.iob]
type=Iob
clk_domain=system.clk_domain
+eventq_index=0
pio_latency=2
platform=system.t1000
system=system
@@ -503,6 +548,7 @@ pio=system.membus.master[0]
[system.t1000.pterm]
type=Terminal
+eventq_index=0
intr_control=system.intrctrl
number=0
output=true
@@ -511,6 +557,7 @@ port=3456
[system.t1000.puart0]
type=Uart8250
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=133412421632
pio_latency=200
platform=system.t1000
@@ -520,5 +567,6 @@ pio=system.iobus.master[12]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
new file mode 100644
index 000000000..5f0592320
--- /dev/null
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.json
@@ -0,0 +1,717 @@
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "bridge": {
+ "slave": {
+ "peer": "system.membus.master[2]",
+ "role": "SLAVE"
+ },
+ "name": "bridge",
+ "req_size": 16,
+ "delay": 5.0000000000000004e-08,
+ "eventq_index": 0,
+ "master": {
+ "peer": "system.iobus.slave[0]",
+ "role": "MASTER"
+ },
+ "cxx_class": "Bridge",
+ "path": "system.bridge",
+ "resp_size": 16,
+ "type": "Bridge"
+ },
+ "iobus": {
+ "slave": {
+ "peer": [
+ "system.bridge.master"
+ ],
+ "role": "SLAVE"
+ },
+ "name": "iobus",
+ "header_cycles": 1,
+ "width": 8,
+ "eventq_index": 0,
+ "master": {
+ "peer": [
+ "system.t1000.fake_clk.pio",
+ "system.t1000.fake_membnks.pio",
+ "system.t1000.fake_l2_1.pio",
+ "system.t1000.fake_l2_2.pio",
+ "system.t1000.fake_l2_3.pio",
+ "system.t1000.fake_l2_4.pio",
+ "system.t1000.fake_l2esr_1.pio",
+ "system.t1000.fake_l2esr_2.pio",
+ "system.t1000.fake_l2esr_3.pio",
+ "system.t1000.fake_l2esr_4.pio",
+ "system.t1000.fake_ssi.pio",
+ "system.t1000.fake_jbi.pio",
+ "system.t1000.puart0.pio",
+ "system.t1000.hvuart.pio",
+ "system.disk0.pio"
+ ],
+ "role": "MASTER"
+ },
+ "cxx_class": "NoncoherentBus",
+ "path": "system.iobus",
+ "type": "NoncoherentBus",
+ "use_default_range": false
+ },
+ "rom": {
+ "latency": 3.0000000000000004e-08,
+ "name": "rom",
+ "eventq_index": 0,
+ "latency_var": 0.0,
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "path": "system.rom",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[3]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ "membus": {
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.icache_port",
+ "system.cpu.dcache_port"
+ ],
+ "role": "SLAVE"
+ },
+ "name": "membus",
+ "badaddr_responder": {
+ "ret_data8": 255,
+ "name": "badaddr_responder",
+ "pio": {
+ "peer": "system.membus.default",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": true,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": false,
+ "ret_data64": 18446744073709551615,
+ "cxx_class": "IsaFake",
+ "path": "system.membus.badaddr_responder",
+ "pio_addr": 0,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "default": {
+ "peer": "system.membus.badaddr_responder.pio",
+ "role": "MASTER"
+ },
+ "header_cycles": 1,
+ "width": 8,
+ "eventq_index": 0,
+ "master": {
+ "peer": [
+ "system.t1000.iob.pio",
+ "system.t1000.htod.pio",
+ "system.bridge.slave",
+ "system.rom.port",
+ "system.nvram.port",
+ "system.hypervisor_desc.port",
+ "system.partition_desc.port",
+ "system.physmem0.port",
+ "system.physmem1.port"
+ ],
+ "role": "MASTER"
+ },
+ "cxx_class": "CoherentBus",
+ "path": "system.membus",
+ "type": "CoherentBus",
+ "use_default_range": false
+ },
+ "t1000": {
+ "htod": {
+ "name": "htod",
+ "pio": {
+ "peer": "system.membus.master[1]",
+ "role": "SLAVE"
+ },
+ "time": "Thu Jan 1 00:00:00 2009",
+ "pio_latency": 1.0000000000000001e-07,
+ "eventq_index": 0,
+ "cxx_class": "DumbTOD",
+ "path": "system.t1000.htod",
+ "pio_addr": 1099255906296,
+ "type": "DumbTOD"
+ },
+ "puart0": {
+ "name": "puart0",
+ "pio": {
+ "peer": "system.iobus.master[12]",
+ "role": "SLAVE"
+ },
+ "pio_latency": 1.0000000000000001e-07,
+ "eventq_index": 0,
+ "cxx_class": "Uart8250",
+ "path": "system.t1000.puart0",
+ "pio_addr": 133412421632,
+ "type": "Uart8250"
+ },
+ "fake_membnks": {
+ "ret_data8": 255,
+ "name": "fake_membnks",
+ "pio": {
+ "peer": "system.iobus.master[1]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 16384,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": false,
+ "ret_data64": 0,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_membnks",
+ "pio_addr": 648540061696,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "cxx_class": "T1000",
+ "fake_jbi": {
+ "ret_data8": 255,
+ "name": "fake_jbi",
+ "pio": {
+ "peer": "system.iobus.master[11]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 4294967296,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": false,
+ "ret_data64": 18446744073709551615,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_jbi",
+ "pio_addr": 549755813888,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "fake_l2esr_2": {
+ "ret_data8": 255,
+ "name": "fake_l2esr_2",
+ "pio": {
+ "peer": "system.iobus.master[7]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": true,
+ "ret_data64": 0,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_l2esr_2",
+ "pio_addr": 734439407680,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "eventq_index": 0,
+ "hterm": {
+ "name": "hterm",
+ "output": true,
+ "number": 0,
+ "eventq_index": 0,
+ "cxx_class": "Terminal",
+ "path": "system.t1000.hterm",
+ "type": "Terminal",
+ "port": 3456
+ },
+ "type": "T1000",
+ "fake_l2_4": {
+ "ret_data8": 255,
+ "name": "fake_l2_4",
+ "pio": {
+ "peer": "system.iobus.master[5]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": true,
+ "ret_data64": 1,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_l2_4",
+ "pio_addr": 725849473216,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "fake_l2_1": {
+ "ret_data8": 255,
+ "name": "fake_l2_1",
+ "pio": {
+ "peer": "system.iobus.master[2]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": true,
+ "ret_data64": 1,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_l2_1",
+ "pio_addr": 725849473024,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "fake_l2_2": {
+ "ret_data8": 255,
+ "name": "fake_l2_2",
+ "pio": {
+ "peer": "system.iobus.master[3]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": true,
+ "ret_data64": 1,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_l2_2",
+ "pio_addr": 725849473088,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "fake_l2_3": {
+ "ret_data8": 255,
+ "name": "fake_l2_3",
+ "pio": {
+ "peer": "system.iobus.master[4]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": true,
+ "ret_data64": 1,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_l2_3",
+ "pio_addr": 725849473152,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "pterm": {
+ "name": "pterm",
+ "output": true,
+ "number": 0,
+ "eventq_index": 0,
+ "cxx_class": "Terminal",
+ "path": "system.t1000.pterm",
+ "type": "Terminal",
+ "port": 3456
+ },
+ "path": "system.t1000",
+ "iob": {
+ "name": "iob",
+ "pio": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "pio_latency": 1e-09,
+ "eventq_index": 0,
+ "cxx_class": "Iob",
+ "path": "system.t1000.iob",
+ "type": "Iob"
+ },
+ "hvuart": {
+ "name": "hvuart",
+ "pio": {
+ "peer": "system.iobus.master[13]",
+ "role": "SLAVE"
+ },
+ "pio_latency": 1.0000000000000001e-07,
+ "eventq_index": 0,
+ "cxx_class": "Uart8250",
+ "path": "system.t1000.hvuart",
+ "pio_addr": 1099255955456,
+ "type": "Uart8250"
+ },
+ "name": "t1000",
+ "fake_l2esr_3": {
+ "ret_data8": 255,
+ "name": "fake_l2esr_3",
+ "pio": {
+ "peer": "system.iobus.master[8]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": true,
+ "ret_data64": 0,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_l2esr_3",
+ "pio_addr": 734439407744,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "fake_ssi": {
+ "ret_data8": 255,
+ "name": "fake_ssi",
+ "pio": {
+ "peer": "system.iobus.master[10]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 268435456,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": false,
+ "ret_data64": 18446744073709551615,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_ssi",
+ "pio_addr": 1095216660480,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "fake_l2esr_1": {
+ "ret_data8": 255,
+ "name": "fake_l2esr_1",
+ "pio": {
+ "peer": "system.iobus.master[6]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": true,
+ "ret_data64": 0,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_l2esr_1",
+ "pio_addr": 734439407616,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "fake_l2esr_4": {
+ "ret_data8": 255,
+ "name": "fake_l2esr_4",
+ "pio": {
+ "peer": "system.iobus.master[9]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 8,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": true,
+ "ret_data64": 0,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_l2esr_4",
+ "pio_addr": 734439407808,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ },
+ "fake_clk": {
+ "ret_data8": 255,
+ "name": "fake_clk",
+ "pio": {
+ "peer": "system.iobus.master[0]",
+ "role": "SLAVE"
+ },
+ "ret_bad_addr": false,
+ "pio_latency": 1.0000000000000001e-07,
+ "fake_mem": false,
+ "pio_size": 4294967296,
+ "ret_data32": 4294967295,
+ "eventq_index": 0,
+ "update_data": false,
+ "ret_data64": 18446744073709551615,
+ "cxx_class": "IsaFake",
+ "path": "system.t1000.fake_clk",
+ "pio_addr": 644245094400,
+ "type": "IsaFake",
+ "ret_data16": 65535
+ }
+ },
+ "partition_desc_addr": 133445976064,
+ "physmem": [
+ {
+ "latency": 3.0000000000000004e-08,
+ "name": "physmem0",
+ "eventq_index": 0,
+ "latency_var": 0.0,
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "path": "system.physmem0",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[7]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ {
+ "latency": 3.0000000000000004e-08,
+ "name": "physmem1",
+ "eventq_index": 0,
+ "latency_var": 0.0,
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "path": "system.physmem1",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[8]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ }
+ ],
+ "hypervisor_addr": 1099243257856,
+ "cxx_class": "SparcSystem",
+ "load_offset": 0,
+ "openboot_addr": 1099243716608,
+ "work_end_ckpt_count": 0,
+ "nvram_addr": 133429198848,
+ "work_begin_ckpt_count": 0,
+ "partition_desc": {
+ "latency": 3.0000000000000004e-08,
+ "name": "partition_desc",
+ "eventq_index": 0,
+ "latency_var": 0.0,
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "path": "system.partition_desc",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[6]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": 1e-09,
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain"
+ },
+ "hypervisor_desc": {
+ "latency": 3.0000000000000004e-08,
+ "name": "hypervisor_desc",
+ "eventq_index": 0,
+ "latency_var": 0.0,
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "path": "system.hypervisor_desc",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[5]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ "nvram": {
+ "latency": 3.0000000000000004e-08,
+ "name": "nvram",
+ "eventq_index": 0,
+ "latency_var": 0.0,
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "path": "system.nvram",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[4]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ "eventq_index": 0,
+ "work_end_exit_count": 0,
+ "type": "SparcSystem",
+ "voltage_domain": {
+ "eventq_index": 0,
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain",
+ "name": "voltage_domain",
+ "cxx_class": "VoltageDomain"
+ },
+ "cache_line_size": 64,
+ "work_cpus_ckpt_count": 0,
+ "work_begin_exit_count": 0,
+ "num_work_ids": 16,
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": 1e-09,
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain"
+ },
+ "mem_mode": "atomic",
+ "name": "system",
+ "init_param": 0,
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "load_addr_mask": 1099511627775,
+ "cpu": {
+ "simpoint_interval": 100000000,
+ "do_statistics_insts": true,
+ "numThreads": 1,
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "SparcISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "SparcTLB",
+ "size": 64
+ },
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "cxx_class": "AtomicSimpleCPU",
+ "max_loads_all_threads": 0,
+ "simpoint_profile": false,
+ "simulate_data_stalls": false,
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "width": 1,
+ "eventq_index": 0,
+ "do_quiesce": true,
+ "type": "AtomicSimpleCPU",
+ "fastmem": false,
+ "profile": 0.0,
+ "icache_port": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "interrupts": {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "SparcInterrupts",
+ "name": "interrupts",
+ "cxx_class": "SparcISA::Interrupts"
+ },
+ "socket_id": 0,
+ "max_insts_all_threads": 0,
+ "path": "system.cpu",
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "SparcISA",
+ "name": "isa",
+ "cxx_class": "SparcISA::ISA"
+ }
+ ],
+ "switched_out": false,
+ "name": "cpu",
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "SparcISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "SparcTLB",
+ "size": 64
+ },
+ "max_insts_any_thread": 0,
+ "simulate_inst_stalls": false,
+ "progress_interval": 0.0,
+ "dcache_port": {
+ "peer": "system.membus.slave[2]",
+ "role": "MASTER"
+ },
+ "max_loads_any_thread": 0,
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ }
+ },
+ "intrctrl": {
+ "eventq_index": 0,
+ "path": "system.intrctrl",
+ "type": "IntrControl",
+ "name": "intrctrl",
+ "cxx_class": "IntrControl"
+ },
+ "disk0": {
+ "name": "disk0",
+ "pio": {
+ "peer": "system.iobus.master[14]",
+ "role": "SLAVE"
+ },
+ "image": {
+ "read_only": false,
+ "name": "image",
+ "child": {
+ "read_only": true,
+ "name": "child",
+ "eventq_index": 0,
+ "cxx_class": "RawDiskImage",
+ "path": "system.disk0.image.child",
+ "type": "RawDiskImage"
+ },
+ "eventq_index": 0,
+ "cxx_class": "CowDiskImage",
+ "path": "system.disk0.image",
+ "table_size": 65536,
+ "type": "CowDiskImage"
+ },
+ "pio_latency": 1.0000000000000001e-07,
+ "eventq_index": 0,
+ "cxx_class": "MmDisk",
+ "path": "system.disk0",
+ "pio_addr": 134217728000,
+ "type": "MmDisk"
+ },
+ "hypervisor_desc_addr": 133446500352,
+ "reset_addr": 1099243192320,
+ "work_item_id": -1,
+ "work_begin_cpu_id_exit": -1
+ },
+ "time_sync_period": 0.1,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 9.999999999999999e-05,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": true
+} \ No newline at end of file
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
index 387f71a0d..c7cb2a7c3 100755
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
@@ -23,7 +23,5 @@ warn: rounding error > tolerance
warn: rounding error > tolerance
0.145519 rounded to 0
warn: Sockets disabled, not accepting terminal connections
-warn: CoherentBus system.membus has no snooping ports attached!
warn: Sockets disabled, not accepting gdb connections
warn: Don't know what interrupt to clear for console.
-hack: be nice to actually delete the event here
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index e75f41d79..001061453 100755
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -1,12 +1,10 @@
-Redirecting stdout to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:07:33
+gem5 compiled May 12 2014 11:27:38
+gem5 started May 12 2014 11:28:05
gem5 executing on zizzer
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re /z/stever/hg/gem5/tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Global frequency set at 2000000000 ticks per second
info: No kernel set for full system simulation. Assuming you know what you're doing
0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index e1724881e..3676ead42 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.233778 # Nu
sim_ticks 4467555024 # Number of ticks simulated
final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 2000000000 # Frequency of simulated ticks
-host_inst_rate 1895600 # Simulator instruction rate (inst/s)
-host_op_rate 1896345 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3800545 # Simulator tick rate (ticks/s)
-host_mem_usage 576292 # Number of bytes of host memory used
-host_seconds 1175.50 # Real time elapsed on the host
+host_inst_rate 2578014 # Simulator instruction rate (inst/s)
+host_op_rate 2579027 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5168737 # Simulator tick rate (ticks/s)
+host_mem_usage 527944 # Number of bytes of host memory used
+host_seconds 864.34 # Real time elapsed on the host
sim_insts 2228284650 # Number of instructions simulated
sim_ops 2229160714 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -35,38 +35,6 @@ system.nvram.bw_write::cpu.data 41 # Wr
system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
-system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
-system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory
-system.physmem1.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
-system.physmem1.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
-system.physmem1.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
-system.physmem1.bytes_written::total 897268422 # Number of bytes written to this memory
-system.physmem1.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
-system.physmem1.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
-system.physmem1.num_reads::total 2403489130 # Number of read requests responded to by this memory
-system.physmem1.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
-system.physmem1.num_writes::total 187387796 # Number of write requests responded to by this memory
-system.physmem1.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
-system.physmem1.num_other::total 5403067 # Number of other requests responded to by this memory
-system.physmem1.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem1.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem1.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
-system.physmem1.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
-system.physmem1.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
-system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
-system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
-system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
-system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
@@ -107,6 +75,38 @@ system.physmem0.bw_write::total 6894251 # Wr
system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
+system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
+system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
+system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory
+system.physmem1.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
+system.physmem1.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
+system.physmem1.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
+system.physmem1.bytes_written::total 897268422 # Number of bytes written to this memory
+system.physmem1.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
+system.physmem1.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
+system.physmem1.num_reads::total 2403489130 # Number of read requests responded to by this memory
+system.physmem1.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
+system.physmem1.num_writes::total 187387796 # Number of write requests responded to by this memory
+system.physmem1.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
+system.physmem1.num_other::total 5403067 # Number of other requests responded to by this memory
+system.physmem1.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
+system.physmem1.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
+system.physmem1.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
+system.physmem1.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem1.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem1.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
+system.physmem1.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
+system.physmem1.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
+system.physmem1.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
+system.physmem1.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
+system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
+system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
+system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
+system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 5163367605 # Throughput (bytes/s)
system.membus.data_through_bus 11533814443 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
@@ -136,6 +136,41 @@ system.cpu.num_busy_cycles 2233777513 # Nu
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 441057355 # Number of branches fetched
+system.cpu.op_class::No_OpClass 49673656 2.22% 2.22% # Class of executed instruction
+system.cpu.op_class::IntAlu 1619015933 72.49% 74.71% # Class of executed instruction
+system.cpu.op_class::IntMult 0 0.00% 74.71% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 74.71% # Class of executed instruction
+system.cpu.op_class::FloatAdd 8419779 0.38% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::MemRead 356274529 15.95% 91.04% # Class of executed instruction
+system.cpu.op_class::MemWrite 200199782 8.96% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 2233583679 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 11:15:57 +0000