diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
| commit | 9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 (patch) | |
| tree | 79c5001cce6b9d92d1ad04d4a2cd4e442f56803c /tests | |
| parent | 77853b9f529947c3a9db78ef3458289f387289ce (diff) | |
| download | gem5-9b67f3723e48efdd0a0b640ff82cfcf8aad3a659.tar.xz | |
Stats: Update stats for previous set of patches.
Diffstat (limited to 'tests')
38 files changed, 2057 insertions, 2034 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 57a3abb33..a359bdb55 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 08:53:40 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:40:29 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 2bb965158..240486239 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 195051 # Simulator instruction rate (inst/s) -host_mem_usage 206584 # Number of bytes of host memory used -host_seconds 2899.51 # Real time elapsed on the host -host_tick_rate 56140502 # Simulator tick rate (ticks/s) +host_inst_rate 207877 # Simulator instruction rate (inst/s) +host_mem_usage 206352 # Number of bytes of host memory used +host_seconds 2720.61 # Real time elapsed on the host +host_tick_rate 59832123 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated sim_seconds 0.162780 # Number of seconds simulated @@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 40819876 # DT system.cpu.dtb.write_misses 27547 # DTB write misses system.cpu.fetch.Branches 76295210 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 65560315 # Number of cache lines fetched -system.cpu.fetch.Cycles 195638983 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 130078631 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 1304986 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 697895611 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 4169829 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.234351 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 65560315 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index f21f452d2..df93e233e 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 15 2011 04:38:18 -M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip -M5 started Jan 15 2011 04:38:23 -M5 executing on tater +M5 compiled Jan 17 2011 21:17:52 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 21:17:55 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 601459117000 because target called exit() +Exiting @ tick 601458924000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 1f89fda21..c2bc04472 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 115319 # Simulator instruction rate (inst/s) -host_mem_usage 220936 # Number of bytes of host memory used -host_seconds 12188.85 # Real time elapsed on the host -host_tick_rate 49345009 # Simulator tick rate (ticks/s) +host_inst_rate 144426 # Simulator instruction rate (inst/s) +host_mem_usage 207996 # Number of bytes of host memory used +host_seconds 9732.45 # Real time elapsed on the host +host_tick_rate 61799305 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1405604152 # Number of instructions simulated sim_seconds 0.601459 # Number of seconds simulated -sim_ticks 601459117000 # Number of ticks simulated +sim_ticks 601458924000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 98804472 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 100538302 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 98804590 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 100538418 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5348297 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 105813027 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 105813027 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 5348296 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 105813144 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 105813144 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 21327805 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 21328117 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1172142381 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1172142071 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::mean 1.270770 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::stdev 1.680117 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 418030405 35.66% 35.66% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 498323124 42.51% 78.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 52996988 4.52% 82.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 103673812 8.84% 91.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 32915552 2.81% 94.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 8294276 0.71% 95.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 25634202 2.19% 97.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 10946217 0.93% 98.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 21327805 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 418029830 35.66% 35.66% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 498322942 42.51% 78.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 52997650 4.52% 82.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 103674512 8.84% 91.54% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 32914783 2.81% 94.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 8294110 0.71% 95.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 25633990 2.19% 97.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 10946137 0.93% 98.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 21328117 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1172142381 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1172142071 # Number of insts commited each cycle system.cpu.commit.COM:count 1489523295 # Number of instructions committed system.cpu.commit.COM:loads 402512844 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed system.cpu.commit.COM:refs 569360986 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5348297 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 5348296 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1489523295 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 219358890 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 219357232 # The number of squashed insts skipped by commit system.cpu.committedInsts 1405604152 # Number of Instructions Simulated system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated -system.cpu.cpi 0.855802 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.855802 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 295702052 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14658.314544 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.427114 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 294883757 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11994825500 # number of ReadReq miss cycles +system.cpu.cpi 0.855801 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.855801 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 295701881 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14657.940821 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7465.771391 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 294883584 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11994549000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002767 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 818295 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 604804 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1593801500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 818297 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 604806 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1593875000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000722 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 213491 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) @@ -71,50 +71,50 @@ system.cpu.dcache.SwapReq_mshr_miss_latency 246000 # system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 15552.195709 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.845351 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 165080578 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 27468879045 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.010586 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1766238 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1498173 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3438428299 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 15553.543798 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12825.966833 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 165080859 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 27466889545 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010584 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1765957 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1497892 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3438192799 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001607 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 268065 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 955.151567 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 955.151791 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 462548868 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 15269.181916 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 10449.936869 # average overall mshr miss latency -system.cpu.dcache.demand_hits 459964335 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 39463704545 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005588 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2584533 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2102977 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5032229799 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 462548697 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 15269.953551 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency +system.cpu.dcache.demand_hits 459964443 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 39461438545 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005587 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2584254 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2102698 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5032067799 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.001041 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 481556 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999859 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.424477 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 462548868 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 15269.181916 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 10449.936869 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4095.424247 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 462548697 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 15269.953551 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 10449.600460 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 459964335 # number of overall hits -system.cpu.dcache.overall_miss_latency 39463704545 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005588 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2584533 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2102977 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5032229799 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 459964443 # number of overall hits +system.cpu.dcache.overall_miss_latency 39461438545 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005587 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2584254 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2102698 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5032067799 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.001041 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 481556 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -122,129 +122,130 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 477467 # number of replacements system.cpu.dcache.sampled_refs 481563 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.424477 # Cycle average of tags in use -system.cpu.dcache.total_refs 459965654 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 132267000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4095.424247 # Cycle average of tags in use +system.cpu.dcache.total_refs 459965762 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 132304000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 428418 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 393632591 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 1750743071 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 405697785 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 351108006 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 30410701 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 21703388 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 105813027 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 173096803 # Number of cache lines fetched -system.cpu.fetch.Cycles 548235394 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1429408 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1755979705 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6170644 # Number of cycles fetch has spent squashing +system.cpu.decode.DECODE:BlockedCycles 393633604 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 1750740297 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 405697462 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 351107020 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 30410517 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 21703374 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 105813144 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 173097327 # Number of cache lines fetched +system.cpu.fetch.Cycles 375137003 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1429156 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1755978912 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 6170643 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.087964 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 173096803 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 98804472 # Number of branches that fetch has predicted taken +system.cpu.fetch.icacheStallCycles 173097327 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 98804590 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 1.459766 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1202552471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.464003 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 1202551977 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.463999 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.699994 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 827413927 68.80% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 82887157 6.89% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 45822503 3.81% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22740108 1.89% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 827414974 68.80% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 82887161 6.89% 75.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 45821959 3.81% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22740624 1.89% 81.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 33832197 2.81% 84.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 32824411 2.73% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 14992283 1.25% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7935666 0.66% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 134104219 11.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 32823900 2.73% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 14990247 1.25% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7935660 0.66% 88.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 134105255 11.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1202552471 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 173096803 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35063.545151 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35058.732612 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 173095009 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 62904000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1202551977 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 173097327 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35070.194986 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35059.073359 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 173095532 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 62951000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1794 # number of ReadReq misses +system.cpu.icache.ReadReq_misses 1795 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 45366000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 45401500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1294 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1295 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 133870.849961 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 133767.799073 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 173096803 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35063.545151 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35058.732612 # average overall mshr miss latency -system.cpu.icache.demand_hits 173095009 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 62904000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 173097327 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35070.194986 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency +system.cpu.icache.demand_hits 173095532 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 62951000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000010 # miss rate for demand accesses -system.cpu.icache.demand_misses 1794 # number of demand (read+write) misses +system.cpu.icache.demand_misses 1795 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 45366000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 45401500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1294 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1295 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.509485 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1043.425085 # Average occupied blocks per context -system.cpu.icache.overall_accesses 173096803 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35063.545151 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35058.732612 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.509893 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1044.260820 # Average occupied blocks per context +system.cpu.icache.overall_accesses 173097327 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35070.194986 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35059.073359 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 173095009 # number of overall hits -system.cpu.icache.overall_miss_latency 62904000 # number of overall miss cycles +system.cpu.icache.overall_hits 173095532 # number of overall hits +system.cpu.icache.overall_miss_latency 62951000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000010 # miss rate for overall accesses -system.cpu.icache.overall_misses 1794 # number of overall misses +system.cpu.icache.overall_misses 1795 # number of overall misses system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 45366000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 45401500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1294 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1295 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 158 # number of replacements -system.cpu.icache.sampled_refs 1293 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 1294 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1043.425085 # Cycle average of tags in use -system.cpu.icache.total_refs 173095009 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1044.260820 # Cycle average of tags in use +system.cpu.icache.total_refs 173095532 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 365764 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 89387997 # Number of branches executed -system.cpu.iew.EXEC:nop 102270118 # number of nop insts executed +system.cpu.idleCycles 365872 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 89387996 # Number of branches executed +system.cpu.iew.EXEC:nop 102270134 # number of nop insts executed system.cpu.iew.EXEC:rate 1.226826 # Inst execution rate -system.cpu.iew.EXEC:refs 590483044 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 169844841 # Number of stores executed +system.cpu.iew.EXEC:refs 590482875 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 169844843 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1212158273 # num instructions consuming a value -system.cpu.iew.WB:count 1472499084 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.958320 # average fanout of values written-back +system.cpu.iew.WB:consumers 1212153101 # num instructions consuming a value +system.cpu.iew.WB:count 1472498717 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.958322 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1161635414 # num instructions producing a value +system.cpu.iew.WB:producers 1161632680 # num instructions producing a value system.cpu.iew.WB:rate 1.224106 # insts written-back per cycle -system.cpu.iew.WB:sent 1473870749 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 5524544 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2522826 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 468104285 # Number of dispatched load instructions +system.cpu.iew.WB:sent 1473870381 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 5524543 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2523096 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 468104279 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 2975263 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 4542157 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 188277600 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1708973999 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 420638203 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6158150 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1475771768 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 67057 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 4542154 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 188276128 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 1708972338 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 420638032 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6157621 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1475771230 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 66958 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9806 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 30410701 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 130988 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9816 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 30410517 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 130917 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 40442 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 124904328 # Number of loads that had data forwarded from stores @@ -253,18 +254,18 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 832421 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 264 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 65591441 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 21429458 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 65591435 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 21427986 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 832421 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 648482 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 648481 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4876062 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.168495 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.168495 # IPC: Total IPC of All Threads +system.cpu.ipc 1.168496 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.168496 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685428 59.70% 59.70% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 884685423 59.70% 59.70% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.70% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.70% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618266 0.18% 59.87% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2618241 0.18% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.87% # Type of FU issued @@ -290,165 +291,165 @@ system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 59.87% system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 59.87% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 59.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 423845992 28.60% 88.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780232 11.52% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 423844959 28.60% 88.48% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 170780228 11.52% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1481929918 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 3245029 # FU busy when requested +system.cpu.iq.ISSUE:FU_type_0::total 1481928851 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 3245613 # FU busy when requested system.cpu.iq.ISSUE:fu_busy_rate 0.002190 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 213200 6.57% 6.57% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 6.57% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 6.57% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 176159 5.43% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 2529947 77.96% 89.96% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 325723 10.04% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 176489 5.44% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 12.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 2530154 77.96% 89.96% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 325770 10.04% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1202552471 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1202551977 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::mean 1.232320 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127769 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.127764 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 320557937 26.66% 26.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 511599256 42.54% 69.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 219311183 18.24% 87.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 94899588 7.89% 95.33% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 39949785 3.32% 98.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 10701869 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5167481 0.43% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 226815 0.02% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 138557 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 320557298 26.66% 26.66% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 511598029 42.54% 69.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 219313490 18.24% 87.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 94900060 7.89% 95.33% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 39948235 3.32% 98.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 10701841 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5167806 0.43% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 227063 0.02% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 138155 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1202552471 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.231946 # Inst issue rate -system.cpu.iq.iqInstsAdded 1603627961 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1481929918 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 3075920 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 200595189 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 67507 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 832249 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 279093354 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 1202551977 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.231945 # Inst issue rate +system.cpu.iq.iqInstsAdded 1603626285 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1481928851 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 3075919 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 200593512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 68539 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 832248 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 279087097 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 268080 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.623615 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31319.356706 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34407.350752 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31318.935009 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 207610 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2080629000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2080612500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 0.225567 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 60470 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893881500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1893856000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.225567 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 60470 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 214777 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34036.417352 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.032810 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 214778 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34037.381235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.958432 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 181098 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1146312500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.156809 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 33679 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1044218500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156809 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 33679 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 1146379000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.156813 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33680 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1044247000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33680 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 428418 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 428418 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.114484 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.114449 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 482857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34274.835633 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.916696 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 482858 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34275.002655 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency system.cpu.l2cache.demand_hits 388708 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3226941500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.194983 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 94149 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 3226991500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.194985 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 94150 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2938100000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.194983 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 94149 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2938103000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.194985 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 94150 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.060598 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.060606 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.478382 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1985.676117 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15675.618625 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 482857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34274.835633 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.916696 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 1985.934249 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15675.618246 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 482858 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34275.002655 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31206.617100 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 388708 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3226941500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.194983 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 94149 # number of overall misses +system.cpu.l2cache.overall_miss_latency 3226991500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.194985 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 94150 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2938100000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.194983 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 94149 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2938103000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.194985 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 94150 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 75916 # number of replacements -system.cpu.l2cache.sampled_refs 91428 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 75917 # number of replacements +system.cpu.l2cache.sampled_refs 91429 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17661.294741 # Cycle average of tags in use -system.cpu.l2cache.total_refs 467607 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17661.552495 # Cycle average of tags in use +system.cpu.l2cache.total_refs 467609 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 59275 # number of writebacks system.cpu.memDep0.conflictingLoads 406523724 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 165665166 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 468104285 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 188277600 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 1202918235 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 123850375 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingStores 165663867 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 468104279 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 188276128 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1202917849 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 123850519 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244770452 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 28358883 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 134234499 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 443701065 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 41034727 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IQFullEvents 134234465 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 443700933 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 41034559 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2924510246 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1732032824 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1445195719 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 329589441 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 30410701 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 217220623 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 200425267 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 57780266 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:RenameLookups 2924501033 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 1732030714 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1445194568 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 329588798 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 30410517 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 217220436 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 200424116 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 57780774 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 3037077 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 385268446 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 385267398 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 3036332 # count of temporary serializing insts renamed -system.cpu.timesIdled 11396 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 11390 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 1cdc4de6d..169564b5c 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 1 2010 12:54:21 -M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase -M5 started Dec 3 2010 12:06:07 +M5 compiled Jan 17 2011 17:11:38 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 17:12:29 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 118370500 -Exiting @ tick 1900831708500 because m5_exit instruction encountered +Exiting @ tick 1900831034500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 39fd478e5..cba8f3d91 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,388 +1,388 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 160492 # Simulator instruction rate (inst/s) -host_mem_usage 293848 # Number of bytes of host memory used -host_seconds 355.10 # Real time elapsed on the host -host_tick_rate 5352987788 # Simulator tick rate (ticks/s) +host_inst_rate 123407 # Simulator instruction rate (inst/s) +host_mem_usage 293584 # Number of bytes of host memory used +host_seconds 461.81 # Real time elapsed on the host +host_tick_rate 4116011383 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56990213 # Number of instructions simulated -sim_seconds 1.900832 # Number of seconds simulated -sim_ticks 1900831708500 # Number of ticks simulated +sim_insts 56990797 # Number of instructions simulated +sim_seconds 1.900831 # Number of seconds simulated +sim_ticks 1900831034500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 5880494 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 11174244 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 27800 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 685606 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 10433425 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 12492393 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 880061 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 7524876 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 920219 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5875698 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 11164328 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 27744 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 509294 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 10430748 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 12489171 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 879952 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 7522146 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 923087 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 78262011 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.636166 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.402915 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 78252168 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.636069 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.403085 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 56998112 72.83% 72.83% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 9312532 11.90% 84.73% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 5431102 6.94% 91.67% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2441098 3.12% 94.79% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1859715 2.38% 97.16% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 630504 0.81% 97.97% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 344653 0.44% 98.41% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 324076 0.41% 98.82% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 920219 1.18% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 56997236 72.84% 72.84% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 9310198 11.90% 84.74% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 5423748 6.93% 91.67% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2443659 3.12% 94.79% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1857092 2.37% 97.16% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 632524 0.81% 97.97% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 342942 0.44% 98.41% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 321682 0.41% 98.82% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 923087 1.18% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 78262011 # Number of insts commited each cycle -system.cpu0.commit.COM:count 49787612 # Number of instructions committed -system.cpu0.commit.COM:loads 7895841 # Number of loads committed +system.cpu0.commit.COM:committed_per_cycle::total 78252168 # Number of insts commited each cycle +system.cpu0.commit.COM:count 49773781 # Number of instructions committed +system.cpu0.commit.COM:loads 7894849 # Number of loads committed system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed -system.cpu0.commit.COM:refs 13320204 # Number of memory references committed +system.cpu0.commit.COM:refs 13318728 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 652972 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 49787612 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 564765 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 7275284 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 46926792 # Number of Instructions Simulated -system.cpu0.committedInsts_total 46926792 # Number of Instructions Simulated -system.cpu0.cpi 2.403365 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.403365 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 178266 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 178266 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.082008 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 652792 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 49773781 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 564764 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 7279166 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 46913211 # Number of Instructions Simulated +system.cpu0.committedInsts_total 46913211 # Number of Instructions Simulated +system.cpu0.cpi 2.403631 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.403631 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 178258 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 178258 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14381.476316 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10555.240699 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 158902 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 158902 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 278514000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108624 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 19364 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19364 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 4366 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158307500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084133 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10558.033333 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 158899 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 158899 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 278411000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108601 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 19359 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19359 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 4359 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158370500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084148 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 14998 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8019167 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8019167 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.581419 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 15000 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 8018067 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8018067 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.598189 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23767.536326 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.786651 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 6641537 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6641537 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 32725024000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.171792 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1377630 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1377630 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 392532 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 23413352500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122843 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6640677 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6640677 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 32719346000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.171786 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1377390 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1377390 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 392262 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 23413327000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122864 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 985098 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920862000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 185115 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 185115 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13269.357045 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 985128 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920863000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 185114 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 185114 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13329.315068 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10269.978106 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 181460 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 181460 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 48499500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019744 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 3655 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3655 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37526500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10326.164384 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 181464 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 181464 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 48652000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019718 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 3650 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3650 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37690500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019718 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 3654 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5224194 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5224194 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 32391.467747 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 3650 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 5223711 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5223711 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 32400.753552 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30578.461362 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30590.522294 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3607293 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3607293 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 52373796592 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.309502 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1616901 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1616901 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1353492 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 8054641929 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050421 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 3606992 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3606992 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 52382913882 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.309496 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1616719 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1616719 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1353304 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 8058002430 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050427 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 263409 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320645998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8778.099961 # average number of cycles each access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 263415 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320187498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8768.456221 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 8.500462 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 83583 # number of cycles access was blocked +system.cpu0.dcache.avg_refs 8.499270 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 83762 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 733699929 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 734463430 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 13243361 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 13241778 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13243361 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 28418.079690 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 13241778 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 28423.233717 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 25204.499798 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 10248830 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 25206.444175 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 10247669 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10248830 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 85098820592 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.226116 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 10247669 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 85102259882 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.226111 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2994531 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2994109 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2994531 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1746024 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 31467994429 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.094274 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2994109 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1745566 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 31471329430 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.094288 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1248507 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1248543 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.973616 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::0 0.973184 # Average percentage of cache occupancy system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 498.491430 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 498.270236 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 13243361 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::0 13241778 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13243361 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 28418.079690 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 13241778 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 28423.233717 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 25204.499798 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 25206.444175 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 10248830 # number of overall hits +system.cpu0.dcache.overall_hits::0 10247669 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10248830 # number of overall hits -system.cpu0.dcache.overall_miss_latency 85098820592 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.226116 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 10247669 # number of overall hits +system.cpu0.dcache.overall_miss_latency 85102259882 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.226111 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2994531 # number of overall misses +system.cpu0.dcache.overall_misses::0 2994109 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2994531 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1746024 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 31467994429 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.094274 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2994109 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1745566 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 31471329430 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.094288 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1248507 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2241507998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1248543 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2241050498 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1246700 # number of replacements -system.cpu0.dcache.sampled_refs 1247212 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1246737 # number of replacements +system.cpu0.dcache.sampled_refs 1247249 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 497.491430 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10601878 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 497.270236 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10600706 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 721554 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33792520 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 33358 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 521061 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 62605463 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 32178672 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 11309201 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1270716 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 100684 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 981617 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 795304 # DTB accesses +system.cpu0.dcache.writebacks 721582 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 33790460 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 33337 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 520850 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 62592464 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 32176672 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 11304141 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1271125 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 100674 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 980894 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 795039 # DTB accesses system.cpu0.dtb.data_acv 690 # DTB access violations -system.cpu0.dtb.data_hits 14242761 # DTB hits -system.cpu0.dtb.data_misses 32467 # DTB misses +system.cpu0.dtb.data_hits 14240441 # DTB hits +system.cpu0.dtb.data_misses 32243 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 599691 # DTB read accesses -system.cpu0.dtb.read_acv 517 # DTB read access violations -system.cpu0.dtb.read_hits 8658240 # DTB read hits -system.cpu0.dtb.read_misses 26670 # DTB read misses -system.cpu0.dtb.write_accesses 195613 # DTB write accesses -system.cpu0.dtb.write_acv 173 # DTB write access violations -system.cpu0.dtb.write_hits 5584521 # DTB write hits -system.cpu0.dtb.write_misses 5797 # DTB write misses -system.cpu0.fetch.Branches 12492393 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 7792591 # Number of cache lines fetched -system.cpu0.fetch.Cycles 20275777 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 374501 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 63694095 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 1162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 745780 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.110766 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 7792591 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 6760555 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.564753 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 79532727 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.800854 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.104099 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 599364 # DTB read accesses +system.cpu0.dtb.read_acv 521 # DTB read access violations +system.cpu0.dtb.read_hits 8656203 # DTB read hits +system.cpu0.dtb.read_misses 26609 # DTB read misses +system.cpu0.dtb.write_accesses 195675 # DTB write accesses +system.cpu0.dtb.write_acv 169 # DTB write access violations +system.cpu0.dtb.write_hits 5584238 # DTB write hits +system.cpu0.dtb.write_misses 5634 # DTB write misses +system.cpu0.fetch.Branches 12489171 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 7790772 # Number of cache lines fetched +system.cpu0.fetch.Cycles 12447663 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 374479 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 63679882 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 30613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 745308 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.110757 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 7790769 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 6755650 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.564728 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 79523293 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.800770 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.103978 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67079150 84.34% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 900735 1.13% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1776168 2.23% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 808150 1.02% 88.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2746406 3.45% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 585611 0.74% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 679507 0.85% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 830147 1.04% 94.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4126853 5.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67075630 84.35% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 894785 1.13% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1774565 2.23% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 813228 1.02% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2745570 3.45% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 583311 0.73% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 681126 0.86% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 829932 1.04% 94.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4125146 5.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79532727 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 7792591 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7792591 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15067.531748 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 79523293 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 7790772 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7790772 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15066.907100 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.722051 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 6935061 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6935061 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 12920860500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.110044 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 857530 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 857530 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 36660 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 9864987500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105340 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12016.512006 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6933292 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6933292 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 12919571500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.110064 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 857480 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 857480 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 36653 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 9863477500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105359 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 820870 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11583.333333 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 820827 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11372.727273 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 8.449643 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 54 # number of cycles access was blocked +system.cpu0.icache.avg_refs 8.447909 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 55 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_mshrs 625500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 7792591 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 7790772 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7792591 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15067.531748 # average overall miss latency +system.cpu0.icache.demand_accesses::total 7790772 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15066.907100 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12017.722051 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 6935061 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12016.512006 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6933292 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6935061 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 12920860500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.110044 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6933292 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 12919571500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.110064 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 857530 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 857480 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 857530 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 36660 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 9864987500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.105340 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 857480 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 36653 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 9863477500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.105359 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 820870 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 820827 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.861229 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 7792591 # number of overall (read+write) accesses +system.cpu0.icache.occ_blocks::0 509.861442 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 7790772 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7792591 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15067.531748 # average overall miss latency +system.cpu0.icache.overall_accesses::total 7790772 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15066.907100 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12017.722051 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12016.512006 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 6935061 # number of overall hits +system.cpu0.icache.overall_hits::0 6933292 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6935061 # number of overall hits -system.cpu0.icache.overall_miss_latency 12920860500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.110044 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6933292 # number of overall hits +system.cpu0.icache.overall_miss_latency 12919571500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.110064 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 857530 # number of overall misses +system.cpu0.icache.overall_misses::0 857480 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 857530 # number of overall misses -system.cpu0.icache.overall_mshr_hits 36660 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 9864987500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.105340 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 857480 # number of overall misses +system.cpu0.icache.overall_mshr_hits 36653 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 9863477500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.105359 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 820870 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 820827 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 820241 # number of replacements -system.cpu0.icache.sampled_refs 820752 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 820200 # number of replacements +system.cpu0.icache.sampled_refs 820711 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.861229 # Cycle average of tags in use -system.cpu0.icache.total_refs 6935061 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 509.861442 # Cycle average of tags in use +system.cpu0.icache.total_refs 6933292 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 24435382000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 109 # number of writebacks -system.cpu0.idleCycles 33249487 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 8091689 # Number of branches executed -system.cpu0.iew.EXEC:nop 3189515 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.446670 # Inst execution rate -system.cpu0.iew.EXEC:refs 14309755 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 5603066 # Number of stores executed +system.cpu0.icache.writebacks 107 # number of writebacks +system.cpu0.idleCycles 33238734 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 8088887 # Number of branches executed +system.cpu0.iew.EXEC:nop 3190702 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.446643 # Inst execution rate +system.cpu0.iew.EXEC:refs 14307235 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 5602635 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 31608779 # num instructions consuming a value -system.cpu0.iew.WB:count 49999865 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.758055 # average fanout of values written-back +system.cpu0.iew.WB:consumers 31606218 # num instructions consuming a value +system.cpu0.iew.WB:count 49988672 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.757998 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 23961182 # num instructions producing a value -system.cpu0.iew.WB:rate 0.443331 # insts written-back per cycle -system.cpu0.iew.WB:sent 50082132 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 711844 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 9016513 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 9135520 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1511943 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 755935 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5842466 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 57173513 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 8706689 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 463253 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 50376392 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 59411 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 23957449 # num instructions producing a value +system.cpu0.iew.WB:rate 0.443311 # insts written-back per cycle +system.cpu0.iew.WB:sent 50070625 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 711853 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 9019183 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 9134564 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1512032 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 755923 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5843380 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 57163450 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 8704600 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 462366 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 50364381 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 59583 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 6975 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1270716 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 547260 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 7004 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1271125 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 547384 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 122212 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 411295 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 10786 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 122021 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 410783 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 10667 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 39006 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 18611 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1239679 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 418103 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 39006 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 331745 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 380099 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.416083 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.416083 # IPC: Total IPC of All Threads +system.cpu0.iew.lsq.thread.0.memOrderViolation 38522 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 18606 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1239715 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 419501 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 38522 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 332064 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 379789 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.416037 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.416037 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35332190 69.50% 69.50% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 55947 0.11% 69.61% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35322205 69.50% 69.50% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 55712 0.11% 69.61% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.61% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.64% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.64% # Type of FU issued @@ -410,80 +410,80 @@ system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 69.65% system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 69.65% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 69.65% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 9005421 17.71% 87.36% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645944 11.11% 98.47% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779180 1.53% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 9003021 17.71% 87.36% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645656 11.11% 98.47% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779190 1.53% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 50839647 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 380083 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007476 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 50826749 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 382289 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007521 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 41221 10.85% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.85% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 225189 59.25% 70.09% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 113673 29.91% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 40958 10.71% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 10.71% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 226307 59.20% 69.91% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 115024 30.09% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 79532727 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639229 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.210023 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 79523293 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639143 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.209985 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 54768244 68.86% 68.86% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 12092577 15.20% 84.07% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 5445890 6.85% 90.91% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 3420529 4.30% 95.22% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 2219923 2.79% 98.01% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 995680 1.25% 99.26% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 437086 0.55% 99.81% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 109289 0.14% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 43509 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 54765331 68.87% 68.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 12086611 15.20% 84.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 5449422 6.85% 90.92% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 3416951 4.30% 95.22% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 2222762 2.80% 98.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 992615 1.25% 99.26% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 434574 0.55% 99.81% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 111342 0.14% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 43685 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 79532727 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.450777 # Inst issue rate -system.cpu0.iq.iqInstsAdded 52261894 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 50839647 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1722104 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 6736109 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 24176 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1157339 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3425002 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 79523293 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.450743 # Inst issue rate +system.cpu0.iq.iqInstsAdded 52250537 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 50826749 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1722211 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 6740578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 24052 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 1157447 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3424469 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 951977 # ITB accesses -system.cpu0.itb.fetch_acv 722 # ITB acv -system.cpu0.itb.fetch_hits 923088 # ITB hits -system.cpu0.itb.fetch_misses 28889 # ITB misses +system.cpu0.itb.fetch_accesses 951927 # ITB accesses +system.cpu0.itb.fetch_acv 732 # ITB acv +system.cpu0.itb.fetch_hits 922973 # ITB hits +system.cpu0.itb.fetch_misses 28954 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -500,7 +500,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.22% # nu system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 147043 90.75% 93.03% # number of callpals executed +system.cpu0.kern.callpal::swpipl 147045 90.75% 93.03% # number of callpals executed system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed @@ -509,45 +509,45 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.96% # nu system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 162035 # number of callpals executed +system.cpu0.kern.callpal::total 162037 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.hwrei 176106 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6625 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 6624 # number of quiesce instructions executed system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 89357 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 153911 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 89359 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 153913 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862701571500 97.99% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96288500 0.01% 98.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398425500 0.02% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 103369500 0.01% 98.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37531203000 1.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900830858000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1862706719500 97.99% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96293500 0.01% 98.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398446500 0.02% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 103381000 0.01% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37525343500 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900830184000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682800 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1170 -system.cpu0.kern.mode_good::user 1171 +system.cpu0.kern.ipl_used::31 0.682785 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1172 +system.cpu0.kern.mode_good::user 1173 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1171 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 6890 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.169762 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170102 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1898856944500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1973905500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1898860791500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1969384500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3288 # number of times the context was actually changed system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed @@ -580,503 +580,503 @@ system.cpu0.kern.syscall::132 1 0.50% 98.51% # nu system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 201 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2309039 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1917455 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 9135520 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5842466 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 112782214 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 12781389 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 33989509 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 1007909 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 33583011 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1370380 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 43256 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 72564759 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 59338809 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 39990302 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 11042113 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1270716 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3987723 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 6000791 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 16867773 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1393581 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 10085074 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 207606 # count of temporary serializing insts renamed -system.cpu0.timesIdled 1187595 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.memDep0.conflictingLoads 2324520 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1920330 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 9134564 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5843380 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 112762027 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 12784616 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 33979042 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 1006695 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 33581656 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1371330 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 43310 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 72537525 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 59326371 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 39979107 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 11035754 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1271125 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3987965 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 6000063 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 16862175 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1393641 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 10087757 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 207582 # count of temporary serializing insts renamed +system.cpu0.timesIdled 1187239 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1159628 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 2701076 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 8300 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 172219 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 2481214 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 2994712 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 209821 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 1517871 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 197774 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1159872 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 2699541 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 8252 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 107435 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 2484356 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 2997970 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 209804 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 1520810 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 200192 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 17831958 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.593915 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.406567 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 17838555 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.594502 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.408069 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 13448737 75.42% 75.42% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 2070572 11.61% 87.03% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 799926 4.49% 91.52% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 567078 3.18% 94.70% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 394341 2.21% 96.91% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 151842 0.85% 97.76% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 111575 0.63% 98.39% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 90113 0.51% 98.89% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 197774 1.11% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 13455309 75.43% 75.43% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 2068240 11.59% 87.02% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 796982 4.47% 91.49% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 568404 3.19% 94.68% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 398869 2.24% 96.91% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 150882 0.85% 97.76% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 111519 0.63% 98.38% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 88158 0.49% 98.88% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 200192 1.12% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 17831958 # Number of insts commited each cycle -system.cpu1.commit.COM:count 10590665 # Number of instructions committed -system.cpu1.commit.COM:loads 1991024 # Number of loads committed -system.cpu1.commit.COM:membars 52740 # Number of memory barriers committed -system.cpu1.commit.COM:refs 3374947 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 17838555 # Number of insts commited each cycle +system.cpu1.commit.COM:count 10605058 # Number of instructions committed +system.cpu1.commit.COM:loads 1991974 # Number of loads committed +system.cpu1.commit.COM:membars 52733 # Number of memory barriers committed +system.cpu1.commit.COM:refs 3376359 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 164356 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 10590665 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 163015 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 1719784 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 10063421 # Number of Instructions Simulated -system.cpu1.committedInsts_total 10063421 # Number of Instructions Simulated -system.cpu1.cpi 1.950737 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.950737 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 46382 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46382 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11099.301842 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 164468 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 10605058 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 163004 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 1721791 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 10077586 # Number of Instructions Simulated +system.cpu1.committedInsts_total 10077586 # Number of Instructions Simulated +system.cpu1.cpi 1.948890 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.948890 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 46378 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46378 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11069.539376 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8021.283727 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 39650 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 39650 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 74720500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145143 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 6732 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 6732 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 765 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47863000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128649 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7993.965806 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 39648 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 39648 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 74498000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145112 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 6730 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 6730 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 764 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47692000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128639 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 5967 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 2063263 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2063263 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15045.752696 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 5966 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2062902 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2062902 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15016.821540 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11684.073615 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11679.389313 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 1869340 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1869340 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 2917717500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.093989 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 193923 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 193923 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 98779 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 1111669500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046113 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 1868657 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1868657 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 2916942500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.094161 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 194245 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 194245 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 99139 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 1110780000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046103 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 95144 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses 95106 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 43195 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 43195 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13108.977686 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_accesses::0 43196 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 43196 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13130.603783 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10107.291126 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 39341 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 39341 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 50522000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089223 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 3854 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3854 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 38953500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089223 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10135.856884 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 39337 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 39337 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 50671000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089337 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 3859 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3859 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39094000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089291 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 3854 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 1334339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1334339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 21230.266809 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 3857 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1334800 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1334800 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 21227.985433 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18781.127505 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18769.279348 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1084932 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1084932 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 5294977154 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.186914 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 249407 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 249407 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 200954 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 910001971 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036312 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1085325 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1085325 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 5295851666 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.186901 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 249475 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 249475 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 201005 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 909746970 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036313 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 48453 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377711000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9964.987699 # average number of cycles each access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 48470 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377654500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9972.984645 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 22.877704 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 5284 # number of cycles access was blocked +system.cpu1.dcache.avg_refs 22.879556 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 5275 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 52654995 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 52607494 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 3397602 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 3397702 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3397602 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 18525.014445 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 3397702 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 18508.956473 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14078.786263 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 2954272 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 14072.874088 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 2953982 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2954272 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 8212694654 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.130483 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 2953982 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 8212794166 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.130594 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 443330 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 443720 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 443330 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 299733 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 2021671471 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.042264 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 443720 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 300144 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 2020526970 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.042257 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 143597 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 143576 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.933246 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 477.822051 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 3397602 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.933238 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 477.817937 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 3397702 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3397602 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 18525.014445 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 3397702 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 18508.956473 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14078.786263 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14072.874088 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 2954272 # number of overall hits +system.cpu1.dcache.overall_hits::0 2953982 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 2954272 # number of overall hits -system.cpu1.dcache.overall_miss_latency 8212694654 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.130483 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 2953982 # number of overall hits +system.cpu1.dcache.overall_miss_latency 8212794166 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.130594 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 443330 # number of overall misses +system.cpu1.dcache.overall_misses::0 443720 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 443330 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 299733 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 2021671471 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.042264 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 443720 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 300144 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 2020526970 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.042257 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 143597 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 395388500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 143576 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 395332000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 132546 # number of replacements -system.cpu1.dcache.sampled_refs 132940 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 132522 # number of replacements +system.cpu1.dcache.sampled_refs 132916 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 477.822051 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3041362 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1877659740000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 88702 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 6966662 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 7945 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 127784 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 13937245 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 8263002 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 2503476 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 305841 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 23696 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 98817 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 453673 # DTB accesses +system.cpu1.dcache.tagsinuse 477.817937 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3041059 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1877659429000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 88703 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 6965197 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 7952 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 127936 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 13953075 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 8268454 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 2505615 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 305805 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 23745 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 99288 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 453627 # DTB accesses system.cpu1.dtb.data_acv 183 # DTB access violations -system.cpu1.dtb.data_hits 3613751 # DTB hits -system.cpu1.dtb.data_misses 13007 # DTB misses +system.cpu1.dtb.data_hits 3614601 # DTB hits +system.cpu1.dtb.data_misses 12965 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 322326 # DTB read accesses -system.cpu1.dtb.read_acv 82 # DTB read access violations -system.cpu1.dtb.read_hits 2187602 # DTB read hits -system.cpu1.dtb.read_misses 10512 # DTB read misses -system.cpu1.dtb.write_accesses 131347 # DTB write accesses -system.cpu1.dtb.write_acv 101 # DTB write access violations -system.cpu1.dtb.write_hits 1426149 # DTB write hits -system.cpu1.dtb.write_misses 2495 # DTB write misses -system.cpu1.fetch.Branches 2994712 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 1675694 # Number of cache lines fetched -system.cpu1.fetch.Cycles 4319661 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 103833 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 14189706 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 191595 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.152550 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 1675694 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 1369449 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.722818 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 18137799 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.782328 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.130924 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 321686 # DTB read accesses +system.cpu1.dtb.read_acv 80 # DTB read access violations +system.cpu1.dtb.read_hits 2187439 # DTB read hits +system.cpu1.dtb.read_misses 10558 # DTB read misses +system.cpu1.dtb.write_accesses 131941 # DTB write accesses +system.cpu1.dtb.write_acv 103 # DTB write access violations +system.cpu1.dtb.write_hits 1427162 # DTB write hits +system.cpu1.dtb.write_misses 2407 # DTB write misses +system.cpu1.fetch.Branches 2997970 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 1676515 # Number of cache lines fetched +system.cpu1.fetch.Cycles 2637646 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 103832 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 14205200 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 9114 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 191574 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.152645 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 1676514 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 1369676 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.723275 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 18144360 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.782899 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.130950 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 15502694 85.47% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 211332 1.17% 86.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 324186 1.79% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 198526 1.09% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 376340 2.07% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 125878 0.69% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 169328 0.93% 93.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 252414 1.39% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 977101 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15506714 85.46% 85.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 209351 1.15% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 321604 1.77% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 202250 1.11% 89.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 379744 2.09% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 126923 0.70% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 169833 0.94% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 250226 1.38% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 977715 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 18137799 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 1675694 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1675694 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14669.843213 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 18144360 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 1676515 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1676515 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14673.731413 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11629.039136 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 1411833 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1411833 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 3870799500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.157464 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 263861 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 263861 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 8268 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 2972301000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152530 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.822702 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 1412481 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1412481 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 3874364000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.157490 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 264034 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 264034 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 8194 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 2975118000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152602 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 255593 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 4444.444444 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 255840 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.524987 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu1.icache.avg_refs 5.522142 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 40000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 1675694 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 1676515 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1675694 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14669.843213 # average overall miss latency +system.cpu1.icache.demand_accesses::total 1676515 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14673.731413 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11629.039136 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 1411833 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11628.822702 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 1412481 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1411833 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 3870799500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.157464 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 1412481 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 3874364000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.157490 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 263861 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 264034 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 263861 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 8268 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 2972301000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.152530 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 264034 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 8194 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 2975118000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.152602 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 255593 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 255840 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.900435 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 461.022612 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 1675694 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.900434 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 461.022394 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 1676515 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1675694 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14669.843213 # average overall miss latency +system.cpu1.icache.overall_accesses::total 1676515 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14673.731413 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11629.039136 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11628.822702 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 1411833 # number of overall hits +system.cpu1.icache.overall_hits::0 1412481 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1411833 # number of overall hits -system.cpu1.icache.overall_miss_latency 3870799500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.157464 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 1412481 # number of overall hits +system.cpu1.icache.overall_miss_latency 3874364000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.157490 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 263861 # number of overall misses +system.cpu1.icache.overall_misses::0 264034 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 263861 # number of overall misses -system.cpu1.icache.overall_mshr_hits 8268 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 2972301000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.152530 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 264034 # number of overall misses +system.cpu1.icache.overall_mshr_hits 8194 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 2975118000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.152602 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 255593 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 255840 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 255024 # number of replacements -system.cpu1.icache.sampled_refs 255536 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 255273 # number of replacements +system.cpu1.icache.sampled_refs 255785 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 461.022612 # Cycle average of tags in use -system.cpu1.icache.total_refs 1411833 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1897916222000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 461.022394 # Cycle average of tags in use +system.cpu1.icache.total_refs 1412481 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1897915849000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 13 # number of writebacks -system.cpu1.idleCycles 1493284 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 1627599 # Number of branches executed -system.cpu1.iew.EXEC:nop 601660 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.551671 # Inst execution rate -system.cpu1.iew.EXEC:refs 3643304 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 1435691 # Number of stores executed +system.cpu1.idleCycles 1495744 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 1630347 # Number of branches executed +system.cpu1.iew.EXEC:nop 601729 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.552052 # Inst execution rate +system.cpu1.iew.EXEC:refs 3644132 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 1436628 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 6256127 # num instructions consuming a value -system.cpu1.iew.WB:count 10722196 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.736602 # average fanout of values written-back +system.cpu1.iew.WB:consumers 6274106 # num instructions consuming a value +system.cpu1.iew.WB:count 10735003 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.735138 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 4608274 # num instructions producing a value -system.cpu1.iew.WB:rate 0.546185 # insts written-back per cycle -system.cpu1.iew.WB:sent 10745464 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 178521 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 256730 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 2308752 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 500484 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 209358 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 1509923 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 12393438 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 2207613 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 106928 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 10829897 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 2615 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 4612335 # num instructions producing a value +system.cpu1.iew.WB:rate 0.546586 # insts written-back per cycle +system.cpu1.iew.WB:sent 10758148 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 178810 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 256636 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 2309588 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 500342 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 209309 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 1512714 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 12409933 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 2207504 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 107468 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 10842361 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 2486 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 4833 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 305841 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 10301 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 4828 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 305805 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 10156 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 22559 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 67759 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 22318 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 68189 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 2236 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 10819 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 10653 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 380 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 317728 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 126000 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 10819 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 104538 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 73983 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.512627 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.512627 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3525 0.03% 0.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6858697 62.71% 62.74% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 17938 0.16% 62.91% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.01% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.01% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.01% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.01% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282943 20.87% 83.90% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1452642 13.28% 97.18% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307886 2.82% 100.00% # Type of FU issued +system.cpu1.iew.lsq.thread.0.squashedLoads 317614 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 128329 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 10653 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 104816 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 73994 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.513113 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.513113 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3524 0.03% 0.03% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6870860 62.75% 62.78% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 18138 0.17% 62.95% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.95% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.05% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.05% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.05% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.05% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282503 20.85% 83.91% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1453754 13.28% 97.19% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307856 2.81% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 10936825 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 157834 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.014431 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 10949829 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 154910 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.014147 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 3969 2.51% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.51% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 94191 59.68% 62.19% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 59674 37.81% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 4092 2.64% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.64% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 90881 58.67% 61.31% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 59937 38.69% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 18137799 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.602985 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.207807 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 18144360 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.603484 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.209438 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 12914156 71.20% 71.20% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 2567061 14.15% 85.35% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 1068417 5.89% 91.24% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 686600 3.79% 95.03% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 525581 2.90% 97.93% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 238380 1.31% 99.24% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 93711 0.52% 99.76% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 34504 0.19% 99.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 9389 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 12920190 71.21% 71.21% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 2565455 14.14% 85.35% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 1066502 5.88% 91.22% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 689185 3.80% 95.02% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 526783 2.90% 97.93% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 236336 1.30% 99.23% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 93675 0.52% 99.75% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 36919 0.20% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 9315 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 18137799 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.557118 # Inst issue rate -system.cpu1.iq.iqInstsAdded 11235835 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 10936825 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 555943 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 1653815 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 10214 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 392928 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 848491 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 18144360 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.557524 # Inst issue rate +system.cpu1.iq.iqInstsAdded 11252421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 10949829 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 555783 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 1655590 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 10152 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 392779 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 854299 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 449298 # ITB accesses -system.cpu1.itb.fetch_acv 268 # ITB acv -system.cpu1.itb.fetch_hits 440704 # ITB hits -system.cpu1.itb.fetch_misses 8594 # ITB misses +system.cpu1.itb.fetch_accesses 448461 # ITB accesses +system.cpu1.itb.fetch_acv 279 # ITB acv +system.cpu1.itb.fetch_hits 439821 # ITB hits +system.cpu1.itb.fetch_misses 8640 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1092,7 +1092,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # nu system.cpu1.kern.callpal::swpctx 1450 2.54% 2.99% # number of callpals executed system.cpu1.kern.callpal::tbi 12 0.02% 3.01% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed -system.cpu1.kern.callpal::swpipl 49369 86.50% 89.53% # number of callpals executed +system.cpu1.kern.callpal::swpipl 49364 86.50% 89.53% # number of callpals executed system.cpu1.kern.callpal::rdps 2383 4.18% 93.70% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.71% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 93.71% # number of callpals executed @@ -1102,42 +1102,42 @@ system.cpu1.kern.callpal::rti 3352 5.87% 99.60% # nu system.cpu1.kern.callpal::callsys 187 0.33% 99.92% # number of callpals executed system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 57071 # number of callpals executed +system.cpu1.kern.callpal::total 57066 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 64910 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 64904 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2510 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 20666 37.58% 37.58% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 3.49% 41.07% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::0 20664 37.58% 37.58% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 3.50% 41.07% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 351 0.64% 41.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 32056 58.29% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 54995 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 20159 47.72% 47.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 32053 58.29% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 54990 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 20157 47.72% 47.72% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1922 4.55% 52.28% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 19808 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 42240 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870775538500 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 348024500 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 137644500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29219363500 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900480571000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.975467 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 19806 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 42236 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870770703000 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 347961500 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 137588500 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29223568000 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900479821000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.975465 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.617919 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 850 -system.cpu1.kern.mode_good::user 574 +system.cpu1.kern.ipl_used::31 0.617914 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 849 +system.cpu1.kern.mode_good::user 573 system.cpu1.kern.mode_good::idle 276 system.cpu1.kern.mode_switch::kernel 1766 # number of protection mode switches -system.cpu1.kern.mode_switch::user 574 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2543 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.481314 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch::user 573 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2541 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.480747 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.108533 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.589847 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6310376000 0.33% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1022366000 0.05% 0.39% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893135370000 99.61% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.108619 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.589366 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6317362000 0.33% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1020701000 0.05% 0.39% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893129288000 99.61% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1451 # number of times the context was actually changed system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed @@ -1162,29 +1162,29 @@ system.cpu1.kern.syscall::92 2 1.60% 96.80% # nu system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 125 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 490785 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 414407 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 2308752 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1509923 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 19631083 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 523690 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 7148714 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 34540 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 8495610 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 254592 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 15458 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 15445784 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 12915573 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 8478574 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 2357052 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 305841 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 801048 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 1329860 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 5654556 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 515569 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2305021 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 52779 # count of temporary serializing insts renamed -system.cpu1.timesIdled 194610 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.memDep0.conflictingLoads 496033 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 413880 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 2309588 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1512714 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 19640104 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 522822 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 7159583 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 32718 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 8500925 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 256778 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 15506 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 15473473 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 12930857 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 8489204 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 2359874 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 305805 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 801183 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 1329621 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 5653749 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 515468 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2303190 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 52722 # count of temporary serializing insts renamed +system.cpu1.timesIdled 194766 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1200,14 +1200,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115273.244186 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115267.430233 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63273.244186 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19826998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63267.430233 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19825998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 172 # number of ReadReq misses system.iocache.ReadReq_misses::total 172 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10882998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10881998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -1215,37 +1215,37 @@ system.iocache.ReadReq_mshr_misses 172 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137691.995716 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137704.871149 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85688.414469 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5721377806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85701.289902 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5721912806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3560524998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561059998 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6177.748159 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6175.549096 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64613068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64590068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137599.578276 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137612.376666 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85596.011792 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85608.810181 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5741204804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5741738804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -1253,7 +1253,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41724 # number of demand (read+write) misses system.iocache.demand_misses::total 41724 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3571407996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571941996 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -1261,20 +1261,20 @@ system.iocache.demand_mshr_misses 41724 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.029207 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.467307 # Average occupied blocks per context +system.iocache.occ_%::1 0.029206 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.467303 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137599.578276 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137612.376666 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85596.011792 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85608.810181 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5741204804 # number of overall miss cycles +system.iocache.overall_miss_latency 5741738804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -1282,7 +1282,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41724 # number of overall misses system.iocache.overall_misses::total 41724 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3571407996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571941996 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -1292,196 +1292,196 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41692 # number of replacements system.iocache.sampled_refs 41708 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.467307 # Cycle average of tags in use +system.iocache.tagsinuse 0.467303 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1711286220000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1711286190000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 257314 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 42271 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 299585 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 55984.756831 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 837468.637532 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 257294 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 42294 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 299588 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 55984.033368 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 838025.398663 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40322.708602 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 140934 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 34491 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 175425 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6515506000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.452288 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.184051 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 116380 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 7780 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124160 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5006467500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.482523 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 2.937238 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40323.668210 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 140895 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 34518 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 175413 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6516485500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.452397 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.183856 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 116399 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 7776 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124175 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 5007191500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.482619 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 2.935996 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 124160 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1807452 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 343469 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2150921 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52799.023345 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3689312.055109 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 124175 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1807450 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 343665 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2151115 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52801.925207 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3681603.345555 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40018.019200 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40018.264766 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1503148 # number of ReadReq hits -system.l2c.ReadReq_hits::1 339114 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1842262 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16066954000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.168361 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.012679 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 304304 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4355 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308659 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1503171 # number of ReadReq hits +system.l2c.ReadReq_hits::1 339301 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1842472 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16066517000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.168347 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.012698 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304279 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4364 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308643 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12351281500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.170761 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.898605 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12350717000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.170753 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.898046 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 308643 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840474000 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 607 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 600 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1207 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 4817.117117 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 4657.665505 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 308627 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840465500 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 609 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 601 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1210 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 4879.928315 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 4727.430556 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40013.728964 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 52 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_latency 2673500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 0.914333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.956667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 555 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 574 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1129 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 45175500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.859967 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.881667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40008.377425 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::0 51 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 25 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 76 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_latency 2723000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.916256 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.958403 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 558 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 576 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1134 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 45369500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.862069 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.886855 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 1129 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 2880 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 1625 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4505 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 5822.515585 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 12443.573668 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 1134 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 2885 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 1622 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4507 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 5855.677656 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 12557.737628 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.987260 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 153 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::0 155 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::1 349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 502 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 15878000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.946875 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.785231 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 2727 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 1276 # number of UpgradeReq misses +system.l2c.UpgradeReq_hits::total 504 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 15986000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.946274 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.784834 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 2730 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 1273 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 4003 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 160188000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.389931 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.463385 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.387522 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.467941 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 4003 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1533346998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 810378 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 810378 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 810378 # number of Writeback hits -system.l2c.Writeback_hits::total 810378 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1532818498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 810405 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 810405 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 810405 # number of Writeback hits +system.l2c.Writeback_hits::total 810405 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.651210 # Average number of references to valid blocks. +system.l2c.avg_refs 5.657708 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2064766 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 385740 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2064744 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 385959 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2450506 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 53680.339637 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1860936.135146 # average overall miss latency +system.l2c.demand_accesses::total 2450703 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 53682.394848 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1860214.373970 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40105.426718 # average overall mshr miss latency -system.l2c.demand_hits::0 1644082 # number of demand (read+write) hits -system.l2c.demand_hits::1 373605 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40105.887912 # average overall mshr miss latency +system.l2c.demand_hits::0 1644066 # number of demand (read+write) hits +system.l2c.demand_hits::1 373819 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2017687 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22582460000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.203744 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.031459 # miss rate for demand accesses +system.l2c.demand_hits::total 2017885 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22583002500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.203743 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.031454 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 420684 # number of demand (read+write) misses -system.l2c.demand_misses::1 12135 # number of demand (read+write) misses +system.l2c.demand_misses::0 420678 # number of demand (read+write) misses +system.l2c.demand_misses::1 12140 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 432819 # number of demand (read+write) misses +system.l2c.demand_misses::total 432818 # number of demand (read+write) misses system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17357749000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.209614 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.122007 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 17357908500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.209615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.121368 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 432803 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 432802 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.187928 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.005741 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.351843 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12316.028373 # Average occupied blocks per context -system.l2c.occ_blocks::1 376.255092 # Average occupied blocks per context -system.l2c.occ_blocks::2 23058.373739 # Average occupied blocks per context -system.l2c.overall_accesses::0 2064766 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 385740 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.187715 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.005740 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.351851 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12302.114841 # Average occupied blocks per context +system.l2c.occ_blocks::1 376.171902 # Average occupied blocks per context +system.l2c.occ_blocks::2 23058.891094 # Average occupied blocks per context +system.l2c.overall_accesses::0 2064744 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 385959 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2450506 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 53680.339637 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1860936.135146 # average overall miss latency +system.l2c.overall_accesses::total 2450703 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 53682.394848 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1860214.373970 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40105.426718 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40105.887912 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1644082 # number of overall hits -system.l2c.overall_hits::1 373605 # number of overall hits +system.l2c.overall_hits::0 1644066 # number of overall hits +system.l2c.overall_hits::1 373819 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2017687 # number of overall hits -system.l2c.overall_miss_latency 22582460000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.203744 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.031459 # miss rate for overall accesses +system.l2c.overall_hits::total 2017885 # number of overall hits +system.l2c.overall_miss_latency 22583002500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.203743 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.031454 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 420684 # number of overall misses -system.l2c.overall_misses::1 12135 # number of overall misses +system.l2c.overall_misses::0 420678 # number of overall misses +system.l2c.overall_misses::1 12140 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 432819 # number of overall misses +system.l2c.overall_misses::total 432818 # number of overall misses system.l2c.overall_mshr_hits 16 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17357749000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.209614 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.122007 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 17357908500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.209615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.121368 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 432803 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2373820998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 432802 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2373283998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 395553 # number of replacements +system.l2c.replacements 395562 # number of replacements system.l2c.sampled_refs 431632 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 35750.657204 # Cycle average of tags in use -system.l2c.total_refs 2439243 # Total number of references to valid blocks. +system.l2c.tagsinuse 35737.177838 # Cycle average of tags in use +system.l2c.total_refs 2442048 # Total number of references to valid blocks. system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 121365 # number of writebacks +system.l2c.writebacks 121361 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 5bcb96563..cd15fbaad 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Dec 1 2010 12:54:21 -M5 revision 9fcc50998835+ 7780+ default qtip tip set.patch qbase -M5 started Dec 3 2010 12:04:42 +M5 compiled Jan 17 2011 17:11:38 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 17:11:41 M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1865725201500 because m5_exit instruction encountered +Exiting @ tick 1866702838500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 8a396ee2c..549afdb19 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 175308 # Simulator instruction rate (inst/s) -host_mem_usage 291488 # Number of bytes of host memory used -host_seconds 302.62 # Real time elapsed on the host -host_tick_rate 6165281708 # Simulator tick rate (ticks/s) +host_inst_rate 145689 # Simulator instruction rate (inst/s) +host_mem_usage 291364 # Number of bytes of host memory used +host_seconds 364.14 # Real time elapsed on the host +host_tick_rate 5126322811 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53051410 # Number of instructions simulated -sim_seconds 1.865725 # Number of seconds simulated -sim_ticks 1865725201500 # Number of ticks simulated +sim_insts 53051251 # Number of instructions simulated +sim_seconds 1.866703 # Number of seconds simulated +sim_ticks 1866702838500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6623532 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12798498 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 40602 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 812765 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11935951 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14337786 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1014820 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8457292 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1010049 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6623157 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12789444 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 40569 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 601028 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11937575 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14339384 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1014923 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8457250 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 1007675 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 89220035 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.630402 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.393670 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 89231545 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.630319 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.393269 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 65107302 72.97% 72.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10633646 11.92% 84.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6059339 6.79% 91.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2842196 3.19% 94.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2097639 2.35% 97.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 698987 0.78% 98.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 396440 0.44% 98.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 374437 0.42% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1010049 1.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 65110491 72.97% 72.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10643752 11.93% 84.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 6057329 6.79% 91.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 2842358 3.19% 94.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2098441 2.35% 97.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 701144 0.79% 98.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 394504 0.44% 98.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 375851 0.42% 98.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 1007675 1.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 89220035 # Number of insts commited each cycle -system.cpu.commit.COM:count 56244494 # Number of instructions committed -system.cpu.commit.COM:loads 9107208 # Number of loads committed -system.cpu.commit.COM:membars 227971 # Number of memory barriers committed -system.cpu.commit.COM:refs 15496285 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 89231545 # Number of insts commited each cycle +system.cpu.commit.COM:count 56244349 # Number of instructions committed +system.cpu.commit.COM:loads 9107235 # Number of loads committed +system.cpu.commit.COM:membars 227951 # Number of memory barriers committed +system.cpu.commit.COM:refs 15496318 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 771538 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56244494 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667580 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8696245 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53051410 # Number of Instructions Simulated -system.cpu.committedInsts_total 53051410 # Number of Instructions Simulated -system.cpu.cpi 2.356931 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.356931 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 215724 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 215724 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14717.635433 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 771510 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56244349 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667563 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 8699299 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53051251 # Number of Instructions Simulated +system.cpu.committedInsts_total 53051251 # Number of Instructions Simulated +system.cpu.cpi 2.358137 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.358137 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 215722 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 215722 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14725.540425 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.423892 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 193462 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 193462 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 327644000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103197 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4800 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207438500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080946 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11882.875143 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 193471 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 193471 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 327658000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103147 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22251 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22251 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4791 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207475000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080938 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17462 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9298342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9298342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 22727.861188 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17460 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9297964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9297964 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 22717.133732 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.930840 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22779.439279 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7723201 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7723201 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 35799586000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.169400 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1575141 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1575141 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 491284 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24690187500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116565 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7723736 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7723736 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 35761948000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.169309 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1574228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1574228 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 490302 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24691226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116577 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1083857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906002000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219691 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219691 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.ReadReq_mshr_misses 1083926 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 905134500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219685 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219685 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 219688 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219688 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::0 219682 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219682 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_miss_latency 42000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_rate::0 0.000014 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_misses::0 3 # number of StoreCondReq misses @@ -104,283 +104,283 @@ system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000014 system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_misses 3 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6154235 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6154235 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 29744.201377 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses::0 6154252 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6154252 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 29747.302403 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28089.748800 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28091.080381 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4298938 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4298938 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 55184327582 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.301467 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 1855297 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1855297 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1555651 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 8416980869 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048689 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 4299090 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4299090 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 55186065021 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.301444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 1855162 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1855162 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1555538 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8416761868 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048686 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 299646 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235741498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8981.209245 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 299624 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235207998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8963.151072 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.877118 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 83266 # number of cycles access was blocked +system.cpu.dcache.avg_refs 8.877326 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 83371 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 747829369 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 747266868 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15452577 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15452216 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15452577 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26522.535484 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15452216 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26520.172107 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23929.957773 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 12022139 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23929.737536 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 12022826 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12022139 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 90983913582 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.221998 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 12022826 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 90948013021 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.221935 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3430438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3429390 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3430438 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2046935 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33107168369 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.089532 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3429390 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2045840 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33107988368 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.089537 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1383503 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1383550 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995488 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15452577 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.995490 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15452216 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15452577 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26522.535484 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15452216 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26520.172107 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23929.957773 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23929.737536 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 12022139 # number of overall hits +system.cpu.dcache.overall_hits::0 12022826 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 12022139 # number of overall hits -system.cpu.dcache.overall_miss_latency 90983913582 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.221998 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 12022826 # number of overall hits +system.cpu.dcache.overall_miss_latency 90948013021 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.221935 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3430438 # number of overall misses +system.cpu.dcache.overall_misses::0 3429390 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3430438 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2046935 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33107168369 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.089532 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3429390 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2045840 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33107988368 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.089537 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1383503 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2141743498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1383550 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140342498 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1400321 # number of replacements -system.cpu.dcache.sampled_refs 1400833 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1400366 # number of replacements +system.cpu.dcache.sampled_refs 1400878 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995488 # Cycle average of tags in use -system.cpu.dcache.total_refs 12435360 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.995490 # Cycle average of tags in use +system.cpu.dcache.total_refs 12436050 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 832778 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 37796755 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42128 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 613699 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 71391245 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37490796 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12847951 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1515207 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134411 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1084532 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1236239 # DTB accesses -system.cpu.dtb.data_acv 812 # DTB access violations -system.cpu.dtb.data_hits 16594781 # DTB hits -system.cpu.dtb.data_misses 46795 # DTB misses +system.cpu.dcache.writebacks 832764 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 37803166 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42143 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 613837 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 71397647 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37493968 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12849862 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1515496 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134350 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1084548 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1235511 # DTB accesses +system.cpu.dtb.data_acv 814 # DTB access violations +system.cpu.dtb.data_hits 16593720 # DTB hits +system.cpu.dtb.data_misses 46888 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 911340 # DTB read accesses -system.cpu.dtb.read_acv 579 # DTB read access violations -system.cpu.dtb.read_hits 10007690 # DTB read hits -system.cpu.dtb.read_misses 38589 # DTB read misses -system.cpu.dtb.write_accesses 324899 # DTB write accesses -system.cpu.dtb.write_acv 233 # DTB write access violations -system.cpu.dtb.write_hits 6587091 # DTB write hits -system.cpu.dtb.write_misses 8206 # DTB write misses -system.cpu.fetch.Branches 14337786 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8855787 # Number of cache lines fetched -system.cpu.fetch.Cycles 23008954 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 454021 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 72656034 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 884311 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.114667 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8855787 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7638352 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.581069 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 90735242 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.800748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.110037 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 910670 # DTB read accesses +system.cpu.dtb.read_acv 580 # DTB read access violations +system.cpu.dtb.read_hits 10006545 # DTB read hits +system.cpu.dtb.read_misses 38646 # DTB read misses +system.cpu.dtb.write_accesses 324841 # DTB write accesses +system.cpu.dtb.write_acv 234 # DTB write access violations +system.cpu.dtb.write_hits 6587175 # DTB write hits +system.cpu.dtb.write_misses 8242 # DTB write misses +system.cpu.fetch.Branches 14339384 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8856318 # Number of cache lines fetched +system.cpu.fetch.Cycles 14115387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 454337 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 72663163 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 43087 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 884394 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.114621 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8856315 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7638080 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.580831 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 90747041 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.800722 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.110012 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76622057 84.45% 84.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1044700 1.15% 85.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1968700 2.17% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 923179 1.02% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2984209 3.29% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 647959 0.71% 92.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 776741 0.86% 93.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1074256 1.18% 94.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4693441 5.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76631654 84.45% 84.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1046048 1.15% 85.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1970042 2.17% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 921005 1.01% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2984540 3.29% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 648959 0.72% 92.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 776516 0.86% 93.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1074251 1.18% 94.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4694026 5.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 90735242 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8855787 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8855787 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14954.156504 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 90747041 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8856318 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8856318 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14954.328072 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.651524 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7815574 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7815574 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15555508000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.117461 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1040213 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1040213 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 47670 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11849625000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112078 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.426022 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7816051 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7816051 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15556494000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.117460 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1040267 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1040267 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 47648 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11850308500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 992543 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 992619 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs 12375 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.875775 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 7.875653 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 693000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8855787 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8856318 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8855787 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14954.156504 # average overall miss latency +system.cpu.icache.demand_accesses::total 8856318 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14954.328072 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11938.651524 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7815574 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11938.426022 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7816051 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7815574 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15555508000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.117461 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7816051 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15556494000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.117460 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1040213 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1040267 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1040213 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 47670 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11849625000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.112078 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1040267 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 47648 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11850308500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.112080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 992543 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 992619 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995724 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.810496 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8855787 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995726 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.811601 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8856318 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8855787 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14954.156504 # average overall miss latency +system.cpu.icache.overall_accesses::total 8856318 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14954.328072 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11938.651524 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11938.426022 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7815574 # number of overall hits +system.cpu.icache.overall_hits::0 7816051 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7815574 # number of overall hits -system.cpu.icache.overall_miss_latency 15555508000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.117461 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7816051 # number of overall hits +system.cpu.icache.overall_miss_latency 15556494000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.117460 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1040213 # number of overall misses +system.cpu.icache.overall_misses::0 1040267 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1040213 # number of overall misses -system.cpu.icache.overall_mshr_hits 47670 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11849625000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.112078 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1040267 # number of overall misses +system.cpu.icache.overall_mshr_hits 47648 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11850308500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.112080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 992543 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 992619 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 991845 # number of replacements -system.cpu.icache.sampled_refs 992356 # Sample count of references to valid blocks. +system.cpu.icache.replacements 991921 # number of replacements +system.cpu.icache.sampled_refs 992432 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.810496 # Cycle average of tags in use -system.cpu.icache.total_refs 7815573 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 509.811601 # Cycle average of tags in use +system.cpu.icache.total_refs 7816050 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 24432989000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 92 # number of writebacks -system.cpu.idleCycles 34303252 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9120523 # Number of branches executed -system.cpu.iew.EXEC:nop 3586903 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.457009 # Inst execution rate -system.cpu.iew.EXEC:refs 16684584 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6610209 # Number of stores executed +system.cpu.idleCycles 34355081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9120774 # Number of branches executed +system.cpu.iew.EXEC:nop 3587033 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.456767 # Inst execution rate +system.cpu.iew.EXEC:refs 16683612 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6610329 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 35266489 # num instructions consuming a value -system.cpu.iew.WB:count 56698013 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757126 # average fanout of values written-back +system.cpu.iew.WB:consumers 35257849 # num instructions consuming a value +system.cpu.iew.WB:count 56697227 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.757274 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26701175 # num instructions producing a value -system.cpu.iew.WB:rate 0.453444 # insts written-back per cycle -system.cpu.iew.WB:sent 56800066 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 837864 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9247048 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 10627556 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1790217 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 887680 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6942367 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65072200 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10074375 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 520995 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57143757 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 61290 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26699852 # num instructions producing a value +system.cpu.iew.WB:rate 0.453208 # insts written-back per cycle +system.cpu.iew.WB:sent 56799146 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 837773 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9250897 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 10628246 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1790214 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 887997 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6943382 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65075490 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10073283 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 520965 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57142461 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61275 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 11719 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1515207 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 557918 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 11738 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1515496 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 557834 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 132136 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 439501 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9711 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 132328 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 438613 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 9607 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 42523 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17618 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1520348 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 553290 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 42523 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 405909 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 431955 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.424281 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.424281 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 42661 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 17611 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1521011 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 554299 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 42661 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 406369 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 431404 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.424064 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.424064 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39528092 68.55% 68.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62364 0.11% 68.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39527901 68.55% 68.56% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62346 0.11% 68.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.71% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.71% # Type of FU issued @@ -408,80 +408,80 @@ system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 68.72% system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 68.72% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 68.72% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 68.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10425722 18.08% 86.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659174 11.55% 98.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 952878 1.65% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10424527 18.08% 86.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659257 11.55% 98.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 952873 1.65% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 57664754 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 434083 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007528 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 57663428 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 432905 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007507 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 49311 11.36% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 268240 61.79% 73.15% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 116532 26.85% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 49058 11.33% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 11.33% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 267419 61.77% 73.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 116428 26.89% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 90735242 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635528 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200743 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 90747041 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635430 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200309 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 62361011 68.73% 68.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 14057815 15.49% 84.22% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 6222317 6.86% 91.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3820698 4.21% 95.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2539136 2.80% 98.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1090667 1.20% 99.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 464211 0.51% 99.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 130030 0.14% 99.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 49357 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 62366198 68.73% 68.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 14061379 15.50% 84.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 6226874 6.86% 91.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 3821617 4.21% 95.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2539194 2.80% 98.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1091409 1.20% 99.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 462366 0.51% 99.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 128599 0.14% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 49405 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 90735242 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.461176 # Inst issue rate -system.cpu.iq.iqInstsAdded 59445556 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 57664754 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2039741 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8057348 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 28990 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1372161 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4163419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 90747041 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.460931 # Inst issue rate +system.cpu.iq.iqInstsAdded 59448706 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 57663428 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2039751 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8060465 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 28817 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1372188 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4168617 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1294712 # ITB accesses -system.cpu.itb.fetch_acv 931 # ITB acv -system.cpu.itb.fetch_hits 1255658 # ITB hits -system.cpu.itb.fetch_misses 39054 # ITB misses +system.cpu.itb.fetch_accesses 1294583 # ITB accesses +system.cpu.itb.fetch_acv 923 # ITB acv +system.cpu.itb.fetch_hits 1255493 # ITB hits +system.cpu.itb.fetch_misses 39090 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -497,51 +497,51 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175584 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175591 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5222 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192554 # number of callpals executed +system.cpu.kern.callpal::total 192561 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211714 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6425 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74913 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 242 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105891 57.88% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182935 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73546 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 242 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73549 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149226 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1826194246000 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 98158000 0.01% 97.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 391805000 0.02% 97.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 39040113000 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865724322000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211718 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6427 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74916 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 238 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105896 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182940 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73549 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 238 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73550 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149227 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1827171336500 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 97547000 0.01% 97.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 392033000 0.02% 97.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 39041048500 2.09% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1866701965000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981753 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694573 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.ipl_used::31 0.694549 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1736 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5963 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2105 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.319805 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::kernel 5956 # number of protection mode switches +system.cpu.kern.mode_switch::user 1736 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2107 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320013 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080760 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400566 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 30090318500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2984804000 0.16% 1.77% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832649191500 98.23% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080683 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.400697 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 30086574000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3015068000 0.16% 1.77% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1833600315000 98.23% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed @@ -574,29 +574,29 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3016554 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2589214 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 10627556 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6942367 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 125038494 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 13289726 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38227615 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1062967 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39056171 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1660859 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 58584 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 82207964 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 67568741 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 45291881 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12513158 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1515207 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4651851 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7064264 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 19709127 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1694237 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 11738316 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 247282 # count of temporary serializing insts renamed -system.cpu.timesIdled 1310688 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3018201 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2591237 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 10628246 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6943382 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 125102122 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 13297534 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38227478 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1065628 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39060011 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1661101 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 58596 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 82213921 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 67573183 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 45293711 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12514369 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1515496 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 4654173 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7066231 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 19705456 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1694142 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 11744700 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 247271 # count of temporary serializing insts renamed +system.cpu.timesIdled 1310957 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -627,37 +627,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137727.806267 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137707.205574 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85724.248652 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5722865806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85703.600260 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5722009806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3562013980 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3561155998 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6169.439863 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6170.205040 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64631052 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64639068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137634.602852 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137614.087573 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85631.059988 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85610.497208 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5742803804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5741947804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -665,7 +665,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3572955978 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3572097996 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -673,20 +673,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.081046 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.296742 # Average occupied blocks per context +system.iocache.occ_%::1 0.081528 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.304443 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137634.602852 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137614.087573 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85631.059988 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85610.497208 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5742803804 # number of overall miss cycles +system.iocache.overall_miss_latency 5741947804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -694,7 +694,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3572955978 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3572097996 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -704,47 +704,47 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.296742 # Cycle average of tags in use +system.iocache.tagsinuse 1.304443 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1711281439000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1711281262000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300867 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300867 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52486.783520 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300850 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300850 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52488.966283 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40337.693248 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 183854 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183854 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6141636000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.388919 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 117013 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 117013 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4720034500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.388919 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40339.814538 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 183845 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183845 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6141471500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.388915 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 117005 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117005 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4719960000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.388915 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 117013 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2092394 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2092394 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52046.378325 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 117005 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2092533 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2092533 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52046.060634 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.178174 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40015.025123 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1784912 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1784912 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16003324500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.146952 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307482 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307482 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1785047 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1785047 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16003435000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.146944 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 307486 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307486 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12303907000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146952 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12304020000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146944 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307481 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 811370500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_misses 307485 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810593000 # number of ReadReq MSHR uncacheable cycles system.l2c.SCUpgradeReq_accesses::0 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits @@ -767,82 +767,82 @@ system.l2c.UpgradeReq_mshr_miss_rate::1 inf # ms system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116153998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 832870 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832870 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 832870 # number of Writeback hits -system.l2c.Writeback_hits::total 832870 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1115666998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 832856 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 832856 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 832856 # number of Writeback hits +system.l2c.Writeback_hits::total 832856 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.629899 # Average number of references to valid blocks. +system.l2c.avg_refs 5.629154 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2393261 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2393383 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2393261 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52167.777006 # average overall miss latency +system.l2c.demand_accesses::total 2393383 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52168.141374 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40104.080387 # average overall mshr miss latency -system.l2c.demand_hits::0 1968766 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40104.548988 # average overall mshr miss latency +system.l2c.demand_hits::0 1968892 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1968766 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22144960500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.177371 # miss rate for demand accesses +system.l2c.demand_hits::total 1968892 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22144906500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.177360 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 424495 # number of demand (read+write) misses +system.l2c.demand_misses::0 424491 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424495 # number of demand (read+write) misses +system.l2c.demand_misses::total 424491 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17023941500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.177371 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 17023980000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.177360 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 424494 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 424490 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.186894 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.344697 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12248.264673 # Average occupied blocks per context -system.l2c.occ_blocks::1 22590.041641 # Average occupied blocks per context -system.l2c.overall_accesses::0 2393261 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.186942 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.344679 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12251.423039 # Average occupied blocks per context +system.l2c.occ_blocks::1 22588.894949 # Average occupied blocks per context +system.l2c.overall_accesses::0 2393383 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2393261 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52167.777006 # average overall miss latency +system.l2c.overall_accesses::total 2393383 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52168.141374 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40104.080387 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.548988 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1968766 # number of overall hits +system.l2c.overall_hits::0 1968892 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1968766 # number of overall hits -system.l2c.overall_miss_latency 22144960500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.177371 # miss rate for overall accesses +system.l2c.overall_hits::total 1968892 # number of overall hits +system.l2c.overall_miss_latency 22144906500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.177360 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 424495 # number of overall misses +system.l2c.overall_misses::0 424491 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424495 # number of overall misses +system.l2c.overall_misses::total 424491 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17023941500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.177371 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 17023980000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.177360 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 424494 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1927524498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 424490 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926259998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 390994 # number of replacements -system.l2c.sampled_refs 423736 # Sample count of references to valid blocks. +system.l2c.replacements 390992 # number of replacements +system.l2c.sampled_refs 423734 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 34838.306314 # Cycle average of tags in use -system.l2c.total_refs 2385591 # Total number of references to valid blocks. +system.l2c.tagsinuse 34840.317988 # Cycle average of tags in use +system.l2c.total_refs 2385264 # Total number of references to valid blocks. system.l2c.warmup_cycle 5637119000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 117624 # number of writebacks +system.l2c.writebacks 117628 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 748f3f017..1688d3208 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:44:21 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:25:09 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 6eff69d6b..eb0b216c3 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 158570 # Simulator instruction rate (inst/s) -host_mem_usage 213052 # Number of bytes of host memory used -host_seconds 2368.51 # Real time elapsed on the host -host_tick_rate 57558166 # Simulator tick rate (ticks/s) +host_inst_rate 178067 # Simulator instruction rate (inst/s) +host_mem_usage 212832 # Number of bytes of host memory used +host_seconds 2109.17 # Real time elapsed on the host +host_tick_rate 64635199 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated sim_seconds 0.136327 # Number of seconds simulated @@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 80299022 # DT system.cpu.dtb.write_misses 1470 # DTB write misses system.cpu.fetch.Branches 62456368 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 64427463 # Number of cache lines fetched -system.cpu.fetch.Cycles 168595579 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 104167812 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 1484985 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 548969588 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 304 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 6021463 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.229068 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 64427463 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 0e29ea50f..7d9e000fc 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 08:53:40 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:24:57 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 9644ea576..63c7a2e36 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 221847 # Simulator instruction rate (inst/s) -host_mem_usage 213388 # Number of bytes of host memory used -host_seconds 8217.59 # Real time elapsed on the host -host_tick_rate 85165348 # Simulator tick rate (ticks/s) +host_inst_rate 156459 # Simulator instruction rate (inst/s) +host_mem_usage 213156 # Number of bytes of host memory used +host_seconds 11651.86 # Real time elapsed on the host +host_tick_rate 60063670 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated sim_seconds 0.699854 # Number of seconds simulated @@ -12,7 +12,7 @@ system.cpu.BPredUnit.BTBCorrect 0 # Nu system.cpu.BPredUnit.BTBHits 236956975 # Number of BTB hits system.cpu.BPredUnit.BTBLookups 289938750 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 831 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 28355381 # Number of conditional branches incorrect +system.cpu.BPredUnit.condIncorrect 28355380 # Number of conditional branches incorrect system.cpu.BPredUnit.condPredicted 231810934 # Number of conditional branches predicted system.cpu.BPredUnit.lookups 346110000 # Number of BP lookups system.cpu.BPredUnit.usedRAS 49326422 # Number of times the RAS was used to get a target. @@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 258285727 # DT system.cpu.dtb.write_misses 37879 # DTB write misses system.cpu.fetch.Branches 346110000 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 346350693 # Number of cache lines fetched -system.cpu.fetch.Cycles 922065710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 575714813 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 4322310 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 3016744002 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 28792194 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.247273 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 346350693 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index daf9d1530..2cca5705e 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:43:59 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:25:07 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 71499661d..4f92cd575 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 163173 # Simulator instruction rate (inst/s) -host_mem_usage 215808 # Number of bytes of host memory used -host_seconds 487.78 # Real time elapsed on the host -host_tick_rate 55274619 # Simulator tick rate (ticks/s) +host_inst_rate 227615 # Simulator instruction rate (inst/s) +host_mem_usage 215572 # Number of bytes of host memory used +host_seconds 349.68 # Real time elapsed on the host +host_tick_rate 77104293 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated sim_seconds 0.026962 # Number of seconds simulated @@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 15053637 # DT system.cpu.dtb.write_misses 17557 # DTB write misses system.cpu.fetch.Branches 16280778 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 13394904 # Number of cache lines fetched -system.cpu.fetch.Cycles 33285903 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 19864093 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 154345 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 103458756 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 26906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 576280 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.301925 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 13394904 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout index 66c445ccc..b301ecfc9 100755 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 08:53:40 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:24:57 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 04e1f7d7c..aaad6352f 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 144806 # Simulator instruction rate (inst/s) -host_mem_usage 206568 # Number of bytes of host memory used -host_seconds 11988.72 # Real time elapsed on the host -host_tick_rate 60389347 # Simulator tick rate (ticks/s) +host_inst_rate 148199 # Simulator instruction rate (inst/s) +host_mem_usage 206348 # Number of bytes of host memory used +host_seconds 11714.26 # Real time elapsed on the host +host_tick_rate 61804258 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated sim_seconds 0.723991 # Number of seconds simulated @@ -153,9 +153,10 @@ system.cpu.dtb.write_hits 194797036 # DT system.cpu.dtb.write_misses 6192363 # DTB write misses system.cpu.fetch.Branches 344584799 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 354412327 # Number of cache lines fetched -system.cpu.fetch.Cycles 911372250 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 556959890 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 8690810 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 2851036906 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 28190849 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.237976 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 354412327 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index e64185111..6d564a58f 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:43:59 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:30:09 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 548b29280..6e4f9aea5 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 130193 # Simulator instruction rate (inst/s) -host_mem_usage 210712 # Number of bytes of host memory used -host_seconds 646.58 # Real time elapsed on the host -host_tick_rate 62840883 # Simulator tick rate (ticks/s) +host_inst_rate 134338 # Simulator instruction rate (inst/s) +host_mem_usage 210480 # Number of bytes of host memory used +host_seconds 626.63 # Real time elapsed on the host +host_tick_rate 64841631 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated sim_seconds 0.040632 # Number of seconds simulated @@ -145,9 +145,10 @@ system.cpu.dtb.write_hits 7182981 # DT system.cpu.dtb.write_misses 1041 # DTB write misses system.cpu.fetch.Branches 19564106 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 19059447 # Number of cache lines fetched -system.cpu.fetch.Cycles 49623738 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 30564219 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 482133 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 167632917 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 2031289 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.240750 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 19059447 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index c56e2a305..7b6a1125b 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:43:59 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:24:57 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 70e07c2b3..72be64488 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 34451 # Simulator instruction rate (inst/s) -host_mem_usage 203748 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 66857161 # Simulator tick rate (ticks/s) +host_inst_rate 10121 # Simulator instruction rate (inst/s) +host_mem_usage 203516 # Number of bytes of host memory used +host_seconds 0.63 # Real time elapsed on the host +host_tick_rate 19665204 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -143,9 +143,10 @@ system.cpu.dtb.write_hits 1051 # DT system.cpu.dtb.write_misses 25 # DTB write misses system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched -system.cpu.fetch.Cycles 4193 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2385 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 62d772708..fe2af5e09 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:43:59 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:48:46 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index c55fb3eb0..2363f1511 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 60581 # Simulator instruction rate (inst/s) -host_mem_usage 202656 # Number of bytes of host memory used +host_inst_rate 61982 # Simulator instruction rate (inst/s) +host_mem_usage 202420 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 184013511 # Simulator tick rate (ticks/s) +host_tick_rate 188319059 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -143,9 +143,10 @@ system.cpu.dtb.write_hits 351 # DT system.cpu.dtb.write_misses 17 # DTB write misses system.cpu.fetch.Branches 926 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 782 # Number of cache lines fetched -system.cpu.fetch.Cycles 1799 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 988 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index ac792f6c6..6b2281542 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 14 2010 23:58:18 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 14 2010 23:58:34 +M5 compiled Jan 17 2011 21:17:36 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 21:17:39 M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index 8e9b6a4ca..a5f35787b 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 72923 # Simulator instruction rate (inst/s) +host_inst_rate 35741 # Simulator instruction rate (inst/s) host_mem_usage 204488 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 179666090 # Simulator tick rate (ticks/s) +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 88262097 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000013 # Number of seconds simulated @@ -136,9 +136,10 @@ system.cpu.dtb.write_hits 0 # DT system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 1744 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1555 # Number of cache lines fetched -system.cpu.fetch.Cycles 4407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2837 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 11052 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 393 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.068205 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1555 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 1fe8a27f7..29a71f392 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 17040520. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 16206088. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index d3bc761bb..6bd581433 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 00:01:15 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 00:01:17 +M5 compiled Jan 17 2011 17:18:01 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 17:18:03 M5 executing on zizzer command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 6f780bef0..8b311d8d3 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 15746 # Simulator instruction rate (inst/s) -host_mem_usage 202164 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host -host_tick_rate 31829526 # Simulator tick rate (ticks/s) +host_inst_rate 12762 # Simulator instruction rate (inst/s) +host_mem_usage 202140 # Number of bytes of host memory used +host_seconds 0.45 # Real time elapsed on the host +host_tick_rate 25804848 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated @@ -136,9 +136,10 @@ system.cpu.dtb.write_hits 0 # DT system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched -system.cpu.fetch.Cycles 3561 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 2070 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 3dc1278fb..1d43d276a 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 15 2010 08:52:32 -M5 revision f440cdaf1c2d+ 7743+ default tip -M5 started Nov 15 2010 13:43:59 +M5 compiled Jan 17 2011 16:24:53 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 16:24:57 M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 91de8ff11..561bc8cb1 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 115372 # Simulator instruction rate (inst/s) -host_mem_usage 204236 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 127463354 # Simulator tick rate (ticks/s) +host_inst_rate 10660 # Simulator instruction rate (inst/s) +host_mem_usage 204092 # Number of bytes of host memory used +host_seconds 1.20 # Real time elapsed on the host +host_tick_rate 11797749 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -213,9 +213,10 @@ system.cpu.dtb.write_hits 2080 # DT system.cpu.dtb.write_misses 54 # DTB write misses system.cpu.fetch.Branches 5341 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 3993 # Number of cache lines fetched -system.cpu.fetch.Cycles 9162 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 611 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 29881 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 1641 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.188868 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 3993 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index f550d7f17..7c5c285a5 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 15 2011 04:38:18 -M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip -M5 started Jan 15 2011 04:38:23 -M5 executing on tater +M5 compiled Jan 17 2011 21:17:52 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 21:18:06 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index e87194a60..5aa081cb3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 46971 # Simulator instruction rate (inst/s) -host_mem_usage 216748 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host -host_tick_rate 60590117 # Simulator tick rate (ticks/s) +host_inst_rate 91156 # Simulator instruction rate (inst/s) +host_mem_usage 203828 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 117504787 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000019 # Number of seconds simulated @@ -126,9 +126,10 @@ system.cpu.decode.DECODE:SquashCycles 1178 # Nu system.cpu.decode.DECODE:UnblockCycles 107 # Number of cycles decode is unblocking system.cpu.fetch.Branches 5172 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 4077 # Number of cache lines fetched -system.cpu.fetch.Cycles 11611 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 7506 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 385 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 23982 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.SquashCycles 826 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.138611 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 4077 # Number of cycles fetch is stalled on an Icache miss diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index b338978a2..c7f419728 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -9,7 +9,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm +kernel=/dist/m5/system/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -155,7 +155,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/chips/pd/randd/dist/disks/ael-arm.ext2 +file=/dist/m5/system/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 122561307..e76a50eec 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -30,8 +30,14 @@ warn: Returning thumbEE disabled for now since we don't support CP14config regis For more information see: http://www.m5sim.org/warn/7998f2ea warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 warn: Need to flush all TLBs in MP For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 715d7a4d1..8382cb48d 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 15 2010 11:17:32 -M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip -M5 started Oct 15 2010 11:17:48 -M5 executing on aus-bc3-b4 -command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing +M5 compiled Jan 17 2011 18:36:49 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 18:36:52 +M5 executing on zizzer +command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 120261685000 because m5_exit instruction encountered +Exiting @ tick 114721074000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index d79fbb100..157177a6b 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,254 +1,254 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 571745 # Simulator instruction rate (inst/s) -host_mem_usage 384580 # Number of bytes of host memory used -host_seconds 88.62 # Real time elapsed on the host -host_tick_rate 1356995451 # Simulator tick rate (ticks/s) +host_inst_rate 1461109 # Simulator instruction rate (inst/s) +host_mem_usage 340352 # Number of bytes of host memory used +host_seconds 34.61 # Real time elapsed on the host +host_tick_rate 3314430509 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50669854 # Number of instructions simulated -sim_seconds 0.120262 # Number of seconds simulated -sim_ticks 120261685000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100213 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100213 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15144.474290 # average LoadLockedReq miss latency +sim_insts 50572425 # Number of instructions simulated +sim_seconds 0.114721 # Number of seconds simulated +sim_ticks 114721074000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100214 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100214 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12144.474290 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 95001 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95001 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 78933000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052009 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5212 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5212 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63297000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052009 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_hits::0 95014 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95014 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 78765000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051889 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5200 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5200 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63165000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051889 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5212 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 5200 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 7824422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7824422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15793.989050 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses::0 7824780 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7824780 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12793.661656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7587704 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7587704 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3738721500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030254 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 236718 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 236718 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3028490000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7588163 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7588163 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3738156500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030239 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 236617 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 236617 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3028228000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030239 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 236718 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 43432839000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 100212 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100212 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100212 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100212 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6671650 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6671650 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40817.981450 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 236617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38190415500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 100213 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100213 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100213 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100213 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6671860 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6671860 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37817.693965 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6499467 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499467 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7028162500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025808 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172183 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172183 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6511564000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025808 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6499787 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499787 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7026784000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025791 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172073 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6510516500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025791 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172183 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 172073 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.639363 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.660375 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14496072 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14496640 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14496072 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26331.273340 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14496640 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26340.112310 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23330.962751 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14087171 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14087950 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14087171 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10766884000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028208 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14087950 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10764940500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028192 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 408901 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 408690 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 408901 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 408690 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9540054000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028208 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9538744500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 408901 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 408690 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994782 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 509.328153 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14496072 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 509.199113 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14496640 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14496072 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26331.273340 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14496640 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26340.112310 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23330.962751 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14087171 # number of overall hits +system.cpu.dcache.overall_hits::0 14087950 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14087171 # number of overall hits -system.cpu.dcache.overall_miss_latency 10766884000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028208 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14087950 # number of overall hits +system.cpu.dcache.overall_miss_latency 10764940500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028192 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 408901 # number of overall misses +system.cpu.dcache.overall_misses::0 408690 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 408901 # number of overall misses +system.cpu.dcache.overall_misses::total 408690 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9540054000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028208 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9538744500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028192 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 408901 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 44358885500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 408690 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39116462000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 411855 # number of replacements -system.cpu.dcache.sampled_refs 412367 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 411628 # number of replacements +system.cpu.dcache.sampled_refs 412140 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.328153 # Cycle average of tags in use -system.cpu.dcache.total_refs 14284130 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.199113 # Cycle average of tags in use +system.cpu.dcache.total_refs 14284927 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 383037 # number of writebacks -system.cpu.dtb.accesses 15524365 # DTB accesses +system.cpu.dcache.writebacks 382676 # number of writebacks +system.cpu.dtb.accesses 15524935 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2228 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2199 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15518843 # DTB hits +system.cpu.dtb.hits 15519414 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5522 # DTB misses +system.cpu.dtb.misses 5521 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8739944 # DTB read accesses -system.cpu.dtb.read_hits 8735402 # DTB read hits -system.cpu.dtb.read_misses 4542 # DTB read misses -system.cpu.dtb.write_accesses 6784421 # DTB write accesses -system.cpu.dtb.write_hits 6783441 # DTB write hits +system.cpu.dtb.read_accesses 8740303 # DTB read accesses +system.cpu.dtb.read_hits 8735762 # DTB read hits +system.cpu.dtb.read_misses 4541 # DTB read misses +system.cpu.dtb.write_accesses 6784632 # DTB write accesses +system.cpu.dtb.write_hits 6783652 # DTB write hits system.cpu.dtb.write_misses 980 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41542689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41542689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14799.146758 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 41543801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41543801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11797.848096 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41109166 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41109166 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6415770500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010436 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 433523 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433523 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5114638500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010436 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41110405 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41110405 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6414604000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010432 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 433396 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433396 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5113853000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010432 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 433523 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 433396 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.826020 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.856667 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41542689 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41543801 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41542689 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14799.146758 # average overall miss latency +system.cpu.icache.demand_accesses::total 41543801 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14800.791885 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11797.848096 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41109166 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41110405 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41109166 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6415770500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010436 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41110405 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6414604000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010432 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 433523 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 433396 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433523 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433396 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5114638500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010436 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5113853000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010432 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 433523 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 433396 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.948287 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 485.522726 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41542689 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.945788 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 484.243503 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41543801 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41542689 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14799.146758 # average overall miss latency +system.cpu.icache.overall_accesses::total 41543801 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14800.791885 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11797.848096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41109166 # number of overall hits +system.cpu.icache.overall_hits::0 41110405 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41109166 # number of overall hits -system.cpu.icache.overall_miss_latency 6415770500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010436 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41110405 # number of overall hits +system.cpu.icache.overall_miss_latency 6414604000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010432 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 433523 # number of overall misses +system.cpu.icache.overall_misses::0 433396 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 433523 # number of overall misses +system.cpu.icache.overall_misses::total 433396 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5114638500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010436 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5113853000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010432 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 433523 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 433396 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 433010 # number of replacements -system.cpu.icache.sampled_refs 433522 # Sample count of references to valid blocks. +system.cpu.icache.replacements 432883 # number of replacements +system.cpu.icache.sampled_refs 433395 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 485.522726 # Cycle average of tags in use -system.cpu.icache.total_refs 41109166 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 484.243503 # Cycle average of tags in use +system.cpu.icache.total_refs 41110405 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33595 # number of writebacks +system.cpu.icache.writebacks 33555 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41545508 # DTB accesses +system.cpu.itb.accesses 41546620 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -256,9 +256,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41542689 # DTB hits -system.cpu.itb.inst_accesses 41545508 # ITB inst accesses -system.cpu.itb.inst_hits 41542689 # ITB inst hits +system.cpu.itb.hits 41543801 # DTB hits +system.cpu.itb.inst_accesses 41546620 # ITB inst accesses +system.cpu.itb.inst_hits 41543801 # ITB inst hits system.cpu.itb.inst_misses 2819 # ITB inst misses system.cpu.itb.misses 2819 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -272,9 +272,9 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 240523370 # number of cpu cycles simulated -system.cpu.num_insts 50669854 # Number of instructions executed -system.cpu.num_refs 16289326 # Number of memory references +system.cpu.numCycles 229442148 # number of cpu cycles simulated +system.cpu.num_insts 50572425 # Number of instructions executed +system.cpu.num_refs 16289993 # Number of memory references system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -344,140 +344,140 @@ system.iocache.warmup_cycle 0 # Cy system.iocache.writebacks 0 # number of writebacks system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 170437 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170437 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 170323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170323 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62185 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62185 # number of ReadExReq hits +system.l2c.ReadExReq_hits::0 62071 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62071 # number of ReadExReq hits system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.635144 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::0 0.635569 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.635144 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.635569 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 673342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 5664 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 679006 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52102.216096 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 26560864.864865 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 26612967.080961 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 673101 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 5652 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 678753 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52096.523258 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 28127657.142857 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 28179753.666115 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 654480 # number of ReadReq hits -system.l2c.ReadReq_hits::1 5627 # number of ReadReq hits -system.l2c.ReadReq_hits::total 660107 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 982752000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.028013 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.006532 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.034545 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18862 # number of ReadReq misses -system.l2c.ReadReq_misses::1 37 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18899 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 755960000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028067 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 3.336688 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.364755 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18899 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 33155867000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1746 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1746 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 721.804511 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 654204 # number of ReadReq hits +system.l2c.ReadReq_hits::1 5617 # number of ReadReq hits +system.l2c.ReadReq_hits::total 659821 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 984468000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.028075 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.006192 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.034267 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18897 # number of ReadReq misses +system.l2c.ReadReq_misses::1 35 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18932 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 757280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.028127 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 3.349611 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.377737 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18932 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 29199338000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1750 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1750 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 660.126947 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 1248000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.990263 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1729 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1729 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 69160000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.990263 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_latency 1144000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.990286 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1733 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1733 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 69320000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.990286 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1729 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1733 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 416632 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 416632 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 416632 # number of Writeback hits -system.l2c.Writeback_hits::total 416632 # number of Writeback hits +system.l2c.Writeback_accesses::0 416231 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 416231 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 416231 # number of Writeback hits +system.l2c.Writeback_hits::total 416231 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.976763 # Average number of references to valid blocks. +system.l2c.avg_refs 6.975292 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 843779 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 5664 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 849443 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52015.167487 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 178698810.810811 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 178750825.978298 # average overall miss latency +system.l2c.demand_accesses::0 843424 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 5652 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 849076 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52014.345374 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 188959200 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 189011214.345374 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 716665 # number of demand (read+write) hits -system.l2c.demand_hits::1 5627 # number of demand (read+write) hits -system.l2c.demand_hits::total 722292 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6611856000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.150648 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.006532 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.157181 # miss rate for demand accesses -system.l2c.demand_misses::0 127114 # number of demand (read+write) misses -system.l2c.demand_misses::1 37 # number of demand (read+write) misses -system.l2c.demand_misses::total 127151 # number of demand (read+write) misses +system.l2c.demand_hits::0 716275 # number of demand (read+write) hits +system.l2c.demand_hits::1 5617 # number of demand (read+write) hits +system.l2c.demand_hits::total 721892 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6613572000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.150753 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.006192 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.156946 # miss rate for demand accesses +system.l2c.demand_misses::0 127149 # number of demand (read+write) misses +system.l2c.demand_misses::1 35 # number of demand (read+write) misses +system.l2c.demand_misses::total 127184 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5086040000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.150692 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 22.448976 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 22.599668 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 127151 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5087360000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.150795 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 22.502477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 22.653272 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 127184 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.087309 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.478511 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5721.907765 # Average occupied blocks per context -system.l2c.occ_blocks::1 31359.701032 # Average occupied blocks per context -system.l2c.overall_accesses::0 843779 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 5664 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 849443 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52015.167487 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 178698810.810811 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 178750825.978298 # average overall miss latency +system.l2c.occ_%::0 0.086431 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.477933 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5664.361976 # Average occupied blocks per context +system.l2c.occ_blocks::1 31321.847814 # Average occupied blocks per context +system.l2c.overall_accesses::0 843424 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 5652 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 849076 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52014.345374 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 188959200 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 189011214.345374 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 716665 # number of overall hits -system.l2c.overall_hits::1 5627 # number of overall hits -system.l2c.overall_hits::total 722292 # number of overall hits -system.l2c.overall_miss_latency 6611856000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.150648 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.006532 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.157181 # miss rate for overall accesses -system.l2c.overall_misses::0 127114 # number of overall misses -system.l2c.overall_misses::1 37 # number of overall misses -system.l2c.overall_misses::total 127151 # number of overall misses +system.l2c.overall_hits::0 716275 # number of overall hits +system.l2c.overall_hits::1 5617 # number of overall hits +system.l2c.overall_hits::total 721892 # number of overall hits +system.l2c.overall_miss_latency 6613572000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.150753 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.006192 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.156946 # miss rate for overall accesses +system.l2c.overall_misses::0 127149 # number of overall misses +system.l2c.overall_misses::1 35 # number of overall misses +system.l2c.overall_misses::total 127184 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5086040000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.150692 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 22.448976 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 22.599668 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 127151 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 33895711000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5087360000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.150795 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 22.502477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 22.653272 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 127184 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29939182000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94181 # number of replacements -system.l2c.sampled_refs 125790 # Sample count of references to valid blocks. +system.l2c.replacements 94170 # number of replacements +system.l2c.sampled_refs 125831 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 37081.608797 # Cycle average of tags in use -system.l2c.total_refs 877607 # Total number of references to valid blocks. +system.l2c.tagsinuse 36986.209790 # Cycle average of tags in use +system.l2c.total_refs 877708 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87612 # number of writebacks +system.l2c.writebacks 87626 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status index 8953751c2..624e9a5f7 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status @@ -1 +1 @@ -build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED! +build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED! diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 4f8a47072..ac49cfc17 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 15 2011 04:38:18 -M5 revision 784f5d201f6e 7838 default callr15stats.patch tip qtip -M5 started Jan 15 2011 04:38:23 -M5 executing on tater +M5 compiled Jan 17 2011 21:17:52 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 21:19:18 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3a768d259..1034fcecd 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 82069 # Simulator instruction rate (inst/s) -host_mem_usage 227196 # Number of bytes of host memory used -host_seconds 14.05 # Real time elapsed on the host -host_tick_rate 8360775 # Simulator tick rate (ticks/s) +host_inst_rate 133732 # Simulator instruction rate (inst/s) +host_mem_usage 214280 # Number of bytes of host memory used +host_seconds 8.62 # Real time elapsed on the host +host_tick_rate 13623692 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1153323 # Number of instructions simulated sim_seconds 0.000117 # Number of seconds simulated @@ -136,9 +136,10 @@ system.cpu0.decode.DECODE:SquashCycles 2062 # Nu system.cpu0.decode.DECODE:UnblockCycles 202 # Number of cycles decode is unblocking system.cpu0.fetch.Branches 92364 # Number of branches that fetch encountered system.cpu0.fetch.CacheLines 5264 # Number of cache lines fetched -system.cpu0.fetch.Cycles 186834 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.Cycles 181529 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.IcacheSquashes 482 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.Insts 550067 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.SquashCycles 1232 # Number of cycles fetch has spent squashing system.cpu0.fetch.branchRate 0.393048 # Number of branch fetches per cycle system.cpu0.fetch.icacheStallCycles 5264 # Number of cycles fetch is stalled on an Icache miss @@ -509,9 +510,10 @@ system.cpu1.decode.DECODE:SquashCycles 1784 # Nu system.cpu1.decode.DECODE:UnblockCycles 8335 # Number of cycles decode is unblocking system.cpu1.fetch.Branches 44023 # Number of branches that fetch encountered system.cpu1.fetch.CacheLines 27242 # Number of cache lines fetched -system.cpu1.fetch.Cycles 120404 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.Cycles 93139 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.IcacheSquashes 219 # Number of outstanding Icache misses that were squashed system.cpu1.fetch.Insts 234880 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.SquashCycles 1183 # Number of cycles fetch has spent squashing system.cpu1.fetch.branchRate 0.220190 # Number of branch fetches per cycle system.cpu1.fetch.icacheStallCycles 27242 # Number of cycles fetch is stalled on an Icache miss @@ -881,9 +883,10 @@ system.cpu2.decode.DECODE:SquashCycles 1740 # Nu system.cpu2.decode.DECODE:UnblockCycles 3898 # Number of cycles decode is unblocking system.cpu2.fetch.Branches 60491 # Number of branches that fetch encountered system.cpu2.fetch.CacheLines 17027 # Number of cache lines fetched -system.cpu2.fetch.Cycles 138086 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.Cycles 121028 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.IcacheSquashes 224 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.Insts 343825 # Number of instructions fetch has processed +system.cpu2.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.SquashCycles 1162 # Number of cycles fetch has spent squashing system.cpu2.fetch.branchRate 0.303000 # Number of branch fetches per cycle system.cpu2.fetch.icacheStallCycles 17027 # Number of cycles fetch is stalled on an Icache miss @@ -1253,9 +1256,10 @@ system.cpu3.decode.DECODE:SquashCycles 1792 # Nu system.cpu3.decode.DECODE:UnblockCycles 5492 # Number of cycles decode is unblocking system.cpu3.fetch.Branches 55399 # Number of branches that fetch encountered system.cpu3.fetch.CacheLines 20572 # Number of cache lines fetched -system.cpu3.fetch.Cycles 133138 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.Cycles 112541 # Number of cycles fetch has run and was not squashing or blocked system.cpu3.fetch.IcacheSquashes 221 # Number of outstanding Icache misses that were squashed system.cpu3.fetch.Insts 309543 # Number of instructions fetch has processed +system.cpu3.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.SquashCycles 1170 # Number of cycles fetch has spent squashing system.cpu3.fetch.branchRate 0.277870 # Number of branch fetches per cycle system.cpu3.fetch.icacheStallCycles 20572 # Number of cycles fetch is stalled on an Icache miss |