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authorMarc Orr <marc.orr@gmail.com>2012-06-11 03:16:43 -0400
committerMarc Orr <marc.orr@gmail.com>2012-06-11 03:16:43 -0400
commit02f8178b44cdbe52b523c7385d56f4744801a589 (patch)
treeb0d9585332afb192e75299c46e06509cd285b061 /tests
parent754a9570f28ded7fc682cc56d33fb49912f63f3e (diff)
downloadgem5-02f8178b44cdbe52b523c7385d56f4744801a589.tar.xz
Regression: Fix some bugs in simple-timing-mp-ruby.py.
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/simple-timing-mp-ruby.py6
1 files changed, 4 insertions, 2 deletions
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 4447967a7..1cab30392 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -77,11 +77,13 @@ Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(system.cpu):
+ # create the interrupt controller
+ cpu.createInterruptController()
+
#
# Tie the cpu ports to the ruby cpu ports
#
- cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
- cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
+ cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i])
# -----------------------
# run simulation